2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
25 #include <core/object.h>
26 #include <core/class.h>
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
30 #include "nouveau_fence.h"
32 #include "nv50_display.h"
34 struct nv50_fence_chan
{
35 struct nouveau_fence_chan base
;
38 struct nv50_fence_priv
{
39 struct nouveau_fence_priv base
;
40 struct nouveau_bo
*bo
;
46 nv50_fence_context_new(struct nouveau_channel
*chan
)
48 struct drm_device
*dev
= chan
->drm
->dev
;
49 struct nv50_fence_priv
*priv
= chan
->drm
->fence
;
50 struct nv50_fence_chan
*fctx
;
51 struct ttm_mem_reg
*mem
= &priv
->bo
->bo
.mem
;
52 struct nouveau_object
*object
;
55 fctx
= chan
->fence
= kzalloc(sizeof(*fctx
), GFP_KERNEL
);
59 nouveau_fence_context_new(&fctx
->base
);
61 ret
= nouveau_object_new(nv_object(chan
->cli
), chan
->handle
,
63 &(struct nv_dma_class
) {
64 .flags
= NV_DMA_TARGET_VRAM
|
66 .start
= mem
->start
* PAGE_SIZE
,
67 .limit
= mem
->size
- 1,
68 }, sizeof(struct nv_dma_class
),
71 /* dma objects for display sync channel semaphore blocks */
72 for (i
= 0; !ret
&& i
< dev
->mode_config
.num_crtc
; i
++) {
73 struct nouveau_bo
*bo
= nv50_display_crtc_sema(dev
, i
);
75 ret
= nouveau_object_new(nv_object(chan
->cli
), chan
->handle
,
76 NvEvoSema0
+ i
, 0x003d,
77 &(struct nv_dma_class
) {
78 .flags
= NV_DMA_TARGET_VRAM
|
80 .start
= bo
->bo
.offset
,
81 .limit
= bo
->bo
.offset
+ 0xfff,
82 }, sizeof(struct nv_dma_class
),
87 nv10_fence_context_del(chan
);
92 nv50_fence_create(struct nouveau_drm
*drm
)
94 struct nv50_fence_priv
*priv
;
97 priv
= drm
->fence
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
101 priv
->base
.dtor
= nv10_fence_destroy
;
102 priv
->base
.context_new
= nv50_fence_context_new
;
103 priv
->base
.context_del
= nv10_fence_context_del
;
104 priv
->base
.emit
= nv10_fence_emit
;
105 priv
->base
.read
= nv10_fence_read
;
106 priv
->base
.sync
= nv17_fence_sync
;
107 spin_lock_init(&priv
->lock
);
109 ret
= nouveau_bo_new(drm
->dev
, 4096, 0x1000, TTM_PL_FLAG_VRAM
,
110 0, 0x0000, NULL
, &priv
->bo
);
112 ret
= nouveau_bo_pin(priv
->bo
, TTM_PL_FLAG_VRAM
);
114 ret
= nouveau_bo_map(priv
->bo
);
116 nouveau_bo_ref(NULL
, &priv
->bo
);
120 nouveau_bo_wr32(priv
->bo
, 0x000, 0x00000000);
121 priv
->base
.sync
= nv17_fence_sync
;
125 nv10_fence_destroy(drm
);
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