drivers/gpu/drm/nouveau/nv50_instmem.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30
  31 #include "nouveau_drv.h"
  32 #include "nouveau_vm.h"
  33
  34 #define BAR1_VM_BASE 0x0020000000ULL
  35 #define BAR1_VM_SIZE pci_resource_len(dev->pdev, 1)
  36 #define BAR3_VM_BASE 0x0000000000ULL
  37 #define BAR3_VM_SIZE pci_resource_len(dev->pdev, 3)
  38
  39 struct nv50_instmem_priv {
  40         uint32_t save1700[5]; /* 0x1700->0x1710 */
  41
  42         struct nouveau_gpuobj *bar1_dmaobj;
  43         struct nouveau_gpuobj *bar3_dmaobj;
  44 };
  45
  46 static void
  47 nv50_channel_del(struct nouveau_channel **pchan)
  48 {
  49         struct nouveau_channel *chan;
  50
  51         chan = *pchan;
  52         *pchan = NULL;
  53         if (!chan)
  54                 return;
  55
  56         nouveau_gpuobj_ref(NULL, &chan->ramfc);
  57         nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
  58         nouveau_gpuobj_ref(NULL, &chan->vm_pd);
  59         if (chan->ramin_heap.free_stack.next)
  60                 drm_mm_takedown(&chan->ramin_heap);
  61         nouveau_gpuobj_ref(NULL, &chan->ramin);
  62         kfree(chan);
  63 }
  64
  65 static int
  66 nv50_channel_new(struct drm_device *dev, u32 size, struct nouveau_vm *vm,
  67                  struct nouveau_channel **pchan)
  68 {
  69         struct drm_nouveau_private *dev_priv = dev->dev_private;
  70         u32 pgd = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
  71         u32  fc = (dev_priv->chipset == 0x50) ? 0x0000 : 0x4200;
  72         struct nouveau_channel *chan;
  73         int ret, i;
  74
  75         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
  76         if (!chan)
  77                 return -ENOMEM;
  78         chan->dev = dev;
  79
  80         ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
  81         if (ret) {
  82                 nv50_channel_del(&chan);
  83                 return ret;
  84         }
  85
  86         ret = drm_mm_init(&chan->ramin_heap, 0x6000, chan->ramin->size);
  87         if (ret) {
  88                 nv50_channel_del(&chan);
  89                 return ret;
  90         }
  91
  92         ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst == ~0 ? ~0 :
  93                                       chan->ramin->pinst + pgd,
  94                                       chan->ramin->vinst + pgd,
  95                                       0x4000, NVOBJ_FLAG_ZERO_ALLOC,
  96                                       &chan->vm_pd);
  97         if (ret) {
  98                 nv50_channel_del(&chan);
  99                 return ret;
 100         }
 101
 102         for (i = 0; i < 0x4000; i += 8) {
 103                 nv_wo32(chan->vm_pd, i + 0, 0x00000000);
 104                 nv_wo32(chan->vm_pd, i + 4, 0xdeadcafe);
 105         }
 106
 107         ret = nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);
 108         if (ret) {
 109                 nv50_channel_del(&chan);
 110                 return ret;
 111         }
 112
 113         ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst == ~0 ? ~0 :
 114                                       chan->ramin->pinst + fc,
 115                                       chan->ramin->vinst + fc, 0x100,
 116                                       NVOBJ_FLAG_ZERO_ALLOC, &chan->ramfc);
 117         if (ret) {
 118                 nv50_channel_del(&chan);
 119                 return ret;
 120         }
 121
 122         *pchan = chan;
 123         return 0;
 124 }
 125
 126 int
 127 nv50_instmem_init(struct drm_device *dev)
 128 {
 129         struct drm_nouveau_private *dev_priv = dev->dev_private;
 130         struct nv50_instmem_priv *priv;
 131         struct nouveau_channel *chan;
 132         struct nouveau_vm *vm;
 133         int ret, i;
 134         u32 tmp;
 135
 136         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 137         if (!priv)
 138                 return -ENOMEM;
 139         dev_priv->engine.instmem.priv = priv;
 140
 141         /* Save state, will restore at takedown. */
 142         for (i = 0x1700; i <= 0x1710; i += 4)
 143                 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
 144
 145         /* Global PRAMIN heap */
 146         ret = drm_mm_init(&dev_priv->ramin_heap, 0, dev_priv->ramin_size);
 147         if (ret) {
 148                 NV_ERROR(dev, "Failed to init RAMIN heap\n");
 149                 goto error;
 150         }
 151
 152         /* BAR3 */
 153         ret = nouveau_vm_new(dev, BAR3_VM_BASE, BAR3_VM_SIZE, BAR3_VM_BASE,
 154                              29, 12, 16, &dev_priv->bar3_vm);
 155         if (ret)
 156                 goto error;
 157
 158         ret = nouveau_gpuobj_new(dev, NULL, (BAR3_VM_SIZE >> 12) * 8,
 159                                  0x1000, NVOBJ_FLAG_DONT_MAP |
 160                                  NVOBJ_FLAG_ZERO_ALLOC,
 161                                  &dev_priv->bar3_vm->pgt[0].obj);
 162         if (ret)
 163                 goto error;
 164         dev_priv->bar3_vm->pgt[0].page_shift = 12;
 165         dev_priv->bar3_vm->pgt[0].refcount = 1;
 166
 167         nv50_instmem_map(dev_priv->bar3_vm->pgt[0].obj);
 168
 169         ret = nv50_channel_new(dev, 128 * 1024, dev_priv->bar3_vm, &chan);
 170         if (ret)
 171                 goto error;
 172         dev_priv->channels.ptr[0] = dev_priv->channels.ptr[127] = chan;
 173
 174         ret = nv50_gpuobj_dma_new(chan, 0x0000, BAR3_VM_BASE, BAR3_VM_SIZE,
 175                                   NV_MEM_TARGET_VM, NV_MEM_ACCESS_VM,
 176                                   NV_MEM_TYPE_VM, NV_MEM_COMP_VM,
 177                                   &priv->bar3_dmaobj);
 178         if (ret)
 179                 goto error;
 180
 181         nv_wr32(dev, 0x001704, 0x00000000 | (chan->ramin->vinst >> 12));
 182         nv_wr32(dev, 0x001704, 0x40000000 | (chan->ramin->vinst >> 12));
 183         nv_wr32(dev, 0x00170c, 0x80000000 | (priv->bar3_dmaobj->cinst >> 4));
 184
 185         tmp = nv_ri32(dev, 0);
 186         nv_wi32(dev, 0, ~tmp);
 187         if (nv_ri32(dev, 0) != ~tmp) {
 188                 NV_ERROR(dev, "PRAMIN readback failed\n");
 189                 ret = -EIO;
 190                 goto error;
 191         }
 192         nv_wi32(dev, 0, tmp);
 193
 194         dev_priv->ramin_available = true;
 195
 196         /* BAR1 */
 197         ret = nouveau_vm_new(dev, BAR1_VM_BASE, BAR1_VM_SIZE, BAR1_VM_BASE,
 198                              29, 12, 16, &vm);
 199         if (ret)
 200                 goto error;
 201
 202         ret = nouveau_vm_ref(vm, &dev_priv->bar1_vm, chan->vm_pd);
 203         if (ret)
 204                 goto error;
 205         nouveau_vm_ref(NULL, &vm, NULL);
 206
 207         ret = nv50_gpuobj_dma_new(chan, 0x0000, BAR1_VM_BASE, BAR1_VM_SIZE,
 208                                   NV_MEM_TARGET_VM, NV_MEM_ACCESS_VM,
 209                                   NV_MEM_TYPE_VM, NV_MEM_COMP_VM,
 210                                   &priv->bar1_dmaobj);
 211         if (ret)
 212                 goto error;
 213
 214         nv_wr32(dev, 0x001708, 0x80000000 | (priv->bar1_dmaobj->cinst >> 4));
 215         for (i = 0; i < 8; i++)
 216                 nv_wr32(dev, 0x1900 + (i*4), 0);
 217
 218         /* Create shared channel VM, space is reserved at the beginning
 219          * to catch "NULL pointer" references
 220          */
 221         ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 222                              29, 12, 16, &dev_priv->chan_vm);
 223         if (ret)
 224                 return ret;
 225
 226         return 0;
 227
 228 error:
 229         nv50_instmem_takedown(dev);
 230         return ret;
 231 }
 232
 233 void
 234 nv50_instmem_takedown(struct drm_device *dev)
 235 {
 236         struct drm_nouveau_private *dev_priv = dev->dev_private;
 237         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 238         struct nouveau_channel *chan = dev_priv->channels.ptr[0];
 239         int i;
 240
 241         NV_DEBUG(dev, "\n");
 242
 243         if (!priv)
 244                 return;
 245
 246         dev_priv->ramin_available = false;
 247
 248         nouveau_vm_ref(NULL, &dev_priv->chan_vm, NULL);
 249
 250         for (i = 0x1700; i <= 0x1710; i += 4)
 251                 nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]);
 252
 253         nouveau_gpuobj_ref(NULL, &priv->bar3_dmaobj);
 254         nouveau_gpuobj_ref(NULL, &priv->bar1_dmaobj);
 255
 256         nouveau_vm_ref(NULL, &dev_priv->bar1_vm, chan->vm_pd);
 257         dev_priv->channels.ptr[127] = 0;
 258         nv50_channel_del(&dev_priv->channels.ptr[0]);
 259
 260         nouveau_gpuobj_ref(NULL, &dev_priv->bar3_vm->pgt[0].obj);
 261         nouveau_vm_ref(NULL, &dev_priv->bar3_vm, NULL);
 262
 263         if (dev_priv->ramin_heap.free_stack.next)
 264                 drm_mm_takedown(&dev_priv->ramin_heap);
 265
 266         dev_priv->engine.instmem.priv = NULL;
 267         kfree(priv);
 268 }
 269
 270 int
 271 nv50_instmem_suspend(struct drm_device *dev)
 272 {
 273         struct drm_nouveau_private *dev_priv = dev->dev_private;
 274
 275         dev_priv->ramin_available = false;
 276         return 0;
 277 }
 278
 279 void
 280 nv50_instmem_resume(struct drm_device *dev)
 281 {
 282         struct drm_nouveau_private *dev_priv = dev->dev_private;
 283         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 284         struct nouveau_channel *chan = dev_priv->channels.ptr[0];
 285         int i;
 286
 287         /* Poke the relevant regs, and pray it works :) */
 288         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12));
 289         nv_wr32(dev, NV50_PUNK_UNK1710, 0);
 290         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12) |
 291                                          NV50_PUNK_BAR_CFG_BASE_VALID);
 292         nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->bar1_dmaobj->cinst >> 4) |
 293                                         NV50_PUNK_BAR1_CTXDMA_VALID);
 294         nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->bar3_dmaobj->cinst >> 4) |
 295                                         NV50_PUNK_BAR3_CTXDMA_VALID);
 296
 297         for (i = 0; i < 8; i++)
 298                 nv_wr32(dev, 0x1900 + (i*4), 0);
 299
 300         dev_priv->ramin_available = true;
 301 }
 302
 303 struct nv50_gpuobj_node {
 304         struct nouveau_vram *vram;
 305         struct nouveau_vma chan_vma;
 306         u32 align;
 307 };
 308
 309
 310 int
 311 nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
 312 {
 313         struct drm_device *dev = gpuobj->dev;
 314         struct drm_nouveau_private *dev_priv = dev->dev_private;
 315         struct nv50_gpuobj_node *node = NULL;
 316         int ret;
 317
 318         node = kzalloc(sizeof(*node), GFP_KERNEL);
 319         if (!node)
 320                 return -ENOMEM;
 321         node->align = align;
 322
 323         size  = (size + 4095) & ~4095;
 324         align = max(align, (u32)4096);
 325
 326         ret = nv50_vram_new(dev, size, align, 0, 0, &node->vram);
 327         if (ret) {
 328                 kfree(node);
 329                 return ret;
 330         }
 331
 332         gpuobj->vinst = node->vram->offset;
 333
 334         if (gpuobj->flags & NVOBJ_FLAG_VM) {
 335                 ret = nouveau_vm_get(dev_priv->chan_vm, size, 12,
 336                                      NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
 337                                      &node->chan_vma);
 338                 if (ret) {
 339                         nv50_vram_del(dev, &node->vram);
 340                         kfree(node);
 341                         return ret;
 342                 }
 343
 344                 nouveau_vm_map(&node->chan_vma, node->vram);
 345                 gpuobj->vinst = node->chan_vma.offset;
 346         }
 347
 348         gpuobj->size = size;
 349         gpuobj->node = node;
 350         return 0;
 351 }
 352
 353 void
 354 nv50_instmem_put(struct nouveau_gpuobj *gpuobj)
 355 {
 356         struct drm_device *dev = gpuobj->dev;
 357         struct nv50_gpuobj_node *node;
 358
 359         node = gpuobj->node;
 360         gpuobj->node = NULL;
 361
 362         if (node->chan_vma.node) {
 363                 nouveau_vm_unmap(&node->chan_vma);
 364                 nouveau_vm_put(&node->chan_vma);
 365         }
 366         nv50_vram_del(dev, &node->vram);
 367         kfree(node);
 368 }
 369
 370 int
 371 nv50_instmem_map(struct nouveau_gpuobj *gpuobj)
 372 {
 373         struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
 374         struct nv50_gpuobj_node *node = gpuobj->node;
 375         int ret;
 376
 377         ret = nouveau_vm_get(dev_priv->bar3_vm, gpuobj->size, 12,
 378                              NV_MEM_ACCESS_RW, &node->vram->bar_vma);
 379         if (ret)
 380                 return ret;
 381
 382         nouveau_vm_map(&node->vram->bar_vma, node->vram);
 383         gpuobj->pinst = node->vram->bar_vma.offset;
 384         return 0;
 385 }
 386
 387 void
 388 nv50_instmem_unmap(struct nouveau_gpuobj *gpuobj)
 389 {
 390         struct nv50_gpuobj_node *node = gpuobj->node;
 391
 392         if (node->vram->bar_vma.node) {
 393                 nouveau_vm_unmap(&node->vram->bar_vma);
 394                 nouveau_vm_put(&node->vram->bar_vma);
 395         }
 396 }
 397
 398 void
 399 nv50_instmem_flush(struct drm_device *dev)
 400 {
 401         nv_wr32(dev, 0x00330c, 0x00000001);
 402         if (!nv_wait(dev, 0x00330c, 0x00000002, 0x00000000))
 403                 NV_ERROR(dev, "PRAMIN flush timeout\n");
 404 }
 405
 406 void
 407 nv84_instmem_flush(struct drm_device *dev)
 408 {
 409         nv_wr32(dev, 0x070000, 0x00000001);
 410         if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000))
 411                 NV_ERROR(dev, "PRAMIN flush timeout\n");
 412 }
 413