2d8f68792d8026c38f826bf7beec84a2de45f339
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / disp / hdagf110.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "nv50.h"
25 #include "outp.h"
26
27 #include <core/client.h>
28 #include <subdev/bios.h>
29 #include <subdev/bios/dcb.h>
30 #include <subdev/timer.h>
31
32 #include <nvif/class.h>
33 #include <nvif/unpack.h>
34
35 int
36 gf110_hda_eld(NV50_DISP_MTHD_V1)
37 {
38 struct nvkm_device *device = disp->base.engine.subdev.device;
39 union {
40 struct nv50_disp_sor_hda_eld_v0 v0;
41 } *args = data;
42 const u32 soff = outp->or * 0x030;
43 const u32 hoff = head * 0x800;
44 int ret, i;
45
46 nv_ioctl(object, "disp sor hda eld size %d\n", size);
47 if (nvif_unpack(args->v0, 0, 0, true)) {
48 nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version);
49 if (size > 0x60)
50 return -E2BIG;
51 } else
52 return ret;
53
54 if (size && args->v0.data[0]) {
55 if (outp->info.type == DCB_OUTPUT_DP) {
56 nvkm_mask(device, 0x616618 + hoff, 0x8000000c, 0x80000001);
57 nvkm_msec(device, 2000,
58 u32 tmp = nvkm_rd32(device, 0x616618 + hoff);
59 if (!(tmp & 0x80000000))
60 break;
61 );
62 }
63 nvkm_mask(device, 0x616548 + hoff, 0x00000070, 0x00000000);
64 for (i = 0; i < size; i++)
65 nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | args->v0.data[i]);
66 for (; i < 0x60; i++)
67 nvkm_wr32(device, 0x10ec00 + soff, (i << 8));
68 nvkm_mask(device, 0x10ec10 + soff, 0x80000003, 0x80000003);
69 } else {
70 if (outp->info.type == DCB_OUTPUT_DP) {
71 nvkm_mask(device, 0x616618 + hoff, 0x80000001, 0x80000000);
72 nvkm_msec(device, 2000,
73 u32 tmp = nvkm_rd32(device, 0x616618 + hoff);
74 if (!(tmp & 0x80000000))
75 break;
76 );
77 }
78 nvkm_mask(device, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size);
79 }
80
81 return 0;
82 }
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