drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25 #include "outpdp.h"
  26
  27 #include <subdev/timer.h>
  28
  29 static inline u32
  30 gm204_sor_soff(struct nvkm_output_dp *outp)
  31 {
  32         return (ffs(outp->base.info.or) - 1) * 0x800;
  33 }
  34
  35 static inline u32
  36 gm204_sor_loff(struct nvkm_output_dp *outp)
  37 {
  38         return gm204_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
  39 }
  40
  41 void
  42 gm204_sor_magic(struct nvkm_output *outp)
  43 {
  44         struct nvkm_device *device = outp->disp->engine.subdev.device;
  45         const u32 soff = outp->or * 0x100;
  46         const u32 data = outp->or + 1;
  47         if (outp->info.sorconf.link & 1)
  48                 nvkm_mask(device, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
  49         if (outp->info.sorconf.link & 2)
  50                 nvkm_mask(device, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
  51 }
  52
  53 static inline u32
  54 gm204_sor_dp_lane_map(struct nvkm_device *device, u8 lane)
  55 {
  56         return lane * 0x08;
  57 }
  58
  59 static int
  60 gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
  61 {
  62         struct nvkm_device *device = outp->base.disp->engine.subdev.device;
  63         const u32 soff = gm204_sor_soff(outp);
  64         const u32 data = 0x01010101 * pattern;
  65         if (outp->base.info.sorconf.link & 1)
  66                 nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, data);
  67         else
  68                 nvkm_mask(device, 0x61c12c + soff, 0x0f0f0f0f, data);
  69         return 0;
  70 }
  71
  72 static int
  73 gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
  74 {
  75         struct nvkm_device *device = outp->base.disp->engine.subdev.device;
  76         const u32 soff = gm204_sor_soff(outp);
  77         const u32 loff = gm204_sor_loff(outp);
  78         u32 mask = 0, i;
  79
  80         for (i = 0; i < nr; i++)
  81                 mask |= 1 << (gm204_sor_dp_lane_map(device, i) >> 3);
  82
  83         nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);
  84         nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);
  85         nvkm_msec(device, 2000,
  86                 if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000))
  87                         break;
  88         );
  89         return 0;
  90 }
  91
  92 static int
  93 gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
  94                      int ln, int vs, int pe, int pc)
  95 {
  96         struct nvkm_device *device = outp->base.disp->engine.subdev.device;
  97         struct nvkm_bios *bios = device->bios;
  98         const u32 shift = gm204_sor_dp_lane_map(device, ln);
  99         const u32 loff = gm204_sor_loff(outp);
 100         u32 addr, data[4];
 101         u8  ver, hdr, cnt, len;
 102         struct nvbios_dpout info;
 103         struct nvbios_dpcfg ocfg;
 104
 105         addr = nvbios_dpout_match(bios, outp->base.info.hasht,
 106                                         outp->base.info.hashm,
 107                                   &ver, &hdr, &cnt, &len, &info);
 108         if (!addr)
 109                 return -ENODEV;
 110
 111         addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
 112                                   &ver, &hdr, &cnt, &len, &ocfg);
 113         if (!addr)
 114                 return -EINVAL;
 115         ocfg.tx_pu &= 0x0f;
 116
 117         data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
 118         data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
 119         data[2] = nvkm_rd32(device, 0x61c130 + loff);
 120         if ((data[2] & 0x00000f00) < (ocfg.tx_pu << 8) || ln == 0)
 121                 data[2] = (data[2] & ~0x00000f00) | (ocfg.tx_pu << 8);
 122         nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
 123         nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
 124         nvkm_wr32(device, 0x61c130 + loff, data[2]);
 125         data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
 126         nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
 127         return 0;
 128 }
 129
 130 static const struct nvkm_output_dp_func
 131 gm204_sor_dp_func = {
 132         .pattern = gm204_sor_dp_pattern,
 133         .lnk_pwr = gm204_sor_dp_lnk_pwr,
 134         .lnk_ctl = gf119_sor_dp_lnk_ctl,
 135         .drv_ctl = gm204_sor_dp_drv_ctl,
 136 };
 137
 138 int
 139 gm204_sor_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
 140                  struct nvkm_output **poutp)
 141 {
 142         return nvkm_output_dp_new_(&gm204_sor_dp_func, disp, index, dcbE, poutp);
 143 }