drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "channv04.h"
  25 #include "regsnv04.h"
  26
  27 #include <core/client.h>
  28 #include <core/ramht.h>
  29 #include <subdev/instmem.h>
  30
  31 #include <nvif/class.h>
  32 #include <nvif/cl006b.h>
  33 #include <nvif/unpack.h>
  34
  35 void
  36 nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie)
  37 {
  38         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
  39         struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
  40         nvkm_ramht_remove(imem->ramht, cookie);
  41 }
  42
  43 static int
  44 nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,
  45                           struct nvkm_object *object)
  46 {
  47         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
  48         struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
  49         u32 context = 0x80000000 | chan->base.chid << 24;
  50         u32 handle  = object->handle;
  51         int hash;
  52
  53         switch (object->engine->subdev.index) {
  54         case NVKM_ENGINE_DMAOBJ:
  55         case NVKM_ENGINE_SW    : context |= 0x00000000; break;
  56         case NVKM_ENGINE_GR    : context |= 0x00010000; break;
  57         case NVKM_ENGINE_MPEG  : context |= 0x00020000; break;
  58         default:
  59                 WARN_ON(1);
  60                 return -EINVAL;
  61         }
  62
  63         mutex_lock(&chan->fifo->base.engine.subdev.mutex);
  64         hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4,
  65                                  handle, context);
  66         mutex_unlock(&chan->fifo->base.engine.subdev.mutex);
  67         return hash;
  68 }
  69
  70 void
  71 nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
  72 {
  73         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
  74         struct nv04_fifo *fifo = chan->fifo;
  75         struct nvkm_device *device = fifo->base.engine.subdev.device;
  76         struct nvkm_memory *fctx = device->imem->ramfc;
  77         const struct nv04_fifo_ramfc *c;
  78         unsigned long flags;
  79         u32 mask = fifo->base.nr - 1;
  80         u32 data = chan->ramfc;
  81         u32 chid;
  82
  83         /* prevent fifo context switches */
  84         spin_lock_irqsave(&fifo->base.lock, flags);
  85         nvkm_wr32(device, NV03_PFIFO_CACHES, 0);
  86
  87         /* if this channel is active, replace it with a null context */
  88         chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & mask;
  89         if (chid == chan->base.chid) {
  90                 nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
  91                 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0);
  92                 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
  93
  94                 c = fifo->ramfc;
  95                 do {
  96                         u32 rm = ((1ULL << c->bits) - 1) << c->regs;
  97                         u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
  98                         u32 rv = (nvkm_rd32(device, c->regp) &  rm) >> c->regs;
  99                         u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm);
 100                         nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs));
 101                 } while ((++c)->bits);
 102
 103                 c = fifo->ramfc;
 104                 do {
 105                         nvkm_wr32(device, c->regp, 0x00000000);
 106                 } while ((++c)->bits);
 107
 108                 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0);
 109                 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0);
 110                 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, mask);
 111                 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
 112                 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
 113         }
 114
 115         /* restore normal operation, after disabling dma mode */
 116         nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0);
 117         nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
 118         spin_unlock_irqrestore(&fifo->base.lock, flags);
 119 }
 120
 121 void
 122 nv04_fifo_dma_init(struct nvkm_fifo_chan *base)
 123 {
 124         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
 125         struct nv04_fifo *fifo = chan->fifo;
 126         struct nvkm_device *device = fifo->base.engine.subdev.device;
 127         u32 mask = 1 << chan->base.chid;
 128         unsigned long flags;
 129         spin_lock_irqsave(&fifo->base.lock, flags);
 130         nvkm_mask(device, NV04_PFIFO_MODE, mask, mask);
 131         spin_unlock_irqrestore(&fifo->base.lock, flags);
 132 }
 133
 134 void *
 135 nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base)
 136 {
 137         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
 138         struct nv04_fifo *fifo = chan->fifo;
 139         struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
 140         const struct nv04_fifo_ramfc *c = fifo->ramfc;
 141
 142         nvkm_kmap(imem->ramfc);
 143         do {
 144                 nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000);
 145         } while ((++c)->bits);
 146         nvkm_done(imem->ramfc);
 147         return chan;
 148 }
 149
 150 const struct nvkm_fifo_chan_func
 151 nv04_fifo_dma_func = {
 152         .dtor = nv04_fifo_dma_dtor,
 153         .init = nv04_fifo_dma_init,
 154         .fini = nv04_fifo_dma_fini,
 155         .object_ctor = nv04_fifo_dma_object_ctor,
 156         .object_dtor = nv04_fifo_dma_object_dtor,
 157 };
 158
 159 static int
 160 nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
 161                   void *data, u32 size, struct nvkm_object **pobject)
 162 {
 163         struct nvkm_object *parent = oclass->parent;
 164         union {
 165                 struct nv03_channel_dma_v0 v0;
 166         } *args = data;
 167         struct nv04_fifo *fifo = nv04_fifo(base);
 168         struct nv04_fifo_chan *chan = NULL;
 169         struct nvkm_device *device = fifo->base.engine.subdev.device;
 170         struct nvkm_instmem *imem = device->imem;
 171         int ret = -ENOSYS;
 172
 173         nvif_ioctl(parent, "create channel dma size %d\n", size);
 174         if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
 175                 nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
 176                                    "offset %08x\n", args->v0.version,
 177                            args->v0.pushbuf, args->v0.offset);
 178                 if (!args->v0.pushbuf)
 179                         return -EINVAL;
 180         } else
 181                 return ret;
 182
 183         if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
 184                 return -ENOMEM;
 185         *pobject = &chan->base.object;
 186
 187         ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,
 188                                   0x1000, 0x1000, false, 0, args->v0.pushbuf,
 189                                   (1ULL << NVKM_ENGINE_DMAOBJ) |
 190                                   (1ULL << NVKM_ENGINE_GR) |
 191                                   (1ULL << NVKM_ENGINE_SW),
 192                                   0, 0x800000, 0x10000, oclass, &chan->base);
 193         chan->fifo = fifo;
 194         if (ret)
 195                 return ret;
 196
 197         args->v0.chid = chan->base.chid;
 198         chan->ramfc = chan->base.chid * 32;
 199
 200         nvkm_kmap(imem->ramfc);
 201         nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
 202         nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
 203         nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4);
 204         nvkm_wo32(imem->ramfc, chan->ramfc + 0x10,
 205                                NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 206                                NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 207 #ifdef __BIG_ENDIAN
 208                                NV_PFIFO_CACHE1_BIG_ENDIAN |
 209 #endif
 210                                NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
 211         nvkm_done(imem->ramfc);
 212         return 0;
 213 }
 214
 215 const struct nvkm_fifo_chan_oclass
 216 nv04_fifo_dma_oclass = {
 217         .base.oclass = NV03_CHANNEL_DMA,
 218         .base.minver = 0,
 219         .base.maxver = 0,
 220         .ctor = nv04_fifo_dma_new,
 221 };