drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include <engine/fifo.h>
  25
  26 #include <core/client.h>
  27 #include <core/engctx.h>
  28 #include <core/enum.h>
  29 #include <core/handle.h>
  30 #include <subdev/bar.h>
  31 #include <subdev/fb.h>
  32 #include <subdev/mmu.h>
  33 #include <subdev/timer.h>
  34
  35 #include <nvif/class.h>
  36 #include <nvif/unpack.h>
  37
  38 struct gf100_fifo {
  39         struct nvkm_fifo base;
  40
  41         struct work_struct fault;
  42         u64 mask;
  43
  44         struct {
  45                 struct nvkm_gpuobj *mem[2];
  46                 int active;
  47                 wait_queue_head_t wait;
  48         } runlist;
  49
  50         struct {
  51                 struct nvkm_gpuobj *mem;
  52                 struct nvkm_vma bar;
  53         } user;
  54         int spoon_nr;
  55 };
  56
  57 struct gf100_fifo_base {
  58         struct nvkm_fifo_base base;
  59         struct nvkm_gpuobj *pgd;
  60         struct nvkm_vm *vm;
  61 };
  62
  63 struct gf100_fifo_chan {
  64         struct nvkm_fifo_chan base;
  65         enum {
  66                 STOPPED,
  67                 RUNNING,
  68                 KILLED
  69         } state;
  70 };
  71
  72 /*******************************************************************************
  73  * FIFO channel objects
  74  ******************************************************************************/
  75
  76 static void
  77 gf100_fifo_runlist_update(struct gf100_fifo *fifo)
  78 {
  79         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
  80         struct nvkm_device *device = subdev->device;
  81         struct nvkm_bar *bar = device->bar;
  82         struct nvkm_gpuobj *cur;
  83         int i, p;
  84
  85         mutex_lock(&nv_subdev(fifo)->mutex);
  86         cur = fifo->runlist.mem[fifo->runlist.active];
  87         fifo->runlist.active = !fifo->runlist.active;
  88
  89         for (i = 0, p = 0; i < 128; i++) {
  90                 struct gf100_fifo_chan *chan = (void *)fifo->base.channel[i];
  91                 if (chan && chan->state == RUNNING) {
  92                         nv_wo32(cur, p + 0, i);
  93                         nv_wo32(cur, p + 4, 0x00000004);
  94                         p += 8;
  95                 }
  96         }
  97         bar->flush(bar);
  98
  99         nvkm_wr32(device, 0x002270, cur->addr >> 12);
 100         nvkm_wr32(device, 0x002274, 0x01f00000 | (p >> 3));
 101
 102         if (wait_event_timeout(fifo->runlist.wait,
 103                                !(nvkm_rd32(device, 0x00227c) & 0x00100000),
 104                                msecs_to_jiffies(2000)) == 0)
 105                 nvkm_error(subdev, "runlist update timeout\n");
 106         mutex_unlock(&nv_subdev(fifo)->mutex);
 107 }
 108
 109 static int
 110 gf100_fifo_context_attach(struct nvkm_object *parent,
 111                           struct nvkm_object *object)
 112 {
 113         struct nvkm_bar *bar = nvkm_bar(parent);
 114         struct gf100_fifo_base *base = (void *)parent->parent;
 115         struct nvkm_engctx *ectx = (void *)object;
 116         u32 addr;
 117         int ret;
 118
 119         switch (nv_engidx(object->engine)) {
 120         case NVDEV_ENGINE_SW    : return 0;
 121         case NVDEV_ENGINE_GR    : addr = 0x0210; break;
 122         case NVDEV_ENGINE_CE0   : addr = 0x0230; break;
 123         case NVDEV_ENGINE_CE1   : addr = 0x0240; break;
 124         case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
 125         case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
 126         case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
 127         default:
 128                 return -EINVAL;
 129         }
 130
 131         if (!ectx->vma.node) {
 132                 ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 133                                          NV_MEM_ACCESS_RW, &ectx->vma);
 134                 if (ret)
 135                         return ret;
 136
 137                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 138         }
 139
 140         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 141         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 142         bar->flush(bar);
 143         return 0;
 144 }
 145
 146 static int
 147 gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend,
 148                           struct nvkm_object *object)
 149 {
 150         struct gf100_fifo *fifo = (void *)parent->engine;
 151         struct gf100_fifo_base *base = (void *)parent->parent;
 152         struct gf100_fifo_chan *chan = (void *)parent;
 153         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 154         struct nvkm_device *device = subdev->device;
 155         struct nvkm_bar *bar = device->bar;
 156         u32 addr;
 157
 158         switch (nv_engidx(object->engine)) {
 159         case NVDEV_ENGINE_SW    : return 0;
 160         case NVDEV_ENGINE_GR    : addr = 0x0210; break;
 161         case NVDEV_ENGINE_CE0   : addr = 0x0230; break;
 162         case NVDEV_ENGINE_CE1   : addr = 0x0240; break;
 163         case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
 164         case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
 165         case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
 166         default:
 167                 return -EINVAL;
 168         }
 169
 170         nvkm_wr32(device, 0x002634, chan->base.chid);
 171         if (nvkm_msec(device, 2000,
 172                 if (nvkm_rd32(device, 0x002634) == chan->base.chid)
 173                         break;
 174         ) < 0) {
 175                 nvkm_error(subdev, "channel %d [%s] kick timeout\n",
 176                            chan->base.chid, nvkm_client_name(chan));
 177                 if (suspend)
 178                         return -EBUSY;
 179         }
 180
 181         nv_wo32(base, addr + 0x00, 0x00000000);
 182         nv_wo32(base, addr + 0x04, 0x00000000);
 183         bar->flush(bar);
 184         return 0;
 185 }
 186
 187 static int
 188 gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 189                      struct nvkm_oclass *oclass, void *data, u32 size,
 190                      struct nvkm_object **pobject)
 191 {
 192         union {
 193                 struct nv50_channel_gpfifo_v0 v0;
 194         } *args = data;
 195         struct nvkm_bar *bar = nvkm_bar(parent);
 196         struct gf100_fifo *fifo = (void *)engine;
 197         struct gf100_fifo_base *base = (void *)parent;
 198         struct gf100_fifo_chan *chan;
 199         u64 usermem, ioffset, ilength;
 200         int ret, i;
 201
 202         nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
 203         if (nvif_unpack(args->v0, 0, 0, false)) {
 204                 nvif_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
 205                                    "ioffset %016llx ilength %08x\n",
 206                            args->v0.version, args->v0.pushbuf, args->v0.ioffset,
 207                            args->v0.ilength);
 208         } else
 209                 return ret;
 210
 211         ret = nvkm_fifo_channel_create(parent, engine, oclass, 1,
 212                                        fifo->user.bar.offset, 0x1000,
 213                                        args->v0.pushbuf,
 214                                        (1ULL << NVDEV_ENGINE_SW) |
 215                                        (1ULL << NVDEV_ENGINE_GR) |
 216                                        (1ULL << NVDEV_ENGINE_CE0) |
 217                                        (1ULL << NVDEV_ENGINE_CE1) |
 218                                        (1ULL << NVDEV_ENGINE_MSVLD) |
 219                                        (1ULL << NVDEV_ENGINE_MSPDEC) |
 220                                        (1ULL << NVDEV_ENGINE_MSPPP), &chan);
 221         *pobject = nv_object(chan);
 222         if (ret)
 223                 return ret;
 224
 225         args->v0.chid = chan->base.chid;
 226
 227         nv_parent(chan)->context_attach = gf100_fifo_context_attach;
 228         nv_parent(chan)->context_detach = gf100_fifo_context_detach;
 229
 230         usermem = chan->base.chid * 0x1000;
 231         ioffset = args->v0.ioffset;
 232         ilength = order_base_2(args->v0.ilength / 8);
 233
 234         for (i = 0; i < 0x1000; i += 4)
 235                 nv_wo32(fifo->user.mem, usermem + i, 0x00000000);
 236
 237         nv_wo32(base, 0x08, lower_32_bits(fifo->user.mem->addr + usermem));
 238         nv_wo32(base, 0x0c, upper_32_bits(fifo->user.mem->addr + usermem));
 239         nv_wo32(base, 0x10, 0x0000face);
 240         nv_wo32(base, 0x30, 0xfffff902);
 241         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 242         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 243         nv_wo32(base, 0x54, 0x00000002);
 244         nv_wo32(base, 0x84, 0x20400000);
 245         nv_wo32(base, 0x94, 0x30000001);
 246         nv_wo32(base, 0x9c, 0x00000100);
 247         nv_wo32(base, 0xa4, 0x1f1f1f1f);
 248         nv_wo32(base, 0xa8, 0x1f1f1f1f);
 249         nv_wo32(base, 0xac, 0x0000001f);
 250         nv_wo32(base, 0xb8, 0xf8000000);
 251         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 252         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 253         bar->flush(bar);
 254         return 0;
 255 }
 256
 257 static int
 258 gf100_fifo_chan_init(struct nvkm_object *object)
 259 {
 260         struct nvkm_gpuobj *base = nv_gpuobj(object->parent);
 261         struct gf100_fifo *fifo = (void *)object->engine;
 262         struct gf100_fifo_chan *chan = (void *)object;
 263         struct nvkm_device *device = fifo->base.engine.subdev.device;
 264         u32 chid = chan->base.chid;
 265         int ret;
 266
 267         ret = nvkm_fifo_channel_init(&chan->base);
 268         if (ret)
 269                 return ret;
 270
 271         nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
 272
 273         if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
 274                 nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001);
 275                 gf100_fifo_runlist_update(fifo);
 276         }
 277
 278         return 0;
 279 }
 280
 281 static void gf100_fifo_intr_engine(struct gf100_fifo *fifo);
 282
 283 static int
 284 gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend)
 285 {
 286         struct gf100_fifo *fifo = (void *)object->engine;
 287         struct gf100_fifo_chan *chan = (void *)object;
 288         struct nvkm_device *device = fifo->base.engine.subdev.device;
 289         u32 chid = chan->base.chid;
 290
 291         if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
 292                 nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
 293                 gf100_fifo_runlist_update(fifo);
 294         }
 295
 296         gf100_fifo_intr_engine(fifo);
 297
 298         nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000);
 299         return nvkm_fifo_channel_fini(&chan->base, suspend);
 300 }
 301
 302 static struct nvkm_ofuncs
 303 gf100_fifo_ofuncs = {
 304         .ctor = gf100_fifo_chan_ctor,
 305         .dtor = _nvkm_fifo_channel_dtor,
 306         .init = gf100_fifo_chan_init,
 307         .fini = gf100_fifo_chan_fini,
 308         .map  = _nvkm_fifo_channel_map,
 309         .rd32 = _nvkm_fifo_channel_rd32,
 310         .wr32 = _nvkm_fifo_channel_wr32,
 311         .ntfy = _nvkm_fifo_channel_ntfy
 312 };
 313
 314 static struct nvkm_oclass
 315 gf100_fifo_sclass[] = {
 316         { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs },
 317         {}
 318 };
 319
 320 /*******************************************************************************
 321  * FIFO context - instmem heap and vm setup
 322  ******************************************************************************/
 323
 324 static int
 325 gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 326                         struct nvkm_oclass *oclass, void *data, u32 size,
 327                         struct nvkm_object **pobject)
 328 {
 329         struct gf100_fifo_base *base;
 330         int ret;
 331
 332         ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 333                                        0x1000, NVOBJ_FLAG_ZERO_ALLOC |
 334                                        NVOBJ_FLAG_HEAP, &base);
 335         *pobject = nv_object(base);
 336         if (ret)
 337                 return ret;
 338
 339         ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
 340                               &base->pgd);
 341         if (ret)
 342                 return ret;
 343
 344         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 345         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 346         nv_wo32(base, 0x0208, 0xffffffff);
 347         nv_wo32(base, 0x020c, 0x000000ff);
 348
 349         ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
 350         if (ret)
 351                 return ret;
 352
 353         return 0;
 354 }
 355
 356 static void
 357 gf100_fifo_context_dtor(struct nvkm_object *object)
 358 {
 359         struct gf100_fifo_base *base = (void *)object;
 360         nvkm_vm_ref(NULL, &base->vm, base->pgd);
 361         nvkm_gpuobj_ref(NULL, &base->pgd);
 362         nvkm_fifo_context_destroy(&base->base);
 363 }
 364
 365 static struct nvkm_oclass
 366 gf100_fifo_cclass = {
 367         .handle = NV_ENGCTX(FIFO, 0xc0),
 368         .ofuncs = &(struct nvkm_ofuncs) {
 369                 .ctor = gf100_fifo_context_ctor,
 370                 .dtor = gf100_fifo_context_dtor,
 371                 .init = _nvkm_fifo_context_init,
 372                 .fini = _nvkm_fifo_context_fini,
 373                 .rd32 = _nvkm_fifo_context_rd32,
 374                 .wr32 = _nvkm_fifo_context_wr32,
 375         },
 376 };
 377
 378 /*******************************************************************************
 379  * PFIFO engine
 380  ******************************************************************************/
 381
 382 static inline int
 383 gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
 384 {
 385         switch (engn) {
 386         case NVDEV_ENGINE_GR    : engn = 0; break;
 387         case NVDEV_ENGINE_MSVLD : engn = 1; break;
 388         case NVDEV_ENGINE_MSPPP : engn = 2; break;
 389         case NVDEV_ENGINE_MSPDEC: engn = 3; break;
 390         case NVDEV_ENGINE_CE0   : engn = 4; break;
 391         case NVDEV_ENGINE_CE1   : engn = 5; break;
 392         default:
 393                 return -1;
 394         }
 395
 396         return engn;
 397 }
 398
 399 static inline struct nvkm_engine *
 400 gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
 401 {
 402         switch (engn) {
 403         case 0: engn = NVDEV_ENGINE_GR; break;
 404         case 1: engn = NVDEV_ENGINE_MSVLD; break;
 405         case 2: engn = NVDEV_ENGINE_MSPPP; break;
 406         case 3: engn = NVDEV_ENGINE_MSPDEC; break;
 407         case 4: engn = NVDEV_ENGINE_CE0; break;
 408         case 5: engn = NVDEV_ENGINE_CE1; break;
 409         default:
 410                 return NULL;
 411         }
 412
 413         return nvkm_engine(fifo, engn);
 414 }
 415
 416 static void
 417 gf100_fifo_recover_work(struct work_struct *work)
 418 {
 419         struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault);
 420         struct nvkm_device *device = fifo->base.engine.subdev.device;
 421         struct nvkm_object *engine;
 422         unsigned long flags;
 423         u32 engn, engm = 0;
 424         u64 mask, todo;
 425
 426         spin_lock_irqsave(&fifo->base.lock, flags);
 427         mask = fifo->mask;
 428         fifo->mask = 0ULL;
 429         spin_unlock_irqrestore(&fifo->base.lock, flags);
 430
 431         for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
 432                 engm |= 1 << gf100_fifo_engidx(fifo, engn);
 433         nvkm_mask(device, 0x002630, engm, engm);
 434
 435         for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
 436                 if ((engine = (void *)nvkm_engine(fifo, engn))) {
 437                         nv_ofuncs(engine)->fini(engine, false);
 438                         WARN_ON(nv_ofuncs(engine)->init(engine));
 439                 }
 440         }
 441
 442         gf100_fifo_runlist_update(fifo);
 443         nvkm_wr32(device, 0x00262c, engm);
 444         nvkm_mask(device, 0x002630, engm, 0x00000000);
 445 }
 446
 447 static void
 448 gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
 449                    struct gf100_fifo_chan *chan)
 450 {
 451         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 452         struct nvkm_device *device = subdev->device;
 453         u32 chid = chan->base.chid;
 454         unsigned long flags;
 455
 456         nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
 457                    engine->subdev.name, chid);
 458
 459         nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
 460         chan->state = KILLED;
 461
 462         spin_lock_irqsave(&fifo->base.lock, flags);
 463         fifo->mask |= 1ULL << nv_engidx(engine);
 464         spin_unlock_irqrestore(&fifo->base.lock, flags);
 465         schedule_work(&fifo->fault);
 466 }
 467
 468 static int
 469 gf100_fifo_swmthd(struct gf100_fifo *fifo, u32 chid, u32 mthd, u32 data)
 470 {
 471         struct gf100_fifo_chan *chan = NULL;
 472         struct nvkm_handle *bind;
 473         unsigned long flags;
 474         int ret = -EINVAL;
 475
 476         spin_lock_irqsave(&fifo->base.lock, flags);
 477         if (likely(chid >= fifo->base.min && chid <= fifo->base.max))
 478                 chan = (void *)fifo->base.channel[chid];
 479         if (unlikely(!chan))
 480                 goto out;
 481
 482         bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e);
 483         if (likely(bind)) {
 484                 if (!mthd || !nv_call(bind->object, mthd, data))
 485                         ret = 0;
 486                 nvkm_namedb_put(bind);
 487         }
 488
 489 out:
 490         spin_unlock_irqrestore(&fifo->base.lock, flags);
 491         return ret;
 492 }
 493
 494 static const struct nvkm_enum
 495 gf100_fifo_sched_reason[] = {
 496         { 0x0a, "CTXSW_TIMEOUT" },
 497         {}
 498 };
 499
 500 static void
 501 gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo)
 502 {
 503         struct nvkm_device *device = fifo->base.engine.subdev.device;
 504         struct nvkm_engine *engine;
 505         struct gf100_fifo_chan *chan;
 506         u32 engn;
 507
 508         for (engn = 0; engn < 6; engn++) {
 509                 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
 510                 u32 busy = (stat & 0x80000000);
 511                 u32 save = (stat & 0x00100000); /* maybe? */
 512                 u32 unk0 = (stat & 0x00040000);
 513                 u32 unk1 = (stat & 0x00001000);
 514                 u32 chid = (stat & 0x0000007f);
 515                 (void)save;
 516
 517                 if (busy && unk0 && unk1) {
 518                         if (!(chan = (void *)fifo->base.channel[chid]))
 519                                 continue;
 520                         if (!(engine = gf100_fifo_engine(fifo, engn)))
 521                                 continue;
 522                         gf100_fifo_recover(fifo, engine, chan);
 523                 }
 524         }
 525 }
 526
 527 static void
 528 gf100_fifo_intr_sched(struct gf100_fifo *fifo)
 529 {
 530         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 531         struct nvkm_device *device = subdev->device;
 532         u32 intr = nvkm_rd32(device, 0x00254c);
 533         u32 code = intr & 0x000000ff;
 534         const struct nvkm_enum *en;
 535
 536         en = nvkm_enum_find(gf100_fifo_sched_reason, code);
 537
 538         nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : "");
 539
 540         switch (code) {
 541         case 0x0a:
 542                 gf100_fifo_intr_sched_ctxsw(fifo);
 543                 break;
 544         default:
 545                 break;
 546         }
 547 }
 548
 549 static const struct nvkm_enum
 550 gf100_fifo_fault_engine[] = {
 551         { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
 552         { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
 553         { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
 554         { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
 555         { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
 556         { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
 557         { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
 558         { 0x13, "PCOUNTER" },
 559         { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
 560         { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
 561         { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 },
 562         { 0x17, "PDAEMON" },
 563         {}
 564 };
 565
 566 static const struct nvkm_enum
 567 gf100_fifo_fault_reason[] = {
 568         { 0x00, "PT_NOT_PRESENT" },
 569         { 0x01, "PT_TOO_SHORT" },
 570         { 0x02, "PAGE_NOT_PRESENT" },
 571         { 0x03, "VM_LIMIT_EXCEEDED" },
 572         { 0x04, "NO_CHANNEL" },
 573         { 0x05, "PAGE_SYSTEM_ONLY" },
 574         { 0x06, "PAGE_READ_ONLY" },
 575         { 0x0a, "COMPRESSED_SYSRAM" },
 576         { 0x0c, "INVALID_STORAGE_TYPE" },
 577         {}
 578 };
 579
 580 static const struct nvkm_enum
 581 gf100_fifo_fault_hubclient[] = {
 582         { 0x01, "PCOPY0" },
 583         { 0x02, "PCOPY1" },
 584         { 0x04, "DISPATCH" },
 585         { 0x05, "CTXCTL" },
 586         { 0x06, "PFIFO" },
 587         { 0x07, "BAR_READ" },
 588         { 0x08, "BAR_WRITE" },
 589         { 0x0b, "PVP" },
 590         { 0x0c, "PMSPPP" },
 591         { 0x0d, "PMSVLD" },
 592         { 0x11, "PCOUNTER" },
 593         { 0x12, "PDAEMON" },
 594         { 0x14, "CCACHE" },
 595         { 0x15, "CCACHE_POST" },
 596         {}
 597 };
 598
 599 static const struct nvkm_enum
 600 gf100_fifo_fault_gpcclient[] = {
 601         { 0x01, "TEX" },
 602         { 0x0c, "ESETUP" },
 603         { 0x0e, "CTXCTL" },
 604         { 0x0f, "PROP" },
 605         {}
 606 };
 607
 608 static void
 609 gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit)
 610 {
 611         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 612         struct nvkm_device *device = subdev->device;
 613         u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
 614         u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
 615         u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
 616         u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));
 617         u32 gpc    = (stat & 0x1f000000) >> 24;
 618         u32 client = (stat & 0x00001f00) >> 8;
 619         u32 write  = (stat & 0x00000080);
 620         u32 hub    = (stat & 0x00000040);
 621         u32 reason = (stat & 0x0000000f);
 622         struct nvkm_object *engctx = NULL, *object;
 623         struct nvkm_engine *engine = NULL;
 624         const struct nvkm_enum *er, *eu, *ec;
 625         char gpcid[8] = "";
 626
 627         er = nvkm_enum_find(gf100_fifo_fault_reason, reason);
 628         eu = nvkm_enum_find(gf100_fifo_fault_engine, unit);
 629         if (hub) {
 630                 ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client);
 631         } else {
 632                 ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client);
 633                 snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc);
 634         }
 635
 636         if (eu) {
 637                 switch (eu->data2) {
 638                 case NVDEV_SUBDEV_BAR:
 639                         nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
 640                         break;
 641                 case NVDEV_SUBDEV_INSTMEM:
 642                         nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
 643                         break;
 644                 case NVDEV_ENGINE_IFB:
 645                         nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
 646                         break;
 647                 default:
 648                         engine = nvkm_engine(fifo, eu->data2);
 649                         if (engine)
 650                                 engctx = nvkm_engctx_get(engine, inst);
 651                         break;
 652                 }
 653         }
 654
 655         nvkm_error(subdev,
 656                    "%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
 657                    "reason %02x [%s] on channel %d [%010llx %s]\n",
 658                    write ? "write" : "read", (u64)vahi << 32 | valo,
 659                    unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "",
 660                    reason, er ? er->name : "", -1, (u64)inst << 12,
 661                    nvkm_client_name(engctx));
 662
 663         object = engctx;
 664         while (object) {
 665                 switch (nv_mclass(object)) {
 666                 case FERMI_CHANNEL_GPFIFO:
 667                         gf100_fifo_recover(fifo, engine, (void *)object);
 668                         break;
 669                 }
 670                 object = object->parent;
 671         }
 672
 673         nvkm_engctx_put(engctx);
 674 }
 675
 676 static const struct nvkm_bitfield
 677 gf100_fifo_pbdma_intr[] = {
 678 /*      { 0x00008000, "" }      seen with null ib push */
 679         { 0x00200000, "ILLEGAL_MTHD" },
 680         { 0x00800000, "EMPTY_SUBC" },
 681         {}
 682 };
 683
 684 static void
 685 gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit)
 686 {
 687         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 688         struct nvkm_device *device = subdev->device;
 689         u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000));
 690         u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
 691         u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
 692         u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f;
 693         u32 subc = (addr & 0x00070000) >> 16;
 694         u32 mthd = (addr & 0x00003ffc);
 695         u32 show= stat;
 696         char msg[128];
 697
 698         if (stat & 0x00800000) {
 699                 if (!gf100_fifo_swmthd(fifo, chid, mthd, data))
 700                         show &= ~0x00800000;
 701         }
 702
 703         if (show) {
 704                 nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show);
 705                 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%s] subc %d "
 706                                    "mthd %04x data %08x\n",
 707                            unit, show, msg, chid,
 708                            nvkm_client_name_for_fifo_chid(&fifo->base, chid),
 709                            subc, mthd, data);
 710         }
 711
 712         nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
 713         nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
 714 }
 715
 716 static void
 717 gf100_fifo_intr_runlist(struct gf100_fifo *fifo)
 718 {
 719         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 720         struct nvkm_device *device = subdev->device;
 721         u32 intr = nvkm_rd32(device, 0x002a00);
 722
 723         if (intr & 0x10000000) {
 724                 wake_up(&fifo->runlist.wait);
 725                 nvkm_wr32(device, 0x002a00, 0x10000000);
 726                 intr &= ~0x10000000;
 727         }
 728
 729         if (intr) {
 730                 nvkm_error(subdev, "RUNLIST %08x\n", intr);
 731                 nvkm_wr32(device, 0x002a00, intr);
 732         }
 733 }
 734
 735 static void
 736 gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn)
 737 {
 738         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 739         struct nvkm_device *device = subdev->device;
 740         u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04));
 741         u32 inte = nvkm_rd32(device, 0x002628);
 742         u32 unkn;
 743
 744         nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr);
 745
 746         for (unkn = 0; unkn < 8; unkn++) {
 747                 u32 ints = (intr >> (unkn * 0x04)) & inte;
 748                 if (ints & 0x1) {
 749                         nvkm_fifo_uevent(&fifo->base);
 750                         ints &= ~1;
 751                 }
 752                 if (ints) {
 753                         nvkm_error(subdev, "ENGINE %d %d %01x",
 754                                    engn, unkn, ints);
 755                         nvkm_mask(device, 0x002628, ints, 0);
 756                 }
 757         }
 758 }
 759
 760 static void
 761 gf100_fifo_intr_engine(struct gf100_fifo *fifo)
 762 {
 763         struct nvkm_device *device = fifo->base.engine.subdev.device;
 764         u32 mask = nvkm_rd32(device, 0x0025a4);
 765         while (mask) {
 766                 u32 unit = __ffs(mask);
 767                 gf100_fifo_intr_engine_unit(fifo, unit);
 768                 mask &= ~(1 << unit);
 769         }
 770 }
 771
 772 static void
 773 gf100_fifo_intr(struct nvkm_subdev *subdev)
 774 {
 775         struct gf100_fifo *fifo = (void *)subdev;
 776         struct nvkm_device *device = fifo->base.engine.subdev.device;
 777         u32 mask = nvkm_rd32(device, 0x002140);
 778         u32 stat = nvkm_rd32(device, 0x002100) & mask;
 779
 780         if (stat & 0x00000001) {
 781                 u32 intr = nvkm_rd32(device, 0x00252c);
 782                 nvkm_warn(subdev, "INTR 00000001: %08x\n", intr);
 783                 nvkm_wr32(device, 0x002100, 0x00000001);
 784                 stat &= ~0x00000001;
 785         }
 786
 787         if (stat & 0x00000100) {
 788                 gf100_fifo_intr_sched(fifo);
 789                 nvkm_wr32(device, 0x002100, 0x00000100);
 790                 stat &= ~0x00000100;
 791         }
 792
 793         if (stat & 0x00010000) {
 794                 u32 intr = nvkm_rd32(device, 0x00256c);
 795                 nvkm_warn(subdev, "INTR 00010000: %08x\n", intr);
 796                 nvkm_wr32(device, 0x002100, 0x00010000);
 797                 stat &= ~0x00010000;
 798         }
 799
 800         if (stat & 0x01000000) {
 801                 u32 intr = nvkm_rd32(device, 0x00258c);
 802                 nvkm_warn(subdev, "INTR 01000000: %08x\n", intr);
 803                 nvkm_wr32(device, 0x002100, 0x01000000);
 804                 stat &= ~0x01000000;
 805         }
 806
 807         if (stat & 0x10000000) {
 808                 u32 mask = nvkm_rd32(device, 0x00259c);
 809                 while (mask) {
 810                         u32 unit = __ffs(mask);
 811                         gf100_fifo_intr_fault(fifo, unit);
 812                         nvkm_wr32(device, 0x00259c, (1 << unit));
 813                         mask &= ~(1 << unit);
 814                 }
 815                 stat &= ~0x10000000;
 816         }
 817
 818         if (stat & 0x20000000) {
 819                 u32 mask = nvkm_rd32(device, 0x0025a0);
 820                 while (mask) {
 821                         u32 unit = __ffs(mask);
 822                         gf100_fifo_intr_pbdma(fifo, unit);
 823                         nvkm_wr32(device, 0x0025a0, (1 << unit));
 824                         mask &= ~(1 << unit);
 825                 }
 826                 stat &= ~0x20000000;
 827         }
 828
 829         if (stat & 0x40000000) {
 830                 gf100_fifo_intr_runlist(fifo);
 831                 stat &= ~0x40000000;
 832         }
 833
 834         if (stat & 0x80000000) {
 835                 gf100_fifo_intr_engine(fifo);
 836                 stat &= ~0x80000000;
 837         }
 838
 839         if (stat) {
 840                 nvkm_error(subdev, "INTR %08x\n", stat);
 841                 nvkm_mask(device, 0x002140, stat, 0x00000000);
 842                 nvkm_wr32(device, 0x002100, stat);
 843         }
 844 }
 845
 846 static void
 847 gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index)
 848 {
 849         struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
 850         struct nvkm_device *device = fifo->engine.subdev.device;
 851         nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
 852 }
 853
 854 static void
 855 gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
 856 {
 857         struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
 858         struct nvkm_device *device = fifo->engine.subdev.device;
 859         nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
 860 }
 861
 862 static const struct nvkm_event_func
 863 gf100_fifo_uevent_func = {
 864         .ctor = nvkm_fifo_uevent_ctor,
 865         .init = gf100_fifo_uevent_init,
 866         .fini = gf100_fifo_uevent_fini,
 867 };
 868
 869 static int
 870 gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 871                 struct nvkm_oclass *oclass, void *data, u32 size,
 872                 struct nvkm_object **pobject)
 873 {
 874         struct gf100_fifo *fifo;
 875         int ret;
 876
 877         ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo);
 878         *pobject = nv_object(fifo);
 879         if (ret)
 880                 return ret;
 881
 882         INIT_WORK(&fifo->fault, gf100_fifo_recover_work);
 883
 884         ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0,
 885                               &fifo->runlist.mem[0]);
 886         if (ret)
 887                 return ret;
 888
 889         ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0,
 890                               &fifo->runlist.mem[1]);
 891         if (ret)
 892                 return ret;
 893
 894         init_waitqueue_head(&fifo->runlist.wait);
 895
 896         ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 0x1000, 0x1000, 0,
 897                               &fifo->user.mem);
 898         if (ret)
 899                 return ret;
 900
 901         ret = nvkm_gpuobj_map(fifo->user.mem, NV_MEM_ACCESS_RW,
 902                               &fifo->user.bar);
 903         if (ret)
 904                 return ret;
 905
 906         ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent);
 907         if (ret)
 908                 return ret;
 909
 910         nv_subdev(fifo)->unit = 0x00000100;
 911         nv_subdev(fifo)->intr = gf100_fifo_intr;
 912         nv_engine(fifo)->cclass = &gf100_fifo_cclass;
 913         nv_engine(fifo)->sclass = gf100_fifo_sclass;
 914         return 0;
 915 }
 916
 917 static void
 918 gf100_fifo_dtor(struct nvkm_object *object)
 919 {
 920         struct gf100_fifo *fifo = (void *)object;
 921
 922         nvkm_gpuobj_unmap(&fifo->user.bar);
 923         nvkm_gpuobj_ref(NULL, &fifo->user.mem);
 924         nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[0]);
 925         nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[1]);
 926
 927         nvkm_fifo_destroy(&fifo->base);
 928 }
 929
 930 static int
 931 gf100_fifo_init(struct nvkm_object *object)
 932 {
 933         struct gf100_fifo *fifo = (void *)object;
 934         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 935         struct nvkm_device *device = subdev->device;
 936         int ret, i;
 937
 938         ret = nvkm_fifo_init(&fifo->base);
 939         if (ret)
 940                 return ret;
 941
 942         nvkm_wr32(device, 0x000204, 0xffffffff);
 943         nvkm_wr32(device, 0x002204, 0xffffffff);
 944
 945         fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204));
 946         nvkm_debug(subdev, "%d PBDMA unit(s)\n", fifo->spoon_nr);
 947
 948         /* assign engines to PBDMAs */
 949         if (fifo->spoon_nr >= 3) {
 950                 nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */
 951                 nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */
 952                 nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */
 953                 nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */
 954                 nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */
 955                 nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */
 956         }
 957
 958         /* PBDMA[n] */
 959         for (i = 0; i < fifo->spoon_nr; i++) {
 960                 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 961                 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 962                 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 963         }
 964
 965         nvkm_mask(device, 0x002200, 0x00000001, 0x00000001);
 966         nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12);
 967
 968         nvkm_wr32(device, 0x002100, 0xffffffff);
 969         nvkm_wr32(device, 0x002140, 0x7fffffff);
 970         nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
 971         return 0;
 972 }
 973
 974 struct nvkm_oclass *
 975 gf100_fifo_oclass = &(struct nvkm_oclass) {
 976         .handle = NV_ENGINE(FIFO, 0xc0),
 977         .ofuncs = &(struct nvkm_ofuncs) {
 978                 .ctor = gf100_fifo_ctor,
 979                 .dtor = gf100_fifo_dtor,
 980                 .init = gf100_fifo_init,
 981                 .fini = _nvkm_fifo_fini,
 982         },
 983 };