drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv04.h"
  25
  26 #include <core/client.h>
  27 #include <core/engctx.h>
  28 #include <core/ramht.h>
  29 #include <subdev/fb.h>
  30 #include <subdev/instmem/nv04.h>
  31
  32 #include <nvif/class.h>
  33 #include <nvif/unpack.h>
  34
  35 static struct ramfc_desc
  36 nv40_ramfc[] = {
  37         { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
  38         { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
  39         { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
  40         { 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
  41         { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
  42         { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_STATE },
  43         { 28,  0, 0x18,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
  44         {  2, 28, 0x18, 28, 0x002058 },
  45         { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_ENGINE },
  46         { 32,  0, 0x20,  0, NV04_PFIFO_CACHE1_PULL1 },
  47         { 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
  48         { 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
  49         { 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
  50         { 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
  51         { 32,  0, 0x34,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
  52         { 32,  0, 0x38,  0, NV40_PFIFO_GRCTX_INSTANCE },
  53         { 17,  0, 0x3c,  0, NV04_PFIFO_DMA_TIMESLICE },
  54         { 32,  0, 0x40,  0, 0x0032e4 },
  55         { 32,  0, 0x44,  0, 0x0032e8 },
  56         { 32,  0, 0x4c,  0, 0x002088 },
  57         { 32,  0, 0x50,  0, 0x003300 },
  58         { 32,  0, 0x54,  0, 0x00330c },
  59         {}
  60 };
  61
  62 /*******************************************************************************
  63  * FIFO channel objects
  64  ******************************************************************************/
  65
  66 static int
  67 nv40_fifo_object_attach(struct nvkm_object *parent,
  68                         struct nvkm_object *object, u32 handle)
  69 {
  70         struct nv04_fifo *fifo = (void *)parent->engine;
  71         struct nv04_fifo_chan *chan = (void *)parent;
  72         u32 context, chid = chan->base.chid;
  73         int ret;
  74
  75         if (nv_iclass(object, NV_GPUOBJ_CLASS))
  76                 context = nv_gpuobj(object)->addr >> 4;
  77         else
  78                 context = 0x00000004; /* just non-zero */
  79
  80         switch (nv_engidx(object->engine)) {
  81         case NVDEV_ENGINE_DMAOBJ:
  82         case NVDEV_ENGINE_SW:
  83                 context |= 0x00000000;
  84                 break;
  85         case NVDEV_ENGINE_GR:
  86                 context |= 0x00100000;
  87                 break;
  88         case NVDEV_ENGINE_MPEG:
  89                 context |= 0x00200000;
  90                 break;
  91         default:
  92                 return -EINVAL;
  93         }
  94
  95         context |= chid << 23;
  96
  97         mutex_lock(&nv_subdev(fifo)->mutex);
  98         ret = nvkm_ramht_insert(fifo->ramht, chid, handle, context);
  99         mutex_unlock(&nv_subdev(fifo)->mutex);
 100         return ret;
 101 }
 102
 103 static int
 104 nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx)
 105 {
 106         struct nv04_fifo *fifo = (void *)parent->engine;
 107         struct nv04_fifo_chan *chan = (void *)parent;
 108         struct nvkm_device *device = fifo->base.engine.subdev.device;
 109         unsigned long flags;
 110         u32 reg, ctx;
 111
 112         switch (nv_engidx(engctx->engine)) {
 113         case NVDEV_ENGINE_SW:
 114                 return 0;
 115         case NVDEV_ENGINE_GR:
 116                 reg = 0x32e0;
 117                 ctx = 0x38;
 118                 break;
 119         case NVDEV_ENGINE_MPEG:
 120                 reg = 0x330c;
 121                 ctx = 0x54;
 122                 break;
 123         default:
 124                 return -EINVAL;
 125         }
 126
 127         spin_lock_irqsave(&fifo->base.lock, flags);
 128         nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4;
 129         nvkm_mask(device, 0x002500, 0x00000001, 0x00000000);
 130
 131         if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid)
 132                 nvkm_wr32(device, reg, nv_engctx(engctx)->addr);
 133         nv_wo32(fifo->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr);
 134
 135         nvkm_mask(device, 0x002500, 0x00000001, 0x00000001);
 136         spin_unlock_irqrestore(&fifo->base.lock, flags);
 137         return 0;
 138 }
 139
 140 static int
 141 nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend,
 142                          struct nvkm_object *engctx)
 143 {
 144         struct nv04_fifo *fifo = (void *)parent->engine;
 145         struct nv04_fifo_chan *chan = (void *)parent;
 146         struct nvkm_device *device = fifo->base.engine.subdev.device;
 147         unsigned long flags;
 148         u32 reg, ctx;
 149
 150         switch (nv_engidx(engctx->engine)) {
 151         case NVDEV_ENGINE_SW:
 152                 return 0;
 153         case NVDEV_ENGINE_GR:
 154                 reg = 0x32e0;
 155                 ctx = 0x38;
 156                 break;
 157         case NVDEV_ENGINE_MPEG:
 158                 reg = 0x330c;
 159                 ctx = 0x54;
 160                 break;
 161         default:
 162                 return -EINVAL;
 163         }
 164
 165         spin_lock_irqsave(&fifo->base.lock, flags);
 166         nvkm_mask(device, 0x002500, 0x00000001, 0x00000000);
 167
 168         if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid)
 169                 nvkm_wr32(device, reg, 0x00000000);
 170         nv_wo32(fifo->ramfc, chan->ramfc + ctx, 0x00000000);
 171
 172         nvkm_mask(device, 0x002500, 0x00000001, 0x00000001);
 173         spin_unlock_irqrestore(&fifo->base.lock, flags);
 174         return 0;
 175 }
 176
 177 static int
 178 nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 179                     struct nvkm_oclass *oclass, void *data, u32 size,
 180                     struct nvkm_object **pobject)
 181 {
 182         union {
 183                 struct nv03_channel_dma_v0 v0;
 184         } *args = data;
 185         struct nv04_fifo *fifo = (void *)engine;
 186         struct nv04_fifo_chan *chan;
 187         int ret;
 188
 189         nvif_ioctl(parent, "create channel dma size %d\n", size);
 190         if (nvif_unpack(args->v0, 0, 0, false)) {
 191                 nvif_ioctl(parent, "create channel dma vers %d pushbuf %08x "
 192                                    "offset %016llx\n", args->v0.version,
 193                            args->v0.pushbuf, args->v0.offset);
 194         } else
 195                 return ret;
 196
 197         ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 198                                        0x1000, args->v0.pushbuf,
 199                                        (1ULL << NVDEV_ENGINE_DMAOBJ) |
 200                                        (1ULL << NVDEV_ENGINE_SW) |
 201                                        (1ULL << NVDEV_ENGINE_GR) |
 202                                        (1ULL << NVDEV_ENGINE_MPEG), &chan);
 203         *pobject = nv_object(chan);
 204         if (ret)
 205                 return ret;
 206
 207         args->v0.chid = chan->base.chid;
 208
 209         nv_parent(chan)->context_attach = nv40_fifo_context_attach;
 210         nv_parent(chan)->context_detach = nv40_fifo_context_detach;
 211         nv_parent(chan)->object_attach = nv40_fifo_object_attach;
 212         nv_parent(chan)->object_detach = nv04_fifo_object_detach;
 213         chan->ramfc = chan->base.chid * 128;
 214
 215         nv_wo32(fifo->ramfc, chan->ramfc + 0x00, args->v0.offset);
 216         nv_wo32(fifo->ramfc, chan->ramfc + 0x04, args->v0.offset);
 217         nv_wo32(fifo->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
 218         nv_wo32(fifo->ramfc, chan->ramfc + 0x18, 0x30000000 |
 219                              NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 220                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 221 #ifdef __BIG_ENDIAN
 222                              NV_PFIFO_CACHE1_BIG_ENDIAN |
 223 #endif
 224                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
 225         nv_wo32(fifo->ramfc, chan->ramfc + 0x3c, 0x0001ffff);
 226         return 0;
 227 }
 228
 229 static struct nvkm_ofuncs
 230 nv40_fifo_ofuncs = {
 231         .ctor = nv40_fifo_chan_ctor,
 232         .dtor = nv04_fifo_chan_dtor,
 233         .init = nv04_fifo_chan_init,
 234         .fini = nv04_fifo_chan_fini,
 235         .map  = _nvkm_fifo_channel_map,
 236         .rd32 = _nvkm_fifo_channel_rd32,
 237         .wr32 = _nvkm_fifo_channel_wr32,
 238         .ntfy = _nvkm_fifo_channel_ntfy
 239 };
 240
 241 static struct nvkm_oclass
 242 nv40_fifo_sclass[] = {
 243         { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs },
 244         {}
 245 };
 246
 247 /*******************************************************************************
 248  * FIFO context - basically just the instmem reserved for the channel
 249  ******************************************************************************/
 250
 251 static struct nvkm_oclass
 252 nv40_fifo_cclass = {
 253         .handle = NV_ENGCTX(FIFO, 0x40),
 254         .ofuncs = &(struct nvkm_ofuncs) {
 255                 .ctor = nv04_fifo_context_ctor,
 256                 .dtor = _nvkm_fifo_context_dtor,
 257                 .init = _nvkm_fifo_context_init,
 258                 .fini = _nvkm_fifo_context_fini,
 259                 .rd32 = _nvkm_fifo_context_rd32,
 260                 .wr32 = _nvkm_fifo_context_wr32,
 261         },
 262 };
 263
 264 /*******************************************************************************
 265  * PFIFO engine
 266  ******************************************************************************/
 267
 268 static int
 269 nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 270                struct nvkm_oclass *oclass, void *data, u32 size,
 271                struct nvkm_object **pobject)
 272 {
 273         struct nv04_instmem *imem = nv04_instmem(parent);
 274         struct nv04_fifo *fifo;
 275         int ret;
 276
 277         ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo);
 278         *pobject = nv_object(fifo);
 279         if (ret)
 280                 return ret;
 281
 282         nvkm_ramht_ref(imem->ramht, &fifo->ramht);
 283         nvkm_gpuobj_ref(imem->ramro, &fifo->ramro);
 284         nvkm_gpuobj_ref(imem->ramfc, &fifo->ramfc);
 285
 286         nv_subdev(fifo)->unit = 0x00000100;
 287         nv_subdev(fifo)->intr = nv04_fifo_intr;
 288         nv_engine(fifo)->cclass = &nv40_fifo_cclass;
 289         nv_engine(fifo)->sclass = nv40_fifo_sclass;
 290         fifo->base.pause = nv04_fifo_pause;
 291         fifo->base.start = nv04_fifo_start;
 292         fifo->ramfc_desc = nv40_ramfc;
 293         return 0;
 294 }
 295
 296 static int
 297 nv40_fifo_init(struct nvkm_object *object)
 298 {
 299         struct nv04_fifo *fifo = (void *)object;
 300         struct nvkm_device *device = fifo->base.engine.subdev.device;
 301         struct nvkm_fb *fb = device->fb;
 302         int ret;
 303
 304         ret = nvkm_fifo_init(&fifo->base);
 305         if (ret)
 306                 return ret;
 307
 308         nvkm_wr32(device, 0x002040, 0x000000ff);
 309         nvkm_wr32(device, 0x002044, 0x2101ffff);
 310         nvkm_wr32(device, 0x002058, 0x00000001);
 311
 312         nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 313                                        ((fifo->ramht->bits - 9) << 16) |
 314                                         (fifo->ramht->gpuobj.addr >> 8));
 315         nvkm_wr32(device, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8);
 316
 317         switch (nv_device(fifo)->chipset) {
 318         case 0x47:
 319         case 0x49:
 320         case 0x4b:
 321                 nvkm_wr32(device, 0x002230, 0x00000001);
 322         case 0x40:
 323         case 0x41:
 324         case 0x42:
 325         case 0x43:
 326         case 0x45:
 327         case 0x48:
 328                 nvkm_wr32(device, 0x002220, 0x00030002);
 329                 break;
 330         default:
 331                 nvkm_wr32(device, 0x002230, 0x00000000);
 332                 nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 +
 333                                          fifo->ramfc->addr) >> 16) |
 334                                         0x00030000);
 335                 break;
 336         }
 337
 338         nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max);
 339
 340         nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
 341         nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
 342
 343         nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
 344         nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
 345         nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
 346         return 0;
 347 }
 348
 349 struct nvkm_oclass *
 350 nv40_fifo_oclass = &(struct nvkm_oclass) {
 351         .handle = NV_ENGINE(FIFO, 0x40),
 352         .ofuncs = &(struct nvkm_ofuncs) {
 353                 .ctor = nv40_fifo_ctor,
 354                 .dtor = nv04_fifo_dtor,
 355                 .init = nv40_fifo_init,
 356                 .fini = _nvkm_fifo_fini,
 357         },
 358 };