drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "gf100.h"
  25 #include "ctxgf100.h"
  26
  27 #include <subdev/pmu.h>
  28
  29 #include <nvif/class.h>
  30
  31 /*******************************************************************************
  32  * PGRAPH register lists
  33  ******************************************************************************/
  34
  35 const struct gf100_gr_init
  36 gk104_gr_init_main_0[] = {
  37         { 0x400080,   1, 0x04, 0x003083c2 },
  38         { 0x400088,   1, 0x04, 0x0001ffe7 },
  39         { 0x40008c,   1, 0x04, 0x00000000 },
  40         { 0x400090,   1, 0x04, 0x00000030 },
  41         { 0x40013c,   1, 0x04, 0x003901f7 },
  42         { 0x400140,   1, 0x04, 0x00000100 },
  43         { 0x400144,   1, 0x04, 0x00000000 },
  44         { 0x400148,   1, 0x04, 0x00000110 },
  45         { 0x400138,   1, 0x04, 0x00000000 },
  46         { 0x400130,   2, 0x04, 0x00000000 },
  47         { 0x400124,   1, 0x04, 0x00000002 },
  48         {}
  49 };
  50
  51 static const struct gf100_gr_init
  52 gk104_gr_init_ds_0[] = {
  53         { 0x405844,   1, 0x04, 0x00ffffff },
  54         { 0x405850,   1, 0x04, 0x00000000 },
  55         { 0x405900,   1, 0x04, 0x0000ff34 },
  56         { 0x405908,   1, 0x04, 0x00000000 },
  57         { 0x405928,   2, 0x04, 0x00000000 },
  58         {}
  59 };
  60
  61 static const struct gf100_gr_init
  62 gk104_gr_init_sked_0[] = {
  63         { 0x407010,   1, 0x04, 0x00000000 },
  64         {}
  65 };
  66
  67 static const struct gf100_gr_init
  68 gk104_gr_init_cwd_0[] = {
  69         { 0x405b50,   1, 0x04, 0x00000000 },
  70         {}
  71 };
  72
  73 static const struct gf100_gr_init
  74 gk104_gr_init_gpc_unk_1[] = {
  75         { 0x418d00,   1, 0x04, 0x00000000 },
  76         { 0x418d28,   2, 0x04, 0x00000000 },
  77         { 0x418f00,   1, 0x04, 0x00000000 },
  78         { 0x418f08,   1, 0x04, 0x00000000 },
  79         { 0x418f20,   2, 0x04, 0x00000000 },
  80         { 0x418e00,   1, 0x04, 0x00000060 },
  81         { 0x418e08,   1, 0x04, 0x00000000 },
  82         { 0x418e1c,   2, 0x04, 0x00000000 },
  83         {}
  84 };
  85
  86 const struct gf100_gr_init
  87 gk104_gr_init_tpccs_0[] = {
  88         { 0x419d0c,   1, 0x04, 0x00000000 },
  89         { 0x419d10,   1, 0x04, 0x00000014 },
  90         {}
  91 };
  92
  93 const struct gf100_gr_init
  94 gk104_gr_init_pe_0[] = {
  95         { 0x41980c,   1, 0x04, 0x00000010 },
  96         { 0x419844,   1, 0x04, 0x00000000 },
  97         { 0x419850,   1, 0x04, 0x00000004 },
  98         { 0x419854,   2, 0x04, 0x00000000 },
  99         {}
 100 };
 101
 102 static const struct gf100_gr_init
 103 gk104_gr_init_l1c_0[] = {
 104         { 0x419c98,   1, 0x04, 0x00000000 },
 105         { 0x419ca8,   1, 0x04, 0x00000000 },
 106         { 0x419cb0,   1, 0x04, 0x01000000 },
 107         { 0x419cb4,   1, 0x04, 0x00000000 },
 108         { 0x419cb8,   1, 0x04, 0x00b08bea },
 109         { 0x419c84,   1, 0x04, 0x00010384 },
 110         { 0x419cbc,   1, 0x04, 0x28137646 },
 111         { 0x419cc0,   2, 0x04, 0x00000000 },
 112         { 0x419c80,   1, 0x04, 0x00020232 },
 113         {}
 114 };
 115
 116 static const struct gf100_gr_init
 117 gk104_gr_init_sm_0[] = {
 118         { 0x419e00,   1, 0x04, 0x00000000 },
 119         { 0x419ea0,   1, 0x04, 0x00000000 },
 120         { 0x419ee4,   1, 0x04, 0x00000000 },
 121         { 0x419ea4,   1, 0x04, 0x00000100 },
 122         { 0x419ea8,   1, 0x04, 0x00000000 },
 123         { 0x419eb4,   4, 0x04, 0x00000000 },
 124         { 0x419edc,   1, 0x04, 0x00000000 },
 125         { 0x419f00,   1, 0x04, 0x00000000 },
 126         { 0x419f74,   1, 0x04, 0x00000555 },
 127         {}
 128 };
 129
 130 const struct gf100_gr_init
 131 gk104_gr_init_be_0[] = {
 132         { 0x40880c,   1, 0x04, 0x00000000 },
 133         { 0x408850,   1, 0x04, 0x00000004 },
 134         { 0x408910,   9, 0x04, 0x00000000 },
 135         { 0x408950,   1, 0x04, 0x00000000 },
 136         { 0x408954,   1, 0x04, 0x0000ffff },
 137         { 0x408958,   1, 0x04, 0x00000034 },
 138         { 0x408984,   1, 0x04, 0x00000000 },
 139         { 0x408988,   1, 0x04, 0x08040201 },
 140         { 0x40898c,   1, 0x04, 0x80402010 },
 141         {}
 142 };
 143
 144 const struct gf100_gr_pack
 145 gk104_gr_pack_mmio[] = {
 146         { gk104_gr_init_main_0 },
 147         { gf100_gr_init_fe_0 },
 148         { gf100_gr_init_pri_0 },
 149         { gf100_gr_init_rstr2d_0 },
 150         { gf119_gr_init_pd_0 },
 151         { gk104_gr_init_ds_0 },
 152         { gf100_gr_init_scc_0 },
 153         { gk104_gr_init_sked_0 },
 154         { gk104_gr_init_cwd_0 },
 155         { gf119_gr_init_prop_0 },
 156         { gf108_gr_init_gpc_unk_0 },
 157         { gf100_gr_init_setup_0 },
 158         { gf100_gr_init_crstr_0 },
 159         { gf108_gr_init_setup_1 },
 160         { gf100_gr_init_zcull_0 },
 161         { gf119_gr_init_gpm_0 },
 162         { gk104_gr_init_gpc_unk_1 },
 163         { gf100_gr_init_gcc_0 },
 164         { gk104_gr_init_tpccs_0 },
 165         { gf119_gr_init_tex_0 },
 166         { gk104_gr_init_pe_0 },
 167         { gk104_gr_init_l1c_0 },
 168         { gf100_gr_init_mpc_0 },
 169         { gk104_gr_init_sm_0 },
 170         { gf117_gr_init_pes_0 },
 171         { gf117_gr_init_wwdx_0 },
 172         { gf117_gr_init_cbm_0 },
 173         { gk104_gr_init_be_0 },
 174         { gf100_gr_init_fe_1 },
 175         {}
 176 };
 177
 178 /*******************************************************************************
 179  * PGRAPH engine/subdev functions
 180  ******************************************************************************/
 181
 182 int
 183 gk104_gr_init(struct nvkm_object *object)
 184 {
 185         struct gf100_gr_oclass *oclass = (void *)object->oclass;
 186         struct gf100_gr *gr = (void *)object;
 187         struct nvkm_device *device = gr->base.engine.subdev.device;
 188         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
 189         u32 data[TPC_MAX / 8] = {};
 190         u8  tpcnr[GPC_MAX];
 191         int gpc, tpc, rop;
 192         int ret, i;
 193
 194         nvkm_pmu_pgob(device->pmu, false);
 195
 196         ret = nvkm_gr_init(&gr->base);
 197         if (ret)
 198                 return ret;
 199
 200         nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
 201         nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000);
 202         nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000);
 203         nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);
 204         nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
 205         nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
 206         nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);
 207         nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);
 208
 209         gf100_gr_mmio(gr, oclass->mmio);
 210
 211         nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
 212
 213         memset(data, 0x00, sizeof(data));
 214         memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
 215         for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
 216                 do {
 217                         gpc = (gpc + 1) % gr->gpc_nr;
 218                 } while (!tpcnr[gpc]);
 219                 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
 220
 221                 data[i / 8] |= tpc << ((i % 8) * 4);
 222         }
 223
 224         nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
 225         nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
 226         nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
 227         nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
 228
 229         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
 230                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
 231                         gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
 232                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
 233                         gr->tpc_total);
 234                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
 235         }
 236
 237         nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
 238         nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
 239
 240         nvkm_wr32(device, 0x400500, 0x00010001);
 241
 242         nvkm_wr32(device, 0x400100, 0xffffffff);
 243         nvkm_wr32(device, 0x40013c, 0xffffffff);
 244
 245         nvkm_wr32(device, 0x409ffc, 0x00000000);
 246         nvkm_wr32(device, 0x409c14, 0x00003e3e);
 247         nvkm_wr32(device, 0x409c24, 0x000f0001);
 248         nvkm_wr32(device, 0x404000, 0xc0000000);
 249         nvkm_wr32(device, 0x404600, 0xc0000000);
 250         nvkm_wr32(device, 0x408030, 0xc0000000);
 251         nvkm_wr32(device, 0x404490, 0xc0000000);
 252         nvkm_wr32(device, 0x406018, 0xc0000000);
 253         nvkm_wr32(device, 0x407020, 0x40000000);
 254         nvkm_wr32(device, 0x405840, 0xc0000000);
 255         nvkm_wr32(device, 0x405844, 0x00ffffff);
 256         nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
 257         nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
 258
 259         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
 260                 nvkm_wr32(device, GPC_UNIT(gpc, 0x3038), 0xc0000000);
 261                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 262                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 263                 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 264                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 265                 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
 266                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
 267                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
 268                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
 269                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
 270                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
 271                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
 272                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
 273                 }
 274                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 275                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 276         }
 277
 278         for (rop = 0; rop < gr->rop_nr; rop++) {
 279                 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
 280                 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
 281                 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
 282                 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
 283         }
 284
 285         nvkm_wr32(device, 0x400108, 0xffffffff);
 286         nvkm_wr32(device, 0x400138, 0xffffffff);
 287         nvkm_wr32(device, 0x400118, 0xffffffff);
 288         nvkm_wr32(device, 0x400130, 0xffffffff);
 289         nvkm_wr32(device, 0x40011c, 0xffffffff);
 290         nvkm_wr32(device, 0x400134, 0xffffffff);
 291
 292         nvkm_wr32(device, 0x400054, 0x34ce3464);
 293
 294         gf100_gr_zbc_init(gr);
 295
 296         return gf100_gr_init_ctxctl(gr);
 297 }
 298
 299 static const struct gf100_gr_func
 300 gk104_gr = {
 301         .grctx = &gk104_grctx,
 302         .sclass = {
 303                 { -1, -1, FERMI_TWOD_A },
 304                 { -1, -1, KEPLER_INLINE_TO_MEMORY_A },
 305                 { -1, -1, KEPLER_A, &gf100_fermi },
 306                 { -1, -1, KEPLER_COMPUTE_A },
 307                 {}
 308         }
 309 };
 310
 311 int
 312 gk104_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 313               struct nvkm_oclass *oclass, void *data, u32 size,
 314               struct nvkm_object **pobject)
 315 {
 316         struct nvkm_device *device = (void *)parent;
 317         nvkm_pmu_pgob(device->pmu, false);
 318         return gf100_gr_ctor(parent, engine, oclass, data, size, pobject);
 319 }
 320
 321 #include "fuc/hubgk104.fuc3.h"
 322
 323 static struct gf100_gr_ucode
 324 gk104_gr_fecs_ucode = {
 325         .code.data = gk104_grhub_code,
 326         .code.size = sizeof(gk104_grhub_code),
 327         .data.data = gk104_grhub_data,
 328         .data.size = sizeof(gk104_grhub_data),
 329 };
 330
 331 #include "fuc/gpcgk104.fuc3.h"
 332
 333 static struct gf100_gr_ucode
 334 gk104_gr_gpccs_ucode = {
 335         .code.data = gk104_grgpc_code,
 336         .code.size = sizeof(gk104_grgpc_code),
 337         .data.data = gk104_grgpc_data,
 338         .data.size = sizeof(gk104_grgpc_data),
 339 };
 340
 341 struct nvkm_oclass *
 342 gk104_gr_oclass = &(struct gf100_gr_oclass) {
 343         .base.handle = NV_ENGINE(GR, 0xe4),
 344         .base.ofuncs = &(struct nvkm_ofuncs) {
 345                 .ctor = gk104_gr_ctor,
 346                 .dtor = gf100_gr_dtor,
 347                 .init = gk104_gr_init,
 348                 .fini = _nvkm_gr_fini,
 349         },
 350         .func = &gk104_gr,
 351         .mmio = gk104_gr_pack_mmio,
 352         .fecs.ucode = &gk104_gr_fecs_ucode,
 353         .gpccs.ucode = &gk104_gr_gpccs_ucode,
 354         .ppc_nr = 1,
 355 }.base;