2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include <nvif/class.h>
26 #include <subdev/timer.h>
28 static struct nvkm_oclass
30 { FERMI_TWOD_A
, &nvkm_object_ofuncs
},
31 { KEPLER_INLINE_TO_MEMORY_A
, &nvkm_object_ofuncs
},
32 { KEPLER_C
, &gf100_fermi_ofuncs
, gf100_gr_9097_omthds
},
33 { KEPLER_COMPUTE_A
, &nvkm_object_ofuncs
, gf100_gr_90c0_omthds
},
38 gk20a_gr_init_dtor(struct gf100_gr_pack
*pack
)
49 static struct gf100_gr_pack
*
50 gk20a_gr_av_to_init(struct gf100_gr_fuc
*fuc
)
52 struct gf100_gr_init
*init
;
53 struct gf100_gr_pack
*pack
;
54 const int nent
= (fuc
->size
/ sizeof(struct gk20a_fw_av
));
57 pack
= vzalloc((sizeof(*pack
) * 2) + (sizeof(*init
) * (nent
+ 1)));
59 return ERR_PTR(-ENOMEM
);
61 init
= (void *)(pack
+ 2);
65 for (i
= 0; i
< nent
; i
++) {
66 struct gf100_gr_init
*ent
= &init
[i
];
67 struct gk20a_fw_av
*av
= &((struct gk20a_fw_av
*)fuc
->data
)[i
];
85 static struct gf100_gr_pack
*
86 gk20a_gr_aiv_to_init(struct gf100_gr_fuc
*fuc
)
88 struct gf100_gr_init
*init
;
89 struct gf100_gr_pack
*pack
;
90 const int nent
= (fuc
->size
/ sizeof(struct gk20a_fw_aiv
));
93 pack
= vzalloc((sizeof(*pack
) * 2) + (sizeof(*init
) * (nent
+ 1)));
95 return ERR_PTR(-ENOMEM
);
97 init
= (void *)(pack
+ 2);
101 for (i
= 0; i
< nent
; i
++) {
102 struct gf100_gr_init
*ent
= &init
[i
];
103 struct gk20a_fw_aiv
*av
= &((struct gk20a_fw_aiv
*)fuc
->data
)[i
];
105 ent
->addr
= av
->addr
;
106 ent
->data
= av
->data
;
114 static struct gf100_gr_pack
*
115 gk20a_gr_av_to_method(struct gf100_gr_fuc
*fuc
)
117 struct gf100_gr_init
*init
;
118 struct gf100_gr_pack
*pack
;
119 /* We don't suppose we will initialize more than 16 classes here... */
120 static const unsigned int max_classes
= 16;
121 const int nent
= (fuc
->size
/ sizeof(struct gk20a_fw_av
));
125 pack
= vzalloc((sizeof(*pack
) * max_classes
) +
126 (sizeof(*init
) * (nent
+ 1)));
128 return ERR_PTR(-ENOMEM
);
130 init
= (void *)(pack
+ max_classes
);
132 for (i
= 0; i
< nent
; i
++) {
133 struct gf100_gr_init
*ent
= &init
[i
];
134 struct gk20a_fw_av
*av
= &((struct gk20a_fw_av
*)fuc
->data
)[i
];
135 u32
class = av
->addr
& 0xffff;
136 u32 addr
= (av
->addr
& 0xffff0000) >> 14;
138 if (prevclass
!= class) {
139 pack
[classidx
].init
= ent
;
140 pack
[classidx
].type
= class;
142 if (++classidx
>= max_classes
) {
144 return ERR_PTR(-ENOSPC
);
149 ent
->data
= av
->data
;
158 gk20a_gr_ctor(struct nvkm_object
*parent
, struct nvkm_object
*engine
,
159 struct nvkm_oclass
*oclass
, void *data
, u32 size
,
160 struct nvkm_object
**pobject
)
164 struct gf100_gr_fuc fuc
;
166 err
= gf100_gr_ctor(parent
, engine
, oclass
, data
, size
, pobject
);
170 gr
= (void *)*pobject
;
172 err
= gf100_gr_ctor_fw(gr
, "sw_nonctx", &fuc
);
175 gr
->fuc_sw_nonctx
= gk20a_gr_av_to_init(&fuc
);
176 gf100_gr_dtor_fw(&fuc
);
177 if (IS_ERR(gr
->fuc_sw_nonctx
))
178 return PTR_ERR(gr
->fuc_sw_nonctx
);
180 err
= gf100_gr_ctor_fw(gr
, "sw_ctx", &fuc
);
183 gr
->fuc_sw_ctx
= gk20a_gr_aiv_to_init(&fuc
);
184 gf100_gr_dtor_fw(&fuc
);
185 if (IS_ERR(gr
->fuc_sw_ctx
))
186 return PTR_ERR(gr
->fuc_sw_ctx
);
188 err
= gf100_gr_ctor_fw(gr
, "sw_bundle_init", &fuc
);
191 gr
->fuc_bundle
= gk20a_gr_av_to_init(&fuc
);
192 gf100_gr_dtor_fw(&fuc
);
193 if (IS_ERR(gr
->fuc_bundle
))
194 return PTR_ERR(gr
->fuc_bundle
);
196 err
= gf100_gr_ctor_fw(gr
, "sw_method_init", &fuc
);
199 gr
->fuc_method
= gk20a_gr_av_to_method(&fuc
);
200 gf100_gr_dtor_fw(&fuc
);
201 if (IS_ERR(gr
->fuc_method
))
202 return PTR_ERR(gr
->fuc_method
);
208 gk20a_gr_dtor(struct nvkm_object
*object
)
210 struct gf100_gr
*gr
= (void *)object
;
212 gk20a_gr_init_dtor(gr
->fuc_method
);
213 gk20a_gr_init_dtor(gr
->fuc_bundle
);
214 gk20a_gr_init_dtor(gr
->fuc_sw_ctx
);
215 gk20a_gr_init_dtor(gr
->fuc_sw_nonctx
);
217 gf100_gr_dtor(object
);
221 gk20a_gr_wait_mem_scrubbing(struct gf100_gr
*gr
)
223 if (!nv_wait(gr
, 0x40910c, 0x6, 0x0)) {
224 nv_error(gr
, "FECS mem scrubbing timeout\n");
228 if (!nv_wait(gr
, 0x41a10c, 0x6, 0x0)) {
229 nv_error(gr
, "GPCCS mem scrubbing timeout\n");
237 gk20a_gr_set_hww_esr_report_mask(struct gf100_gr
*gr
)
239 struct nvkm_device
*device
= gr
->base
.engine
.subdev
.device
;
240 nvkm_wr32(device
, 0x419e44, 0x1ffffe);
241 nvkm_wr32(device
, 0x419e4c, 0x7f);
245 gk20a_gr_init(struct nvkm_object
*object
)
247 struct gk20a_gr_oclass
*oclass
= (void *)object
->oclass
;
248 struct gf100_gr
*gr
= (void *)object
;
249 struct nvkm_device
*device
= gr
->base
.engine
.subdev
.device
;
250 const u32 magicgpc918
= DIV_ROUND_UP(0x00800000, gr
->tpc_total
);
251 u32 data
[TPC_MAX
/ 8] = {};
256 ret
= nvkm_gr_init(&gr
->base
);
261 nvkm_wr32(device
, 0x40802c, 0x1);
263 gf100_gr_mmio(gr
, gr
->fuc_sw_nonctx
);
265 ret
= gk20a_gr_wait_mem_scrubbing(gr
);
269 ret
= gf100_gr_wait_idle(gr
);
273 /* MMU debug buffer */
274 nvkm_wr32(device
, 0x100cc8, gr
->unk4188b4
->addr
>> 8);
275 nvkm_wr32(device
, 0x100ccc, gr
->unk4188b8
->addr
>> 8);
277 if (oclass
->init_gpc_mmu
)
278 oclass
->init_gpc_mmu(gr
);
280 /* Set the PE as stream master */
281 nvkm_mask(device
, 0x503018, 0x1, 0x1);
284 memset(data
, 0x00, sizeof(data
));
285 memcpy(tpcnr
, gr
->tpc_nr
, sizeof(gr
->tpc_nr
));
286 for (i
= 0, gpc
= -1; i
< gr
->tpc_total
; i
++) {
288 gpc
= (gpc
+ 1) % gr
->gpc_nr
;
289 } while (!tpcnr
[gpc
]);
290 tpc
= gr
->tpc_nr
[gpc
] - tpcnr
[gpc
]--;
292 data
[i
/ 8] |= tpc
<< ((i
% 8) * 4);
295 nvkm_wr32(device
, GPC_BCAST(0x0980), data
[0]);
296 nvkm_wr32(device
, GPC_BCAST(0x0984), data
[1]);
297 nvkm_wr32(device
, GPC_BCAST(0x0988), data
[2]);
298 nvkm_wr32(device
, GPC_BCAST(0x098c), data
[3]);
300 for (gpc
= 0; gpc
< gr
->gpc_nr
; gpc
++) {
301 nvkm_wr32(device
, GPC_UNIT(gpc
, 0x0914),
302 gr
->magic_not_rop_nr
<< 8 | gr
->tpc_nr
[gpc
]);
303 nvkm_wr32(device
, GPC_UNIT(gpc
, 0x0910), 0x00040000 |
305 nvkm_wr32(device
, GPC_UNIT(gpc
, 0x0918), magicgpc918
);
308 nvkm_wr32(device
, GPC_BCAST(0x3fd4), magicgpc918
);
310 /* Enable FIFO access */
311 nvkm_wr32(device
, 0x400500, 0x00010001);
313 /* Enable interrupts */
314 nvkm_wr32(device
, 0x400100, 0xffffffff);
315 nvkm_wr32(device
, 0x40013c, 0xffffffff);
317 /* Enable FECS error interrupts */
318 nvkm_wr32(device
, 0x409c24, 0x000f0000);
320 /* Enable hardware warning exceptions */
321 nvkm_wr32(device
, 0x404000, 0xc0000000);
322 nvkm_wr32(device
, 0x404600, 0xc0000000);
324 if (oclass
->set_hww_esr_report_mask
)
325 oclass
->set_hww_esr_report_mask(gr
);
327 /* Enable TPC exceptions per GPC */
328 nvkm_wr32(device
, 0x419d0c, 0x2);
329 nvkm_wr32(device
, 0x41ac94, (((1 << gr
->tpc_total
) - 1) & 0xff) << 16);
331 /* Reset and enable all exceptions */
332 nvkm_wr32(device
, 0x400108, 0xffffffff);
333 nvkm_wr32(device
, 0x400138, 0xffffffff);
334 nvkm_wr32(device
, 0x400118, 0xffffffff);
335 nvkm_wr32(device
, 0x400130, 0xffffffff);
336 nvkm_wr32(device
, 0x40011c, 0xffffffff);
337 nvkm_wr32(device
, 0x400134, 0xffffffff);
339 gf100_gr_zbc_init(gr
);
341 return gf100_gr_init_ctxctl(gr
);
345 gk20a_gr_oclass
= &(struct gk20a_gr_oclass
) {
347 .base
.handle
= NV_ENGINE(GR
, 0xea),
348 .base
.ofuncs
= &(struct nvkm_ofuncs
) {
349 .ctor
= gk20a_gr_ctor
,
350 .dtor
= gk20a_gr_dtor
,
351 .init
= gk20a_gr_init
,
352 .fini
= _nvkm_gr_fini
,
354 .cclass
= &gk20a_grctx_oclass
,
355 .sclass
= gk20a_gr_sclass
,
358 .set_hww_esr_report_mask
= gk20a_gr_set_hww_esr_report_mask
,