drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c

   1 /*
   2  * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "gk20a.h"
  23 #include "ctxgf100.h"
  24
  25 #include <subdev/timer.h>
  26
  27 #include <nvif/class.h>
  28
  29 static void
  30 gk20a_gr_init_dtor(struct gf100_gr_pack *pack)
  31 {
  32         vfree(pack);
  33 }
  34
  35 struct gk20a_fw_av
  36 {
  37         u32 addr;
  38         u32 data;
  39 };
  40
  41 static struct gf100_gr_pack *
  42 gk20a_gr_av_to_init(struct gf100_gr_fuc *fuc)
  43 {
  44         struct gf100_gr_init *init;
  45         struct gf100_gr_pack *pack;
  46         const int nent = (fuc->size / sizeof(struct gk20a_fw_av));
  47         int i;
  48
  49         pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
  50         if (!pack)
  51                 return ERR_PTR(-ENOMEM);
  52
  53         init = (void *)(pack + 2);
  54
  55         pack[0].init = init;
  56
  57         for (i = 0; i < nent; i++) {
  58                 struct gf100_gr_init *ent = &init[i];
  59                 struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc->data)[i];
  60
  61                 ent->addr = av->addr;
  62                 ent->data = av->data;
  63                 ent->count = 1;
  64                 ent->pitch = 1;
  65         }
  66
  67         return pack;
  68 }
  69
  70 struct gk20a_fw_aiv
  71 {
  72         u32 addr;
  73         u32 index;
  74         u32 data;
  75 };
  76
  77 static struct gf100_gr_pack *
  78 gk20a_gr_aiv_to_init(struct gf100_gr_fuc *fuc)
  79 {
  80         struct gf100_gr_init *init;
  81         struct gf100_gr_pack *pack;
  82         const int nent = (fuc->size / sizeof(struct gk20a_fw_aiv));
  83         int i;
  84
  85         pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
  86         if (!pack)
  87                 return ERR_PTR(-ENOMEM);
  88
  89         init = (void *)(pack + 2);
  90
  91         pack[0].init = init;
  92
  93         for (i = 0; i < nent; i++) {
  94                 struct gf100_gr_init *ent = &init[i];
  95                 struct gk20a_fw_aiv *av = &((struct gk20a_fw_aiv *)fuc->data)[i];
  96
  97                 ent->addr = av->addr;
  98                 ent->data = av->data;
  99                 ent->count = 1;
 100                 ent->pitch = 1;
 101         }
 102
 103         return pack;
 104 }
 105
 106 static struct gf100_gr_pack *
 107 gk20a_gr_av_to_method(struct gf100_gr_fuc *fuc)
 108 {
 109         struct gf100_gr_init *init;
 110         struct gf100_gr_pack *pack;
 111         /* We don't suppose we will initialize more than 16 classes here... */
 112         static const unsigned int max_classes = 16;
 113         const int nent = (fuc->size / sizeof(struct gk20a_fw_av));
 114         int i, classidx = 0;
 115         u32 prevclass = 0;
 116
 117         pack = vzalloc((sizeof(*pack) * max_classes) +
 118                        (sizeof(*init) * (nent + 1)));
 119         if (!pack)
 120                 return ERR_PTR(-ENOMEM);
 121
 122         init = (void *)(pack + max_classes);
 123
 124         for (i = 0; i < nent; i++) {
 125                 struct gf100_gr_init *ent = &init[i];
 126                 struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc->data)[i];
 127                 u32 class = av->addr & 0xffff;
 128                 u32 addr = (av->addr & 0xffff0000) >> 14;
 129
 130                 if (prevclass != class) {
 131                         pack[classidx].init = ent;
 132                         pack[classidx].type = class;
 133                         prevclass = class;
 134                         if (++classidx >= max_classes) {
 135                                 vfree(pack);
 136                                 return ERR_PTR(-ENOSPC);
 137                         }
 138                 }
 139
 140                 ent->addr = addr;
 141                 ent->data = av->data;
 142                 ent->count = 1;
 143                 ent->pitch = 1;
 144         }
 145
 146         return pack;
 147 }
 148
 149 int
 150 gk20a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 151               struct nvkm_oclass *oclass, void *data, u32 size,
 152               struct nvkm_object **pobject)
 153 {
 154         int err;
 155         struct gf100_gr *gr;
 156         struct gf100_gr_fuc fuc;
 157
 158         err = gf100_gr_ctor(parent, engine, oclass, data, size, pobject);
 159         if (err)
 160                 return err;
 161
 162         gr = (void *)*pobject;
 163
 164         err = gf100_gr_ctor_fw(gr, "sw_nonctx", &fuc);
 165         if (err)
 166                 return err;
 167         gr->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc);
 168         gf100_gr_dtor_fw(&fuc);
 169         if (IS_ERR(gr->fuc_sw_nonctx))
 170                 return PTR_ERR(gr->fuc_sw_nonctx);
 171
 172         err = gf100_gr_ctor_fw(gr, "sw_ctx", &fuc);
 173         if (err)
 174                 return err;
 175         gr->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc);
 176         gf100_gr_dtor_fw(&fuc);
 177         if (IS_ERR(gr->fuc_sw_ctx))
 178                 return PTR_ERR(gr->fuc_sw_ctx);
 179
 180         err = gf100_gr_ctor_fw(gr, "sw_bundle_init", &fuc);
 181         if (err)
 182                 return err;
 183         gr->fuc_bundle = gk20a_gr_av_to_init(&fuc);
 184         gf100_gr_dtor_fw(&fuc);
 185         if (IS_ERR(gr->fuc_bundle))
 186                 return PTR_ERR(gr->fuc_bundle);
 187
 188         err = gf100_gr_ctor_fw(gr, "sw_method_init", &fuc);
 189         if (err)
 190                 return err;
 191         gr->fuc_method = gk20a_gr_av_to_method(&fuc);
 192         gf100_gr_dtor_fw(&fuc);
 193         if (IS_ERR(gr->fuc_method))
 194                 return PTR_ERR(gr->fuc_method);
 195
 196         return 0;
 197 }
 198
 199 void
 200 gk20a_gr_dtor(struct nvkm_object *object)
 201 {
 202         struct gf100_gr *gr = (void *)object;
 203
 204         gk20a_gr_init_dtor(gr->fuc_method);
 205         gk20a_gr_init_dtor(gr->fuc_bundle);
 206         gk20a_gr_init_dtor(gr->fuc_sw_ctx);
 207         gk20a_gr_init_dtor(gr->fuc_sw_nonctx);
 208
 209         gf100_gr_dtor(object);
 210 }
 211
 212 static int
 213 gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
 214 {
 215         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
 216         struct nvkm_device *device = subdev->device;
 217
 218         if (nvkm_msec(device, 2000,
 219                 if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
 220                         break;
 221         ) < 0) {
 222                 nvkm_error(subdev, "FECS mem scrubbing timeout\n");
 223                 return -ETIMEDOUT;
 224         }
 225
 226         if (nvkm_msec(device, 2000,
 227                 if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
 228                         break;
 229         ) < 0) {
 230                 nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
 231                 return -ETIMEDOUT;
 232         }
 233
 234         return 0;
 235 }
 236
 237 static void
 238 gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
 239 {
 240         struct nvkm_device *device = gr->base.engine.subdev.device;
 241         nvkm_wr32(device, 0x419e44, 0x1ffffe);
 242         nvkm_wr32(device, 0x419e4c, 0x7f);
 243 }
 244
 245 int
 246 gk20a_gr_init(struct nvkm_object *object)
 247 {
 248         struct gk20a_gr_oclass *oclass = (void *)object->oclass;
 249         struct gf100_gr *gr = (void *)object;
 250         struct nvkm_device *device = gr->base.engine.subdev.device;
 251         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
 252         u32 data[TPC_MAX / 8] = {};
 253         u8  tpcnr[GPC_MAX];
 254         int gpc, tpc;
 255         int ret, i;
 256
 257         ret = nvkm_gr_init(&gr->base);
 258         if (ret)
 259                 return ret;
 260
 261         /* Clear SCC RAM */
 262         nvkm_wr32(device, 0x40802c, 0x1);
 263
 264         gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
 265
 266         ret = gk20a_gr_wait_mem_scrubbing(gr);
 267         if (ret)
 268                 return ret;
 269
 270         ret = gf100_gr_wait_idle(gr);
 271         if (ret)
 272                 return ret;
 273
 274         /* MMU debug buffer */
 275         nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8);
 276         nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8);
 277
 278         if (oclass->init_gpc_mmu)
 279                 oclass->init_gpc_mmu(gr);
 280
 281         /* Set the PE as stream master */
 282         nvkm_mask(device, 0x503018, 0x1, 0x1);
 283
 284         /* Zcull init */
 285         memset(data, 0x00, sizeof(data));
 286         memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
 287         for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
 288                 do {
 289                         gpc = (gpc + 1) % gr->gpc_nr;
 290                 } while (!tpcnr[gpc]);
 291                 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
 292
 293                 data[i / 8] |= tpc << ((i % 8) * 4);
 294         }
 295
 296         nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
 297         nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
 298         nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
 299         nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
 300
 301         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
 302                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
 303                           gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
 304                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
 305                           gr->tpc_total);
 306                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
 307         }
 308
 309         nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
 310
 311         /* Enable FIFO access */
 312         nvkm_wr32(device, 0x400500, 0x00010001);
 313
 314         /* Enable interrupts */
 315         nvkm_wr32(device, 0x400100, 0xffffffff);
 316         nvkm_wr32(device, 0x40013c, 0xffffffff);
 317
 318         /* Enable FECS error interrupts */
 319         nvkm_wr32(device, 0x409c24, 0x000f0000);
 320
 321         /* Enable hardware warning exceptions */
 322         nvkm_wr32(device, 0x404000, 0xc0000000);
 323         nvkm_wr32(device, 0x404600, 0xc0000000);
 324
 325         if (oclass->set_hww_esr_report_mask)
 326                 oclass->set_hww_esr_report_mask(gr);
 327
 328         /* Enable TPC exceptions per GPC */
 329         nvkm_wr32(device, 0x419d0c, 0x2);
 330         nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
 331
 332         /* Reset and enable all exceptions */
 333         nvkm_wr32(device, 0x400108, 0xffffffff);
 334         nvkm_wr32(device, 0x400138, 0xffffffff);
 335         nvkm_wr32(device, 0x400118, 0xffffffff);
 336         nvkm_wr32(device, 0x400130, 0xffffffff);
 337         nvkm_wr32(device, 0x40011c, 0xffffffff);
 338         nvkm_wr32(device, 0x400134, 0xffffffff);
 339
 340         gf100_gr_zbc_init(gr);
 341
 342         return gf100_gr_init_ctxctl(gr);
 343 }
 344
 345 static const struct gf100_gr_func
 346 gk20a_gr = {
 347         .grctx = &gk20a_grctx,
 348         .sclass = {
 349                 { -1, -1, FERMI_TWOD_A },
 350                 { -1, -1, KEPLER_INLINE_TO_MEMORY_A },
 351                 { -1, -1, KEPLER_C, &gf100_fermi },
 352                 { -1, -1, KEPLER_COMPUTE_A },
 353                 {}
 354         }
 355 };
 356
 357 struct nvkm_oclass *
 358 gk20a_gr_oclass = &(struct gk20a_gr_oclass) {
 359         .gf100 = {
 360                 .base.handle = NV_ENGINE(GR, 0xea),
 361                 .base.ofuncs = &(struct nvkm_ofuncs) {
 362                         .ctor = gk20a_gr_ctor,
 363                         .dtor = gk20a_gr_dtor,
 364                         .init = gk20a_gr_init,
 365                         .fini = _nvkm_gr_fini,
 366                 },
 367                 .func = &gk20a_gr,
 368                 .ppc_nr = 1,
 369         },
 370         .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
 371 }.gf100.base;