drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

   1 #include "nv20.h"
   2 #include "regs.h"
   3
   4 #include <core/client.h>
   5 #include <core/handle.h>
   6 #include <engine/fifo.h>
   7 #include <subdev/fb.h>
   8 #include <subdev/timer.h>
   9
  10 /*******************************************************************************
  11  * Graphics object classes
  12  ******************************************************************************/
  13
  14 static struct nvkm_oclass
  15 nv20_gr_sclass[] = {
  16         { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
  17         { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
  18         { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
  19         { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
  20         { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
  21         { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
  22         { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
  23         { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
  24         { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
  25         { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
  26         { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
  27         { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
  28         { 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */
  29         { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
  30         { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
  31         {},
  32 };
  33
  34 /*******************************************************************************
  35  * PGRAPH context
  36  ******************************************************************************/
  37
  38 static int
  39 nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  40                      struct nvkm_oclass *oclass, void *data, u32 size,
  41                      struct nvkm_object **pobject)
  42 {
  43         struct nv20_gr_chan *chan;
  44         int ret, i;
  45
  46         ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0,
  47                                      16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
  48         *pobject = nv_object(chan);
  49         if (ret)
  50                 return ret;
  51
  52         chan->chid = nvkm_fifo_chan(parent)->chid;
  53
  54         nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
  55         nv_wo32(chan, 0x033c, 0xffff0000);
  56         nv_wo32(chan, 0x03a0, 0x0fff0000);
  57         nv_wo32(chan, 0x03a4, 0x0fff0000);
  58         nv_wo32(chan, 0x047c, 0x00000101);
  59         nv_wo32(chan, 0x0490, 0x00000111);
  60         nv_wo32(chan, 0x04a8, 0x44400000);
  61         for (i = 0x04d4; i <= 0x04e0; i += 4)
  62                 nv_wo32(chan, i, 0x00030303);
  63         for (i = 0x04f4; i <= 0x0500; i += 4)
  64                 nv_wo32(chan, i, 0x00080000);
  65         for (i = 0x050c; i <= 0x0518; i += 4)
  66                 nv_wo32(chan, i, 0x01012000);
  67         for (i = 0x051c; i <= 0x0528; i += 4)
  68                 nv_wo32(chan, i, 0x000105b8);
  69         for (i = 0x052c; i <= 0x0538; i += 4)
  70                 nv_wo32(chan, i, 0x00080008);
  71         for (i = 0x055c; i <= 0x0598; i += 4)
  72                 nv_wo32(chan, i, 0x07ff0000);
  73         nv_wo32(chan, 0x05a4, 0x4b7fffff);
  74         nv_wo32(chan, 0x05fc, 0x00000001);
  75         nv_wo32(chan, 0x0604, 0x00004000);
  76         nv_wo32(chan, 0x0610, 0x00000001);
  77         nv_wo32(chan, 0x0618, 0x00040000);
  78         nv_wo32(chan, 0x061c, 0x00010000);
  79         for (i = 0x1c1c; i <= 0x248c; i += 16) {
  80                 nv_wo32(chan, (i + 0), 0x10700ff9);
  81                 nv_wo32(chan, (i + 4), 0x0436086c);
  82                 nv_wo32(chan, (i + 8), 0x000c001b);
  83         }
  84         nv_wo32(chan, 0x281c, 0x3f800000);
  85         nv_wo32(chan, 0x2830, 0x3f800000);
  86         nv_wo32(chan, 0x285c, 0x40000000);
  87         nv_wo32(chan, 0x2860, 0x3f800000);
  88         nv_wo32(chan, 0x2864, 0x3f000000);
  89         nv_wo32(chan, 0x286c, 0x40000000);
  90         nv_wo32(chan, 0x2870, 0x3f800000);
  91         nv_wo32(chan, 0x2878, 0xbf800000);
  92         nv_wo32(chan, 0x2880, 0xbf800000);
  93         nv_wo32(chan, 0x34a4, 0x000fe000);
  94         nv_wo32(chan, 0x3530, 0x000003f8);
  95         nv_wo32(chan, 0x3540, 0x002fe000);
  96         for (i = 0x355c; i <= 0x3578; i += 4)
  97                 nv_wo32(chan, i, 0x001c527c);
  98         return 0;
  99 }
 100
 101 int
 102 nv20_gr_context_init(struct nvkm_object *object)
 103 {
 104         struct nv20_gr *gr = (void *)object->engine;
 105         struct nv20_gr_chan *chan = (void *)object;
 106         int ret;
 107
 108         ret = nvkm_gr_context_init(&chan->base);
 109         if (ret)
 110                 return ret;
 111
 112         nv_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
 113         return 0;
 114 }
 115
 116 int
 117 nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
 118 {
 119         struct nv20_gr *gr = (void *)object->engine;
 120         struct nv20_gr_chan *chan = (void *)object;
 121         struct nvkm_device *device = gr->base.engine.subdev.device;
 122         int chid = -1;
 123
 124         nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
 125         if (nvkm_rd32(device, 0x400144) & 0x00010000)
 126                 chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
 127         if (chan->chid == chid) {
 128                 nvkm_wr32(device, 0x400784, nv_gpuobj(chan)->addr >> 4);
 129                 nvkm_wr32(device, 0x400788, 0x00000002);
 130                 nv_wait(gr, 0x400700, 0xffffffff, 0x00000000);
 131                 nvkm_wr32(device, 0x400144, 0x10000000);
 132                 nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
 133         }
 134         nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
 135
 136         nv_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
 137         return nvkm_gr_context_fini(&chan->base, suspend);
 138 }
 139
 140 static struct nvkm_oclass
 141 nv20_gr_cclass = {
 142         .handle = NV_ENGCTX(GR, 0x20),
 143         .ofuncs = &(struct nvkm_ofuncs) {
 144                 .ctor = nv20_gr_context_ctor,
 145                 .dtor = _nvkm_gr_context_dtor,
 146                 .init = nv20_gr_context_init,
 147                 .fini = nv20_gr_context_fini,
 148                 .rd32 = _nvkm_gr_context_rd32,
 149                 .wr32 = _nvkm_gr_context_wr32,
 150         },
 151 };
 152
 153 /*******************************************************************************
 154  * PGRAPH engine/subdev functions
 155  ******************************************************************************/
 156
 157 void
 158 nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
 159 {
 160         struct nv20_gr *gr = (void *)engine;
 161         struct nvkm_device *device = gr->base.engine.subdev.device;
 162         struct nvkm_fifo *fifo = device->fifo;
 163         struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
 164         unsigned long flags;
 165
 166         fifo->pause(fifo, &flags);
 167         nv04_gr_idle(gr);
 168
 169         nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
 170         nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
 171         nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
 172
 173         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
 174         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
 175         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
 176         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
 177         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
 178         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
 179
 180         if (nv_device(engine)->chipset != 0x34) {
 181                 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
 182                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
 183                 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
 184         }
 185
 186         fifo->start(fifo, &flags);
 187 }
 188
 189 void
 190 nv20_gr_intr(struct nvkm_subdev *subdev)
 191 {
 192         struct nvkm_engine *engine = nv_engine(subdev);
 193         struct nvkm_object *engctx;
 194         struct nvkm_handle *handle;
 195         struct nv20_gr *gr = (void *)subdev;
 196         struct nvkm_device *device = gr->base.engine.subdev.device;
 197         u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
 198         u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
 199         u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
 200         u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
 201         u32 chid = (addr & 0x01f00000) >> 20;
 202         u32 subc = (addr & 0x00070000) >> 16;
 203         u32 mthd = (addr & 0x00001ffc);
 204         u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
 205         u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
 206         u32 show = stat;
 207
 208         engctx = nvkm_engctx_get(engine, chid);
 209         if (stat & NV_PGRAPH_INTR_ERROR) {
 210                 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 211                         handle = nvkm_handle_get_class(engctx, class);
 212                         if (handle && !nv_call(handle->object, mthd, data))
 213                                 show &= ~NV_PGRAPH_INTR_ERROR;
 214                         nvkm_handle_put(handle);
 215                 }
 216         }
 217
 218         nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
 219         nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
 220
 221         if (show) {
 222                 nv_error(gr, "%s", "");
 223                 nvkm_bitfield_print(nv10_gr_intr_name, show);
 224                 pr_cont(" nsource:");
 225                 nvkm_bitfield_print(nv04_gr_nsource, nsource);
 226                 pr_cont(" nstatus:");
 227                 nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
 228                 pr_cont("\n");
 229                 nv_error(gr,
 230                          "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
 231                          chid, nvkm_client_name(engctx), subc, class, mthd,
 232                          data);
 233         }
 234
 235         nvkm_engctx_put(engctx);
 236 }
 237
 238 static int
 239 nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 240              struct nvkm_oclass *oclass, void *data, u32 size,
 241              struct nvkm_object **pobject)
 242 {
 243         struct nv20_gr *gr;
 244         int ret;
 245
 246         ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
 247         *pobject = nv_object(gr);
 248         if (ret)
 249                 return ret;
 250
 251         ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
 252                               NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
 253         if (ret)
 254                 return ret;
 255
 256         nv_subdev(gr)->unit = 0x00001000;
 257         nv_subdev(gr)->intr = nv20_gr_intr;
 258         nv_engine(gr)->cclass = &nv20_gr_cclass;
 259         nv_engine(gr)->sclass = nv20_gr_sclass;
 260         nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
 261         return 0;
 262 }
 263
 264 void
 265 nv20_gr_dtor(struct nvkm_object *object)
 266 {
 267         struct nv20_gr *gr = (void *)object;
 268         nvkm_gpuobj_ref(NULL, &gr->ctxtab);
 269         nvkm_gr_destroy(&gr->base);
 270 }
 271
 272 int
 273 nv20_gr_init(struct nvkm_object *object)
 274 {
 275         struct nvkm_engine *engine = nv_engine(object);
 276         struct nv20_gr *gr = (void *)engine;
 277         struct nvkm_device *device = gr->base.engine.subdev.device;
 278         struct nvkm_fb *fb = device->fb;
 279         u32 tmp, vramsz;
 280         int ret, i;
 281
 282         ret = nvkm_gr_init(&gr->base);
 283         if (ret)
 284                 return ret;
 285
 286         nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4);
 287
 288         if (nv_device(gr)->chipset == 0x20) {
 289                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
 290                 for (i = 0; i < 15; i++)
 291                         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
 292                 nv_wait(gr, 0x400700, 0xffffffff, 0x00000000);
 293         } else {
 294                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
 295                 for (i = 0; i < 32; i++)
 296                         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
 297                 nv_wait(gr, 0x400700, 0xffffffff, 0x00000000);
 298         }
 299
 300         nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 301         nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 302
 303         nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 304         nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
 305         nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
 306         nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
 307         nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
 308         nvkm_wr32(device, 0x40009C           , 0x00000040);
 309
 310         if (nv_device(gr)->chipset >= 0x25) {
 311                 nvkm_wr32(device, 0x400890, 0x00a8cfff);
 312                 nvkm_wr32(device, 0x400610, 0x304B1FB6);
 313                 nvkm_wr32(device, 0x400B80, 0x1cbd3883);
 314                 nvkm_wr32(device, 0x400B84, 0x44000000);
 315                 nvkm_wr32(device, 0x400098, 0x40000080);
 316                 nvkm_wr32(device, 0x400B88, 0x000000ff);
 317
 318         } else {
 319                 nvkm_wr32(device, 0x400880, 0x0008c7df);
 320                 nvkm_wr32(device, 0x400094, 0x00000005);
 321                 nvkm_wr32(device, 0x400B80, 0x45eae20e);
 322                 nvkm_wr32(device, 0x400B84, 0x24000000);
 323                 nvkm_wr32(device, 0x400098, 0x00000040);
 324                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
 325                 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
 326                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
 327                 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
 328         }
 329
 330         /* Turn all the tiling regions off. */
 331         for (i = 0; i < fb->tile.regions; i++)
 332                 engine->tile_prog(engine, i);
 333
 334         nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
 335         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
 336         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
 337
 338         nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
 339         nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 340
 341         tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
 342         nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
 343         tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
 344         nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
 345
 346         /* begin RAM config */
 347         vramsz = nv_device_resource_len(nv_device(gr), 1) - 1;
 348         nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
 349         nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
 350         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
 351         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
 352         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
 353         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
 354         nvkm_wr32(device, 0x400820, 0);
 355         nvkm_wr32(device, 0x400824, 0);
 356         nvkm_wr32(device, 0x400864, vramsz - 1);
 357         nvkm_wr32(device, 0x400868, vramsz - 1);
 358
 359         /* interesting.. the below overwrites some of the tile setup above.. */
 360         nvkm_wr32(device, 0x400B20, 0x00000000);
 361         nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
 362
 363         nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
 364         nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
 365         nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
 366         nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
 367         return 0;
 368 }
 369
 370 struct nvkm_oclass
 371 nv20_gr_oclass = {
 372         .handle = NV_ENGINE(GR, 0x20),
 373         .ofuncs = &(struct nvkm_ofuncs) {
 374                 .ctor = nv20_gr_ctor,
 375                 .dtor = nv20_gr_dtor,
 376                 .init = nv20_gr_init,
 377                 .fini = _nvkm_gr_fini,
 378         },
 379 };