drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv31.h"
  25
  26 #include <subdev/instmem.h>
  27
  28 /*******************************************************************************
  29  * MPEG object classes
  30  ******************************************************************************/
  31
  32 static int
  33 nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
  34 {
  35         struct nvkm_instmem *imem = nvkm_instmem(object);
  36         struct nv31_mpeg_priv *priv = (void *)object->engine;
  37         u32 inst = *(u32 *)arg << 4;
  38         u32 dma0 = nv_ro32(imem, inst + 0);
  39         u32 dma1 = nv_ro32(imem, inst + 4);
  40         u32 dma2 = nv_ro32(imem, inst + 8);
  41         u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
  42         u32 size = dma1 + 1;
  43
  44         /* only allow linear DMA objects */
  45         if (!(dma0 & 0x00002000))
  46                 return -EINVAL;
  47
  48         if (mthd == 0x0190) {
  49                 /* DMA_CMD */
  50                 nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
  51                 nv_wr32(priv, 0x00b334, base);
  52                 nv_wr32(priv, 0x00b324, size);
  53         } else
  54         if (mthd == 0x01a0) {
  55                 /* DMA_DATA */
  56                 nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
  57                 nv_wr32(priv, 0x00b360, base);
  58                 nv_wr32(priv, 0x00b364, size);
  59         } else {
  60                 /* DMA_IMAGE, VRAM only */
  61                 if (dma0 & 0x00030000)
  62                         return -EINVAL;
  63
  64                 nv_wr32(priv, 0x00b370, base);
  65                 nv_wr32(priv, 0x00b374, size);
  66         }
  67
  68         return 0;
  69 }
  70
  71 static struct nvkm_omthds
  72 nv40_mpeg_omthds[] = {
  73         { 0x0190, 0x0190, nv40_mpeg_mthd_dma },
  74         { 0x01a0, 0x01a0, nv40_mpeg_mthd_dma },
  75         { 0x01b0, 0x01b0, nv40_mpeg_mthd_dma },
  76         {}
  77 };
  78
  79 struct nvkm_oclass
  80 nv40_mpeg_sclass[] = {
  81         { 0x3174, &nv31_mpeg_ofuncs, nv40_mpeg_omthds },
  82         {}
  83 };
  84
  85 /*******************************************************************************
  86  * PMPEG engine/subdev functions
  87  ******************************************************************************/
  88
  89 static void
  90 nv40_mpeg_intr(struct nvkm_subdev *subdev)
  91 {
  92         struct nv31_mpeg_priv *priv = (void *)subdev;
  93         u32 stat;
  94
  95         if ((stat = nv_rd32(priv, 0x00b100)))
  96                 nv31_mpeg_intr(subdev);
  97
  98         if ((stat = nv_rd32(priv, 0x00b800))) {
  99                 nv_error(priv, "PMSRCH 0x%08x\n", stat);
 100                 nv_wr32(priv, 0x00b800, stat);
 101         }
 102 }
 103
 104 static int
 105 nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 106                struct nvkm_oclass *oclass, void *data, u32 size,
 107                struct nvkm_object **pobject)
 108 {
 109         struct nv31_mpeg_priv *priv;
 110         int ret;
 111
 112         ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
 113         *pobject = nv_object(priv);
 114         if (ret)
 115                 return ret;
 116
 117         nv_subdev(priv)->unit = 0x00000002;
 118         nv_subdev(priv)->intr = nv40_mpeg_intr;
 119         nv_engine(priv)->cclass = &nv31_mpeg_cclass;
 120         nv_engine(priv)->sclass = nv40_mpeg_sclass;
 121         nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
 122         return 0;
 123 }
 124
 125 struct nvkm_oclass
 126 nv40_mpeg_oclass = {
 127         .handle = NV_ENGINE(MPEG, 0x40),
 128         .ofuncs = &(struct nvkm_ofuncs) {
 129                 .ctor = nv40_mpeg_ctor,
 130                 .dtor = _nvkm_mpeg_dtor,
 131                 .init = nv31_mpeg_init,
 132                 .fini = _nvkm_mpeg_fini,
 133         },
 134 };