drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c

   1 /*
   2  * Copyright (C) 2010 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26 #include "nv04.h"
  27 #include "fbmem.h"
  28
  29 #include <subdev/bios.h>
  30 #include <subdev/bios/bmp.h>
  31 #include <subdev/bios/init.h>
  32 #include <subdev/vga.h>
  33
  34 static void
  35 nv05_devinit_meminit(struct nvkm_devinit *init)
  36 {
  37         static const u8 default_config_tab[][2] = {
  38                 { 0x24, 0x00 },
  39                 { 0x28, 0x00 },
  40                 { 0x24, 0x01 },
  41                 { 0x1f, 0x00 },
  42                 { 0x0f, 0x00 },
  43                 { 0x17, 0x00 },
  44                 { 0x06, 0x00 },
  45                 { 0x00, 0x00 }
  46         };
  47         struct nvkm_subdev *subdev = &init->subdev;
  48         struct nvkm_device *device = subdev->device;
  49         struct nvkm_bios *bios = device->bios;
  50         struct io_mapping *fb;
  51         u32 patt = 0xdeadbeef;
  52         u16 data;
  53         u8 strap, ramcfg[2];
  54         int i, v;
  55
  56         /* Map the framebuffer aperture */
  57         fb = fbmem_init(device);
  58         if (!fb) {
  59                 nvkm_error(subdev, "failed to map fb\n");
  60                 return;
  61         }
  62
  63         strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2;
  64         if ((data = bmp_mem_init_table(bios))) {
  65                 ramcfg[0] = nvbios_rd08(bios, data + 2 * strap + 0);
  66                 ramcfg[1] = nvbios_rd08(bios, data + 2 * strap + 1);
  67         } else {
  68                 ramcfg[0] = default_config_tab[strap][0];
  69                 ramcfg[1] = default_config_tab[strap][1];
  70         }
  71
  72         /* Sequencer off */
  73         nv_wrvgas(init, 0, 1, nv_rdvgas(init, 0, 1) | 0x20);
  74
  75         if (nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
  76                 goto out;
  77
  78         nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
  79
  80         /* If present load the hardcoded scrambling table */
  81         if (data) {
  82                 for (i = 0, data += 0x10; i < 8; i++, data += 4) {
  83                         u32 scramble = nvbios_rd32(bios, data);
  84                         nvkm_wr32(device, NV04_PFB_SCRAMBLE(i), scramble);
  85                 }
  86         }
  87
  88         /* Set memory type/width/length defaults depending on the straps */
  89         nvkm_mask(device, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
  90
  91         if (ramcfg[1] & 0x80)
  92                 nvkm_mask(device, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
  93
  94         nvkm_mask(device, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
  95         nvkm_mask(device, NV04_PFB_CFG1, 0, 1);
  96
  97         /* Probe memory bus width */
  98         for (i = 0; i < 4; i++)
  99                 fbmem_poke(fb, 4 * i, patt);
 100
 101         if (fbmem_peek(fb, 0xc) != patt)
 102                 nvkm_mask(device, NV04_PFB_BOOT_0,
 103                           NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
 104
 105         /* Probe memory length */
 106         v = nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
 107
 108         if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
 109             (!fbmem_readback(fb, 0x1000000, ++patt) ||
 110              !fbmem_readback(fb, 0, ++patt)))
 111                 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
 112                           NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
 113
 114         if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
 115             !fbmem_readback(fb, 0x800000, ++patt))
 116                 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
 117                           NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
 118
 119         if (!fbmem_readback(fb, 0x400000, ++patt))
 120                 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
 121                           NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
 122
 123 out:
 124         /* Sequencer on */
 125         nv_wrvgas(init, 0, 1, nv_rdvgas(init, 0, 1) & ~0x20);
 126         fbmem_fini(fb);
 127 }
 128
 129 struct nvkm_oclass *
 130 nv05_devinit_oclass = &(struct nvkm_devinit_impl) {
 131         .base.handle = NV_SUBDEV(DEVINIT, 0x05),
 132         .base.ofuncs = &(struct nvkm_ofuncs) {
 133                 .ctor = nv04_devinit_ctor,
 134                 .dtor = nv04_devinit_dtor,
 135                 .init = nv04_devinit_init,
 136                 .fini = nv04_devinit_fini,
 137         },
 138         .meminit = nv05_devinit_meminit,
 139         .pll_set = nv04_devinit_pll_set,
 140         .post = nvbios_init,
 141 }.base;