drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "port.h"
  25
  26 struct anx9805_i2c_port {
  27         struct nvkm_i2c_port base;
  28         u32 addr;
  29         u32 ctrl;
  30 };
  31
  32 static int
  33 anx9805_train(struct nvkm_i2c_port *port, int link_nr, int link_bw, bool enh)
  34 {
  35         struct anx9805_i2c_port *chan = (void *)port;
  36         struct nvkm_i2c_port *mast = (void *)nv_object(chan)->parent;
  37         u8 tmp, i;
  38
  39         DBG("ANX9805 train %d 0x%02x %d\n", link_nr, link_bw, enh);
  40
  41         nv_wri2cr(mast, chan->addr, 0xa0, link_bw);
  42         nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00));
  43         nv_wri2cr(mast, chan->addr, 0xa2, 0x01);
  44         nv_wri2cr(mast, chan->addr, 0xa8, 0x01);
  45
  46         i = 0;
  47         while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) {
  48                 mdelay(5);
  49                 if (i++ == 100) {
  50                         nv_error(port, "link training timed out\n");
  51                         return -ETIMEDOUT;
  52                 }
  53         }
  54
  55         if (tmp & 0x70) {
  56                 nv_error(port, "link training failed: 0x%02x\n", tmp);
  57                 return -EIO;
  58         }
  59
  60         return 1;
  61 }
  62
  63 static int
  64 anx9805_aux(struct nvkm_i2c_port *port, bool retry,
  65             u8 type, u32 addr, u8 *data, u8 size)
  66 {
  67         struct anx9805_i2c_port *chan = (void *)port;
  68         struct nvkm_i2c_port *mast = (void *)nv_object(chan)->parent;
  69         int i, ret = -ETIMEDOUT;
  70         u8 buf[16] = {};
  71         u8 tmp;
  72
  73         DBG("%02x %05x %d\n", type, addr, size);
  74
  75         tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04;
  76         nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04);
  77         nv_wri2cr(mast, chan->ctrl, 0x07, tmp);
  78         nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);
  79
  80         nv_wri2cr(mast, chan->addr, 0xe4, 0x80);
  81         if (!(type & 1)) {
  82                 memcpy(buf, data, size);
  83                 DBG("%16ph", buf);
  84                 for (i = 0; i < size; i++)
  85                         nv_wri2cr(mast, chan->addr, 0xf0 + i, buf[i]);
  86         }
  87         nv_wri2cr(mast, chan->addr, 0xe5, ((size - 1) << 4) | type);
  88         nv_wri2cr(mast, chan->addr, 0xe6, (addr & 0x000ff) >>  0);
  89         nv_wri2cr(mast, chan->addr, 0xe7, (addr & 0x0ff00) >>  8);
  90         nv_wri2cr(mast, chan->addr, 0xe8, (addr & 0xf0000) >> 16);
  91         nv_wri2cr(mast, chan->addr, 0xe9, 0x01);
  92
  93         i = 0;
  94         while ((tmp = nv_rdi2cr(mast, chan->addr, 0xe9)) & 0x01) {
  95                 mdelay(5);
  96                 if (i++ == 32)
  97                         goto done;
  98         }
  99
 100         if ((tmp = nv_rdi2cr(mast, chan->ctrl, 0xf7)) & 0x01) {
 101                 ret = -EIO;
 102                 goto done;
 103         }
 104
 105         if (type & 1) {
 106                 for (i = 0; i < size; i++)
 107                         buf[i] = nv_rdi2cr(mast, chan->addr, 0xf0 + i);
 108                 DBG("%16ph", buf);
 109                 memcpy(data, buf, size);
 110         }
 111
 112         ret = 0;
 113 done:
 114         nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);
 115         return ret;
 116 }
 117
 118 static const struct nvkm_i2c_func
 119 anx9805_aux_func = {
 120         .aux = anx9805_aux,
 121         .lnk_ctl = anx9805_train,
 122 };
 123
 124 static int
 125 anx9805_aux_chan_ctor(struct nvkm_object *parent,
 126                       struct nvkm_object *engine,
 127                       struct nvkm_oclass *oclass, void *data, u32 index,
 128                       struct nvkm_object **pobject)
 129 {
 130         struct nvkm_i2c_port *mast = (void *)parent;
 131         struct anx9805_i2c_port *chan;
 132         int ret;
 133
 134         ret = nvkm_i2c_port_create(parent, engine, oclass, index,
 135                                    &nvkm_i2c_aux_algo, &anx9805_aux_func,
 136                                    &chan);
 137         *pobject = nv_object(chan);
 138         if (ret)
 139                 return ret;
 140
 141         switch ((oclass->handle & 0xff00) >> 8) {
 142         case 0x0d:
 143                 chan->addr = 0x38;
 144                 chan->ctrl = 0x39;
 145                 break;
 146         case 0x0e:
 147                 chan->addr = 0x3c;
 148                 chan->ctrl = 0x3b;
 149                 break;
 150         default:
 151                 BUG_ON(1);
 152         }
 153
 154         if (mast->adapter.algo == &i2c_bit_algo) {
 155                 struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
 156                 algo->udelay = max(algo->udelay, 40);
 157         }
 158
 159         return 0;
 160 }
 161
 162 static struct nvkm_ofuncs
 163 anx9805_aux_ofuncs = {
 164         .ctor =  anx9805_aux_chan_ctor,
 165         .dtor = _nvkm_i2c_port_dtor,
 166         .init = _nvkm_i2c_port_init,
 167         .fini = _nvkm_i2c_port_fini,
 168 };
 169
 170 static int
 171 anx9805_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 172 {
 173         struct anx9805_i2c_port *port = adap->algo_data;
 174         struct nvkm_i2c_port *mast = (void *)nv_object(port)->parent;
 175         struct i2c_msg *msg = msgs;
 176         int ret = -ETIMEDOUT;
 177         int i, j, cnt = num;
 178         u8 seg = 0x00, off = 0x00, tmp;
 179
 180         tmp = nv_rdi2cr(mast, port->ctrl, 0x07) & ~0x10;
 181         nv_wri2cr(mast, port->ctrl, 0x07, tmp | 0x10);
 182         nv_wri2cr(mast, port->ctrl, 0x07, tmp);
 183         nv_wri2cr(mast, port->addr, 0x43, 0x05);
 184         mdelay(5);
 185
 186         while (cnt--) {
 187                 if ( (msg->flags & I2C_M_RD) && msg->addr == 0x50) {
 188                         nv_wri2cr(mast, port->addr, 0x40, msg->addr << 1);
 189                         nv_wri2cr(mast, port->addr, 0x41, seg);
 190                         nv_wri2cr(mast, port->addr, 0x42, off);
 191                         nv_wri2cr(mast, port->addr, 0x44, msg->len);
 192                         nv_wri2cr(mast, port->addr, 0x45, 0x00);
 193                         nv_wri2cr(mast, port->addr, 0x43, 0x01);
 194                         for (i = 0; i < msg->len; i++) {
 195                                 j = 0;
 196                                 while (nv_rdi2cr(mast, port->addr, 0x46) & 0x10) {
 197                                         mdelay(5);
 198                                         if (j++ == 32)
 199                                                 goto done;
 200                                 }
 201                                 msg->buf[i] = nv_rdi2cr(mast, port->addr, 0x47);
 202                         }
 203                 } else
 204                 if (!(msg->flags & I2C_M_RD)) {
 205                         if (msg->addr == 0x50 && msg->len == 0x01) {
 206                                 off = msg->buf[0];
 207                         } else
 208                         if (msg->addr == 0x30 && msg->len == 0x01) {
 209                                 seg = msg->buf[0];
 210                         } else
 211                                 goto done;
 212                 } else {
 213                         goto done;
 214                 }
 215                 msg++;
 216         }
 217
 218         ret = num;
 219 done:
 220         nv_wri2cr(mast, port->addr, 0x43, 0x00);
 221         return ret;
 222 }
 223
 224 static u32
 225 anx9805_func(struct i2c_adapter *adap)
 226 {
 227         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 228 }
 229
 230 static const struct i2c_algorithm
 231 anx9805_i2c_algo = {
 232         .master_xfer = anx9805_xfer,
 233         .functionality = anx9805_func
 234 };
 235
 236 static const struct nvkm_i2c_func
 237 anx9805_i2c_func = {
 238 };
 239
 240 static int
 241 anx9805_ddc_port_ctor(struct nvkm_object *parent,
 242                       struct nvkm_object *engine,
 243                       struct nvkm_oclass *oclass, void *data, u32 index,
 244                       struct nvkm_object **pobject)
 245 {
 246         struct nvkm_i2c_port *mast = (void *)parent;
 247         struct anx9805_i2c_port *port;
 248         int ret;
 249
 250         ret = nvkm_i2c_port_create(parent, engine, oclass, index,
 251                                    &anx9805_i2c_algo, &anx9805_i2c_func, &port);
 252         *pobject = nv_object(port);
 253         if (ret)
 254                 return ret;
 255
 256         switch ((oclass->handle & 0xff00) >> 8) {
 257         case 0x0d:
 258                 port->addr = 0x3d;
 259                 port->ctrl = 0x39;
 260                 break;
 261         case 0x0e:
 262                 port->addr = 0x3f;
 263                 port->ctrl = 0x3b;
 264                 break;
 265         default:
 266                 BUG_ON(1);
 267         }
 268
 269         if (mast->adapter.algo == &i2c_bit_algo) {
 270                 struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
 271                 algo->udelay = max(algo->udelay, 40);
 272         }
 273
 274         return 0;
 275 }
 276
 277 static struct nvkm_ofuncs
 278 anx9805_ddc_ofuncs = {
 279         .ctor =  anx9805_ddc_port_ctor,
 280         .dtor = _nvkm_i2c_port_dtor,
 281         .init = _nvkm_i2c_port_init,
 282         .fini = _nvkm_i2c_port_fini,
 283 };
 284
 285 struct nvkm_oclass
 286 nvkm_anx9805_sclass[] = {
 287         { .handle = NV_I2C_TYPE_EXTDDC(0x0d), .ofuncs = &anx9805_ddc_ofuncs },
 288         { .handle = NV_I2C_TYPE_EXTAUX(0x0d), .ofuncs = &anx9805_aux_ofuncs },
 289         { .handle = NV_I2C_TYPE_EXTDDC(0x0e), .ofuncs = &anx9805_ddc_ofuncs },
 290         { .handle = NV_I2C_TYPE_EXTAUX(0x0e), .ofuncs = &anx9805_aux_ofuncs },
 291         {}
 292 };