2 * linux/drivers/video/omap2/dss/dss.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DSS"
25 #include <linux/kernel.h>
26 #include <linux/module.h>
28 #include <linux/export.h>
29 #include <linux/err.h>
30 #include <linux/delay.h>
31 #include <linux/seq_file.h>
32 #include <linux/clk.h>
33 #include <linux/pinctrl/consumer.h>
34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/gfp.h>
37 #include <linux/sizes.h>
38 #include <linux/mfd/syscon.h>
39 #include <linux/regmap.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/suspend.h>
43 #include <linux/component.h>
47 #include "dss_features.h"
49 #define DSS_SZ_REGS SZ_512
55 #define DSS_REG(idx) ((const struct dss_reg) { idx })
57 #define DSS_REVISION DSS_REG(0x0000)
58 #define DSS_SYSCONFIG DSS_REG(0x0010)
59 #define DSS_SYSSTATUS DSS_REG(0x0014)
60 #define DSS_CONTROL DSS_REG(0x0040)
61 #define DSS_SDI_CONTROL DSS_REG(0x0044)
62 #define DSS_PLL_CONTROL DSS_REG(0x0048)
63 #define DSS_SDI_STATUS DSS_REG(0x005C)
65 #define REG_GET(idx, start, end) \
66 FLD_GET(dss_read_reg(idx), start, end)
68 #define REG_FLD_MOD(idx, val, start, end) \
69 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
73 u8 dss_fck_multiplier
;
74 const char *parent_clk_name
;
75 const enum omap_display_type
*ports
;
77 int (*dpi_select_source
)(int port
, enum omap_channel channel
);
78 int (*select_lcd_source
)(enum omap_channel channel
,
79 enum dss_clk_source clk_src
);
83 struct platform_device
*pdev
;
85 struct regmap
*syscon_pll_ctrl
;
86 u32 syscon_pll_ctrl_offset
;
88 struct clk
*parent_clk
;
90 unsigned long dss_clk_rate
;
92 unsigned long cache_req_pck
;
93 unsigned long cache_prate
;
94 struct dispc_clock_info cache_dispc_cinfo
;
96 enum dss_clk_source dsi_clk_source
[MAX_NUM_DSI
];
97 enum dss_clk_source dispc_clk_source
;
98 enum dss_clk_source lcd_clk_source
[MAX_DSS_LCD_MANAGERS
];
101 u32 ctx
[DSS_SZ_REGS
/ sizeof(u32
)];
103 const struct dss_features
*feat
;
105 struct dss_pll
*video1_pll
;
106 struct dss_pll
*video2_pll
;
109 static const char * const dss_generic_clk_source_names
[] = {
110 [DSS_CLK_SRC_FCK
] = "FCK",
111 [DSS_CLK_SRC_PLL1_1
] = "PLL1:1",
112 [DSS_CLK_SRC_PLL1_2
] = "PLL1:2",
113 [DSS_CLK_SRC_PLL1_3
] = "PLL1:3",
114 [DSS_CLK_SRC_PLL2_1
] = "PLL2:1",
115 [DSS_CLK_SRC_PLL2_2
] = "PLL2:2",
116 [DSS_CLK_SRC_PLL2_3
] = "PLL2:3",
117 [DSS_CLK_SRC_HDMI_PLL
] = "HDMI PLL",
120 static bool dss_initialized
;
122 bool omapdss_is_initialized(void)
124 return dss_initialized
;
126 EXPORT_SYMBOL(omapdss_is_initialized
);
128 static inline void dss_write_reg(const struct dss_reg idx
, u32 val
)
130 __raw_writel(val
, dss
.base
+ idx
.idx
);
133 static inline u32
dss_read_reg(const struct dss_reg idx
)
135 return __raw_readl(dss
.base
+ idx
.idx
);
139 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
141 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
143 static void dss_save_context(void)
145 DSSDBG("dss_save_context\n");
149 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD
) &
150 OMAP_DISPLAY_TYPE_SDI
) {
155 dss
.ctx_valid
= true;
157 DSSDBG("context saved\n");
160 static void dss_restore_context(void)
162 DSSDBG("dss_restore_context\n");
169 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD
) &
170 OMAP_DISPLAY_TYPE_SDI
) {
175 DSSDBG("context restored\n");
181 void dss_ctrl_pll_enable(enum dss_pll_id pll_id
, bool enable
)
186 if (!dss
.syscon_pll_ctrl
)
202 DSSERR("illegal DSS PLL ID %d\n", pll_id
);
206 regmap_update_bits(dss
.syscon_pll_ctrl
, dss
.syscon_pll_ctrl_offset
,
207 1 << shift
, val
<< shift
);
210 static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src
,
211 enum omap_channel channel
)
215 if (!dss
.syscon_pll_ctrl
)
219 case OMAP_DSS_CHANNEL_LCD
:
223 case DSS_CLK_SRC_PLL1_1
:
225 case DSS_CLK_SRC_HDMI_PLL
:
228 DSSERR("error in PLL mux config for LCD\n");
233 case OMAP_DSS_CHANNEL_LCD2
:
237 case DSS_CLK_SRC_PLL1_3
:
239 case DSS_CLK_SRC_PLL2_3
:
241 case DSS_CLK_SRC_HDMI_PLL
:
244 DSSERR("error in PLL mux config for LCD2\n");
249 case OMAP_DSS_CHANNEL_LCD3
:
253 case DSS_CLK_SRC_PLL2_1
:
255 case DSS_CLK_SRC_PLL1_3
:
257 case DSS_CLK_SRC_HDMI_PLL
:
260 DSSERR("error in PLL mux config for LCD3\n");
266 DSSERR("error in PLL mux config\n");
270 regmap_update_bits(dss
.syscon_pll_ctrl
, dss
.syscon_pll_ctrl_offset
,
271 0x3 << shift
, val
<< shift
);
276 void dss_sdi_init(int datapairs
)
280 BUG_ON(datapairs
> 3 || datapairs
< 1);
282 l
= dss_read_reg(DSS_SDI_CONTROL
);
283 l
= FLD_MOD(l
, 0xf, 19, 15); /* SDI_PDIV */
284 l
= FLD_MOD(l
, datapairs
-1, 3, 2); /* SDI_PRSEL */
285 l
= FLD_MOD(l
, 2, 1, 0); /* SDI_BWSEL */
286 dss_write_reg(DSS_SDI_CONTROL
, l
);
288 l
= dss_read_reg(DSS_PLL_CONTROL
);
289 l
= FLD_MOD(l
, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
290 l
= FLD_MOD(l
, 0xb, 16, 11); /* SDI_PLL_REGN */
291 l
= FLD_MOD(l
, 0xb4, 10, 1); /* SDI_PLL_REGM */
292 dss_write_reg(DSS_PLL_CONTROL
, l
);
295 int dss_sdi_enable(void)
297 unsigned long timeout
;
299 dispc_pck_free_enable(1);
302 REG_FLD_MOD(DSS_PLL_CONTROL
, 1, 18, 18); /* SDI_PLL_SYSRESET */
303 udelay(1); /* wait 2x PCLK */
306 REG_FLD_MOD(DSS_PLL_CONTROL
, 1, 28, 28); /* SDI_PLL_GOBIT */
308 /* Waiting for PLL lock request to complete */
309 timeout
= jiffies
+ msecs_to_jiffies(500);
310 while (dss_read_reg(DSS_SDI_STATUS
) & (1 << 6)) {
311 if (time_after_eq(jiffies
, timeout
)) {
312 DSSERR("PLL lock request timed out\n");
317 /* Clearing PLL_GO bit */
318 REG_FLD_MOD(DSS_PLL_CONTROL
, 0, 28, 28);
320 /* Waiting for PLL to lock */
321 timeout
= jiffies
+ msecs_to_jiffies(500);
322 while (!(dss_read_reg(DSS_SDI_STATUS
) & (1 << 5))) {
323 if (time_after_eq(jiffies
, timeout
)) {
324 DSSERR("PLL lock timed out\n");
329 dispc_lcd_enable_signal(1);
331 /* Waiting for SDI reset to complete */
332 timeout
= jiffies
+ msecs_to_jiffies(500);
333 while (!(dss_read_reg(DSS_SDI_STATUS
) & (1 << 2))) {
334 if (time_after_eq(jiffies
, timeout
)) {
335 DSSERR("SDI reset timed out\n");
343 dispc_lcd_enable_signal(0);
346 REG_FLD_MOD(DSS_PLL_CONTROL
, 0, 18, 18); /* SDI_PLL_SYSRESET */
348 dispc_pck_free_enable(0);
353 void dss_sdi_disable(void)
355 dispc_lcd_enable_signal(0);
357 dispc_pck_free_enable(0);
360 REG_FLD_MOD(DSS_PLL_CONTROL
, 0, 18, 18); /* SDI_PLL_SYSRESET */
363 const char *dss_get_clk_source_name(enum dss_clk_source clk_src
)
365 return dss_generic_clk_source_names
[clk_src
];
368 void dss_dump_clocks(struct seq_file
*s
)
370 const char *fclk_name
;
371 unsigned long fclk_rate
;
373 if (dss_runtime_get())
376 seq_printf(s
, "- DSS -\n");
378 fclk_name
= dss_get_clk_source_name(DSS_CLK_SRC_FCK
);
379 fclk_rate
= clk_get_rate(dss
.dss_clk
);
381 seq_printf(s
, "%s = %lu\n",
388 static void dss_dump_regs(struct seq_file
*s
)
390 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
392 if (dss_runtime_get())
395 DUMPREG(DSS_REVISION
);
396 DUMPREG(DSS_SYSCONFIG
);
397 DUMPREG(DSS_SYSSTATUS
);
398 DUMPREG(DSS_CONTROL
);
400 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD
) &
401 OMAP_DISPLAY_TYPE_SDI
) {
402 DUMPREG(DSS_SDI_CONTROL
);
403 DUMPREG(DSS_PLL_CONTROL
);
404 DUMPREG(DSS_SDI_STATUS
);
411 static int dss_get_channel_index(enum omap_channel channel
)
414 case OMAP_DSS_CHANNEL_LCD
:
416 case OMAP_DSS_CHANNEL_LCD2
:
418 case OMAP_DSS_CHANNEL_LCD3
:
426 static void dss_select_dispc_clk_source(enum dss_clk_source clk_src
)
432 * We always use PRCM clock as the DISPC func clock, except on DSS3,
433 * where we don't have separate DISPC and LCD clock sources.
435 if (WARN_ON(dss_has_feature(FEAT_LCD_CLK_SRC
) &&
436 clk_src
!= DSS_CLK_SRC_FCK
))
440 case DSS_CLK_SRC_FCK
:
443 case DSS_CLK_SRC_PLL1_1
:
446 case DSS_CLK_SRC_PLL2_1
:
454 dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH
, &start
, &end
);
456 REG_FLD_MOD(DSS_CONTROL
, b
, start
, end
); /* DISPC_CLK_SWITCH */
458 dss
.dispc_clk_source
= clk_src
;
461 void dss_select_dsi_clk_source(int dsi_module
,
462 enum dss_clk_source clk_src
)
467 case DSS_CLK_SRC_FCK
:
470 case DSS_CLK_SRC_PLL1_2
:
471 BUG_ON(dsi_module
!= 0);
474 case DSS_CLK_SRC_PLL2_2
:
475 BUG_ON(dsi_module
!= 1);
483 pos
= dsi_module
== 0 ? 1 : 10;
484 REG_FLD_MOD(DSS_CONTROL
, b
, pos
, pos
); /* DSIx_CLK_SWITCH */
486 dss
.dsi_clk_source
[dsi_module
] = clk_src
;
489 static int dss_lcd_clk_mux_dra7(enum omap_channel channel
,
490 enum dss_clk_source clk_src
)
492 const u8 ctrl_bits
[] = {
493 [OMAP_DSS_CHANNEL_LCD
] = 0,
494 [OMAP_DSS_CHANNEL_LCD2
] = 12,
495 [OMAP_DSS_CHANNEL_LCD3
] = 19,
498 u8 ctrl_bit
= ctrl_bits
[channel
];
501 if (clk_src
== DSS_CLK_SRC_FCK
) {
502 /* LCDx_CLK_SWITCH */
503 REG_FLD_MOD(DSS_CONTROL
, 0, ctrl_bit
, ctrl_bit
);
507 r
= dss_ctrl_pll_set_control_mux(clk_src
, channel
);
511 REG_FLD_MOD(DSS_CONTROL
, 1, ctrl_bit
, ctrl_bit
);
516 static int dss_lcd_clk_mux_omap5(enum omap_channel channel
,
517 enum dss_clk_source clk_src
)
519 const u8 ctrl_bits
[] = {
520 [OMAP_DSS_CHANNEL_LCD
] = 0,
521 [OMAP_DSS_CHANNEL_LCD2
] = 12,
522 [OMAP_DSS_CHANNEL_LCD3
] = 19,
524 const enum dss_clk_source allowed_plls
[] = {
525 [OMAP_DSS_CHANNEL_LCD
] = DSS_CLK_SRC_PLL1_1
,
526 [OMAP_DSS_CHANNEL_LCD2
] = DSS_CLK_SRC_FCK
,
527 [OMAP_DSS_CHANNEL_LCD3
] = DSS_CLK_SRC_PLL2_1
,
530 u8 ctrl_bit
= ctrl_bits
[channel
];
532 if (clk_src
== DSS_CLK_SRC_FCK
) {
533 /* LCDx_CLK_SWITCH */
534 REG_FLD_MOD(DSS_CONTROL
, 0, ctrl_bit
, ctrl_bit
);
538 if (WARN_ON(allowed_plls
[channel
] != clk_src
))
541 REG_FLD_MOD(DSS_CONTROL
, 1, ctrl_bit
, ctrl_bit
);
546 static int dss_lcd_clk_mux_omap4(enum omap_channel channel
,
547 enum dss_clk_source clk_src
)
549 const u8 ctrl_bits
[] = {
550 [OMAP_DSS_CHANNEL_LCD
] = 0,
551 [OMAP_DSS_CHANNEL_LCD2
] = 12,
553 const enum dss_clk_source allowed_plls
[] = {
554 [OMAP_DSS_CHANNEL_LCD
] = DSS_CLK_SRC_PLL1_1
,
555 [OMAP_DSS_CHANNEL_LCD2
] = DSS_CLK_SRC_PLL2_1
,
558 u8 ctrl_bit
= ctrl_bits
[channel
];
560 if (clk_src
== DSS_CLK_SRC_FCK
) {
561 /* LCDx_CLK_SWITCH */
562 REG_FLD_MOD(DSS_CONTROL
, 0, ctrl_bit
, ctrl_bit
);
566 if (WARN_ON(allowed_plls
[channel
] != clk_src
))
569 REG_FLD_MOD(DSS_CONTROL
, 1, ctrl_bit
, ctrl_bit
);
574 void dss_select_lcd_clk_source(enum omap_channel channel
,
575 enum dss_clk_source clk_src
)
577 int idx
= dss_get_channel_index(channel
);
580 if (!dss_has_feature(FEAT_LCD_CLK_SRC
)) {
581 dss_select_dispc_clk_source(clk_src
);
582 dss
.lcd_clk_source
[idx
] = clk_src
;
586 r
= dss
.feat
->select_lcd_source(channel
, clk_src
);
590 dss
.lcd_clk_source
[idx
] = clk_src
;
593 enum dss_clk_source
dss_get_dispc_clk_source(void)
595 return dss
.dispc_clk_source
;
598 enum dss_clk_source
dss_get_dsi_clk_source(int dsi_module
)
600 return dss
.dsi_clk_source
[dsi_module
];
603 enum dss_clk_source
dss_get_lcd_clk_source(enum omap_channel channel
)
605 if (dss_has_feature(FEAT_LCD_CLK_SRC
)) {
606 int idx
= dss_get_channel_index(channel
);
607 return dss
.lcd_clk_source
[idx
];
609 /* LCD_CLK source is the same as DISPC_FCLK source for
611 return dss
.dispc_clk_source
;
615 bool dss_div_calc(unsigned long pck
, unsigned long fck_min
,
616 dss_div_calc_func func
, void *data
)
618 int fckd
, fckd_start
, fckd_stop
;
620 unsigned long fck_hw_max
;
621 unsigned long fckd_hw_max
;
625 fck_hw_max
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
627 if (dss
.parent_clk
== NULL
) {
630 pckd
= fck_hw_max
/ pck
;
634 fck
= clk_round_rate(dss
.dss_clk
, fck
);
636 return func(fck
, data
);
639 fckd_hw_max
= dss
.feat
->fck_div_max
;
641 m
= dss
.feat
->dss_fck_multiplier
;
642 prate
= clk_get_rate(dss
.parent_clk
);
644 fck_min
= fck_min
? fck_min
: 1;
646 fckd_start
= min(prate
* m
/ fck_min
, fckd_hw_max
);
647 fckd_stop
= max(DIV_ROUND_UP(prate
* m
, fck_hw_max
), 1ul);
649 for (fckd
= fckd_start
; fckd
>= fckd_stop
; --fckd
) {
650 fck
= DIV_ROUND_UP(prate
, fckd
) * m
;
659 int dss_set_fck_rate(unsigned long rate
)
663 DSSDBG("set fck to %lu\n", rate
);
665 r
= clk_set_rate(dss
.dss_clk
, rate
);
669 dss
.dss_clk_rate
= clk_get_rate(dss
.dss_clk
);
671 WARN_ONCE(dss
.dss_clk_rate
!= rate
,
672 "clk rate mismatch: %lu != %lu", dss
.dss_clk_rate
,
678 unsigned long dss_get_dispc_clk_rate(void)
680 return dss
.dss_clk_rate
;
683 static int dss_setup_default_clock(void)
685 unsigned long max_dss_fck
, prate
;
690 max_dss_fck
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
692 if (dss
.parent_clk
== NULL
) {
693 fck
= clk_round_rate(dss
.dss_clk
, max_dss_fck
);
695 prate
= clk_get_rate(dss
.parent_clk
);
697 fck_div
= DIV_ROUND_UP(prate
* dss
.feat
->dss_fck_multiplier
,
699 fck
= DIV_ROUND_UP(prate
, fck_div
) * dss
.feat
->dss_fck_multiplier
;
702 r
= dss_set_fck_rate(fck
);
709 void dss_set_venc_output(enum omap_dss_venc_type type
)
713 if (type
== OMAP_DSS_VENC_TYPE_COMPOSITE
)
715 else if (type
== OMAP_DSS_VENC_TYPE_SVIDEO
)
720 /* venc out selection. 0 = comp, 1 = svideo */
721 REG_FLD_MOD(DSS_CONTROL
, l
, 6, 6);
724 void dss_set_dac_pwrdn_bgz(bool enable
)
726 REG_FLD_MOD(DSS_CONTROL
, enable
, 5, 5); /* DAC Power-Down Control */
729 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src
)
731 enum omap_display_type dp
;
732 dp
= dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT
);
734 /* Complain about invalid selections */
735 WARN_ON((src
== DSS_VENC_TV_CLK
) && !(dp
& OMAP_DISPLAY_TYPE_VENC
));
736 WARN_ON((src
== DSS_HDMI_M_PCLK
) && !(dp
& OMAP_DISPLAY_TYPE_HDMI
));
738 /* Select only if we have options */
739 if ((dp
& OMAP_DISPLAY_TYPE_VENC
) && (dp
& OMAP_DISPLAY_TYPE_HDMI
))
740 REG_FLD_MOD(DSS_CONTROL
, src
, 15, 15); /* VENC_HDMI_SWITCH */
743 enum dss_hdmi_venc_clk_source_select
dss_get_hdmi_venc_clk_source(void)
745 enum omap_display_type displays
;
747 displays
= dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT
);
748 if ((displays
& OMAP_DISPLAY_TYPE_HDMI
) == 0)
749 return DSS_VENC_TV_CLK
;
751 if ((displays
& OMAP_DISPLAY_TYPE_VENC
) == 0)
752 return DSS_HDMI_M_PCLK
;
754 return REG_GET(DSS_CONTROL
, 15, 15);
757 static int dss_dpi_select_source_omap2_omap3(int port
, enum omap_channel channel
)
759 if (channel
!= OMAP_DSS_CHANNEL_LCD
)
765 static int dss_dpi_select_source_omap4(int port
, enum omap_channel channel
)
770 case OMAP_DSS_CHANNEL_LCD2
:
773 case OMAP_DSS_CHANNEL_DIGIT
:
780 REG_FLD_MOD(DSS_CONTROL
, val
, 17, 17);
785 static int dss_dpi_select_source_omap5(int port
, enum omap_channel channel
)
790 case OMAP_DSS_CHANNEL_LCD
:
793 case OMAP_DSS_CHANNEL_LCD2
:
796 case OMAP_DSS_CHANNEL_LCD3
:
799 case OMAP_DSS_CHANNEL_DIGIT
:
806 REG_FLD_MOD(DSS_CONTROL
, val
, 17, 16);
811 static int dss_dpi_select_source_dra7xx(int port
, enum omap_channel channel
)
815 return dss_dpi_select_source_omap5(port
, channel
);
817 if (channel
!= OMAP_DSS_CHANNEL_LCD2
)
821 if (channel
!= OMAP_DSS_CHANNEL_LCD3
)
831 int dss_dpi_select_source(int port
, enum omap_channel channel
)
833 return dss
.feat
->dpi_select_source(port
, channel
);
836 static int dss_get_clocks(void)
840 clk
= devm_clk_get(&dss
.pdev
->dev
, "fck");
842 DSSERR("can't get clock fck\n");
848 if (dss
.feat
->parent_clk_name
) {
849 clk
= clk_get(NULL
, dss
.feat
->parent_clk_name
);
851 DSSERR("Failed to get %s\n", dss
.feat
->parent_clk_name
);
858 dss
.parent_clk
= clk
;
863 static void dss_put_clocks(void)
866 clk_put(dss
.parent_clk
);
869 int dss_runtime_get(void)
873 DSSDBG("dss_runtime_get\n");
875 r
= pm_runtime_get_sync(&dss
.pdev
->dev
);
877 return r
< 0 ? r
: 0;
880 void dss_runtime_put(void)
884 DSSDBG("dss_runtime_put\n");
886 r
= pm_runtime_put_sync(&dss
.pdev
->dev
);
887 WARN_ON(r
< 0 && r
!= -ENOSYS
&& r
!= -EBUSY
);
891 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
892 void dss_debug_dump_clocks(struct seq_file
*s
)
895 dispc_dump_clocks(s
);
896 #ifdef CONFIG_OMAP2_DSS_DSI
903 static const enum omap_display_type omap2plus_ports
[] = {
904 OMAP_DISPLAY_TYPE_DPI
,
907 static const enum omap_display_type omap34xx_ports
[] = {
908 OMAP_DISPLAY_TYPE_DPI
,
909 OMAP_DISPLAY_TYPE_SDI
,
912 static const enum omap_display_type dra7xx_ports
[] = {
913 OMAP_DISPLAY_TYPE_DPI
,
914 OMAP_DISPLAY_TYPE_DPI
,
915 OMAP_DISPLAY_TYPE_DPI
,
918 static const struct dss_features omap24xx_dss_feats
= {
920 * fck div max is really 16, but the divider range has gaps. The range
921 * from 1 to 6 has no gaps, so let's use that as a max.
924 .dss_fck_multiplier
= 2,
925 .parent_clk_name
= "core_ck",
926 .dpi_select_source
= &dss_dpi_select_source_omap2_omap3
,
927 .ports
= omap2plus_ports
,
928 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
931 static const struct dss_features omap34xx_dss_feats
= {
933 .dss_fck_multiplier
= 2,
934 .parent_clk_name
= "dpll4_ck",
935 .dpi_select_source
= &dss_dpi_select_source_omap2_omap3
,
936 .ports
= omap34xx_ports
,
937 .num_ports
= ARRAY_SIZE(omap34xx_ports
),
940 static const struct dss_features omap3630_dss_feats
= {
942 .dss_fck_multiplier
= 1,
943 .parent_clk_name
= "dpll4_ck",
944 .dpi_select_source
= &dss_dpi_select_source_omap2_omap3
,
945 .ports
= omap2plus_ports
,
946 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
949 static const struct dss_features omap44xx_dss_feats
= {
951 .dss_fck_multiplier
= 1,
952 .parent_clk_name
= "dpll_per_x2_ck",
953 .dpi_select_source
= &dss_dpi_select_source_omap4
,
954 .ports
= omap2plus_ports
,
955 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
956 .select_lcd_source
= &dss_lcd_clk_mux_omap4
,
959 static const struct dss_features omap54xx_dss_feats
= {
961 .dss_fck_multiplier
= 1,
962 .parent_clk_name
= "dpll_per_x2_ck",
963 .dpi_select_source
= &dss_dpi_select_source_omap5
,
964 .ports
= omap2plus_ports
,
965 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
966 .select_lcd_source
= &dss_lcd_clk_mux_omap5
,
969 static const struct dss_features am43xx_dss_feats
= {
971 .dss_fck_multiplier
= 0,
972 .parent_clk_name
= NULL
,
973 .dpi_select_source
= &dss_dpi_select_source_omap2_omap3
,
974 .ports
= omap2plus_ports
,
975 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
978 static const struct dss_features dra7xx_dss_feats
= {
980 .dss_fck_multiplier
= 1,
981 .parent_clk_name
= "dpll_per_x2_ck",
982 .dpi_select_source
= &dss_dpi_select_source_dra7xx
,
983 .ports
= dra7xx_ports
,
984 .num_ports
= ARRAY_SIZE(dra7xx_ports
),
985 .select_lcd_source
= &dss_lcd_clk_mux_dra7
,
988 static int dss_init_features(struct platform_device
*pdev
)
990 const struct dss_features
*src
;
991 struct dss_features
*dst
;
993 dst
= devm_kzalloc(&pdev
->dev
, sizeof(*dst
), GFP_KERNEL
);
995 dev_err(&pdev
->dev
, "Failed to allocate local DSS Features\n");
999 switch (omapdss_get_version()) {
1000 case OMAPDSS_VER_OMAP24xx
:
1001 src
= &omap24xx_dss_feats
;
1004 case OMAPDSS_VER_OMAP34xx_ES1
:
1005 case OMAPDSS_VER_OMAP34xx_ES3
:
1006 case OMAPDSS_VER_AM35xx
:
1007 src
= &omap34xx_dss_feats
;
1010 case OMAPDSS_VER_OMAP3630
:
1011 src
= &omap3630_dss_feats
;
1014 case OMAPDSS_VER_OMAP4430_ES1
:
1015 case OMAPDSS_VER_OMAP4430_ES2
:
1016 case OMAPDSS_VER_OMAP4
:
1017 src
= &omap44xx_dss_feats
;
1020 case OMAPDSS_VER_OMAP5
:
1021 src
= &omap54xx_dss_feats
;
1024 case OMAPDSS_VER_AM43xx
:
1025 src
= &am43xx_dss_feats
;
1028 case OMAPDSS_VER_DRA7xx
:
1029 src
= &dra7xx_dss_feats
;
1036 memcpy(dst
, src
, sizeof(*dst
));
1042 static int dss_init_ports(struct platform_device
*pdev
)
1044 struct device_node
*parent
= pdev
->dev
.of_node
;
1045 struct device_node
*port
;
1051 port
= omapdss_of_get_next_port(parent
, NULL
);
1055 if (dss
.feat
->num_ports
== 0)
1059 enum omap_display_type port_type
;
1062 r
= of_property_read_u32(port
, "reg", ®
);
1066 if (reg
>= dss
.feat
->num_ports
)
1069 port_type
= dss
.feat
->ports
[reg
];
1071 switch (port_type
) {
1072 case OMAP_DISPLAY_TYPE_DPI
:
1073 dpi_init_port(pdev
, port
);
1075 case OMAP_DISPLAY_TYPE_SDI
:
1076 sdi_init_port(pdev
, port
);
1081 } while ((port
= omapdss_of_get_next_port(parent
, port
)) != NULL
);
1086 static void dss_uninit_ports(struct platform_device
*pdev
)
1088 struct device_node
*parent
= pdev
->dev
.of_node
;
1089 struct device_node
*port
;
1094 port
= omapdss_of_get_next_port(parent
, NULL
);
1098 if (dss
.feat
->num_ports
== 0)
1102 enum omap_display_type port_type
;
1106 r
= of_property_read_u32(port
, "reg", ®
);
1110 if (reg
>= dss
.feat
->num_ports
)
1113 port_type
= dss
.feat
->ports
[reg
];
1115 switch (port_type
) {
1116 case OMAP_DISPLAY_TYPE_DPI
:
1117 dpi_uninit_port(port
);
1119 case OMAP_DISPLAY_TYPE_SDI
:
1120 sdi_uninit_port(port
);
1125 } while ((port
= omapdss_of_get_next_port(parent
, port
)) != NULL
);
1128 static int dss_video_pll_probe(struct platform_device
*pdev
)
1130 struct device_node
*np
= pdev
->dev
.of_node
;
1131 struct regulator
*pll_regulator
;
1137 if (of_property_read_bool(np
, "syscon-pll-ctrl")) {
1138 dss
.syscon_pll_ctrl
= syscon_regmap_lookup_by_phandle(np
,
1140 if (IS_ERR(dss
.syscon_pll_ctrl
)) {
1142 "failed to get syscon-pll-ctrl regmap\n");
1143 return PTR_ERR(dss
.syscon_pll_ctrl
);
1146 if (of_property_read_u32_index(np
, "syscon-pll-ctrl", 1,
1147 &dss
.syscon_pll_ctrl_offset
)) {
1149 "failed to get syscon-pll-ctrl offset\n");
1154 pll_regulator
= devm_regulator_get(&pdev
->dev
, "vdda_video");
1155 if (IS_ERR(pll_regulator
)) {
1156 r
= PTR_ERR(pll_regulator
);
1160 pll_regulator
= NULL
;
1164 return -EPROBE_DEFER
;
1167 DSSERR("can't get DPLL VDDA regulator\n");
1172 if (of_property_match_string(np
, "reg-names", "pll1") >= 0) {
1173 dss
.video1_pll
= dss_video_pll_init(pdev
, 0, pll_regulator
);
1174 if (IS_ERR(dss
.video1_pll
))
1175 return PTR_ERR(dss
.video1_pll
);
1178 if (of_property_match_string(np
, "reg-names", "pll2") >= 0) {
1179 dss
.video2_pll
= dss_video_pll_init(pdev
, 1, pll_regulator
);
1180 if (IS_ERR(dss
.video2_pll
)) {
1181 dss_video_pll_uninit(dss
.video1_pll
);
1182 return PTR_ERR(dss
.video2_pll
);
1189 /* DSS HW IP initialisation */
1190 static int dss_bind(struct device
*dev
)
1192 struct platform_device
*pdev
= to_platform_device(dev
);
1193 struct resource
*dss_mem
;
1199 r
= dss_init_features(dss
.pdev
);
1203 dss_mem
= platform_get_resource(dss
.pdev
, IORESOURCE_MEM
, 0);
1205 DSSERR("can't get IORESOURCE_MEM DSS\n");
1209 dss
.base
= devm_ioremap(&pdev
->dev
, dss_mem
->start
,
1210 resource_size(dss_mem
));
1212 DSSERR("can't ioremap DSS\n");
1216 r
= dss_get_clocks();
1220 r
= dss_setup_default_clock();
1222 goto err_setup_clocks
;
1224 r
= dss_video_pll_probe(pdev
);
1228 r
= dss_init_ports(pdev
);
1230 goto err_init_ports
;
1232 pm_runtime_enable(&pdev
->dev
);
1234 r
= dss_runtime_get();
1236 goto err_runtime_get
;
1238 dss
.dss_clk_rate
= clk_get_rate(dss
.dss_clk
);
1241 REG_FLD_MOD(DSS_CONTROL
, 0, 0, 0);
1243 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK
);
1245 #ifdef CONFIG_OMAP2_DSS_VENC
1246 REG_FLD_MOD(DSS_CONTROL
, 1, 4, 4); /* venc dac demen */
1247 REG_FLD_MOD(DSS_CONTROL
, 1, 3, 3); /* venc clock 4x enable */
1248 REG_FLD_MOD(DSS_CONTROL
, 0, 2, 2); /* venc clock mode = normal */
1250 dss
.dsi_clk_source
[0] = DSS_CLK_SRC_FCK
;
1251 dss
.dsi_clk_source
[1] = DSS_CLK_SRC_FCK
;
1252 dss
.dispc_clk_source
= DSS_CLK_SRC_FCK
;
1253 dss
.lcd_clk_source
[0] = DSS_CLK_SRC_FCK
;
1254 dss
.lcd_clk_source
[1] = DSS_CLK_SRC_FCK
;
1256 rev
= dss_read_reg(DSS_REVISION
);
1257 printk(KERN_INFO
"OMAP DSS rev %d.%d\n",
1258 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
1262 r
= component_bind_all(&pdev
->dev
, NULL
);
1266 dss_debugfs_create_file("dss", dss_dump_regs
);
1268 pm_set_vt_switch(0);
1270 dss_initialized
= true;
1276 pm_runtime_disable(&pdev
->dev
);
1277 dss_uninit_ports(pdev
);
1280 dss_video_pll_uninit(dss
.video1_pll
);
1283 dss_video_pll_uninit(dss
.video2_pll
);
1290 static void dss_unbind(struct device
*dev
)
1292 struct platform_device
*pdev
= to_platform_device(dev
);
1294 dss_initialized
= false;
1296 component_unbind_all(&pdev
->dev
, NULL
);
1299 dss_video_pll_uninit(dss
.video1_pll
);
1302 dss_video_pll_uninit(dss
.video2_pll
);
1304 dss_uninit_ports(pdev
);
1306 pm_runtime_disable(&pdev
->dev
);
1311 static const struct component_master_ops dss_component_ops
= {
1313 .unbind
= dss_unbind
,
1316 static int dss_component_compare(struct device
*dev
, void *data
)
1318 struct device
*child
= data
;
1319 return dev
== child
;
1322 static int dss_add_child_component(struct device
*dev
, void *data
)
1324 struct component_match
**match
= data
;
1328 * We don't have a working driver for rfbi, so skip it here always.
1329 * Otherwise dss will never get probed successfully, as it will wait
1330 * for rfbi to get probed.
1332 if (strstr(dev_name(dev
), "rfbi"))
1335 component_match_add(dev
->parent
, match
, dss_component_compare
, dev
);
1340 static int dss_probe(struct platform_device
*pdev
)
1342 struct component_match
*match
= NULL
;
1345 /* add all the child devices as components */
1346 device_for_each_child(&pdev
->dev
, &match
, dss_add_child_component
);
1348 r
= component_master_add_with_match(&pdev
->dev
, &dss_component_ops
, match
);
1355 static int dss_remove(struct platform_device
*pdev
)
1357 component_master_del(&pdev
->dev
, &dss_component_ops
);
1361 static int dss_runtime_suspend(struct device
*dev
)
1364 dss_set_min_bus_tput(dev
, 0);
1366 pinctrl_pm_select_sleep_state(dev
);
1371 static int dss_runtime_resume(struct device
*dev
)
1375 pinctrl_pm_select_default_state(dev
);
1378 * Set an arbitrarily high tput request to ensure OPP100.
1379 * What we should really do is to make a request to stay in OPP100,
1380 * without any tput requirements, but that is not currently possible
1384 r
= dss_set_min_bus_tput(dev
, 1000000000);
1388 dss_restore_context();
1392 static const struct dev_pm_ops dss_pm_ops
= {
1393 .runtime_suspend
= dss_runtime_suspend
,
1394 .runtime_resume
= dss_runtime_resume
,
1397 static const struct of_device_id dss_of_match
[] = {
1398 { .compatible
= "ti,omap2-dss", },
1399 { .compatible
= "ti,omap3-dss", },
1400 { .compatible
= "ti,omap4-dss", },
1401 { .compatible
= "ti,omap5-dss", },
1402 { .compatible
= "ti,dra7-dss", },
1406 MODULE_DEVICE_TABLE(of
, dss_of_match
);
1408 static struct platform_driver omap_dsshw_driver
= {
1410 .remove
= dss_remove
,
1412 .name
= "omapdss_dss",
1414 .of_match_table
= dss_of_match
,
1415 .suppress_bind_attrs
= true,
1419 int __init
dss_init_platform_driver(void)
1421 return platform_driver_register(&omap_dsshw_driver
);
1424 void dss_uninit_platform_driver(void)
1426 platform_driver_unregister(&omap_dsshw_driver
);