drivers/gpu/drm/omapdrm/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #include <linux/interrupt.h>
  27
  28 #include "omapdss.h"
  29
  30 #ifdef pr_fmt
  31 #undef pr_fmt
  32 #endif
  33
  34 #ifdef DSS_SUBSYS_NAME
  35 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
  36 #else
  37 #define pr_fmt(fmt) fmt
  38 #endif
  39
  40 #define DSSDBG(format, ...) \
  41         pr_debug(format, ## __VA_ARGS__)
  42
  43 #ifdef DSS_SUBSYS_NAME
  44 #define DSSERR(format, ...) \
  45         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  46         ## __VA_ARGS__)
  47 #else
  48 #define DSSERR(format, ...) \
  49         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  50 #endif
  51
  52 #ifdef DSS_SUBSYS_NAME
  53 #define DSSINFO(format, ...) \
  54         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  55         ## __VA_ARGS__)
  56 #else
  57 #define DSSINFO(format, ...) \
  58         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  59 #endif
  60
  61 #ifdef DSS_SUBSYS_NAME
  62 #define DSSWARN(format, ...) \
  63         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  64         ## __VA_ARGS__)
  65 #else
  66 #define DSSWARN(format, ...) \
  67         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  68 #endif
  69
  70 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  71    number. For example 7:0 */
  72 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  73 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  74 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  75 #define FLD_MOD(orig, val, start, end) \
  76         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  77
  78 enum dss_io_pad_mode {
  79         DSS_IO_PAD_MODE_RESET,
  80         DSS_IO_PAD_MODE_RFBI,
  81         DSS_IO_PAD_MODE_BYPASS,
  82 };
  83
  84 enum dss_hdmi_venc_clk_source_select {
  85         DSS_VENC_TV_CLK = 0,
  86         DSS_HDMI_M_PCLK = 1,
  87 };
  88
  89 enum dss_dsi_content_type {
  90         DSS_DSI_CONTENT_DCS,
  91         DSS_DSI_CONTENT_GENERIC,
  92 };
  93
  94 enum dss_writeback_channel {
  95         DSS_WB_LCD1_MGR =       0,
  96         DSS_WB_LCD2_MGR =       1,
  97         DSS_WB_TV_MGR =         2,
  98         DSS_WB_OVL0 =           3,
  99         DSS_WB_OVL1 =           4,
 100         DSS_WB_OVL2 =           5,
 101         DSS_WB_OVL3 =           6,
 102         DSS_WB_LCD3_MGR =       7,
 103 };
 104
 105 enum dss_clk_source {
 106         DSS_CLK_SRC_FCK = 0,
 107
 108         DSS_CLK_SRC_PLL1_1,
 109         DSS_CLK_SRC_PLL1_2,
 110         DSS_CLK_SRC_PLL1_3,
 111
 112         DSS_CLK_SRC_PLL2_1,
 113         DSS_CLK_SRC_PLL2_2,
 114         DSS_CLK_SRC_PLL2_3,
 115
 116         DSS_CLK_SRC_HDMI_PLL,
 117 };
 118
 119 enum dss_pll_id {
 120         DSS_PLL_DSI1,
 121         DSS_PLL_DSI2,
 122         DSS_PLL_HDMI,
 123         DSS_PLL_VIDEO1,
 124         DSS_PLL_VIDEO2,
 125 };
 126
 127 struct dss_pll;
 128
 129 #define DSS_PLL_MAX_HSDIVS 4
 130
 131 enum dss_pll_type {
 132         DSS_PLL_TYPE_A,
 133         DSS_PLL_TYPE_B,
 134 };
 135
 136 /*
 137  * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
 138  * Type-B PLLs: clkout[0] refers to m2.
 139  */
 140 struct dss_pll_clock_info {
 141         /* rates that we get with dividers below */
 142         unsigned long fint;
 143         unsigned long clkdco;
 144         unsigned long clkout[DSS_PLL_MAX_HSDIVS];
 145
 146         /* dividers */
 147         u16 n;
 148         u16 m;
 149         u32 mf;
 150         u16 mX[DSS_PLL_MAX_HSDIVS];
 151         u16 sd;
 152 };
 153
 154 struct dss_pll_ops {
 155         int (*enable)(struct dss_pll *pll);
 156         void (*disable)(struct dss_pll *pll);
 157         int (*set_config)(struct dss_pll *pll,
 158                 const struct dss_pll_clock_info *cinfo);
 159 };
 160
 161 struct dss_pll_hw {
 162         enum dss_pll_type type;
 163
 164         unsigned n_max;
 165         unsigned m_min;
 166         unsigned m_max;
 167         unsigned mX_max;
 168
 169         unsigned long fint_min, fint_max;
 170         unsigned long clkdco_min, clkdco_low, clkdco_max;
 171
 172         u8 n_msb, n_lsb;
 173         u8 m_msb, m_lsb;
 174         u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
 175
 176         bool has_stopmode;
 177         bool has_freqsel;
 178         bool has_selfreqdco;
 179         bool has_refsel;
 180 };
 181
 182 struct dss_pll {
 183         const char *name;
 184         enum dss_pll_id id;
 185
 186         struct clk *clkin;
 187         struct regulator *regulator;
 188
 189         void __iomem *base;
 190
 191         const struct dss_pll_hw *hw;
 192
 193         const struct dss_pll_ops *ops;
 194
 195         struct dss_pll_clock_info cinfo;
 196 };
 197
 198 struct dispc_clock_info {
 199         /* rates that we get with dividers below */
 200         unsigned long lck;
 201         unsigned long pck;
 202
 203         /* dividers */
 204         u16 lck_div;
 205         u16 pck_div;
 206 };
 207
 208 struct dss_lcd_mgr_config {
 209         enum dss_io_pad_mode io_pad_mode;
 210
 211         bool stallmode;
 212         bool fifohandcheck;
 213
 214         struct dispc_clock_info clock_info;
 215
 216         int video_port_width;
 217
 218         int lcden_sig_polarity;
 219 };
 220
 221 struct seq_file;
 222 struct platform_device;
 223
 224 /* core */
 225 struct platform_device *dss_get_core_pdev(void);
 226 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
 227 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
 228 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
 229 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
 230
 231 static inline bool dss_mgr_is_lcd(enum omap_channel id)
 232 {
 233         if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
 234                         id == OMAP_DSS_CHANNEL_LCD3)
 235                 return true;
 236         else
 237                 return false;
 238 }
 239
 240 /* DSS */
 241 int dss_init_platform_driver(void) __init;
 242 void dss_uninit_platform_driver(void);
 243
 244 int dss_runtime_get(void);
 245 void dss_runtime_put(void);
 246
 247 unsigned long dss_get_dispc_clk_rate(void);
 248 int dss_dpi_select_source(int port, enum omap_channel channel);
 249 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 250 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 251 const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
 252 void dss_dump_clocks(struct seq_file *s);
 253
 254 /* DSS VIDEO PLL */
 255 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
 256         struct regulator *regulator);
 257 void dss_video_pll_uninit(struct dss_pll *pll);
 258
 259 /* dss-of */
 260 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
 261 u32 dss_of_port_get_port_number(struct device_node *port);
 262
 263 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 264 void dss_debug_dump_clocks(struct seq_file *s);
 265 #endif
 266
 267 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
 268
 269 void dss_sdi_init(int datapairs);
 270 int dss_sdi_enable(void);
 271 void dss_sdi_disable(void);
 272
 273 void dss_select_dsi_clk_source(int dsi_module,
 274                 enum dss_clk_source clk_src);
 275 void dss_select_lcd_clk_source(enum omap_channel channel,
 276                 enum dss_clk_source clk_src);
 277 enum dss_clk_source dss_get_dispc_clk_source(void);
 278 enum dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 279 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 280
 281 void dss_set_venc_output(enum omap_dss_venc_type type);
 282 void dss_set_dac_pwrdn_bgz(bool enable);
 283
 284 int dss_set_fck_rate(unsigned long rate);
 285
 286 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
 287 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
 288                 dss_div_calc_func func, void *data);
 289
 290 /* SDI */
 291 int sdi_init_platform_driver(void) __init;
 292 void sdi_uninit_platform_driver(void);
 293
 294 #ifdef CONFIG_OMAP2_DSS_SDI
 295 int sdi_init_port(struct platform_device *pdev, struct device_node *port);
 296 void sdi_uninit_port(struct device_node *port);
 297 #else
 298 static inline int sdi_init_port(struct platform_device *pdev,
 299                 struct device_node *port)
 300 {
 301         return 0;
 302 }
 303 static inline void sdi_uninit_port(struct device_node *port)
 304 {
 305 }
 306 #endif
 307
 308 /* DSI */
 309
 310 #ifdef CONFIG_OMAP2_DSS_DSI
 311
 312 struct dentry;
 313 struct file_operations;
 314
 315 int dsi_init_platform_driver(void) __init;
 316 void dsi_uninit_platform_driver(void);
 317
 318 void dsi_dump_clocks(struct seq_file *s);
 319
 320 void dsi_irq_handler(void);
 321 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 322
 323 #else
 324 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 325 {
 326         WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
 327              __func__);
 328         return 0;
 329 }
 330 #endif
 331
 332 /* DPI */
 333 int dpi_init_platform_driver(void) __init;
 334 void dpi_uninit_platform_driver(void);
 335
 336 #ifdef CONFIG_OMAP2_DSS_DPI
 337 int dpi_init_port(struct platform_device *pdev, struct device_node *port);
 338 void dpi_uninit_port(struct device_node *port);
 339 #else
 340 static inline int dpi_init_port(struct platform_device *pdev,
 341                 struct device_node *port)
 342 {
 343         return 0;
 344 }
 345 static inline void dpi_uninit_port(struct device_node *port)
 346 {
 347 }
 348 #endif
 349
 350 /* DISPC */
 351 int dispc_init_platform_driver(void) __init;
 352 void dispc_uninit_platform_driver(void);
 353 void dispc_dump_clocks(struct seq_file *s);
 354
 355 void dispc_enable_sidle(void);
 356 void dispc_disable_sidle(void);
 357
 358 void dispc_lcd_enable_signal(bool enable);
 359 void dispc_pck_free_enable(bool enable);
 360 void dispc_enable_fifomerge(bool enable);
 361 void dispc_enable_gamma_table(bool enable);
 362
 363 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
 364                 unsigned long pck, void *data);
 365 bool dispc_div_calc(unsigned long dispc,
 366                 unsigned long pck_min, unsigned long pck_max,
 367                 dispc_div_calc_func func, void *data);
 368
 369 bool dispc_mgr_timings_ok(enum omap_channel channel,
 370                 const struct omap_video_timings *timings);
 371 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 372                 struct dispc_clock_info *cinfo);
 373
 374
 375 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 376 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
 377                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
 378                 bool manual_update);
 379
 380 void dispc_mgr_set_clock_div(enum omap_channel channel,
 381                 const struct dispc_clock_info *cinfo);
 382 int dispc_mgr_get_clock_div(enum omap_channel channel,
 383                 struct dispc_clock_info *cinfo);
 384 void dispc_set_tv_pclk(unsigned long pclk);
 385
 386 u32 dispc_wb_get_framedone_irq(void);
 387 bool dispc_wb_go_busy(void);
 388 void dispc_wb_go(void);
 389 void dispc_wb_enable(bool enable);
 390 bool dispc_wb_is_enabled(void);
 391 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
 392 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
 393                 bool mem_to_mem, const struct omap_video_timings *timings);
 394
 395 /* VENC */
 396 int venc_init_platform_driver(void) __init;
 397 void venc_uninit_platform_driver(void);
 398
 399 /* HDMI */
 400 int hdmi4_init_platform_driver(void) __init;
 401 void hdmi4_uninit_platform_driver(void);
 402
 403 int hdmi5_init_platform_driver(void) __init;
 404 void hdmi5_uninit_platform_driver(void);
 405
 406 /* RFBI */
 407 int rfbi_init_platform_driver(void) __init;
 408 void rfbi_uninit_platform_driver(void);
 409
 410
 411 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 412 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 413 {
 414         int b;
 415         for (b = 0; b < 32; ++b) {
 416                 if (irqstatus & (1 << b))
 417                         irq_arr[b]++;
 418         }
 419 }
 420 #endif
 421
 422 /* PLL */
 423 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
 424                 unsigned long clkdco, void *data);
 425 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
 426                 void *data);
 427
 428 int dss_pll_register(struct dss_pll *pll);
 429 void dss_pll_unregister(struct dss_pll *pll);
 430 struct dss_pll *dss_pll_find(const char *name);
 431 struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src);
 432 unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
 433 int dss_pll_enable(struct dss_pll *pll);
 434 void dss_pll_disable(struct dss_pll *pll);
 435 int dss_pll_set_config(struct dss_pll *pll,
 436                 const struct dss_pll_clock_info *cinfo);
 437
 438 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
 439                 unsigned long out_min, unsigned long out_max,
 440                 dss_hsdiv_calc_func func, void *data);
 441 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
 442                 unsigned long pll_min, unsigned long pll_max,
 443                 dss_pll_calc_func func, void *data);
 444
 445 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
 446         unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
 447
 448 int dss_pll_write_config_type_a(struct dss_pll *pll,
 449                 const struct dss_pll_clock_info *cinfo);
 450 int dss_pll_write_config_type_b(struct dss_pll *pll,
 451                 const struct dss_pll_clock_info *cinfo);
 452 int dss_pll_wait_reset_done(struct dss_pll *pll);
 453
 454 #endif