drivers/gpu/drm/omapdrm/dss/hdmi.h

   1 /*
   2  * HDMI driver definition for TI OMAP4 Processor.
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef _HDMI_H
  20 #define _HDMI_H
  21
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/hdmi.h>
  26 #include <sound/omap-hdmi-audio.h>
  27
  28 #include "omapdss.h"
  29 #include "dss.h"
  30
  31 /* HDMI Wrapper */
  32
  33 #define HDMI_WP_REVISION                        0x0
  34 #define HDMI_WP_SYSCONFIG                       0x10
  35 #define HDMI_WP_IRQSTATUS_RAW                   0x24
  36 #define HDMI_WP_IRQSTATUS                       0x28
  37 #define HDMI_WP_IRQENABLE_SET                   0x2C
  38 #define HDMI_WP_IRQENABLE_CLR                   0x30
  39 #define HDMI_WP_IRQWAKEEN                       0x34
  40 #define HDMI_WP_PWR_CTRL                        0x40
  41 #define HDMI_WP_DEBOUNCE                        0x44
  42 #define HDMI_WP_VIDEO_CFG                       0x50
  43 #define HDMI_WP_VIDEO_SIZE                      0x60
  44 #define HDMI_WP_VIDEO_TIMING_H                  0x68
  45 #define HDMI_WP_VIDEO_TIMING_V                  0x6C
  46 #define HDMI_WP_CLK                             0x70
  47 #define HDMI_WP_AUDIO_CFG                       0x80
  48 #define HDMI_WP_AUDIO_CFG2                      0x84
  49 #define HDMI_WP_AUDIO_CTRL                      0x88
  50 #define HDMI_WP_AUDIO_DATA                      0x8C
  51
  52 /* HDMI WP IRQ flags */
  53 #define HDMI_IRQ_CORE                           (1 << 0)
  54 #define HDMI_IRQ_OCP_TIMEOUT                    (1 << 4)
  55 #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW           (1 << 8)
  56 #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW            (1 << 9)
  57 #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ          (1 << 10)
  58 #define HDMI_IRQ_VIDEO_VSYNC                    (1 << 16)
  59 #define HDMI_IRQ_VIDEO_FRAME_DONE               (1 << 17)
  60 #define HDMI_IRQ_PHY_LINE5V_ASSERT              (1 << 24)
  61 #define HDMI_IRQ_LINK_CONNECT                   (1 << 25)
  62 #define HDMI_IRQ_LINK_DISCONNECT                (1 << 26)
  63 #define HDMI_IRQ_PLL_LOCK                       (1 << 29)
  64 #define HDMI_IRQ_PLL_UNLOCK                     (1 << 30)
  65 #define HDMI_IRQ_PLL_RECAL                      (1 << 31)
  66
  67 /* HDMI PLL */
  68
  69 #define PLLCTRL_PLL_CONTROL                     0x0
  70 #define PLLCTRL_PLL_STATUS                      0x4
  71 #define PLLCTRL_PLL_GO                          0x8
  72 #define PLLCTRL_CFG1                            0xC
  73 #define PLLCTRL_CFG2                            0x10
  74 #define PLLCTRL_CFG3                            0x14
  75 #define PLLCTRL_SSC_CFG1                        0x18
  76 #define PLLCTRL_SSC_CFG2                        0x1C
  77 #define PLLCTRL_CFG4                            0x20
  78
  79 /* HDMI PHY */
  80
  81 #define HDMI_TXPHY_TX_CTRL                      0x0
  82 #define HDMI_TXPHY_DIGITAL_CTRL                 0x4
  83 #define HDMI_TXPHY_POWER_CTRL                   0x8
  84 #define HDMI_TXPHY_PAD_CFG_CTRL                 0xC
  85 #define HDMI_TXPHY_BIST_CONTROL                 0x1C
  86
  87 enum hdmi_pll_pwr {
  88         HDMI_PLLPWRCMD_ALLOFF = 0,
  89         HDMI_PLLPWRCMD_PLLONLY = 1,
  90         HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
  91         HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
  92 };
  93
  94 enum hdmi_phy_pwr {
  95         HDMI_PHYPWRCMD_OFF = 0,
  96         HDMI_PHYPWRCMD_LDOON = 1,
  97         HDMI_PHYPWRCMD_TXON = 2
  98 };
  99
 100 enum hdmi_core_hdmi_dvi {
 101         HDMI_DVI = 0,
 102         HDMI_HDMI = 1
 103 };
 104
 105 enum hdmi_packing_mode {
 106         HDMI_PACK_10b_RGB_YUV444 = 0,
 107         HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
 108         HDMI_PACK_20b_YUV422 = 2,
 109         HDMI_PACK_ALREADYPACKED = 7
 110 };
 111
 112 enum hdmi_stereo_channels {
 113         HDMI_AUDIO_STEREO_NOCHANNELS = 0,
 114         HDMI_AUDIO_STEREO_ONECHANNEL = 1,
 115         HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
 116         HDMI_AUDIO_STEREO_THREECHANNELS = 3,
 117         HDMI_AUDIO_STEREO_FOURCHANNELS = 4
 118 };
 119
 120 enum hdmi_audio_type {
 121         HDMI_AUDIO_TYPE_LPCM = 0,
 122         HDMI_AUDIO_TYPE_IEC = 1
 123 };
 124
 125 enum hdmi_audio_justify {
 126         HDMI_AUDIO_JUSTIFY_LEFT = 0,
 127         HDMI_AUDIO_JUSTIFY_RIGHT = 1
 128 };
 129
 130 enum hdmi_audio_sample_order {
 131         HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
 132         HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
 133 };
 134
 135 enum hdmi_audio_samples_perword {
 136         HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
 137         HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
 138 };
 139
 140 enum hdmi_audio_sample_size_omap {
 141         HDMI_AUDIO_SAMPLE_16BITS = 0,
 142         HDMI_AUDIO_SAMPLE_24BITS = 1
 143 };
 144
 145 enum hdmi_audio_transf_mode {
 146         HDMI_AUDIO_TRANSF_DMA = 0,
 147         HDMI_AUDIO_TRANSF_IRQ = 1
 148 };
 149
 150 enum hdmi_audio_blk_strt_end_sig {
 151         HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
 152         HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
 153 };
 154
 155 enum hdmi_core_audio_layout {
 156         HDMI_AUDIO_LAYOUT_2CH = 0,
 157         HDMI_AUDIO_LAYOUT_8CH = 1,
 158         HDMI_AUDIO_LAYOUT_6CH = 2
 159 };
 160
 161 enum hdmi_core_cts_mode {
 162         HDMI_AUDIO_CTS_MODE_HW = 0,
 163         HDMI_AUDIO_CTS_MODE_SW = 1
 164 };
 165
 166 enum hdmi_audio_mclk_mode {
 167         HDMI_AUDIO_MCLK_128FS = 0,
 168         HDMI_AUDIO_MCLK_256FS = 1,
 169         HDMI_AUDIO_MCLK_384FS = 2,
 170         HDMI_AUDIO_MCLK_512FS = 3,
 171         HDMI_AUDIO_MCLK_768FS = 4,
 172         HDMI_AUDIO_MCLK_1024FS = 5,
 173         HDMI_AUDIO_MCLK_1152FS = 6,
 174         HDMI_AUDIO_MCLK_192FS = 7
 175 };
 176
 177 struct hdmi_video_format {
 178         enum hdmi_packing_mode  packing_mode;
 179         u32                     y_res;  /* Line per panel */
 180         u32                     x_res;  /* pixel per line */
 181 };
 182
 183 struct hdmi_config {
 184         struct omap_video_timings timings;
 185         struct hdmi_avi_infoframe infoframe;
 186         enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
 187 };
 188
 189 struct hdmi_audio_format {
 190         enum hdmi_stereo_channels               stereo_channels;
 191         u8                                      active_chnnls_msk;
 192         enum hdmi_audio_type                    type;
 193         enum hdmi_audio_justify                 justification;
 194         enum hdmi_audio_sample_order            sample_order;
 195         enum hdmi_audio_samples_perword         samples_per_word;
 196         enum hdmi_audio_sample_size_omap        sample_size;
 197         enum hdmi_audio_blk_strt_end_sig        en_sig_blk_strt_end;
 198 };
 199
 200 struct hdmi_audio_dma {
 201         u8                              transfer_size;
 202         u8                              block_size;
 203         enum hdmi_audio_transf_mode     mode;
 204         u16                             fifo_threshold;
 205 };
 206
 207 struct hdmi_core_audio_i2s_config {
 208         u8 in_length_bits;
 209         u8 justification;
 210         u8 sck_edge_mode;
 211         u8 vbit;
 212         u8 direction;
 213         u8 shift;
 214         u8 active_sds;
 215 };
 216
 217 struct hdmi_core_audio_config {
 218         struct hdmi_core_audio_i2s_config       i2s_cfg;
 219         struct snd_aes_iec958                   *iec60958_cfg;
 220         bool                                    fs_override;
 221         u32                                     n;
 222         u32                                     cts;
 223         u32                                     aud_par_busclk;
 224         enum hdmi_core_audio_layout             layout;
 225         enum hdmi_core_cts_mode                 cts_mode;
 226         bool                                    use_mclk;
 227         enum hdmi_audio_mclk_mode               mclk_mode;
 228         bool                                    en_acr_pkt;
 229         bool                                    en_dsd_audio;
 230         bool                                    en_parallel_aud_input;
 231         bool                                    en_spdif;
 232 };
 233
 234 struct hdmi_wp_data {
 235         void __iomem *base;
 236         phys_addr_t phys_base;
 237 };
 238
 239 struct hdmi_pll_data {
 240         struct dss_pll pll;
 241
 242         void __iomem *base;
 243
 244         struct platform_device *pdev;
 245         struct hdmi_wp_data *wp;
 246 };
 247
 248 struct hdmi_phy_data {
 249         void __iomem *base;
 250
 251         u8 lane_function[4];
 252         u8 lane_polarity[4];
 253 };
 254
 255 struct hdmi_core_data {
 256         void __iomem *base;
 257 };
 258
 259 static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
 260                 u32 val)
 261 {
 262         __raw_writel(val, base_addr + idx);
 263 }
 264
 265 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
 266 {
 267         return __raw_readl(base_addr + idx);
 268 }
 269
 270 #define REG_FLD_MOD(base, idx, val, start, end) \
 271         hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
 272                                                         val, start, end))
 273 #define REG_GET(base, idx, start, end) \
 274         FLD_GET(hdmi_read_reg(base, idx), start, end)
 275
 276 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
 277                 const u32 idx, int b2, int b1, u32 val)
 278 {
 279         u32 t = 0, v;
 280         while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
 281                 if (t++ > 10000)
 282                         return v;
 283                 udelay(1);
 284         }
 285         return v;
 286 }
 287
 288 /* HDMI wrapper funcs */
 289 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
 290 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
 291 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
 292 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
 293 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
 294 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
 295 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
 296 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
 297 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
 298 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
 299                 struct hdmi_video_format *video_fmt);
 300 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
 301                 struct omap_video_timings *timings);
 302 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
 303                 struct omap_video_timings *timings);
 304 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
 305                 struct omap_video_timings *timings, struct hdmi_config *param);
 306 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
 307 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
 308
 309 /* HDMI PLL funcs */
 310 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
 311 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
 312         struct hdmi_wp_data *wp);
 313 void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
 314
 315 /* HDMI PHY funcs */
 316 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
 317         unsigned long lfbitclk);
 318 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
 319 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
 320 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
 321
 322 /* HDMI common funcs */
 323 int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
 324         struct hdmi_phy_data *phy);
 325
 326 /* Audio funcs */
 327 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
 328 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
 329 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
 330 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
 331                 struct hdmi_audio_format *aud_fmt);
 332 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
 333                 struct hdmi_audio_dma *aud_dma);
 334 static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)
 335 {
 336         return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;
 337 }
 338
 339 /* HDMI DRV data */
 340 struct omap_hdmi {
 341         struct mutex lock;
 342         struct platform_device *pdev;
 343
 344         struct hdmi_wp_data     wp;
 345         struct hdmi_pll_data    pll;
 346         struct hdmi_phy_data    phy;
 347         struct hdmi_core_data   core;
 348
 349         struct hdmi_config cfg;
 350
 351         struct regulator *vdda_reg;
 352
 353         bool core_enabled;
 354
 355         struct omap_dss_device output;
 356
 357         struct platform_device *audio_pdev;
 358         void (*audio_abort_cb)(struct device *dev);
 359         int wp_idlemode;
 360
 361         bool audio_configured;
 362         struct omap_dss_audio audio_config;
 363
 364         /* This lock should be taken when booleans bellow are touched. */
 365         spinlock_t audio_playing_lock;
 366         bool audio_playing;
 367         bool display_enabled;
 368 };
 369
 370 #endif