4 * Copyright (C) 2013 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/err.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/seq_file.h>
22 struct hdmi_phy_features
{
25 unsigned long max_phy
;
28 static const struct hdmi_phy_features
*phy_feat
;
30 void hdmi_phy_dump(struct hdmi_phy_data
*phy
, struct seq_file
*s
)
32 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
33 hdmi_read_reg(phy->base, r))
35 DUMPPHY(HDMI_TXPHY_TX_CTRL
);
36 DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL
);
37 DUMPPHY(HDMI_TXPHY_POWER_CTRL
);
38 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL
);
39 if (phy_feat
->bist_ctrl
)
40 DUMPPHY(HDMI_TXPHY_BIST_CONTROL
);
43 int hdmi_phy_parse_lanes(struct hdmi_phy_data
*phy
, const u32
*lanes
)
47 for (i
= 0; i
< 8; i
+= 2) {
54 if (dx
< 0 || dx
>= 8)
57 if (dy
< 0 || dy
>= 8)
72 phy
->lane_function
[lane
] = i
/ 2;
73 phy
->lane_polarity
[lane
] = pol
;
79 static void hdmi_phy_configure_lanes(struct hdmi_phy_data
*phy
)
81 static const u16 pad_cfg_list
[] = {
110 unsigned lane_cfg_val
;
113 for (i
= 0; i
< 4; ++i
)
114 lane_cfg
|= phy
->lane_function
[i
] << ((3 - i
) * 4);
116 pol_val
|= phy
->lane_polarity
[0] << 0;
117 pol_val
|= phy
->lane_polarity
[1] << 3;
118 pol_val
|= phy
->lane_polarity
[2] << 2;
119 pol_val
|= phy
->lane_polarity
[3] << 1;
121 for (i
= 0; i
< ARRAY_SIZE(pad_cfg_list
); ++i
)
122 if (pad_cfg_list
[i
] == lane_cfg
)
125 if (WARN_ON(i
== ARRAY_SIZE(pad_cfg_list
)))
130 REG_FLD_MOD(phy
->base
, HDMI_TXPHY_PAD_CFG_CTRL
, lane_cfg_val
, 26, 22);
131 REG_FLD_MOD(phy
->base
, HDMI_TXPHY_PAD_CFG_CTRL
, pol_val
, 30, 27);
134 int hdmi_phy_configure(struct hdmi_phy_data
*phy
, unsigned long hfbitclk
,
135 unsigned long lfbitclk
)
140 * Read address 0 in order to get the SCP reset done completed
141 * Dummy access performed to make sure reset is done
143 hdmi_read_reg(phy
->base
, HDMI_TXPHY_TX_CTRL
);
146 * In OMAP5+, the HFBITCLK must be divided by 2 before issuing the
147 * HDMI_PHYPWRCMD_LDOON command.
149 if (phy_feat
->bist_ctrl
)
150 REG_FLD_MOD(phy
->base
, HDMI_TXPHY_BIST_CONTROL
, 1, 11, 11);
153 * If the hfbitclk != lfbitclk, it means the lfbitclk was configured
154 * to be used for TMDS.
156 if (hfbitclk
!= lfbitclk
)
158 else if (hfbitclk
/ 10 < phy_feat
->max_phy
)
164 * Write to phy address 0 to configure the clock
165 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
167 REG_FLD_MOD(phy
->base
, HDMI_TXPHY_TX_CTRL
, freqout
, 31, 30);
169 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
170 hdmi_write_reg(phy
->base
, HDMI_TXPHY_DIGITAL_CTRL
, 0xF0000000);
172 /* Setup max LDO voltage */
173 if (phy_feat
->ldo_voltage
)
174 REG_FLD_MOD(phy
->base
, HDMI_TXPHY_POWER_CTRL
, 0xB, 3, 0);
176 hdmi_phy_configure_lanes(phy
);
181 static const struct hdmi_phy_features omap44xx_phy_feats
= {
184 .max_phy
= 185675000,
187 static const struct hdmi_phy_features omap54xx_phy_feats
= {
189 .ldo_voltage
= false,
190 .max_phy
= 186000000,
193 static int hdmi_phy_init_features(struct platform_device
*pdev
)
195 struct hdmi_phy_features
*dst
;
196 const struct hdmi_phy_features
*src
;
198 dst
= devm_kzalloc(&pdev
->dev
, sizeof(*dst
), GFP_KERNEL
);
200 dev_err(&pdev
->dev
, "Failed to allocate HDMI PHY Features\n");
204 switch (omapdss_get_version()) {
205 case OMAPDSS_VER_OMAP4430_ES1
:
206 case OMAPDSS_VER_OMAP4430_ES2
:
207 case OMAPDSS_VER_OMAP4
:
208 src
= &omap44xx_phy_feats
;
211 case OMAPDSS_VER_OMAP5
:
212 case OMAPDSS_VER_DRA7xx
:
213 src
= &omap54xx_phy_feats
;
220 memcpy(dst
, src
, sizeof(*dst
));
226 int hdmi_phy_init(struct platform_device
*pdev
, struct hdmi_phy_data
*phy
)
229 struct resource
*res
;
231 r
= hdmi_phy_init_features(pdev
);
235 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "phy");
237 DSSERR("can't get PHY mem resource\n");
241 phy
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
242 if (IS_ERR(phy
->base
)) {
243 DSSERR("can't ioremap TX PHY\n");
244 return PTR_ERR(phy
->base
);