2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
31 #include <linux/backlight.h>
33 extern int atom_debug
;
36 radeon_atom_get_backlight_level_from_reg(struct radeon_device
*rdev
)
41 if (rdev
->family
>= CHIP_R600
)
42 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
44 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
46 backlight_level
= ((bios_2_scratch
& ATOM_S2_CURRENT_BL_LEVEL_MASK
) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT
);
49 return backlight_level
;
53 radeon_atom_set_backlight_level_to_reg(struct radeon_device
*rdev
,
58 if (rdev
->family
>= CHIP_R600
)
59 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
61 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
63 bios_2_scratch
&= ~ATOM_S2_CURRENT_BL_LEVEL_MASK
;
64 bios_2_scratch
|= ((backlight_level
<< ATOM_S2_CURRENT_BL_LEVEL_SHIFT
) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK
);
67 if (rdev
->family
>= CHIP_R600
)
68 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
70 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
74 atombios_get_backlight_level(struct radeon_encoder
*radeon_encoder
)
76 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
77 struct radeon_device
*rdev
= dev
->dev_private
;
79 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
82 return radeon_atom_get_backlight_level_from_reg(rdev
);
86 atombios_set_backlight_level(struct radeon_encoder
*radeon_encoder
, u8 level
)
88 struct drm_encoder
*encoder
= &radeon_encoder
->base
;
89 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
90 struct radeon_device
*rdev
= dev
->dev_private
;
91 struct radeon_encoder_atom_dig
*dig
;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
95 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
98 if ((radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
99 radeon_encoder
->enc_priv
) {
100 dig
= radeon_encoder
->enc_priv
;
101 dig
->backlight_level
= level
;
102 radeon_atom_set_backlight_level_to_reg(rdev
, dig
->backlight_level
);
104 switch (radeon_encoder
->encoder_id
) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
107 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
108 if (dig
->backlight_level
== 0) {
109 args
.ucAction
= ATOM_LCD_BLOFF
;
110 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
112 args
.ucAction
= ATOM_LCD_BL_BRIGHTNESS_CONTROL
;
113 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
114 args
.ucAction
= ATOM_LCD_BLON
;
115 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
122 if (dig
->backlight_level
== 0)
123 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
125 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
, 0, 0);
126 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137 static u8
radeon_atom_bl_level(struct backlight_device
*bd
)
141 /* Convert brightness to hardware level */
142 if (bd
->props
.brightness
< 0)
144 else if (bd
->props
.brightness
> RADEON_MAX_BL_LEVEL
)
145 level
= RADEON_MAX_BL_LEVEL
;
147 level
= bd
->props
.brightness
;
152 static int radeon_atom_backlight_update_status(struct backlight_device
*bd
)
154 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
155 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
157 atombios_set_backlight_level(radeon_encoder
, radeon_atom_bl_level(bd
));
162 static int radeon_atom_backlight_get_brightness(struct backlight_device
*bd
)
164 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
165 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
166 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
167 struct radeon_device
*rdev
= dev
->dev_private
;
169 return radeon_atom_get_backlight_level_from_reg(rdev
);
172 static const struct backlight_ops radeon_atom_backlight_ops
= {
173 .get_brightness
= radeon_atom_backlight_get_brightness
,
174 .update_status
= radeon_atom_backlight_update_status
,
177 void radeon_atom_backlight_init(struct radeon_encoder
*radeon_encoder
,
178 struct drm_connector
*drm_connector
)
180 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
181 struct radeon_device
*rdev
= dev
->dev_private
;
182 struct backlight_device
*bd
;
183 struct backlight_properties props
;
184 struct radeon_backlight_privdata
*pdata
;
185 struct radeon_encoder_atom_dig
*dig
;
189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
192 if ((rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
193 (rdev
->pdev
->device
== 0x6741))
196 if (!radeon_encoder
->enc_priv
)
199 if (!rdev
->is_atom_bios
)
202 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
205 pdata
= kmalloc(sizeof(struct radeon_backlight_privdata
), GFP_KERNEL
);
207 DRM_ERROR("Memory allocation failed\n");
211 memset(&props
, 0, sizeof(props
));
212 props
.max_brightness
= RADEON_MAX_BL_LEVEL
;
213 props
.type
= BACKLIGHT_RAW
;
214 snprintf(bl_name
, sizeof(bl_name
),
215 "radeon_bl%d", dev
->primary
->index
);
216 bd
= backlight_device_register(bl_name
, &drm_connector
->kdev
,
217 pdata
, &radeon_atom_backlight_ops
, &props
);
219 DRM_ERROR("Backlight registration failed\n");
223 pdata
->encoder
= radeon_encoder
;
225 backlight_level
= radeon_atom_get_backlight_level_from_reg(rdev
);
227 dig
= radeon_encoder
->enc_priv
;
230 bd
->props
.brightness
= radeon_atom_backlight_get_brightness(bd
);
231 bd
->props
.power
= FB_BLANK_UNBLANK
;
232 backlight_update_status(bd
);
234 DRM_INFO("radeon atom DIG backlight initialized\n");
243 static void radeon_atom_backlight_exit(struct radeon_encoder
*radeon_encoder
)
245 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
246 struct radeon_device
*rdev
= dev
->dev_private
;
247 struct backlight_device
*bd
= NULL
;
248 struct radeon_encoder_atom_dig
*dig
;
250 if (!radeon_encoder
->enc_priv
)
253 if (!rdev
->is_atom_bios
)
256 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
259 dig
= radeon_encoder
->enc_priv
;
264 struct radeon_legacy_backlight_privdata
*pdata
;
266 pdata
= bl_get_data(bd
);
267 backlight_device_unregister(bd
);
270 DRM_INFO("radeon atom LVDS backlight unloaded\n");
274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
276 void radeon_atom_backlight_init(struct radeon_encoder
*encoder
)
280 static void radeon_atom_backlight_exit(struct radeon_encoder
*encoder
)
286 /* evil but including atombios.h is much worse */
287 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
288 struct drm_display_mode
*mode
);
291 static inline bool radeon_encoder_is_digital(struct drm_encoder
*encoder
)
293 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
294 switch (radeon_encoder
->encoder_id
) {
295 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
296 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
298 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
299 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
301 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
313 static bool radeon_atom_mode_fixup(struct drm_encoder
*encoder
,
314 const struct drm_display_mode
*mode
,
315 struct drm_display_mode
*adjusted_mode
)
317 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
318 struct drm_device
*dev
= encoder
->dev
;
319 struct radeon_device
*rdev
= dev
->dev_private
;
321 /* set the active encoder to connector routing */
322 radeon_encoder_set_active_device(encoder
);
323 drm_mode_set_crtcinfo(adjusted_mode
, 0);
326 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
327 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
328 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
330 /* get the native mode for LVDS */
331 if (radeon_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
))
332 radeon_panel_mode_fixup(encoder
, adjusted_mode
);
334 /* get the native mode for TV */
335 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)) {
336 struct radeon_encoder_atom_dac
*tv_dac
= radeon_encoder
->enc_priv
;
338 if (tv_dac
->tv_std
== TV_STD_NTSC
||
339 tv_dac
->tv_std
== TV_STD_NTSC_J
||
340 tv_dac
->tv_std
== TV_STD_PAL_M
)
341 radeon_atom_get_tv_timings(rdev
, 0, adjusted_mode
);
343 radeon_atom_get_tv_timings(rdev
, 1, adjusted_mode
);
347 if (ASIC_IS_DCE3(rdev
) &&
348 ((radeon_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
349 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
))) {
350 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
351 radeon_dp_set_link_config(connector
, adjusted_mode
);
358 atombios_dac_setup(struct drm_encoder
*encoder
, int action
)
360 struct drm_device
*dev
= encoder
->dev
;
361 struct radeon_device
*rdev
= dev
->dev_private
;
362 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
363 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
365 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
367 memset(&args
, 0, sizeof(args
));
369 switch (radeon_encoder
->encoder_id
) {
370 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
372 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
374 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
376 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
380 args
.ucAction
= action
;
382 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CRT_SUPPORT
))
383 args
.ucDacStandard
= ATOM_DAC1_PS2
;
384 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
385 args
.ucDacStandard
= ATOM_DAC1_CV
;
387 switch (dac_info
->tv_std
) {
390 case TV_STD_SCART_PAL
:
393 args
.ucDacStandard
= ATOM_DAC1_PAL
;
399 args
.ucDacStandard
= ATOM_DAC1_NTSC
;
403 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
405 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
410 atombios_tv_setup(struct drm_encoder
*encoder
, int action
)
412 struct drm_device
*dev
= encoder
->dev
;
413 struct radeon_device
*rdev
= dev
->dev_private
;
414 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
415 TV_ENCODER_CONTROL_PS_ALLOCATION args
;
417 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
419 memset(&args
, 0, sizeof(args
));
421 index
= GetIndexIntoMasterTable(COMMAND
, TVEncoderControl
);
423 args
.sTVEncoder
.ucAction
= action
;
425 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
426 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_CV
;
428 switch (dac_info
->tv_std
) {
430 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
433 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
;
436 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALM
;
439 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL60
;
442 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSCJ
;
444 case TV_STD_SCART_PAL
:
445 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
; /* ??? */
448 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_SECAM
;
451 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALCN
;
454 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
459 args
.sTVEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
461 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
465 static u8
radeon_atom_get_bpc(struct drm_encoder
*encoder
)
467 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
471 bpc
= radeon_get_monitor_bpc(connector
);
475 return PANEL_BPC_UNDEFINE
;
477 return PANEL_6BIT_PER_COLOR
;
480 return PANEL_8BIT_PER_COLOR
;
482 return PANEL_10BIT_PER_COLOR
;
484 return PANEL_12BIT_PER_COLOR
;
486 return PANEL_16BIT_PER_COLOR
;
490 union dvo_encoder_control
{
491 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds
;
492 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo
;
493 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3
;
494 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4
;
498 atombios_dvo_setup(struct drm_encoder
*encoder
, int action
)
500 struct drm_device
*dev
= encoder
->dev
;
501 struct radeon_device
*rdev
= dev
->dev_private
;
502 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
503 union dvo_encoder_control args
;
504 int index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
507 memset(&args
, 0, sizeof(args
));
509 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
512 /* some R4xx chips have the wrong frev */
513 if (rdev
->family
<= CHIP_RV410
)
521 args
.ext_tmds
.sXTmdsEncoder
.ucEnable
= action
;
523 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
524 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
526 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
530 args
.dvo
.sDVOEncoder
.ucAction
= action
;
531 args
.dvo
.sDVOEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
532 /* DFP1, CRT1, TV1 depending on the type of port */
533 args
.dvo
.sDVOEncoder
.ucDeviceType
= ATOM_DEVICE_DFP1_INDEX
;
535 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
536 args
.dvo
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
|= PANEL_ENCODER_MISC_DUAL
;
540 args
.dvo_v3
.ucAction
= action
;
541 args
.dvo_v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
542 args
.dvo_v3
.ucDVOConfig
= 0; /* XXX */
546 args
.dvo_v4
.ucAction
= action
;
547 args
.dvo_v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
548 args
.dvo_v4
.ucDVOConfig
= 0; /* XXX */
549 args
.dvo_v4
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
552 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
557 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
561 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
564 union lvds_encoder_control
{
565 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1
;
566 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2
;
570 atombios_digital_setup(struct drm_encoder
*encoder
, int action
)
572 struct drm_device
*dev
= encoder
->dev
;
573 struct radeon_device
*rdev
= dev
->dev_private
;
574 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
575 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
576 union lvds_encoder_control args
;
578 int hdmi_detected
= 0;
584 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
587 memset(&args
, 0, sizeof(args
));
589 switch (radeon_encoder
->encoder_id
) {
590 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
591 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
593 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
595 index
= GetIndexIntoMasterTable(COMMAND
, TMDS1EncoderControl
);
597 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
598 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
599 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
601 index
= GetIndexIntoMasterTable(COMMAND
, TMDS2EncoderControl
);
605 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
614 args
.v1
.ucAction
= action
;
616 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
617 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
618 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
619 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
620 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
621 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
622 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
625 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
626 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
627 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
628 /*if (pScrn->rgbBits == 8) */
629 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
635 args
.v2
.ucAction
= action
;
637 if (dig
->coherent_mode
)
638 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_COHERENT
;
641 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
642 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
643 args
.v2
.ucTruncate
= 0;
644 args
.v2
.ucSpatial
= 0;
645 args
.v2
.ucTemporal
= 0;
647 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
648 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
649 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
650 if (dig
->lcd_misc
& ATOM_PANEL_MISC_SPATIAL
) {
651 args
.v2
.ucSpatial
= PANEL_ENCODER_SPATIAL_DITHER_EN
;
652 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
653 args
.v2
.ucSpatial
|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH
;
655 if (dig
->lcd_misc
& ATOM_PANEL_MISC_TEMPORAL
) {
656 args
.v2
.ucTemporal
= PANEL_ENCODER_TEMPORAL_DITHER_EN
;
657 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
658 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH
;
659 if (((dig
->lcd_misc
>> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT
) & 0x3) == 2)
660 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_LEVEL_4
;
664 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
665 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
666 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
670 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
675 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
679 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
683 atombios_get_encoder_mode(struct drm_encoder
*encoder
)
685 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
686 struct drm_connector
*connector
;
687 struct radeon_connector
*radeon_connector
;
688 struct radeon_connector_atom_dig
*dig_connector
;
690 /* dp bridges are always DP */
691 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)
692 return ATOM_ENCODER_MODE_DP
;
694 /* DVO is always DVO */
695 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DVO1
) ||
696 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
))
697 return ATOM_ENCODER_MODE_DVO
;
699 connector
= radeon_get_connector_for_encoder(encoder
);
700 /* if we don't have an active device yet, just use one of
701 * the connectors tied to the encoder.
704 connector
= radeon_get_connector_for_encoder_init(encoder
);
705 radeon_connector
= to_radeon_connector(connector
);
707 switch (connector
->connector_type
) {
708 case DRM_MODE_CONNECTOR_DVII
:
709 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
710 if ((radeon_connector
->audio
== RADEON_AUDIO_ENABLE
) ||
711 (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
712 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
)))
713 return ATOM_ENCODER_MODE_HDMI
;
714 else if (radeon_connector
->use_digital
)
715 return ATOM_ENCODER_MODE_DVI
;
717 return ATOM_ENCODER_MODE_CRT
;
719 case DRM_MODE_CONNECTOR_DVID
:
720 case DRM_MODE_CONNECTOR_HDMIA
:
722 if ((radeon_connector
->audio
== RADEON_AUDIO_ENABLE
) ||
723 (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
724 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
)))
725 return ATOM_ENCODER_MODE_HDMI
;
727 return ATOM_ENCODER_MODE_DVI
;
729 case DRM_MODE_CONNECTOR_LVDS
:
730 return ATOM_ENCODER_MODE_LVDS
;
732 case DRM_MODE_CONNECTOR_DisplayPort
:
733 dig_connector
= radeon_connector
->con_priv
;
734 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
735 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
))
736 return ATOM_ENCODER_MODE_DP
;
737 else if ((radeon_connector
->audio
== RADEON_AUDIO_ENABLE
) ||
738 (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
739 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
)))
740 return ATOM_ENCODER_MODE_HDMI
;
742 return ATOM_ENCODER_MODE_DVI
;
744 case DRM_MODE_CONNECTOR_eDP
:
745 return ATOM_ENCODER_MODE_DP
;
746 case DRM_MODE_CONNECTOR_DVIA
:
747 case DRM_MODE_CONNECTOR_VGA
:
748 return ATOM_ENCODER_MODE_CRT
;
750 case DRM_MODE_CONNECTOR_Composite
:
751 case DRM_MODE_CONNECTOR_SVIDEO
:
752 case DRM_MODE_CONNECTOR_9PinDIN
:
754 return ATOM_ENCODER_MODE_TV
;
755 /*return ATOM_ENCODER_MODE_CV;*/
761 * DIG Encoder/Transmitter Setup
764 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
765 * Supports up to 3 digital outputs
766 * - 2 DIG encoder blocks.
767 * DIG1 can drive UNIPHY link A or link B
768 * DIG2 can drive UNIPHY link B or LVTMA
771 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
772 * Supports up to 5 digital outputs
773 * - 2 DIG encoder blocks.
774 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
777 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
778 * Supports up to 6 digital outputs
779 * - 6 DIG encoder blocks.
780 * - DIG to PHY mapping is hardcoded
781 * DIG1 drives UNIPHY0 link A, A+B
782 * DIG2 drives UNIPHY0 link B
783 * DIG3 drives UNIPHY1 link A, A+B
784 * DIG4 drives UNIPHY1 link B
785 * DIG5 drives UNIPHY2 link A, A+B
786 * DIG6 drives UNIPHY2 link B
789 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
790 * Supports up to 6 digital outputs
791 * - 2 DIG encoder blocks.
793 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
795 * DIG1 drives UNIPHY0/1/2 link A
796 * DIG2 drives UNIPHY0/1/2 link B
799 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
801 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
802 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
803 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
804 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
807 union dig_encoder_control
{
808 DIG_ENCODER_CONTROL_PS_ALLOCATION v1
;
809 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2
;
810 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3
;
811 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4
;
815 atombios_dig_encoder_setup(struct drm_encoder
*encoder
, int action
, int panel_mode
)
817 struct drm_device
*dev
= encoder
->dev
;
818 struct radeon_device
*rdev
= dev
->dev_private
;
819 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
820 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
821 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
822 union dig_encoder_control args
;
826 int dp_lane_count
= 0;
827 int hpd_id
= RADEON_HPD_NONE
;
830 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
831 struct radeon_connector_atom_dig
*dig_connector
=
832 radeon_connector
->con_priv
;
834 dp_clock
= dig_connector
->dp_clock
;
835 dp_lane_count
= dig_connector
->dp_lane_count
;
836 hpd_id
= radeon_connector
->hpd
.hpd
;
839 /* no dig encoder assigned */
840 if (dig
->dig_encoder
== -1)
843 memset(&args
, 0, sizeof(args
));
845 if (ASIC_IS_DCE4(rdev
))
846 index
= GetIndexIntoMasterTable(COMMAND
, DIGxEncoderControl
);
848 if (dig
->dig_encoder
)
849 index
= GetIndexIntoMasterTable(COMMAND
, DIG2EncoderControl
);
851 index
= GetIndexIntoMasterTable(COMMAND
, DIG1EncoderControl
);
854 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
861 args
.v1
.ucAction
= action
;
862 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
863 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
864 args
.v3
.ucPanelMode
= panel_mode
;
866 args
.v1
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
868 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
))
869 args
.v1
.ucLaneNum
= dp_lane_count
;
870 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
871 args
.v1
.ucLaneNum
= 8;
873 args
.v1
.ucLaneNum
= 4;
875 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
) && (dp_clock
== 270000))
876 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
877 switch (radeon_encoder
->encoder_id
) {
878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
879 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
882 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
883 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
885 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
886 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
890 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
892 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
896 args
.v3
.ucAction
= action
;
897 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
898 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
899 args
.v3
.ucPanelMode
= panel_mode
;
901 args
.v3
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
903 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
))
904 args
.v3
.ucLaneNum
= dp_lane_count
;
905 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
906 args
.v3
.ucLaneNum
= 8;
908 args
.v3
.ucLaneNum
= 4;
910 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
) && (dp_clock
== 270000))
911 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
912 args
.v3
.acConfig
.ucDigSel
= dig
->dig_encoder
;
913 args
.v3
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
916 args
.v4
.ucAction
= action
;
917 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
918 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
919 args
.v4
.ucPanelMode
= panel_mode
;
921 args
.v4
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
923 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
))
924 args
.v4
.ucLaneNum
= dp_lane_count
;
925 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
926 args
.v4
.ucLaneNum
= 8;
928 args
.v4
.ucLaneNum
= 4;
930 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
)) {
931 if (dp_clock
== 540000)
932 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
;
933 else if (dp_clock
== 324000)
934 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ
;
935 else if (dp_clock
== 270000)
936 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
;
938 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ
;
940 args
.v4
.acConfig
.ucDigSel
= dig
->dig_encoder
;
941 args
.v4
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
942 if (hpd_id
== RADEON_HPD_NONE
)
943 args
.v4
.ucHPD_ID
= 0;
945 args
.v4
.ucHPD_ID
= hpd_id
+ 1;
948 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
953 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
957 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
961 union dig_transmitter_control
{
962 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
963 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
964 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3
;
965 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4
;
966 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5
;
970 atombios_dig_transmitter_setup(struct drm_encoder
*encoder
, int action
, uint8_t lane_num
, uint8_t lane_set
)
972 struct drm_device
*dev
= encoder
->dev
;
973 struct radeon_device
*rdev
= dev
->dev_private
;
974 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
975 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
976 struct drm_connector
*connector
;
977 union dig_transmitter_control args
;
983 int dp_lane_count
= 0;
984 int connector_object_id
= 0;
985 int igp_lane_info
= 0;
986 int dig_encoder
= dig
->dig_encoder
;
987 int hpd_id
= RADEON_HPD_NONE
;
989 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
990 connector
= radeon_get_connector_for_encoder_init(encoder
);
991 /* just needed to avoid bailing in the encoder check. the encoder
992 * isn't used for init
996 connector
= radeon_get_connector_for_encoder(encoder
);
999 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1000 struct radeon_connector_atom_dig
*dig_connector
=
1001 radeon_connector
->con_priv
;
1003 hpd_id
= radeon_connector
->hpd
.hpd
;
1004 dp_clock
= dig_connector
->dp_clock
;
1005 dp_lane_count
= dig_connector
->dp_lane_count
;
1006 connector_object_id
=
1007 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1008 igp_lane_info
= dig_connector
->igp_lane_info
;
1011 if (encoder
->crtc
) {
1012 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1013 pll_id
= radeon_crtc
->pll_id
;
1016 /* no dig encoder assigned */
1017 if (dig_encoder
== -1)
1020 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)))
1023 memset(&args
, 0, sizeof(args
));
1025 switch (radeon_encoder
->encoder_id
) {
1026 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1027 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1029 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1030 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1031 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1032 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1033 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1035 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1036 index
= GetIndexIntoMasterTable(COMMAND
, LVTMATransmitterControl
);
1040 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1047 args
.v1
.ucAction
= action
;
1048 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1049 args
.v1
.usInitInfo
= cpu_to_le16(connector_object_id
);
1050 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1051 args
.v1
.asMode
.ucLaneSel
= lane_num
;
1052 args
.v1
.asMode
.ucLaneSet
= lane_set
;
1055 args
.v1
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1056 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1057 args
.v1
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1059 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1062 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
1065 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
1067 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
1069 if ((rdev
->flags
& RADEON_IS_IGP
) &&
1070 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_UNIPHY
)) {
1072 !radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
)) {
1073 if (igp_lane_info
& 0x1)
1074 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
1075 else if (igp_lane_info
& 0x2)
1076 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
1077 else if (igp_lane_info
& 0x4)
1078 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
1079 else if (igp_lane_info
& 0x8)
1080 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
1082 if (igp_lane_info
& 0x3)
1083 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
1084 else if (igp_lane_info
& 0xc)
1085 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
1090 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
1092 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
1095 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1096 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1097 if (dig
->coherent_mode
)
1098 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1099 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1100 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
1104 args
.v2
.ucAction
= action
;
1105 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1106 args
.v2
.usInitInfo
= cpu_to_le16(connector_object_id
);
1107 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1108 args
.v2
.asMode
.ucLaneSel
= lane_num
;
1109 args
.v2
.asMode
.ucLaneSet
= lane_set
;
1112 args
.v2
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1113 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1114 args
.v2
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1116 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1119 args
.v2
.acConfig
.ucEncoderSel
= dig_encoder
;
1121 args
.v2
.acConfig
.ucLinkSel
= 1;
1123 switch (radeon_encoder
->encoder_id
) {
1124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1125 args
.v2
.acConfig
.ucTransmitterSel
= 0;
1127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1128 args
.v2
.acConfig
.ucTransmitterSel
= 1;
1130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1131 args
.v2
.acConfig
.ucTransmitterSel
= 2;
1136 args
.v2
.acConfig
.fCoherentMode
= 1;
1137 args
.v2
.acConfig
.fDPConnector
= 1;
1138 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1139 if (dig
->coherent_mode
)
1140 args
.v2
.acConfig
.fCoherentMode
= 1;
1141 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1142 args
.v2
.acConfig
.fDualLinkConnector
= 1;
1146 args
.v3
.ucAction
= action
;
1147 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1148 args
.v3
.usInitInfo
= cpu_to_le16(connector_object_id
);
1149 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1150 args
.v3
.asMode
.ucLaneSel
= lane_num
;
1151 args
.v3
.asMode
.ucLaneSet
= lane_set
;
1154 args
.v3
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1155 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1156 args
.v3
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1158 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1162 args
.v3
.ucLaneNum
= dp_lane_count
;
1163 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1164 args
.v3
.ucLaneNum
= 8;
1166 args
.v3
.ucLaneNum
= 4;
1169 args
.v3
.acConfig
.ucLinkSel
= 1;
1170 if (dig_encoder
& 1)
1171 args
.v3
.acConfig
.ucEncoderSel
= 1;
1173 /* Select the PLL for the PHY
1174 * DP PHY should be clocked from external src if there is
1177 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1178 if (is_dp
&& rdev
->clock
.dp_extclk
)
1179 args
.v3
.acConfig
.ucRefClkSource
= 2; /* external src */
1181 args
.v3
.acConfig
.ucRefClkSource
= pll_id
;
1183 switch (radeon_encoder
->encoder_id
) {
1184 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1185 args
.v3
.acConfig
.ucTransmitterSel
= 0;
1187 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1188 args
.v3
.acConfig
.ucTransmitterSel
= 1;
1190 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1191 args
.v3
.acConfig
.ucTransmitterSel
= 2;
1196 args
.v3
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1197 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1198 if (dig
->coherent_mode
)
1199 args
.v3
.acConfig
.fCoherentMode
= 1;
1200 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1201 args
.v3
.acConfig
.fDualLinkConnector
= 1;
1205 args
.v4
.ucAction
= action
;
1206 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1207 args
.v4
.usInitInfo
= cpu_to_le16(connector_object_id
);
1208 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1209 args
.v4
.asMode
.ucLaneSel
= lane_num
;
1210 args
.v4
.asMode
.ucLaneSet
= lane_set
;
1213 args
.v4
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1214 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1215 args
.v4
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1217 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1221 args
.v4
.ucLaneNum
= dp_lane_count
;
1222 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1223 args
.v4
.ucLaneNum
= 8;
1225 args
.v4
.ucLaneNum
= 4;
1228 args
.v4
.acConfig
.ucLinkSel
= 1;
1229 if (dig_encoder
& 1)
1230 args
.v4
.acConfig
.ucEncoderSel
= 1;
1232 /* Select the PLL for the PHY
1233 * DP PHY should be clocked from external src if there is
1236 /* On DCE5 DCPLL usually generates the DP ref clock */
1238 if (rdev
->clock
.dp_extclk
)
1239 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_EXTCLK
;
1241 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_DCPLL
;
1243 args
.v4
.acConfig
.ucRefClkSource
= pll_id
;
1245 switch (radeon_encoder
->encoder_id
) {
1246 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1247 args
.v4
.acConfig
.ucTransmitterSel
= 0;
1249 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1250 args
.v4
.acConfig
.ucTransmitterSel
= 1;
1252 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1253 args
.v4
.acConfig
.ucTransmitterSel
= 2;
1258 args
.v4
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1259 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1260 if (dig
->coherent_mode
)
1261 args
.v4
.acConfig
.fCoherentMode
= 1;
1262 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1263 args
.v4
.acConfig
.fDualLinkConnector
= 1;
1267 args
.v5
.ucAction
= action
;
1269 args
.v5
.usSymClock
= cpu_to_le16(dp_clock
/ 10);
1271 args
.v5
.usSymClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1273 switch (radeon_encoder
->encoder_id
) {
1274 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1276 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1278 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1280 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1282 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1284 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1286 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1288 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1290 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1293 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYG
;
1297 args
.v5
.ucLaneNum
= dp_lane_count
;
1298 else if (radeon_encoder
->pixel_clock
> 165000)
1299 args
.v5
.ucLaneNum
= 8;
1301 args
.v5
.ucLaneNum
= 4;
1302 args
.v5
.ucConnObjId
= connector_object_id
;
1303 args
.v5
.ucDigMode
= atombios_get_encoder_mode(encoder
);
1305 if (is_dp
&& rdev
->clock
.dp_extclk
)
1306 args
.v5
.asConfig
.ucPhyClkSrcId
= ENCODER_REFCLK_SRC_EXTCLK
;
1308 args
.v5
.asConfig
.ucPhyClkSrcId
= pll_id
;
1311 args
.v5
.asConfig
.ucCoherentMode
= 1; /* DP requires coherent */
1312 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1313 if (dig
->coherent_mode
)
1314 args
.v5
.asConfig
.ucCoherentMode
= 1;
1316 if (hpd_id
== RADEON_HPD_NONE
)
1317 args
.v5
.asConfig
.ucHPDSel
= 0;
1319 args
.v5
.asConfig
.ucHPDSel
= hpd_id
+ 1;
1320 args
.v5
.ucDigEncoderSel
= 1 << dig_encoder
;
1321 args
.v5
.ucDPLaneSet
= lane_set
;
1324 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1329 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1333 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1337 atombios_set_edp_panel_power(struct drm_connector
*connector
, int action
)
1339 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1340 struct drm_device
*dev
= radeon_connector
->base
.dev
;
1341 struct radeon_device
*rdev
= dev
->dev_private
;
1342 union dig_transmitter_control args
;
1343 int index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1346 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
1349 if (!ASIC_IS_DCE4(rdev
))
1352 if ((action
!= ATOM_TRANSMITTER_ACTION_POWER_ON
) &&
1353 (action
!= ATOM_TRANSMITTER_ACTION_POWER_OFF
))
1356 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1359 memset(&args
, 0, sizeof(args
));
1361 args
.v1
.ucAction
= action
;
1363 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1365 /* wait for the panel to power up */
1366 if (action
== ATOM_TRANSMITTER_ACTION_POWER_ON
) {
1369 for (i
= 0; i
< 300; i
++) {
1370 if (radeon_hpd_sense(rdev
, radeon_connector
->hpd
.hpd
))
1380 union external_encoder_control
{
1381 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1
;
1382 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3
;
1386 atombios_external_encoder_setup(struct drm_encoder
*encoder
,
1387 struct drm_encoder
*ext_encoder
,
1390 struct drm_device
*dev
= encoder
->dev
;
1391 struct radeon_device
*rdev
= dev
->dev_private
;
1392 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1393 struct radeon_encoder
*ext_radeon_encoder
= to_radeon_encoder(ext_encoder
);
1394 union external_encoder_control args
;
1395 struct drm_connector
*connector
;
1396 int index
= GetIndexIntoMasterTable(COMMAND
, ExternalEncoderControl
);
1399 int dp_lane_count
= 0;
1400 int connector_object_id
= 0;
1401 u32 ext_enum
= (ext_radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1403 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1404 connector
= radeon_get_connector_for_encoder_init(encoder
);
1406 connector
= radeon_get_connector_for_encoder(encoder
);
1409 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1410 struct radeon_connector_atom_dig
*dig_connector
=
1411 radeon_connector
->con_priv
;
1413 dp_clock
= dig_connector
->dp_clock
;
1414 dp_lane_count
= dig_connector
->dp_lane_count
;
1415 connector_object_id
=
1416 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1419 memset(&args
, 0, sizeof(args
));
1421 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1426 /* no params on frev 1 */
1432 args
.v1
.sDigEncoder
.ucAction
= action
;
1433 args
.v1
.sDigEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1434 args
.v1
.sDigEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1436 if (ENCODER_MODE_IS_DP(args
.v1
.sDigEncoder
.ucEncoderMode
)) {
1437 if (dp_clock
== 270000)
1438 args
.v1
.sDigEncoder
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
1439 args
.v1
.sDigEncoder
.ucLaneNum
= dp_lane_count
;
1440 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1441 args
.v1
.sDigEncoder
.ucLaneNum
= 8;
1443 args
.v1
.sDigEncoder
.ucLaneNum
= 4;
1446 args
.v3
.sExtEncoder
.ucAction
= action
;
1447 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1448 args
.v3
.sExtEncoder
.usConnectorId
= cpu_to_le16(connector_object_id
);
1450 args
.v3
.sExtEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1451 args
.v3
.sExtEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1453 if (ENCODER_MODE_IS_DP(args
.v3
.sExtEncoder
.ucEncoderMode
)) {
1454 if (dp_clock
== 270000)
1455 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
1456 else if (dp_clock
== 540000)
1457 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
;
1458 args
.v3
.sExtEncoder
.ucLaneNum
= dp_lane_count
;
1459 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1460 args
.v3
.sExtEncoder
.ucLaneNum
= 8;
1462 args
.v3
.sExtEncoder
.ucLaneNum
= 4;
1464 case GRAPH_OBJECT_ENUM_ID1
:
1465 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
;
1467 case GRAPH_OBJECT_ENUM_ID2
:
1468 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
;
1470 case GRAPH_OBJECT_ENUM_ID3
:
1471 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
;
1474 args
.v3
.sExtEncoder
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
1477 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1482 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1485 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1489 atombios_yuv_setup(struct drm_encoder
*encoder
, bool enable
)
1491 struct drm_device
*dev
= encoder
->dev
;
1492 struct radeon_device
*rdev
= dev
->dev_private
;
1493 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1494 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1495 ENABLE_YUV_PS_ALLOCATION args
;
1496 int index
= GetIndexIntoMasterTable(COMMAND
, EnableYUV
);
1499 memset(&args
, 0, sizeof(args
));
1501 if (rdev
->family
>= CHIP_R600
)
1502 reg
= R600_BIOS_3_SCRATCH
;
1504 reg
= RADEON_BIOS_3_SCRATCH
;
1506 /* XXX: fix up scratch reg handling */
1508 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1509 WREG32(reg
, (ATOM_S3_TV1_ACTIVE
|
1510 (radeon_crtc
->crtc_id
<< 18)));
1511 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1512 WREG32(reg
, (ATOM_S3_CV_ACTIVE
| (radeon_crtc
->crtc_id
<< 24)));
1517 args
.ucEnable
= ATOM_ENABLE
;
1518 args
.ucCRTC
= radeon_crtc
->crtc_id
;
1520 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1526 radeon_atom_encoder_dpms_avivo(struct drm_encoder
*encoder
, int mode
)
1528 struct drm_device
*dev
= encoder
->dev
;
1529 struct radeon_device
*rdev
= dev
->dev_private
;
1530 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1531 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
1534 memset(&args
, 0, sizeof(args
));
1536 switch (radeon_encoder
->encoder_id
) {
1537 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1538 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1539 index
= GetIndexIntoMasterTable(COMMAND
, TMDSAOutputControl
);
1541 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1542 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1543 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1544 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1546 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1547 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1549 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1550 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1551 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1553 index
= GetIndexIntoMasterTable(COMMAND
, LVTMAOutputControl
);
1555 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1556 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1557 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1558 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1559 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1560 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1562 index
= GetIndexIntoMasterTable(COMMAND
, DAC1OutputControl
);
1564 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1565 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1566 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1567 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1568 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1569 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1571 index
= GetIndexIntoMasterTable(COMMAND
, DAC2OutputControl
);
1578 case DRM_MODE_DPMS_ON
:
1579 args
.ucAction
= ATOM_ENABLE
;
1580 /* workaround for DVOOutputControl on some RS690 systems */
1581 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DDI
) {
1582 u32 reg
= RREG32(RADEON_BIOS_3_SCRATCH
);
1583 WREG32(RADEON_BIOS_3_SCRATCH
, reg
& ~ATOM_S3_DFP2I_ACTIVE
);
1584 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1585 WREG32(RADEON_BIOS_3_SCRATCH
, reg
);
1587 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1588 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1589 args
.ucAction
= ATOM_LCD_BLON
;
1590 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1593 case DRM_MODE_DPMS_STANDBY
:
1594 case DRM_MODE_DPMS_SUSPEND
:
1595 case DRM_MODE_DPMS_OFF
:
1596 args
.ucAction
= ATOM_DISABLE
;
1597 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1598 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1599 args
.ucAction
= ATOM_LCD_BLOFF
;
1600 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1607 radeon_atom_encoder_dpms_dig(struct drm_encoder
*encoder
, int mode
)
1609 struct drm_device
*dev
= encoder
->dev
;
1610 struct radeon_device
*rdev
= dev
->dev_private
;
1611 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1612 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
1613 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
1614 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1615 struct radeon_connector
*radeon_connector
= NULL
;
1616 struct radeon_connector_atom_dig
*radeon_dig_connector
= NULL
;
1619 radeon_connector
= to_radeon_connector(connector
);
1620 radeon_dig_connector
= radeon_connector
->con_priv
;
1624 case DRM_MODE_DPMS_ON
:
1625 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE5(rdev
)) {
1627 dig
->panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
1629 dig
->panel_mode
= radeon_dp_get_panel_mode(encoder
, connector
);
1631 /* setup and enable the encoder */
1632 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1633 atombios_dig_encoder_setup(encoder
,
1634 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
,
1637 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
))
1638 atombios_external_encoder_setup(encoder
, ext_encoder
,
1639 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
);
1641 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1642 } else if (ASIC_IS_DCE4(rdev
)) {
1643 /* setup and enable the encoder */
1644 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1645 /* enable the transmitter */
1646 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1647 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT
, 0, 0);
1649 /* setup and enable the encoder and transmitter */
1650 atombios_dig_encoder_setup(encoder
, ATOM_ENABLE
, 0);
1651 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_SETUP
, 0, 0);
1652 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1653 /* some dce3.x boards have a bug in their transmitter control table.
1654 * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1655 * does the same thing and more.
1657 if ((rdev
->family
!= CHIP_RV710
) && (rdev
->family
!= CHIP_RV730
) &&
1658 (rdev
->family
!= CHIP_RS880
))
1659 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT
, 0, 0);
1661 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1662 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1663 atombios_set_edp_panel_power(connector
,
1664 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1665 radeon_dig_connector
->edp_on
= true;
1667 radeon_dp_link_train(encoder
, connector
);
1668 if (ASIC_IS_DCE4(rdev
))
1669 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_ON
, 0);
1671 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1672 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
1674 case DRM_MODE_DPMS_STANDBY
:
1675 case DRM_MODE_DPMS_SUSPEND
:
1676 case DRM_MODE_DPMS_OFF
:
1677 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE5(rdev
)) {
1678 /* disable the transmitter */
1679 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1680 } else if (ASIC_IS_DCE4(rdev
)) {
1681 /* disable the transmitter */
1682 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT
, 0, 0);
1683 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1685 /* disable the encoder and transmitter */
1686 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT
, 0, 0);
1687 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1688 atombios_dig_encoder_setup(encoder
, ATOM_DISABLE
, 0);
1690 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1691 if (ASIC_IS_DCE4(rdev
))
1692 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_OFF
, 0);
1693 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1694 atombios_set_edp_panel_power(connector
,
1695 ATOM_TRANSMITTER_ACTION_POWER_OFF
);
1696 radeon_dig_connector
->edp_on
= false;
1699 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1700 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
1706 radeon_atom_encoder_dpms_ext(struct drm_encoder
*encoder
,
1707 struct drm_encoder
*ext_encoder
,
1710 struct drm_device
*dev
= encoder
->dev
;
1711 struct radeon_device
*rdev
= dev
->dev_private
;
1714 case DRM_MODE_DPMS_ON
:
1716 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)) {
1717 atombios_external_encoder_setup(encoder
, ext_encoder
,
1718 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT
);
1719 atombios_external_encoder_setup(encoder
, ext_encoder
,
1720 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF
);
1722 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_ENABLE
);
1724 case DRM_MODE_DPMS_STANDBY
:
1725 case DRM_MODE_DPMS_SUSPEND
:
1726 case DRM_MODE_DPMS_OFF
:
1727 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)) {
1728 atombios_external_encoder_setup(encoder
, ext_encoder
,
1729 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING
);
1730 atombios_external_encoder_setup(encoder
, ext_encoder
,
1731 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT
);
1733 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_DISABLE
);
1739 radeon_atom_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
1741 struct drm_device
*dev
= encoder
->dev
;
1742 struct radeon_device
*rdev
= dev
->dev_private
;
1743 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1744 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
1746 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1747 radeon_encoder
->encoder_id
, mode
, radeon_encoder
->devices
,
1748 radeon_encoder
->active_device
);
1749 switch (radeon_encoder
->encoder_id
) {
1750 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1751 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1752 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1753 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1754 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1755 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1756 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1757 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1758 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1760 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1761 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1762 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1763 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1764 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1765 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1767 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1768 if (ASIC_IS_DCE5(rdev
)) {
1770 case DRM_MODE_DPMS_ON
:
1771 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
1773 case DRM_MODE_DPMS_STANDBY
:
1774 case DRM_MODE_DPMS_SUSPEND
:
1775 case DRM_MODE_DPMS_OFF
:
1776 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
1779 } else if (ASIC_IS_DCE3(rdev
))
1780 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1782 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1784 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1785 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1786 if (ASIC_IS_DCE5(rdev
)) {
1788 case DRM_MODE_DPMS_ON
:
1789 atombios_dac_setup(encoder
, ATOM_ENABLE
);
1791 case DRM_MODE_DPMS_STANDBY
:
1792 case DRM_MODE_DPMS_SUSPEND
:
1793 case DRM_MODE_DPMS_OFF
:
1794 atombios_dac_setup(encoder
, ATOM_DISABLE
);
1798 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1805 radeon_atom_encoder_dpms_ext(encoder
, ext_encoder
, mode
);
1807 radeon_atombios_encoder_dpms_scratch_regs(encoder
, (mode
== DRM_MODE_DPMS_ON
) ? true : false);
1811 union crtc_source_param
{
1812 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1813 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1817 atombios_set_encoder_crtc_source(struct drm_encoder
*encoder
)
1819 struct drm_device
*dev
= encoder
->dev
;
1820 struct radeon_device
*rdev
= dev
->dev_private
;
1821 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1822 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1823 union crtc_source_param args
;
1824 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1826 struct radeon_encoder_atom_dig
*dig
;
1828 memset(&args
, 0, sizeof(args
));
1830 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1838 if (ASIC_IS_AVIVO(rdev
))
1839 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1841 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) {
1842 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1844 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
<< 2;
1847 switch (radeon_encoder
->encoder_id
) {
1848 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1849 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1850 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1852 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1853 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1854 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1855 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1857 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1859 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1860 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1861 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1862 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1864 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1865 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1866 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1867 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1868 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1869 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1871 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1873 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1874 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1875 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1876 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1877 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1878 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1880 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1885 args
.v2
.ucCRTC
= radeon_crtc
->crtc_id
;
1886 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1887 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1889 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1890 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1891 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1892 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1894 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1896 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1897 switch (radeon_encoder
->encoder_id
) {
1898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1901 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1902 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1903 dig
= radeon_encoder
->enc_priv
;
1904 switch (dig
->dig_encoder
) {
1906 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1909 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1912 args
.v2
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1915 args
.v2
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1918 args
.v2
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1921 args
.v2
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1924 args
.v2
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1928 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1929 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1931 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1932 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1933 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1934 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1935 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1937 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1939 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1940 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1941 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1942 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1943 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1945 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1952 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1956 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1958 /* update scratch regs with new routing */
1959 radeon_atombios_encoder_crtc_scratch_regs(encoder
, radeon_crtc
->crtc_id
);
1963 atombios_apply_encoder_quirks(struct drm_encoder
*encoder
,
1964 struct drm_display_mode
*mode
)
1966 struct drm_device
*dev
= encoder
->dev
;
1967 struct radeon_device
*rdev
= dev
->dev_private
;
1968 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1969 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1971 /* Funky macbooks */
1972 if ((dev
->pdev
->device
== 0x71C5) &&
1973 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
1974 (dev
->pdev
->subsystem_device
== 0x0080)) {
1975 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1976 uint32_t lvtma_bit_depth_control
= RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
);
1978 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
;
1979 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
;
1981 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
, lvtma_bit_depth_control
);
1985 /* set scaler clears this on some chips */
1986 if (ASIC_IS_AVIVO(rdev
) &&
1987 (!(radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)))) {
1988 if (ASIC_IS_DCE8(rdev
)) {
1989 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1990 WREG32(CIK_LB_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1993 WREG32(CIK_LB_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
1994 } else if (ASIC_IS_DCE4(rdev
)) {
1995 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1996 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1997 EVERGREEN_INTERLEAVE_EN
);
1999 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
2001 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2002 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
2003 AVIVO_D1MODE_INTERLEAVE_EN
);
2005 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
2010 static int radeon_atom_pick_dig_encoder(struct drm_encoder
*encoder
)
2012 struct drm_device
*dev
= encoder
->dev
;
2013 struct radeon_device
*rdev
= dev
->dev_private
;
2014 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
2015 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2016 struct drm_encoder
*test_encoder
;
2017 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
2018 uint32_t dig_enc_in_use
= 0;
2020 if (ASIC_IS_DCE6(rdev
)) {
2022 switch (radeon_encoder
->encoder_id
) {
2023 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2029 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2035 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2041 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2045 } else if (ASIC_IS_DCE4(rdev
)) {
2047 if (ASIC_IS_DCE41(rdev
) && !ASIC_IS_DCE61(rdev
)) {
2048 /* ontario follows DCE4 */
2049 if (rdev
->family
== CHIP_PALM
) {
2055 /* llano follows DCE3.2 */
2056 return radeon_crtc
->crtc_id
;
2058 switch (radeon_encoder
->encoder_id
) {
2059 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2065 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2071 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2081 /* on DCE32 and encoder can driver any block so just crtc id */
2082 if (ASIC_IS_DCE32(rdev
)) {
2083 return radeon_crtc
->crtc_id
;
2086 /* on DCE3 - LVTMA can only be driven by DIGB */
2087 list_for_each_entry(test_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2088 struct radeon_encoder
*radeon_test_encoder
;
2090 if (encoder
== test_encoder
)
2093 if (!radeon_encoder_is_digital(test_encoder
))
2096 radeon_test_encoder
= to_radeon_encoder(test_encoder
);
2097 dig
= radeon_test_encoder
->enc_priv
;
2099 if (dig
->dig_encoder
>= 0)
2100 dig_enc_in_use
|= (1 << dig
->dig_encoder
);
2103 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
) {
2104 if (dig_enc_in_use
& 0x2)
2105 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2108 if (!(dig_enc_in_use
& 1))
2113 /* This only needs to be called once at startup */
2115 radeon_atom_encoder_init(struct radeon_device
*rdev
)
2117 struct drm_device
*dev
= rdev
->ddev
;
2118 struct drm_encoder
*encoder
;
2120 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2121 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2122 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2124 switch (radeon_encoder
->encoder_id
) {
2125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2128 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2129 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2130 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_INIT
, 0, 0);
2136 if (ext_encoder
&& (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)))
2137 atombios_external_encoder_setup(encoder
, ext_encoder
,
2138 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
);
2143 radeon_atom_encoder_mode_set(struct drm_encoder
*encoder
,
2144 struct drm_display_mode
*mode
,
2145 struct drm_display_mode
*adjusted_mode
)
2147 struct drm_device
*dev
= encoder
->dev
;
2148 struct radeon_device
*rdev
= dev
->dev_private
;
2149 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2151 radeon_encoder
->pixel_clock
= adjusted_mode
->clock
;
2153 /* need to call this here rather than in prepare() since we need some crtc info */
2154 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2156 if (ASIC_IS_AVIVO(rdev
) && !ASIC_IS_DCE4(rdev
)) {
2157 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
| ATOM_DEVICE_TV_SUPPORT
))
2158 atombios_yuv_setup(encoder
, true);
2160 atombios_yuv_setup(encoder
, false);
2163 switch (radeon_encoder
->encoder_id
) {
2164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2166 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2167 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2168 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_ENABLE
);
2170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2174 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2175 /* handled in dpms */
2177 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2178 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2179 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2180 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
2182 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2183 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2184 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2185 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2186 atombios_dac_setup(encoder
, ATOM_ENABLE
);
2187 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) {
2188 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2189 atombios_tv_setup(encoder
, ATOM_ENABLE
);
2191 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2196 atombios_apply_encoder_quirks(encoder
, adjusted_mode
);
2198 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
2199 if (rdev
->asic
->display
.hdmi_enable
)
2200 radeon_hdmi_enable(rdev
, encoder
, true);
2201 if (rdev
->asic
->display
.hdmi_setmode
)
2202 radeon_hdmi_setmode(rdev
, encoder
, adjusted_mode
);
2207 atombios_dac_load_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2209 struct drm_device
*dev
= encoder
->dev
;
2210 struct radeon_device
*rdev
= dev
->dev_private
;
2211 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2212 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2214 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
2215 ATOM_DEVICE_CV_SUPPORT
|
2216 ATOM_DEVICE_CRT_SUPPORT
)) {
2217 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
2218 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
2221 memset(&args
, 0, sizeof(args
));
2223 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2226 args
.sDacload
.ucMisc
= 0;
2228 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
2229 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
2230 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
2232 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
2234 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
2235 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
2236 else if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
2237 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
2238 else if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2239 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
2241 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2242 } else if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2243 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
2245 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2248 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2255 static enum drm_connector_status
2256 radeon_atom_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2258 struct drm_device
*dev
= encoder
->dev
;
2259 struct radeon_device
*rdev
= dev
->dev_private
;
2260 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2261 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2262 uint32_t bios_0_scratch
;
2264 if (!atombios_dac_load_detect(encoder
, connector
)) {
2265 DRM_DEBUG_KMS("detect returned false \n");
2266 return connector_status_unknown
;
2269 if (rdev
->family
>= CHIP_R600
)
2270 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2272 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2274 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2275 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2276 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2277 return connector_status_connected
;
2279 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2280 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2281 return connector_status_connected
;
2283 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2284 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2285 return connector_status_connected
;
2287 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2288 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2289 return connector_status_connected
; /* CTV */
2290 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2291 return connector_status_connected
; /* STV */
2293 return connector_status_disconnected
;
2296 static enum drm_connector_status
2297 radeon_atom_dig_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2299 struct drm_device
*dev
= encoder
->dev
;
2300 struct radeon_device
*rdev
= dev
->dev_private
;
2301 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2302 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2303 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2306 if (!ASIC_IS_DCE4(rdev
))
2307 return connector_status_unknown
;
2310 return connector_status_unknown
;
2312 if ((radeon_connector
->devices
& ATOM_DEVICE_CRT_SUPPORT
) == 0)
2313 return connector_status_unknown
;
2315 /* load detect on the dp bridge */
2316 atombios_external_encoder_setup(encoder
, ext_encoder
,
2317 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION
);
2319 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2321 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2322 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2323 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2324 return connector_status_connected
;
2326 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2327 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2328 return connector_status_connected
;
2330 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2331 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2332 return connector_status_connected
;
2334 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2335 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2336 return connector_status_connected
; /* CTV */
2337 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2338 return connector_status_connected
; /* STV */
2340 return connector_status_disconnected
;
2344 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder
*encoder
)
2346 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2349 /* ddc_setup on the dp bridge */
2350 atombios_external_encoder_setup(encoder
, ext_encoder
,
2351 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP
);
2355 static void radeon_atom_encoder_prepare(struct drm_encoder
*encoder
)
2357 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
2358 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2359 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
2361 if ((radeon_encoder
->active_device
&
2362 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
2363 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) !=
2364 ENCODER_OBJECT_ID_NONE
)) {
2365 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
2367 dig
->dig_encoder
= radeon_atom_pick_dig_encoder(encoder
);
2368 if (radeon_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
) {
2369 if (rdev
->family
>= CHIP_R600
)
2370 dig
->afmt
= rdev
->mode_info
.afmt
[dig
->dig_encoder
];
2372 /* RS600/690/740 have only 1 afmt block */
2373 dig
->afmt
= rdev
->mode_info
.afmt
[0];
2378 radeon_atom_output_lock(encoder
, true);
2381 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2383 /* select the clock/data port if it uses a router */
2384 if (radeon_connector
->router
.cd_valid
)
2385 radeon_router_select_cd_port(radeon_connector
);
2387 /* turn eDP panel on for mode set */
2388 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
2389 atombios_set_edp_panel_power(connector
,
2390 ATOM_TRANSMITTER_ACTION_POWER_ON
);
2393 /* this is needed for the pll/ss setup to work correctly in some cases */
2394 atombios_set_encoder_crtc_source(encoder
);
2397 static void radeon_atom_encoder_commit(struct drm_encoder
*encoder
)
2399 /* need to call this here as we need the crtc set up */
2400 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
2401 radeon_atom_output_lock(encoder
, false);
2404 static void radeon_atom_encoder_disable(struct drm_encoder
*encoder
)
2406 struct drm_device
*dev
= encoder
->dev
;
2407 struct radeon_device
*rdev
= dev
->dev_private
;
2408 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2409 struct radeon_encoder_atom_dig
*dig
;
2411 /* check for pre-DCE3 cards with shared encoders;
2412 * can't really use the links individually, so don't disable
2413 * the encoder if it's in use by another connector
2415 if (!ASIC_IS_DCE3(rdev
)) {
2416 struct drm_encoder
*other_encoder
;
2417 struct radeon_encoder
*other_radeon_encoder
;
2419 list_for_each_entry(other_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2420 other_radeon_encoder
= to_radeon_encoder(other_encoder
);
2421 if ((radeon_encoder
->encoder_id
== other_radeon_encoder
->encoder_id
) &&
2422 drm_helper_encoder_in_use(other_encoder
))
2427 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2429 switch (radeon_encoder
->encoder_id
) {
2430 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2431 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2432 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2433 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2434 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_DISABLE
);
2436 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2437 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2438 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2439 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2440 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2441 /* handled in dpms */
2443 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2444 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2445 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2446 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
2448 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2449 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2450 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2451 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2452 atombios_dac_setup(encoder
, ATOM_DISABLE
);
2453 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2454 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2459 if (radeon_encoder_is_digital(encoder
)) {
2460 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
2461 if (rdev
->asic
->display
.hdmi_enable
)
2462 radeon_hdmi_enable(rdev
, encoder
, false);
2464 dig
= radeon_encoder
->enc_priv
;
2465 dig
->dig_encoder
= -1;
2467 radeon_encoder
->active_device
= 0;
2470 /* these are handled by the primary encoders */
2471 static void radeon_atom_ext_prepare(struct drm_encoder
*encoder
)
2476 static void radeon_atom_ext_commit(struct drm_encoder
*encoder
)
2482 radeon_atom_ext_mode_set(struct drm_encoder
*encoder
,
2483 struct drm_display_mode
*mode
,
2484 struct drm_display_mode
*adjusted_mode
)
2489 static void radeon_atom_ext_disable(struct drm_encoder
*encoder
)
2495 radeon_atom_ext_dpms(struct drm_encoder
*encoder
, int mode
)
2500 static bool radeon_atom_ext_mode_fixup(struct drm_encoder
*encoder
,
2501 const struct drm_display_mode
*mode
,
2502 struct drm_display_mode
*adjusted_mode
)
2507 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs
= {
2508 .dpms
= radeon_atom_ext_dpms
,
2509 .mode_fixup
= radeon_atom_ext_mode_fixup
,
2510 .prepare
= radeon_atom_ext_prepare
,
2511 .mode_set
= radeon_atom_ext_mode_set
,
2512 .commit
= radeon_atom_ext_commit
,
2513 .disable
= radeon_atom_ext_disable
,
2514 /* no detect for TMDS/LVDS yet */
2517 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs
= {
2518 .dpms
= radeon_atom_encoder_dpms
,
2519 .mode_fixup
= radeon_atom_mode_fixup
,
2520 .prepare
= radeon_atom_encoder_prepare
,
2521 .mode_set
= radeon_atom_encoder_mode_set
,
2522 .commit
= radeon_atom_encoder_commit
,
2523 .disable
= radeon_atom_encoder_disable
,
2524 .detect
= radeon_atom_dig_detect
,
2527 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs
= {
2528 .dpms
= radeon_atom_encoder_dpms
,
2529 .mode_fixup
= radeon_atom_mode_fixup
,
2530 .prepare
= radeon_atom_encoder_prepare
,
2531 .mode_set
= radeon_atom_encoder_mode_set
,
2532 .commit
= radeon_atom_encoder_commit
,
2533 .detect
= radeon_atom_dac_detect
,
2536 void radeon_enc_destroy(struct drm_encoder
*encoder
)
2538 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2539 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2540 radeon_atom_backlight_exit(radeon_encoder
);
2541 kfree(radeon_encoder
->enc_priv
);
2542 drm_encoder_cleanup(encoder
);
2543 kfree(radeon_encoder
);
2546 static const struct drm_encoder_funcs radeon_atom_enc_funcs
= {
2547 .destroy
= radeon_enc_destroy
,
2550 static struct radeon_encoder_atom_dac
*
2551 radeon_atombios_set_dac_info(struct radeon_encoder
*radeon_encoder
)
2553 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
2554 struct radeon_device
*rdev
= dev
->dev_private
;
2555 struct radeon_encoder_atom_dac
*dac
= kzalloc(sizeof(struct radeon_encoder_atom_dac
), GFP_KERNEL
);
2560 dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
2564 static struct radeon_encoder_atom_dig
*
2565 radeon_atombios_set_dig_info(struct radeon_encoder
*radeon_encoder
)
2567 int encoder_enum
= (radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2568 struct radeon_encoder_atom_dig
*dig
= kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
2573 /* coherent mode by default */
2574 dig
->coherent_mode
= true;
2575 dig
->dig_encoder
= -1;
2577 if (encoder_enum
== 2)
2586 radeon_add_atom_encoder(struct drm_device
*dev
,
2587 uint32_t encoder_enum
,
2588 uint32_t supported_device
,
2591 struct radeon_device
*rdev
= dev
->dev_private
;
2592 struct drm_encoder
*encoder
;
2593 struct radeon_encoder
*radeon_encoder
;
2595 /* see if we already added it */
2596 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2597 radeon_encoder
= to_radeon_encoder(encoder
);
2598 if (radeon_encoder
->encoder_enum
== encoder_enum
) {
2599 radeon_encoder
->devices
|= supported_device
;
2606 radeon_encoder
= kzalloc(sizeof(struct radeon_encoder
), GFP_KERNEL
);
2607 if (!radeon_encoder
)
2610 encoder
= &radeon_encoder
->base
;
2611 switch (rdev
->num_crtc
) {
2613 encoder
->possible_crtcs
= 0x1;
2617 encoder
->possible_crtcs
= 0x3;
2620 encoder
->possible_crtcs
= 0xf;
2623 encoder
->possible_crtcs
= 0x3f;
2627 radeon_encoder
->enc_priv
= NULL
;
2629 radeon_encoder
->encoder_enum
= encoder_enum
;
2630 radeon_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
2631 radeon_encoder
->devices
= supported_device
;
2632 radeon_encoder
->rmx_type
= RMX_OFF
;
2633 radeon_encoder
->underscan_type
= UNDERSCAN_OFF
;
2634 radeon_encoder
->is_ext_encoder
= false;
2635 radeon_encoder
->caps
= caps
;
2637 switch (radeon_encoder
->encoder_id
) {
2638 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2639 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2640 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2641 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2642 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2643 radeon_encoder
->rmx_type
= RMX_FULL
;
2644 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2645 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2647 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2648 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2650 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2652 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2653 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2654 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2655 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2657 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2658 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2659 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2660 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TVDAC
);
2661 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2662 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2664 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2665 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2666 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2667 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2668 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2669 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2670 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2671 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2672 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2673 radeon_encoder
->rmx_type
= RMX_FULL
;
2674 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2675 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2676 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
2677 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2678 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2680 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2681 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2683 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2685 case ENCODER_OBJECT_ID_SI170B
:
2686 case ENCODER_OBJECT_ID_CH7303
:
2687 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
2688 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
2689 case ENCODER_OBJECT_ID_TITFP513
:
2690 case ENCODER_OBJECT_ID_VT1623
:
2691 case ENCODER_OBJECT_ID_HDMI_SI1930
:
2692 case ENCODER_OBJECT_ID_TRAVIS
:
2693 case ENCODER_OBJECT_ID_NUTMEG
:
2694 /* these are handled by the primary encoders */
2695 radeon_encoder
->is_ext_encoder
= true;
2696 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2697 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2698 else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
2699 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2701 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2702 drm_encoder_helper_add(encoder
, &radeon_atom_ext_helper_funcs
);