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drm/radeon/kms: move atom encoder setup to a new file
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_encoders.c
1 /*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38
39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
40 {
41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42 switch (radeon_encoder->encoder_id) {
43 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49 case ENCODER_OBJECT_ID_INTERNAL_DDI:
50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
54 return true;
55 default:
56 return false;
57 }
58 }
59
60 static struct drm_connector *
61 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
62 {
63 struct drm_device *dev = encoder->dev;
64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65 struct drm_connector *connector;
66 struct radeon_connector *radeon_connector;
67
68 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
69 radeon_connector = to_radeon_connector(connector);
70 if (radeon_encoder->devices & radeon_connector->devices)
71 return connector;
72 }
73 return NULL;
74 }
75
76 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
77 struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode)
79 {
80 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
81 struct drm_device *dev = encoder->dev;
82 struct radeon_device *rdev = dev->dev_private;
83
84 /* set the active encoder to connector routing */
85 radeon_encoder_set_active_device(encoder);
86 drm_mode_set_crtcinfo(adjusted_mode, 0);
87
88 /* hw bug */
89 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
90 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
91 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
92
93 /* get the native mode for LVDS */
94 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
95 radeon_panel_mode_fixup(encoder, adjusted_mode);
96
97 /* get the native mode for TV */
98 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
100 if (tv_dac) {
101 if (tv_dac->tv_std == TV_STD_NTSC ||
102 tv_dac->tv_std == TV_STD_NTSC_J ||
103 tv_dac->tv_std == TV_STD_PAL_M)
104 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
105 else
106 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
107 }
108 }
109
110 if (ASIC_IS_DCE3(rdev) &&
111 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
112 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
113 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
114 radeon_dp_set_link_config(connector, mode);
115 }
116
117 return true;
118 }
119
120 static void
121 atombios_dac_setup(struct drm_encoder *encoder, int action)
122 {
123 struct drm_device *dev = encoder->dev;
124 struct radeon_device *rdev = dev->dev_private;
125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
126 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
127 int index = 0;
128 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
129
130 memset(&args, 0, sizeof(args));
131
132 switch (radeon_encoder->encoder_id) {
133 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
135 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
136 break;
137 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
139 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
140 break;
141 }
142
143 args.ucAction = action;
144
145 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
146 args.ucDacStandard = ATOM_DAC1_PS2;
147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
148 args.ucDacStandard = ATOM_DAC1_CV;
149 else {
150 switch (dac_info->tv_std) {
151 case TV_STD_PAL:
152 case TV_STD_PAL_M:
153 case TV_STD_SCART_PAL:
154 case TV_STD_SECAM:
155 case TV_STD_PAL_CN:
156 args.ucDacStandard = ATOM_DAC1_PAL;
157 break;
158 case TV_STD_NTSC:
159 case TV_STD_NTSC_J:
160 case TV_STD_PAL_60:
161 default:
162 args.ucDacStandard = ATOM_DAC1_NTSC;
163 break;
164 }
165 }
166 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
167
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
169
170 }
171
172 static void
173 atombios_tv_setup(struct drm_encoder *encoder, int action)
174 {
175 struct drm_device *dev = encoder->dev;
176 struct radeon_device *rdev = dev->dev_private;
177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
178 TV_ENCODER_CONTROL_PS_ALLOCATION args;
179 int index = 0;
180 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
181
182 memset(&args, 0, sizeof(args));
183
184 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
185
186 args.sTVEncoder.ucAction = action;
187
188 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
189 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
190 else {
191 switch (dac_info->tv_std) {
192 case TV_STD_NTSC:
193 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
194 break;
195 case TV_STD_PAL:
196 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
197 break;
198 case TV_STD_PAL_M:
199 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
200 break;
201 case TV_STD_PAL_60:
202 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
203 break;
204 case TV_STD_NTSC_J:
205 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
206 break;
207 case TV_STD_SCART_PAL:
208 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
209 break;
210 case TV_STD_SECAM:
211 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
212 break;
213 case TV_STD_PAL_CN:
214 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
215 break;
216 default:
217 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
218 break;
219 }
220 }
221
222 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
223
224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
225
226 }
227
228 union dvo_encoder_control {
229 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
230 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
231 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
232 };
233
234 void
235 atombios_dvo_setup(struct drm_encoder *encoder, int action)
236 {
237 struct drm_device *dev = encoder->dev;
238 struct radeon_device *rdev = dev->dev_private;
239 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
240 union dvo_encoder_control args;
241 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
242
243 memset(&args, 0, sizeof(args));
244
245 if (ASIC_IS_DCE3(rdev)) {
246 /* DCE3+ */
247 args.dvo_v3.ucAction = action;
248 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
249 args.dvo_v3.ucDVOConfig = 0; /* XXX */
250 } else if (ASIC_IS_DCE2(rdev)) {
251 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
252 args.dvo.sDVOEncoder.ucAction = action;
253 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
254 /* DFP1, CRT1, TV1 depending on the type of port */
255 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
256
257 if (radeon_encoder->pixel_clock > 165000)
258 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
259 } else {
260 /* R4xx, R5xx */
261 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
262
263 if (radeon_encoder->pixel_clock > 165000)
264 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
265
266 /*if (pScrn->rgbBits == 8)*/
267 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
268 }
269
270 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
271 }
272
273 union lvds_encoder_control {
274 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
275 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
276 };
277
278 void
279 atombios_digital_setup(struct drm_encoder *encoder, int action)
280 {
281 struct drm_device *dev = encoder->dev;
282 struct radeon_device *rdev = dev->dev_private;
283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
284 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
285 union lvds_encoder_control args;
286 int index = 0;
287 int hdmi_detected = 0;
288 uint8_t frev, crev;
289
290 if (!dig)
291 return;
292
293 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
294 hdmi_detected = 1;
295
296 memset(&args, 0, sizeof(args));
297
298 switch (radeon_encoder->encoder_id) {
299 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
300 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
301 break;
302 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
304 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
305 break;
306 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
307 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
308 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
309 else
310 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
311 break;
312 }
313
314 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
315 return;
316
317 switch (frev) {
318 case 1:
319 case 2:
320 switch (crev) {
321 case 1:
322 args.v1.ucMisc = 0;
323 args.v1.ucAction = action;
324 if (hdmi_detected)
325 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
326 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
327 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
328 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
329 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
330 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
331 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
332 } else {
333 if (dig->linkb)
334 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
335 if (radeon_encoder->pixel_clock > 165000)
336 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
337 /*if (pScrn->rgbBits == 8) */
338 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
339 }
340 break;
341 case 2:
342 case 3:
343 args.v2.ucMisc = 0;
344 args.v2.ucAction = action;
345 if (crev == 3) {
346 if (dig->coherent_mode)
347 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
348 }
349 if (hdmi_detected)
350 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
351 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
352 args.v2.ucTruncate = 0;
353 args.v2.ucSpatial = 0;
354 args.v2.ucTemporal = 0;
355 args.v2.ucFRC = 0;
356 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
357 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
358 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
359 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
360 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
361 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
362 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
363 }
364 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
365 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
366 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
367 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
368 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
369 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
370 }
371 } else {
372 if (dig->linkb)
373 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
374 if (radeon_encoder->pixel_clock > 165000)
375 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
376 }
377 break;
378 default:
379 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
380 break;
381 }
382 break;
383 default:
384 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
385 break;
386 }
387
388 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
389 }
390
391 int
392 atombios_get_encoder_mode(struct drm_encoder *encoder)
393 {
394 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
395 struct drm_device *dev = encoder->dev;
396 struct radeon_device *rdev = dev->dev_private;
397 struct drm_connector *connector;
398 struct radeon_connector *radeon_connector;
399 struct radeon_connector_atom_dig *dig_connector;
400
401 /* dp bridges are always DP */
402 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
403 return ATOM_ENCODER_MODE_DP;
404
405 /* DVO is always DVO */
406 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
407 return ATOM_ENCODER_MODE_DVO;
408
409 connector = radeon_get_connector_for_encoder(encoder);
410 /* if we don't have an active device yet, just use one of
411 * the connectors tied to the encoder.
412 */
413 if (!connector)
414 connector = radeon_get_connector_for_encoder_init(encoder);
415 radeon_connector = to_radeon_connector(connector);
416
417 switch (connector->connector_type) {
418 case DRM_MODE_CONNECTOR_DVII:
419 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
420 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
421 /* fix me */
422 if (ASIC_IS_DCE4(rdev))
423 return ATOM_ENCODER_MODE_DVI;
424 else
425 return ATOM_ENCODER_MODE_HDMI;
426 } else if (radeon_connector->use_digital)
427 return ATOM_ENCODER_MODE_DVI;
428 else
429 return ATOM_ENCODER_MODE_CRT;
430 break;
431 case DRM_MODE_CONNECTOR_DVID:
432 case DRM_MODE_CONNECTOR_HDMIA:
433 default:
434 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
435 /* fix me */
436 if (ASIC_IS_DCE4(rdev))
437 return ATOM_ENCODER_MODE_DVI;
438 else
439 return ATOM_ENCODER_MODE_HDMI;
440 } else
441 return ATOM_ENCODER_MODE_DVI;
442 break;
443 case DRM_MODE_CONNECTOR_LVDS:
444 return ATOM_ENCODER_MODE_LVDS;
445 break;
446 case DRM_MODE_CONNECTOR_DisplayPort:
447 dig_connector = radeon_connector->con_priv;
448 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
449 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
450 return ATOM_ENCODER_MODE_DP;
451 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
452 /* fix me */
453 if (ASIC_IS_DCE4(rdev))
454 return ATOM_ENCODER_MODE_DVI;
455 else
456 return ATOM_ENCODER_MODE_HDMI;
457 } else
458 return ATOM_ENCODER_MODE_DVI;
459 break;
460 case DRM_MODE_CONNECTOR_eDP:
461 return ATOM_ENCODER_MODE_DP;
462 case DRM_MODE_CONNECTOR_DVIA:
463 case DRM_MODE_CONNECTOR_VGA:
464 return ATOM_ENCODER_MODE_CRT;
465 break;
466 case DRM_MODE_CONNECTOR_Composite:
467 case DRM_MODE_CONNECTOR_SVIDEO:
468 case DRM_MODE_CONNECTOR_9PinDIN:
469 /* fix me */
470 return ATOM_ENCODER_MODE_TV;
471 /*return ATOM_ENCODER_MODE_CV;*/
472 break;
473 }
474 }
475
476 /*
477 * DIG Encoder/Transmitter Setup
478 *
479 * DCE 3.0/3.1
480 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
481 * Supports up to 3 digital outputs
482 * - 2 DIG encoder blocks.
483 * DIG1 can drive UNIPHY link A or link B
484 * DIG2 can drive UNIPHY link B or LVTMA
485 *
486 * DCE 3.2
487 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
488 * Supports up to 5 digital outputs
489 * - 2 DIG encoder blocks.
490 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
491 *
492 * DCE 4.0/5.0
493 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
494 * Supports up to 6 digital outputs
495 * - 6 DIG encoder blocks.
496 * - DIG to PHY mapping is hardcoded
497 * DIG1 drives UNIPHY0 link A, A+B
498 * DIG2 drives UNIPHY0 link B
499 * DIG3 drives UNIPHY1 link A, A+B
500 * DIG4 drives UNIPHY1 link B
501 * DIG5 drives UNIPHY2 link A, A+B
502 * DIG6 drives UNIPHY2 link B
503 *
504 * DCE 4.1
505 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
506 * Supports up to 6 digital outputs
507 * - 2 DIG encoder blocks.
508 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
509 *
510 * Routing
511 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
512 * Examples:
513 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
514 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
515 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
516 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
517 */
518
519 union dig_encoder_control {
520 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
521 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
522 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
523 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
524 };
525
526 void
527 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
528 {
529 struct drm_device *dev = encoder->dev;
530 struct radeon_device *rdev = dev->dev_private;
531 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
532 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
533 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
534 union dig_encoder_control args;
535 int index = 0;
536 uint8_t frev, crev;
537 int dp_clock = 0;
538 int dp_lane_count = 0;
539 int hpd_id = RADEON_HPD_NONE;
540 int bpc = 8;
541
542 if (connector) {
543 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
544 struct radeon_connector_atom_dig *dig_connector =
545 radeon_connector->con_priv;
546
547 dp_clock = dig_connector->dp_clock;
548 dp_lane_count = dig_connector->dp_lane_count;
549 hpd_id = radeon_connector->hpd.hpd;
550 bpc = connector->display_info.bpc;
551 }
552
553 /* no dig encoder assigned */
554 if (dig->dig_encoder == -1)
555 return;
556
557 memset(&args, 0, sizeof(args));
558
559 if (ASIC_IS_DCE4(rdev))
560 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
561 else {
562 if (dig->dig_encoder)
563 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
564 else
565 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
566 }
567
568 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
569 return;
570
571 args.v1.ucAction = action;
572 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
573 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
574 args.v3.ucPanelMode = panel_mode;
575 else
576 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
577
578 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
579 args.v1.ucLaneNum = dp_lane_count;
580 else if (radeon_encoder->pixel_clock > 165000)
581 args.v1.ucLaneNum = 8;
582 else
583 args.v1.ucLaneNum = 4;
584
585 if (ASIC_IS_DCE5(rdev)) {
586 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
587 if (dp_clock == 270000)
588 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
589 else if (dp_clock == 540000)
590 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
591 }
592 args.v4.acConfig.ucDigSel = dig->dig_encoder;
593 switch (bpc) {
594 case 0:
595 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
596 break;
597 case 6:
598 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
599 break;
600 case 8:
601 default:
602 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
603 break;
604 case 10:
605 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
606 break;
607 case 12:
608 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
609 break;
610 case 16:
611 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
612 break;
613 }
614 if (hpd_id == RADEON_HPD_NONE)
615 args.v4.ucHPD_ID = 0;
616 else
617 args.v4.ucHPD_ID = hpd_id + 1;
618 } else if (ASIC_IS_DCE4(rdev)) {
619 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
620 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
621 args.v3.acConfig.ucDigSel = dig->dig_encoder;
622 switch (bpc) {
623 case 0:
624 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
625 break;
626 case 6:
627 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
628 break;
629 case 8:
630 default:
631 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
632 break;
633 case 10:
634 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
635 break;
636 case 12:
637 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
638 break;
639 case 16:
640 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
641 break;
642 }
643 } else {
644 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
645 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
646 switch (radeon_encoder->encoder_id) {
647 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
648 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
649 break;
650 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
651 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
652 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
653 break;
654 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
655 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
656 break;
657 }
658 if (dig->linkb)
659 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
660 else
661 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
662 }
663
664 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
665
666 }
667
668 union dig_transmitter_control {
669 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
670 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
671 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
672 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
673 };
674
675 void
676 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
677 {
678 struct drm_device *dev = encoder->dev;
679 struct radeon_device *rdev = dev->dev_private;
680 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
681 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
682 struct drm_connector *connector;
683 union dig_transmitter_control args;
684 int index = 0;
685 uint8_t frev, crev;
686 bool is_dp = false;
687 int pll_id = 0;
688 int dp_clock = 0;
689 int dp_lane_count = 0;
690 int connector_object_id = 0;
691 int igp_lane_info = 0;
692 int dig_encoder = dig->dig_encoder;
693
694 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
695 connector = radeon_get_connector_for_encoder_init(encoder);
696 /* just needed to avoid bailing in the encoder check. the encoder
697 * isn't used for init
698 */
699 dig_encoder = 0;
700 } else
701 connector = radeon_get_connector_for_encoder(encoder);
702
703 if (connector) {
704 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
705 struct radeon_connector_atom_dig *dig_connector =
706 radeon_connector->con_priv;
707
708 dp_clock = dig_connector->dp_clock;
709 dp_lane_count = dig_connector->dp_lane_count;
710 connector_object_id =
711 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
712 igp_lane_info = dig_connector->igp_lane_info;
713 }
714
715 /* no dig encoder assigned */
716 if (dig_encoder == -1)
717 return;
718
719 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
720 is_dp = true;
721
722 memset(&args, 0, sizeof(args));
723
724 switch (radeon_encoder->encoder_id) {
725 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
726 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
727 break;
728 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
729 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
730 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
731 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
732 break;
733 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
734 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
735 break;
736 }
737
738 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
739 return;
740
741 args.v1.ucAction = action;
742 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
743 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
744 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
745 args.v1.asMode.ucLaneSel = lane_num;
746 args.v1.asMode.ucLaneSet = lane_set;
747 } else {
748 if (is_dp)
749 args.v1.usPixelClock =
750 cpu_to_le16(dp_clock / 10);
751 else if (radeon_encoder->pixel_clock > 165000)
752 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
753 else
754 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
755 }
756 if (ASIC_IS_DCE4(rdev)) {
757 if (is_dp)
758 args.v3.ucLaneNum = dp_lane_count;
759 else if (radeon_encoder->pixel_clock > 165000)
760 args.v3.ucLaneNum = 8;
761 else
762 args.v3.ucLaneNum = 4;
763
764 if (dig->linkb)
765 args.v3.acConfig.ucLinkSel = 1;
766 if (dig_encoder & 1)
767 args.v3.acConfig.ucEncoderSel = 1;
768
769 /* Select the PLL for the PHY
770 * DP PHY should be clocked from external src if there is
771 * one.
772 */
773 if (encoder->crtc) {
774 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
775 pll_id = radeon_crtc->pll_id;
776 }
777
778 if (ASIC_IS_DCE5(rdev)) {
779 /* On DCE5 DCPLL usually generates the DP ref clock */
780 if (is_dp) {
781 if (rdev->clock.dp_extclk)
782 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
783 else
784 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
785 } else
786 args.v4.acConfig.ucRefClkSource = pll_id;
787 } else {
788 /* On DCE4, if there is an external clock, it generates the DP ref clock */
789 if (is_dp && rdev->clock.dp_extclk)
790 args.v3.acConfig.ucRefClkSource = 2; /* external src */
791 else
792 args.v3.acConfig.ucRefClkSource = pll_id;
793 }
794
795 switch (radeon_encoder->encoder_id) {
796 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
797 args.v3.acConfig.ucTransmitterSel = 0;
798 break;
799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
800 args.v3.acConfig.ucTransmitterSel = 1;
801 break;
802 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
803 args.v3.acConfig.ucTransmitterSel = 2;
804 break;
805 }
806
807 if (is_dp)
808 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
809 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
810 if (dig->coherent_mode)
811 args.v3.acConfig.fCoherentMode = 1;
812 if (radeon_encoder->pixel_clock > 165000)
813 args.v3.acConfig.fDualLinkConnector = 1;
814 }
815 } else if (ASIC_IS_DCE32(rdev)) {
816 args.v2.acConfig.ucEncoderSel = dig_encoder;
817 if (dig->linkb)
818 args.v2.acConfig.ucLinkSel = 1;
819
820 switch (radeon_encoder->encoder_id) {
821 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
822 args.v2.acConfig.ucTransmitterSel = 0;
823 break;
824 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
825 args.v2.acConfig.ucTransmitterSel = 1;
826 break;
827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
828 args.v2.acConfig.ucTransmitterSel = 2;
829 break;
830 }
831
832 if (is_dp) {
833 args.v2.acConfig.fCoherentMode = 1;
834 args.v2.acConfig.fDPConnector = 1;
835 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
836 if (dig->coherent_mode)
837 args.v2.acConfig.fCoherentMode = 1;
838 if (radeon_encoder->pixel_clock > 165000)
839 args.v2.acConfig.fDualLinkConnector = 1;
840 }
841 } else {
842 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
843
844 if (dig_encoder)
845 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
846 else
847 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
848
849 if ((rdev->flags & RADEON_IS_IGP) &&
850 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
851 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
852 if (igp_lane_info & 0x1)
853 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
854 else if (igp_lane_info & 0x2)
855 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
856 else if (igp_lane_info & 0x4)
857 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
858 else if (igp_lane_info & 0x8)
859 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
860 } else {
861 if (igp_lane_info & 0x3)
862 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
863 else if (igp_lane_info & 0xc)
864 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
865 }
866 }
867
868 if (dig->linkb)
869 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
870 else
871 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
872
873 if (is_dp)
874 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
875 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
876 if (dig->coherent_mode)
877 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
878 if (radeon_encoder->pixel_clock > 165000)
879 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
880 }
881 }
882
883 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
884 }
885
886 bool
887 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
888 {
889 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
890 struct drm_device *dev = radeon_connector->base.dev;
891 struct radeon_device *rdev = dev->dev_private;
892 union dig_transmitter_control args;
893 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
894 uint8_t frev, crev;
895
896 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
897 goto done;
898
899 if (!ASIC_IS_DCE4(rdev))
900 goto done;
901
902 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
903 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
904 goto done;
905
906 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
907 goto done;
908
909 memset(&args, 0, sizeof(args));
910
911 args.v1.ucAction = action;
912
913 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
914
915 /* wait for the panel to power up */
916 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
917 int i;
918
919 for (i = 0; i < 300; i++) {
920 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
921 return true;
922 mdelay(1);
923 }
924 return false;
925 }
926 done:
927 return true;
928 }
929
930 union external_encoder_control {
931 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
932 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
933 };
934
935 static void
936 atombios_external_encoder_setup(struct drm_encoder *encoder,
937 struct drm_encoder *ext_encoder,
938 int action)
939 {
940 struct drm_device *dev = encoder->dev;
941 struct radeon_device *rdev = dev->dev_private;
942 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
943 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
944 union external_encoder_control args;
945 struct drm_connector *connector;
946 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
947 u8 frev, crev;
948 int dp_clock = 0;
949 int dp_lane_count = 0;
950 int connector_object_id = 0;
951 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
952 int bpc = 8;
953
954 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
955 connector = radeon_get_connector_for_encoder_init(encoder);
956 else
957 connector = radeon_get_connector_for_encoder(encoder);
958
959 if (connector) {
960 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
961 struct radeon_connector_atom_dig *dig_connector =
962 radeon_connector->con_priv;
963
964 dp_clock = dig_connector->dp_clock;
965 dp_lane_count = dig_connector->dp_lane_count;
966 connector_object_id =
967 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
968 bpc = connector->display_info.bpc;
969 }
970
971 memset(&args, 0, sizeof(args));
972
973 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
974 return;
975
976 switch (frev) {
977 case 1:
978 /* no params on frev 1 */
979 break;
980 case 2:
981 switch (crev) {
982 case 1:
983 case 2:
984 args.v1.sDigEncoder.ucAction = action;
985 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
986 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
987
988 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
989 if (dp_clock == 270000)
990 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
991 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
992 } else if (radeon_encoder->pixel_clock > 165000)
993 args.v1.sDigEncoder.ucLaneNum = 8;
994 else
995 args.v1.sDigEncoder.ucLaneNum = 4;
996 break;
997 case 3:
998 args.v3.sExtEncoder.ucAction = action;
999 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1000 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1001 else
1002 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1003 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1004
1005 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1006 if (dp_clock == 270000)
1007 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1008 else if (dp_clock == 540000)
1009 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1010 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1011 } else if (radeon_encoder->pixel_clock > 165000)
1012 args.v3.sExtEncoder.ucLaneNum = 8;
1013 else
1014 args.v3.sExtEncoder.ucLaneNum = 4;
1015 switch (ext_enum) {
1016 case GRAPH_OBJECT_ENUM_ID1:
1017 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1018 break;
1019 case GRAPH_OBJECT_ENUM_ID2:
1020 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1021 break;
1022 case GRAPH_OBJECT_ENUM_ID3:
1023 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1024 break;
1025 }
1026 switch (bpc) {
1027 case 0:
1028 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1029 break;
1030 case 6:
1031 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1032 break;
1033 case 8:
1034 default:
1035 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1036 break;
1037 case 10:
1038 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1039 break;
1040 case 12:
1041 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1042 break;
1043 case 16:
1044 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1045 break;
1046 }
1047 break;
1048 default:
1049 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1050 return;
1051 }
1052 break;
1053 default:
1054 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1055 return;
1056 }
1057 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1058 }
1059
1060 static void
1061 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1062 {
1063 struct drm_device *dev = encoder->dev;
1064 struct radeon_device *rdev = dev->dev_private;
1065 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1066 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1067 ENABLE_YUV_PS_ALLOCATION args;
1068 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1069 uint32_t temp, reg;
1070
1071 memset(&args, 0, sizeof(args));
1072
1073 if (rdev->family >= CHIP_R600)
1074 reg = R600_BIOS_3_SCRATCH;
1075 else
1076 reg = RADEON_BIOS_3_SCRATCH;
1077
1078 /* XXX: fix up scratch reg handling */
1079 temp = RREG32(reg);
1080 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1081 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1082 (radeon_crtc->crtc_id << 18)));
1083 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1084 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1085 else
1086 WREG32(reg, 0);
1087
1088 if (enable)
1089 args.ucEnable = ATOM_ENABLE;
1090 args.ucCRTC = radeon_crtc->crtc_id;
1091
1092 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1093
1094 WREG32(reg, temp);
1095 }
1096
1097 static void
1098 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1099 {
1100 struct drm_device *dev = encoder->dev;
1101 struct radeon_device *rdev = dev->dev_private;
1102 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1103 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1104 int index = 0;
1105
1106 memset(&args, 0, sizeof(args));
1107
1108 switch (radeon_encoder->encoder_id) {
1109 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1110 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1111 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1112 break;
1113 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1114 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1115 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1116 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1117 break;
1118 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1119 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1120 break;
1121 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1122 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1123 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1124 else
1125 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1126 break;
1127 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1128 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1129 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1130 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1131 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1132 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1133 else
1134 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1135 break;
1136 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1137 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1138 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1139 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1140 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1141 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1142 else
1143 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1144 break;
1145 default:
1146 return;
1147 }
1148
1149 switch (mode) {
1150 case DRM_MODE_DPMS_ON:
1151 args.ucAction = ATOM_ENABLE;
1152 /* workaround for DVOOutputControl on some RS690 systems */
1153 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1154 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1155 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1157 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1158 } else
1159 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1160 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1161 args.ucAction = ATOM_LCD_BLON;
1162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1163 }
1164 break;
1165 case DRM_MODE_DPMS_STANDBY:
1166 case DRM_MODE_DPMS_SUSPEND:
1167 case DRM_MODE_DPMS_OFF:
1168 args.ucAction = ATOM_DISABLE;
1169 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1170 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1171 args.ucAction = ATOM_LCD_BLOFF;
1172 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1173 }
1174 break;
1175 }
1176 }
1177
1178 static void
1179 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1180 {
1181 struct drm_device *dev = encoder->dev;
1182 struct radeon_device *rdev = dev->dev_private;
1183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1184 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1185 struct radeon_connector *radeon_connector = NULL;
1186 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1187
1188 if (connector) {
1189 radeon_connector = to_radeon_connector(connector);
1190 radeon_dig_connector = radeon_connector->con_priv;
1191 }
1192
1193 switch (mode) {
1194 case DRM_MODE_DPMS_ON:
1195 /* some early dce3.2 boards have a bug in their transmitter control table */
1196 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1197 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1198 else
1199 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1200 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1201 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1202 atombios_set_edp_panel_power(connector,
1203 ATOM_TRANSMITTER_ACTION_POWER_ON);
1204 radeon_dig_connector->edp_on = true;
1205 }
1206 if (ASIC_IS_DCE4(rdev))
1207 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1208 radeon_dp_link_train(encoder, connector);
1209 if (ASIC_IS_DCE4(rdev))
1210 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1211 }
1212 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1213 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1214 break;
1215 case DRM_MODE_DPMS_STANDBY:
1216 case DRM_MODE_DPMS_SUSPEND:
1217 case DRM_MODE_DPMS_OFF:
1218 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1219 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1220 if (ASIC_IS_DCE4(rdev))
1221 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1222 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1223 atombios_set_edp_panel_power(connector,
1224 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1225 radeon_dig_connector->edp_on = false;
1226 }
1227 }
1228 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1229 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1230 break;
1231 }
1232 }
1233
1234 static void
1235 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1236 struct drm_encoder *ext_encoder,
1237 int mode)
1238 {
1239 struct drm_device *dev = encoder->dev;
1240 struct radeon_device *rdev = dev->dev_private;
1241
1242 switch (mode) {
1243 case DRM_MODE_DPMS_ON:
1244 default:
1245 if (ASIC_IS_DCE41(rdev)) {
1246 atombios_external_encoder_setup(encoder, ext_encoder,
1247 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1248 atombios_external_encoder_setup(encoder, ext_encoder,
1249 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1250 } else
1251 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1252 break;
1253 case DRM_MODE_DPMS_STANDBY:
1254 case DRM_MODE_DPMS_SUSPEND:
1255 case DRM_MODE_DPMS_OFF:
1256 if (ASIC_IS_DCE41(rdev)) {
1257 atombios_external_encoder_setup(encoder, ext_encoder,
1258 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1259 atombios_external_encoder_setup(encoder, ext_encoder,
1260 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1261 } else
1262 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1263 break;
1264 }
1265 }
1266
1267 static void
1268 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1269 {
1270 struct drm_device *dev = encoder->dev;
1271 struct radeon_device *rdev = dev->dev_private;
1272 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1273 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1274
1275 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1276 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1277 radeon_encoder->active_device);
1278 switch (radeon_encoder->encoder_id) {
1279 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1280 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1281 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1282 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1283 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1284 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1285 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1286 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1287 radeon_atom_encoder_dpms_avivo(encoder, mode);
1288 break;
1289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1290 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1292 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1293 radeon_atom_encoder_dpms_dig(encoder, mode);
1294 break;
1295 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1296 if (ASIC_IS_DCE5(rdev)) {
1297 switch (mode) {
1298 case DRM_MODE_DPMS_ON:
1299 atombios_dvo_setup(encoder, ATOM_ENABLE);
1300 break;
1301 case DRM_MODE_DPMS_STANDBY:
1302 case DRM_MODE_DPMS_SUSPEND:
1303 case DRM_MODE_DPMS_OFF:
1304 atombios_dvo_setup(encoder, ATOM_DISABLE);
1305 break;
1306 }
1307 } else if (ASIC_IS_DCE3(rdev))
1308 radeon_atom_encoder_dpms_dig(encoder, mode);
1309 else
1310 radeon_atom_encoder_dpms_avivo(encoder, mode);
1311 break;
1312 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1314 if (ASIC_IS_DCE5(rdev)) {
1315 switch (mode) {
1316 case DRM_MODE_DPMS_ON:
1317 atombios_dac_setup(encoder, ATOM_ENABLE);
1318 break;
1319 case DRM_MODE_DPMS_STANDBY:
1320 case DRM_MODE_DPMS_SUSPEND:
1321 case DRM_MODE_DPMS_OFF:
1322 atombios_dac_setup(encoder, ATOM_DISABLE);
1323 break;
1324 }
1325 } else
1326 radeon_atom_encoder_dpms_avivo(encoder, mode);
1327 break;
1328 default:
1329 return;
1330 }
1331
1332 if (ext_encoder)
1333 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1334
1335 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1336
1337 }
1338
1339 union crtc_source_param {
1340 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1341 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1342 };
1343
1344 static void
1345 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1346 {
1347 struct drm_device *dev = encoder->dev;
1348 struct radeon_device *rdev = dev->dev_private;
1349 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1350 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1351 union crtc_source_param args;
1352 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1353 uint8_t frev, crev;
1354 struct radeon_encoder_atom_dig *dig;
1355
1356 memset(&args, 0, sizeof(args));
1357
1358 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1359 return;
1360
1361 switch (frev) {
1362 case 1:
1363 switch (crev) {
1364 case 1:
1365 default:
1366 if (ASIC_IS_AVIVO(rdev))
1367 args.v1.ucCRTC = radeon_crtc->crtc_id;
1368 else {
1369 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1370 args.v1.ucCRTC = radeon_crtc->crtc_id;
1371 } else {
1372 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1373 }
1374 }
1375 switch (radeon_encoder->encoder_id) {
1376 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1377 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1378 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1379 break;
1380 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1381 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1382 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1383 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1384 else
1385 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1386 break;
1387 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1388 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1389 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1390 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1391 break;
1392 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1393 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1394 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1395 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1396 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1397 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1398 else
1399 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1400 break;
1401 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1402 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1403 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1404 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1405 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1406 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1407 else
1408 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1409 break;
1410 }
1411 break;
1412 case 2:
1413 args.v2.ucCRTC = radeon_crtc->crtc_id;
1414 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1415 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1416
1417 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1418 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1419 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1420 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1421 else
1422 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1423 } else
1424 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1425 switch (radeon_encoder->encoder_id) {
1426 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1427 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1428 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1429 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1430 dig = radeon_encoder->enc_priv;
1431 switch (dig->dig_encoder) {
1432 case 0:
1433 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1434 break;
1435 case 1:
1436 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1437 break;
1438 case 2:
1439 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1440 break;
1441 case 3:
1442 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1443 break;
1444 case 4:
1445 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1446 break;
1447 case 5:
1448 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1449 break;
1450 }
1451 break;
1452 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1453 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1454 break;
1455 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1456 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1457 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1458 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1459 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1460 else
1461 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1462 break;
1463 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1464 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1465 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1466 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1467 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1468 else
1469 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1470 break;
1471 }
1472 break;
1473 }
1474 break;
1475 default:
1476 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1477 return;
1478 }
1479
1480 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1481
1482 /* update scratch regs with new routing */
1483 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1484 }
1485
1486 static void
1487 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1488 struct drm_display_mode *mode)
1489 {
1490 struct drm_device *dev = encoder->dev;
1491 struct radeon_device *rdev = dev->dev_private;
1492 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1493 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1494
1495 /* Funky macbooks */
1496 if ((dev->pdev->device == 0x71C5) &&
1497 (dev->pdev->subsystem_vendor == 0x106b) &&
1498 (dev->pdev->subsystem_device == 0x0080)) {
1499 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1500 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1501
1502 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1503 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1504
1505 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1506 }
1507 }
1508
1509 /* set scaler clears this on some chips */
1510 if (ASIC_IS_AVIVO(rdev) &&
1511 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1512 if (ASIC_IS_DCE4(rdev)) {
1513 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1514 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1515 EVERGREEN_INTERLEAVE_EN);
1516 else
1517 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1518 } else {
1519 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1520 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1521 AVIVO_D1MODE_INTERLEAVE_EN);
1522 else
1523 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1524 }
1525 }
1526 }
1527
1528 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1529 {
1530 struct drm_device *dev = encoder->dev;
1531 struct radeon_device *rdev = dev->dev_private;
1532 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1533 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1534 struct drm_encoder *test_encoder;
1535 struct radeon_encoder_atom_dig *dig;
1536 uint32_t dig_enc_in_use = 0;
1537
1538 /* DCE4/5 */
1539 if (ASIC_IS_DCE4(rdev)) {
1540 dig = radeon_encoder->enc_priv;
1541 if (ASIC_IS_DCE41(rdev)) {
1542 /* ontario follows DCE4 */
1543 if (rdev->family == CHIP_PALM) {
1544 if (dig->linkb)
1545 return 1;
1546 else
1547 return 0;
1548 } else
1549 /* llano follows DCE3.2 */
1550 return radeon_crtc->crtc_id;
1551 } else {
1552 switch (radeon_encoder->encoder_id) {
1553 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1554 if (dig->linkb)
1555 return 1;
1556 else
1557 return 0;
1558 break;
1559 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1560 if (dig->linkb)
1561 return 3;
1562 else
1563 return 2;
1564 break;
1565 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1566 if (dig->linkb)
1567 return 5;
1568 else
1569 return 4;
1570 break;
1571 }
1572 }
1573 }
1574
1575 /* on DCE32 and encoder can driver any block so just crtc id */
1576 if (ASIC_IS_DCE32(rdev)) {
1577 return radeon_crtc->crtc_id;
1578 }
1579
1580 /* on DCE3 - LVTMA can only be driven by DIGB */
1581 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1582 struct radeon_encoder *radeon_test_encoder;
1583
1584 if (encoder == test_encoder)
1585 continue;
1586
1587 if (!radeon_encoder_is_digital(test_encoder))
1588 continue;
1589
1590 radeon_test_encoder = to_radeon_encoder(test_encoder);
1591 dig = radeon_test_encoder->enc_priv;
1592
1593 if (dig->dig_encoder >= 0)
1594 dig_enc_in_use |= (1 << dig->dig_encoder);
1595 }
1596
1597 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1598 if (dig_enc_in_use & 0x2)
1599 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1600 return 1;
1601 }
1602 if (!(dig_enc_in_use & 1))
1603 return 0;
1604 return 1;
1605 }
1606
1607 /* This only needs to be called once at startup */
1608 void
1609 radeon_atom_encoder_init(struct radeon_device *rdev)
1610 {
1611 struct drm_device *dev = rdev->ddev;
1612 struct drm_encoder *encoder;
1613
1614 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1615 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1616 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1617
1618 switch (radeon_encoder->encoder_id) {
1619 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1620 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1621 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1623 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1624 break;
1625 default:
1626 break;
1627 }
1628
1629 if (ext_encoder && ASIC_IS_DCE41(rdev))
1630 atombios_external_encoder_setup(encoder, ext_encoder,
1631 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1632 }
1633 }
1634
1635 static void
1636 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1637 struct drm_display_mode *mode,
1638 struct drm_display_mode *adjusted_mode)
1639 {
1640 struct drm_device *dev = encoder->dev;
1641 struct radeon_device *rdev = dev->dev_private;
1642 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1643 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1644
1645 radeon_encoder->pixel_clock = adjusted_mode->clock;
1646
1647 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1648 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1649 atombios_yuv_setup(encoder, true);
1650 else
1651 atombios_yuv_setup(encoder, false);
1652 }
1653
1654 switch (radeon_encoder->encoder_id) {
1655 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1656 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1657 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1658 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1659 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1660 break;
1661 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1662 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1663 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1664 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1665 if (ASIC_IS_DCE4(rdev)) {
1666 /* disable the transmitter */
1667 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1668 /* setup and enable the encoder */
1669 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1670
1671 /* enable the transmitter */
1672 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1673 } else {
1674 /* disable the encoder and transmitter */
1675 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1676 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1677
1678 /* setup and enable the encoder and transmitter */
1679 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1680 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1681 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1682 }
1683 break;
1684 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1685 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1686 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1687 atombios_dvo_setup(encoder, ATOM_ENABLE);
1688 break;
1689 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1690 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1691 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1692 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1693 atombios_dac_setup(encoder, ATOM_ENABLE);
1694 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1695 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1696 atombios_tv_setup(encoder, ATOM_ENABLE);
1697 else
1698 atombios_tv_setup(encoder, ATOM_DISABLE);
1699 }
1700 break;
1701 }
1702
1703 if (ext_encoder) {
1704 if (ASIC_IS_DCE41(rdev))
1705 atombios_external_encoder_setup(encoder, ext_encoder,
1706 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1707 else
1708 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1709 }
1710
1711 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1712
1713 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1714 r600_hdmi_enable(encoder);
1715 r600_hdmi_setmode(encoder, adjusted_mode);
1716 }
1717 }
1718
1719 static bool
1720 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1721 {
1722 struct drm_device *dev = encoder->dev;
1723 struct radeon_device *rdev = dev->dev_private;
1724 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1725 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1726
1727 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1728 ATOM_DEVICE_CV_SUPPORT |
1729 ATOM_DEVICE_CRT_SUPPORT)) {
1730 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1731 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1732 uint8_t frev, crev;
1733
1734 memset(&args, 0, sizeof(args));
1735
1736 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1737 return false;
1738
1739 args.sDacload.ucMisc = 0;
1740
1741 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1742 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1743 args.sDacload.ucDacType = ATOM_DAC_A;
1744 else
1745 args.sDacload.ucDacType = ATOM_DAC_B;
1746
1747 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1748 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1749 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1750 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1751 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1752 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1753 if (crev >= 3)
1754 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1755 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1756 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1757 if (crev >= 3)
1758 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1759 }
1760
1761 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1762
1763 return true;
1764 } else
1765 return false;
1766 }
1767
1768 static enum drm_connector_status
1769 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1770 {
1771 struct drm_device *dev = encoder->dev;
1772 struct radeon_device *rdev = dev->dev_private;
1773 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1774 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1775 uint32_t bios_0_scratch;
1776
1777 if (!atombios_dac_load_detect(encoder, connector)) {
1778 DRM_DEBUG_KMS("detect returned false \n");
1779 return connector_status_unknown;
1780 }
1781
1782 if (rdev->family >= CHIP_R600)
1783 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1784 else
1785 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1786
1787 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1788 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1789 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1790 return connector_status_connected;
1791 }
1792 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1793 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1794 return connector_status_connected;
1795 }
1796 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1797 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1798 return connector_status_connected;
1799 }
1800 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1801 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1802 return connector_status_connected; /* CTV */
1803 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1804 return connector_status_connected; /* STV */
1805 }
1806 return connector_status_disconnected;
1807 }
1808
1809 static enum drm_connector_status
1810 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1811 {
1812 struct drm_device *dev = encoder->dev;
1813 struct radeon_device *rdev = dev->dev_private;
1814 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1815 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1816 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1817 u32 bios_0_scratch;
1818
1819 if (!ASIC_IS_DCE4(rdev))
1820 return connector_status_unknown;
1821
1822 if (!ext_encoder)
1823 return connector_status_unknown;
1824
1825 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
1826 return connector_status_unknown;
1827
1828 /* load detect on the dp bridge */
1829 atombios_external_encoder_setup(encoder, ext_encoder,
1830 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
1831
1832 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1833
1834 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1835 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1836 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1837 return connector_status_connected;
1838 }
1839 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1840 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1841 return connector_status_connected;
1842 }
1843 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1844 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1845 return connector_status_connected;
1846 }
1847 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1848 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1849 return connector_status_connected; /* CTV */
1850 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1851 return connector_status_connected; /* STV */
1852 }
1853 return connector_status_disconnected;
1854 }
1855
1856 void
1857 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
1858 {
1859 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1860
1861 if (ext_encoder)
1862 /* ddc_setup on the dp bridge */
1863 atombios_external_encoder_setup(encoder, ext_encoder,
1864 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
1865
1866 }
1867
1868 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1869 {
1870 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1871 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1872
1873 if ((radeon_encoder->active_device &
1874 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
1875 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
1876 ENCODER_OBJECT_ID_NONE)) {
1877 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1878 if (dig)
1879 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1880 }
1881
1882 radeon_atom_output_lock(encoder, true);
1883 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1884
1885 if (connector) {
1886 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1887
1888 /* select the clock/data port if it uses a router */
1889 if (radeon_connector->router.cd_valid)
1890 radeon_router_select_cd_port(radeon_connector);
1891
1892 /* turn eDP panel on for mode set */
1893 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1894 atombios_set_edp_panel_power(connector,
1895 ATOM_TRANSMITTER_ACTION_POWER_ON);
1896 }
1897
1898 /* this is needed for the pll/ss setup to work correctly in some cases */
1899 atombios_set_encoder_crtc_source(encoder);
1900 }
1901
1902 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1903 {
1904 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1905 radeon_atom_output_lock(encoder, false);
1906 }
1907
1908 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1909 {
1910 struct drm_device *dev = encoder->dev;
1911 struct radeon_device *rdev = dev->dev_private;
1912 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1913 struct radeon_encoder_atom_dig *dig;
1914
1915 /* check for pre-DCE3 cards with shared encoders;
1916 * can't really use the links individually, so don't disable
1917 * the encoder if it's in use by another connector
1918 */
1919 if (!ASIC_IS_DCE3(rdev)) {
1920 struct drm_encoder *other_encoder;
1921 struct radeon_encoder *other_radeon_encoder;
1922
1923 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1924 other_radeon_encoder = to_radeon_encoder(other_encoder);
1925 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1926 drm_helper_encoder_in_use(other_encoder))
1927 goto disable_done;
1928 }
1929 }
1930
1931 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1932
1933 switch (radeon_encoder->encoder_id) {
1934 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1935 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1936 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1937 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1938 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1939 break;
1940 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1941 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1942 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1943 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1944 if (ASIC_IS_DCE4(rdev))
1945 /* disable the transmitter */
1946 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1947 else {
1948 /* disable the encoder and transmitter */
1949 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1950 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1951 }
1952 break;
1953 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1954 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1955 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1956 atombios_dvo_setup(encoder, ATOM_DISABLE);
1957 break;
1958 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1959 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1960 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1961 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1962 atombios_dac_setup(encoder, ATOM_DISABLE);
1963 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1964 atombios_tv_setup(encoder, ATOM_DISABLE);
1965 break;
1966 }
1967
1968 disable_done:
1969 if (radeon_encoder_is_digital(encoder)) {
1970 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1971 r600_hdmi_disable(encoder);
1972 dig = radeon_encoder->enc_priv;
1973 dig->dig_encoder = -1;
1974 }
1975 radeon_encoder->active_device = 0;
1976 }
1977
1978 /* these are handled by the primary encoders */
1979 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
1980 {
1981
1982 }
1983
1984 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
1985 {
1986
1987 }
1988
1989 static void
1990 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
1991 struct drm_display_mode *mode,
1992 struct drm_display_mode *adjusted_mode)
1993 {
1994
1995 }
1996
1997 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
1998 {
1999
2000 }
2001
2002 static void
2003 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2004 {
2005
2006 }
2007
2008 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2009 struct drm_display_mode *mode,
2010 struct drm_display_mode *adjusted_mode)
2011 {
2012 return true;
2013 }
2014
2015 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2016 .dpms = radeon_atom_ext_dpms,
2017 .mode_fixup = radeon_atom_ext_mode_fixup,
2018 .prepare = radeon_atom_ext_prepare,
2019 .mode_set = radeon_atom_ext_mode_set,
2020 .commit = radeon_atom_ext_commit,
2021 .disable = radeon_atom_ext_disable,
2022 /* no detect for TMDS/LVDS yet */
2023 };
2024
2025 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2026 .dpms = radeon_atom_encoder_dpms,
2027 .mode_fixup = radeon_atom_mode_fixup,
2028 .prepare = radeon_atom_encoder_prepare,
2029 .mode_set = radeon_atom_encoder_mode_set,
2030 .commit = radeon_atom_encoder_commit,
2031 .disable = radeon_atom_encoder_disable,
2032 .detect = radeon_atom_dig_detect,
2033 };
2034
2035 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2036 .dpms = radeon_atom_encoder_dpms,
2037 .mode_fixup = radeon_atom_mode_fixup,
2038 .prepare = radeon_atom_encoder_prepare,
2039 .mode_set = radeon_atom_encoder_mode_set,
2040 .commit = radeon_atom_encoder_commit,
2041 .detect = radeon_atom_dac_detect,
2042 };
2043
2044 void radeon_enc_destroy(struct drm_encoder *encoder)
2045 {
2046 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2047 kfree(radeon_encoder->enc_priv);
2048 drm_encoder_cleanup(encoder);
2049 kfree(radeon_encoder);
2050 }
2051
2052 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2053 .destroy = radeon_enc_destroy,
2054 };
2055
2056 struct radeon_encoder_atom_dac *
2057 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2058 {
2059 struct drm_device *dev = radeon_encoder->base.dev;
2060 struct radeon_device *rdev = dev->dev_private;
2061 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2062
2063 if (!dac)
2064 return NULL;
2065
2066 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2067 return dac;
2068 }
2069
2070 struct radeon_encoder_atom_dig *
2071 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2072 {
2073 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2074 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2075
2076 if (!dig)
2077 return NULL;
2078
2079 /* coherent mode by default */
2080 dig->coherent_mode = true;
2081 dig->dig_encoder = -1;
2082
2083 if (encoder_enum == 2)
2084 dig->linkb = true;
2085 else
2086 dig->linkb = false;
2087
2088 return dig;
2089 }
2090
2091 void
2092 radeon_add_atom_encoder(struct drm_device *dev,
2093 uint32_t encoder_enum,
2094 uint32_t supported_device,
2095 u16 caps)
2096 {
2097 struct radeon_device *rdev = dev->dev_private;
2098 struct drm_encoder *encoder;
2099 struct radeon_encoder *radeon_encoder;
2100
2101 /* see if we already added it */
2102 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2103 radeon_encoder = to_radeon_encoder(encoder);
2104 if (radeon_encoder->encoder_enum == encoder_enum) {
2105 radeon_encoder->devices |= supported_device;
2106 return;
2107 }
2108
2109 }
2110
2111 /* add a new one */
2112 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2113 if (!radeon_encoder)
2114 return;
2115
2116 encoder = &radeon_encoder->base;
2117 switch (rdev->num_crtc) {
2118 case 1:
2119 encoder->possible_crtcs = 0x1;
2120 break;
2121 case 2:
2122 default:
2123 encoder->possible_crtcs = 0x3;
2124 break;
2125 case 4:
2126 encoder->possible_crtcs = 0xf;
2127 break;
2128 case 6:
2129 encoder->possible_crtcs = 0x3f;
2130 break;
2131 }
2132
2133 radeon_encoder->enc_priv = NULL;
2134
2135 radeon_encoder->encoder_enum = encoder_enum;
2136 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2137 radeon_encoder->devices = supported_device;
2138 radeon_encoder->rmx_type = RMX_OFF;
2139 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2140 radeon_encoder->is_ext_encoder = false;
2141 radeon_encoder->caps = caps;
2142
2143 switch (radeon_encoder->encoder_id) {
2144 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2145 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2146 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2147 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2148 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2149 radeon_encoder->rmx_type = RMX_FULL;
2150 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2151 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2152 } else {
2153 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2154 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2155 }
2156 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2157 break;
2158 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2159 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2160 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2161 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2162 break;
2163 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2164 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2166 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2167 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2168 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2169 break;
2170 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2172 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2174 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2175 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2176 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2177 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2178 radeon_encoder->rmx_type = RMX_FULL;
2179 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2180 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2181 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2182 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2183 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2184 } else {
2185 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2186 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2187 }
2188 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2189 break;
2190 case ENCODER_OBJECT_ID_SI170B:
2191 case ENCODER_OBJECT_ID_CH7303:
2192 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2193 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2194 case ENCODER_OBJECT_ID_TITFP513:
2195 case ENCODER_OBJECT_ID_VT1623:
2196 case ENCODER_OBJECT_ID_HDMI_SI1930:
2197 case ENCODER_OBJECT_ID_TRAVIS:
2198 case ENCODER_OBJECT_ID_NUTMEG:
2199 /* these are handled by the primary encoders */
2200 radeon_encoder->is_ext_encoder = true;
2201 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2202 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2203 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2204 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2205 else
2206 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2207 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2208 break;
2209 }
2210 }
Linux kernel - Deliverables
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