2 * Copyright 2010 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include "evergreend.h"
31 #include "evergreen_reg_safe.h"
32 #include "cayman_reg_safe.h"
34 #define MAX(a,b) (((a)>(b))?(a):(b))
35 #define MIN(a,b) (((a)<(b))?(a):(b))
37 int r600_dma_cs_next_reloc(struct radeon_cs_parser
*p
,
38 struct radeon_cs_reloc
**cs_reloc
);
39 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser
*p
,
40 struct radeon_cs_reloc
**cs_reloc
);
42 struct evergreen_cs_track
{
48 u32 nsamples
; /* unused */
49 struct radeon_bo
*cb_color_bo
[12];
50 u32 cb_color_bo_offset
[12];
51 struct radeon_bo
*cb_color_fmask_bo
[8]; /* unused */
52 struct radeon_bo
*cb_color_cmask_bo
[8]; /* unused */
53 u32 cb_color_info
[12];
54 u32 cb_color_view
[12];
55 u32 cb_color_pitch
[12];
56 u32 cb_color_slice
[12];
57 u32 cb_color_slice_idx
[12];
58 u32 cb_color_attrib
[12];
59 u32 cb_color_cmask_slice
[8];/* unused */
60 u32 cb_color_fmask_slice
[8];/* unused */
62 u32 cb_shader_mask
; /* unused */
63 u32 vgt_strmout_config
;
64 u32 vgt_strmout_buffer_config
;
65 struct radeon_bo
*vgt_strmout_bo
[4];
66 u32 vgt_strmout_bo_offset
[4];
67 u32 vgt_strmout_size
[4];
74 u32 db_z_write_offset
;
75 struct radeon_bo
*db_z_read_bo
;
76 struct radeon_bo
*db_z_write_bo
;
79 u32 db_s_write_offset
;
80 struct radeon_bo
*db_s_read_bo
;
81 struct radeon_bo
*db_s_write_bo
;
82 bool sx_misc_kill_all_prims
;
88 struct radeon_bo
*htile_bo
;
91 static u32
evergreen_cs_get_aray_mode(u32 tiling_flags
)
93 if (tiling_flags
& RADEON_TILING_MACRO
)
94 return ARRAY_2D_TILED_THIN1
;
95 else if (tiling_flags
& RADEON_TILING_MICRO
)
96 return ARRAY_1D_TILED_THIN1
;
98 return ARRAY_LINEAR_GENERAL
;
101 static u32
evergreen_cs_get_num_banks(u32 nbanks
)
105 return ADDR_SURF_2_BANK
;
107 return ADDR_SURF_4_BANK
;
110 return ADDR_SURF_8_BANK
;
112 return ADDR_SURF_16_BANK
;
116 static void evergreen_cs_track_init(struct evergreen_cs_track
*track
)
120 for (i
= 0; i
< 8; i
++) {
121 track
->cb_color_fmask_bo
[i
] = NULL
;
122 track
->cb_color_cmask_bo
[i
] = NULL
;
123 track
->cb_color_cmask_slice
[i
] = 0;
124 track
->cb_color_fmask_slice
[i
] = 0;
127 for (i
= 0; i
< 12; i
++) {
128 track
->cb_color_bo
[i
] = NULL
;
129 track
->cb_color_bo_offset
[i
] = 0xFFFFFFFF;
130 track
->cb_color_info
[i
] = 0;
131 track
->cb_color_view
[i
] = 0xFFFFFFFF;
132 track
->cb_color_pitch
[i
] = 0;
133 track
->cb_color_slice
[i
] = 0xfffffff;
134 track
->cb_color_slice_idx
[i
] = 0;
136 track
->cb_target_mask
= 0xFFFFFFFF;
137 track
->cb_shader_mask
= 0xFFFFFFFF;
138 track
->cb_dirty
= true;
140 track
->db_depth_slice
= 0xffffffff;
141 track
->db_depth_view
= 0xFFFFC000;
142 track
->db_depth_size
= 0xFFFFFFFF;
143 track
->db_depth_control
= 0xFFFFFFFF;
144 track
->db_z_info
= 0xFFFFFFFF;
145 track
->db_z_read_offset
= 0xFFFFFFFF;
146 track
->db_z_write_offset
= 0xFFFFFFFF;
147 track
->db_z_read_bo
= NULL
;
148 track
->db_z_write_bo
= NULL
;
149 track
->db_s_info
= 0xFFFFFFFF;
150 track
->db_s_read_offset
= 0xFFFFFFFF;
151 track
->db_s_write_offset
= 0xFFFFFFFF;
152 track
->db_s_read_bo
= NULL
;
153 track
->db_s_write_bo
= NULL
;
154 track
->db_dirty
= true;
155 track
->htile_bo
= NULL
;
156 track
->htile_offset
= 0xFFFFFFFF;
157 track
->htile_surface
= 0;
159 for (i
= 0; i
< 4; i
++) {
160 track
->vgt_strmout_size
[i
] = 0;
161 track
->vgt_strmout_bo
[i
] = NULL
;
162 track
->vgt_strmout_bo_offset
[i
] = 0xFFFFFFFF;
164 track
->streamout_dirty
= true;
165 track
->sx_misc_kill_all_prims
= false;
169 /* value gathered from cs */
185 unsigned long base_align
;
188 static int evergreen_surface_check_linear(struct radeon_cs_parser
*p
,
189 struct eg_surface
*surf
,
192 surf
->layer_size
= surf
->nbx
* surf
->nby
* surf
->bpe
* surf
->nsamples
;
193 surf
->base_align
= surf
->bpe
;
199 static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser
*p
,
200 struct eg_surface
*surf
,
203 struct evergreen_cs_track
*track
= p
->track
;
206 palign
= MAX(64, track
->group_size
/ surf
->bpe
);
207 surf
->layer_size
= surf
->nbx
* surf
->nby
* surf
->bpe
* surf
->nsamples
;
208 surf
->base_align
= track
->group_size
;
209 surf
->palign
= palign
;
211 if (surf
->nbx
& (palign
- 1)) {
213 dev_warn(p
->dev
, "%s:%d %s pitch %d invalid must be aligned with %d\n",
214 __func__
, __LINE__
, prefix
, surf
->nbx
, palign
);
221 static int evergreen_surface_check_1d(struct radeon_cs_parser
*p
,
222 struct eg_surface
*surf
,
225 struct evergreen_cs_track
*track
= p
->track
;
228 palign
= track
->group_size
/ (8 * surf
->bpe
* surf
->nsamples
);
229 palign
= MAX(8, palign
);
230 surf
->layer_size
= surf
->nbx
* surf
->nby
* surf
->bpe
;
231 surf
->base_align
= track
->group_size
;
232 surf
->palign
= palign
;
234 if ((surf
->nbx
& (palign
- 1))) {
236 dev_warn(p
->dev
, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
237 __func__
, __LINE__
, prefix
, surf
->nbx
, palign
,
238 track
->group_size
, surf
->bpe
, surf
->nsamples
);
242 if ((surf
->nby
& (8 - 1))) {
244 dev_warn(p
->dev
, "%s:%d %s height %d invalid must be aligned with 8\n",
245 __func__
, __LINE__
, prefix
, surf
->nby
);
252 static int evergreen_surface_check_2d(struct radeon_cs_parser
*p
,
253 struct eg_surface
*surf
,
256 struct evergreen_cs_track
*track
= p
->track
;
257 unsigned palign
, halign
, tileb
, slice_pt
;
258 unsigned mtile_pr
, mtile_ps
, mtileb
;
260 tileb
= 64 * surf
->bpe
* surf
->nsamples
;
262 if (tileb
> surf
->tsplit
) {
263 slice_pt
= tileb
/ surf
->tsplit
;
265 tileb
= tileb
/ slice_pt
;
266 /* macro tile width & height */
267 palign
= (8 * surf
->bankw
* track
->npipes
) * surf
->mtilea
;
268 halign
= (8 * surf
->bankh
* surf
->nbanks
) / surf
->mtilea
;
269 mtileb
= (palign
/ 8) * (halign
/ 8) * tileb
;
270 mtile_pr
= surf
->nbx
/ palign
;
271 mtile_ps
= (mtile_pr
* surf
->nby
) / halign
;
272 surf
->layer_size
= mtile_ps
* mtileb
* slice_pt
;
273 surf
->base_align
= (palign
/ 8) * (halign
/ 8) * tileb
;
274 surf
->palign
= palign
;
275 surf
->halign
= halign
;
277 if ((surf
->nbx
& (palign
- 1))) {
279 dev_warn(p
->dev
, "%s:%d %s pitch %d invalid must be aligned with %d\n",
280 __func__
, __LINE__
, prefix
, surf
->nbx
, palign
);
284 if ((surf
->nby
& (halign
- 1))) {
286 dev_warn(p
->dev
, "%s:%d %s height %d invalid must be aligned with %d\n",
287 __func__
, __LINE__
, prefix
, surf
->nby
, halign
);
295 static int evergreen_surface_check(struct radeon_cs_parser
*p
,
296 struct eg_surface
*surf
,
299 /* some common value computed here */
300 surf
->bpe
= r600_fmt_get_blocksize(surf
->format
);
302 switch (surf
->mode
) {
303 case ARRAY_LINEAR_GENERAL
:
304 return evergreen_surface_check_linear(p
, surf
, prefix
);
305 case ARRAY_LINEAR_ALIGNED
:
306 return evergreen_surface_check_linear_aligned(p
, surf
, prefix
);
307 case ARRAY_1D_TILED_THIN1
:
308 return evergreen_surface_check_1d(p
, surf
, prefix
);
309 case ARRAY_2D_TILED_THIN1
:
310 return evergreen_surface_check_2d(p
, surf
, prefix
);
312 dev_warn(p
->dev
, "%s:%d %s invalid array mode %d\n",
313 __func__
, __LINE__
, prefix
, surf
->mode
);
319 static int evergreen_surface_value_conv_check(struct radeon_cs_parser
*p
,
320 struct eg_surface
*surf
,
323 switch (surf
->mode
) {
324 case ARRAY_2D_TILED_THIN1
:
326 case ARRAY_LINEAR_GENERAL
:
327 case ARRAY_LINEAR_ALIGNED
:
328 case ARRAY_1D_TILED_THIN1
:
331 dev_warn(p
->dev
, "%s:%d %s invalid array mode %d\n",
332 __func__
, __LINE__
, prefix
, surf
->mode
);
336 switch (surf
->nbanks
) {
337 case 0: surf
->nbanks
= 2; break;
338 case 1: surf
->nbanks
= 4; break;
339 case 2: surf
->nbanks
= 8; break;
340 case 3: surf
->nbanks
= 16; break;
342 dev_warn(p
->dev
, "%s:%d %s invalid number of banks %d\n",
343 __func__
, __LINE__
, prefix
, surf
->nbanks
);
346 switch (surf
->bankw
) {
347 case 0: surf
->bankw
= 1; break;
348 case 1: surf
->bankw
= 2; break;
349 case 2: surf
->bankw
= 4; break;
350 case 3: surf
->bankw
= 8; break;
352 dev_warn(p
->dev
, "%s:%d %s invalid bankw %d\n",
353 __func__
, __LINE__
, prefix
, surf
->bankw
);
356 switch (surf
->bankh
) {
357 case 0: surf
->bankh
= 1; break;
358 case 1: surf
->bankh
= 2; break;
359 case 2: surf
->bankh
= 4; break;
360 case 3: surf
->bankh
= 8; break;
362 dev_warn(p
->dev
, "%s:%d %s invalid bankh %d\n",
363 __func__
, __LINE__
, prefix
, surf
->bankh
);
366 switch (surf
->mtilea
) {
367 case 0: surf
->mtilea
= 1; break;
368 case 1: surf
->mtilea
= 2; break;
369 case 2: surf
->mtilea
= 4; break;
370 case 3: surf
->mtilea
= 8; break;
372 dev_warn(p
->dev
, "%s:%d %s invalid macro tile aspect %d\n",
373 __func__
, __LINE__
, prefix
, surf
->mtilea
);
376 switch (surf
->tsplit
) {
377 case 0: surf
->tsplit
= 64; break;
378 case 1: surf
->tsplit
= 128; break;
379 case 2: surf
->tsplit
= 256; break;
380 case 3: surf
->tsplit
= 512; break;
381 case 4: surf
->tsplit
= 1024; break;
382 case 5: surf
->tsplit
= 2048; break;
383 case 6: surf
->tsplit
= 4096; break;
385 dev_warn(p
->dev
, "%s:%d %s invalid tile split %d\n",
386 __func__
, __LINE__
, prefix
, surf
->tsplit
);
392 static int evergreen_cs_track_validate_cb(struct radeon_cs_parser
*p
, unsigned id
)
394 struct evergreen_cs_track
*track
= p
->track
;
395 struct eg_surface surf
;
396 unsigned pitch
, slice
, mslice
;
397 unsigned long offset
;
400 mslice
= G_028C6C_SLICE_MAX(track
->cb_color_view
[id
]) + 1;
401 pitch
= track
->cb_color_pitch
[id
];
402 slice
= track
->cb_color_slice
[id
];
403 surf
.nbx
= (pitch
+ 1) * 8;
404 surf
.nby
= ((slice
+ 1) * 64) / surf
.nbx
;
405 surf
.mode
= G_028C70_ARRAY_MODE(track
->cb_color_info
[id
]);
406 surf
.format
= G_028C70_FORMAT(track
->cb_color_info
[id
]);
407 surf
.tsplit
= G_028C74_TILE_SPLIT(track
->cb_color_attrib
[id
]);
408 surf
.nbanks
= G_028C74_NUM_BANKS(track
->cb_color_attrib
[id
]);
409 surf
.bankw
= G_028C74_BANK_WIDTH(track
->cb_color_attrib
[id
]);
410 surf
.bankh
= G_028C74_BANK_HEIGHT(track
->cb_color_attrib
[id
]);
411 surf
.mtilea
= G_028C74_MACRO_TILE_ASPECT(track
->cb_color_attrib
[id
]);
414 if (!r600_fmt_is_valid_color(surf
.format
)) {
415 dev_warn(p
->dev
, "%s:%d cb invalid format %d for %d (0x%08x)\n",
416 __func__
, __LINE__
, surf
.format
,
417 id
, track
->cb_color_info
[id
]);
421 r
= evergreen_surface_value_conv_check(p
, &surf
, "cb");
426 r
= evergreen_surface_check(p
, &surf
, "cb");
428 dev_warn(p
->dev
, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
429 __func__
, __LINE__
, id
, track
->cb_color_pitch
[id
],
430 track
->cb_color_slice
[id
], track
->cb_color_attrib
[id
],
431 track
->cb_color_info
[id
]);
435 offset
= track
->cb_color_bo_offset
[id
] << 8;
436 if (offset
& (surf
.base_align
- 1)) {
437 dev_warn(p
->dev
, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
438 __func__
, __LINE__
, id
, offset
, surf
.base_align
);
442 offset
+= surf
.layer_size
* mslice
;
443 if (offset
> radeon_bo_size(track
->cb_color_bo
[id
])) {
444 /* old ddx are broken they allocate bo with w*h*bpp but
445 * program slice with ALIGN(h, 8), catch this and patch
449 volatile u32
*ib
= p
->ib
.ptr
;
450 unsigned long tmp
, nby
, bsize
, size
, min
= 0;
452 /* find the height the ddx wants */
456 bsize
= radeon_bo_size(track
->cb_color_bo
[id
]);
457 tmp
= track
->cb_color_bo_offset
[id
] << 8;
458 for (nby
= surf
.nby
; nby
> min
; nby
--) {
459 size
= nby
* surf
.nbx
* surf
.bpe
* surf
.nsamples
;
460 if ((tmp
+ size
* mslice
) <= bsize
) {
466 slice
= ((nby
* surf
.nbx
) / 64) - 1;
467 if (!evergreen_surface_check(p
, &surf
, "cb")) {
468 /* check if this one works */
469 tmp
+= surf
.layer_size
* mslice
;
471 ib
[track
->cb_color_slice_idx
[id
]] = slice
;
477 dev_warn(p
->dev
, "%s:%d cb[%d] bo too small (layer size %d, "
478 "offset %d, max layer %d, bo size %ld, slice %d)\n",
479 __func__
, __LINE__
, id
, surf
.layer_size
,
480 track
->cb_color_bo_offset
[id
] << 8, mslice
,
481 radeon_bo_size(track
->cb_color_bo
[id
]), slice
);
482 dev_warn(p
->dev
, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
483 __func__
, __LINE__
, surf
.nbx
, surf
.nby
,
484 surf
.mode
, surf
.bpe
, surf
.nsamples
,
485 surf
.bankw
, surf
.bankh
,
486 surf
.tsplit
, surf
.mtilea
);
494 static int evergreen_cs_track_validate_htile(struct radeon_cs_parser
*p
,
495 unsigned nbx
, unsigned nby
)
497 struct evergreen_cs_track
*track
= p
->track
;
500 if (track
->htile_bo
== NULL
) {
501 dev_warn(p
->dev
, "%s:%d htile enabled without htile surface 0x%08x\n",
502 __func__
, __LINE__
, track
->db_z_info
);
506 if (G_028ABC_LINEAR(track
->htile_surface
)) {
507 /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
508 nbx
= round_up(nbx
, 16 * 8);
509 /* height is npipes htiles aligned == npipes * 8 pixel aligned */
510 nby
= round_up(nby
, track
->npipes
* 8);
512 /* always assume 8x8 htile */
513 /* align is htile align * 8, htile align vary according to
514 * number of pipe and tile width and nby
516 switch (track
->npipes
) {
518 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
519 nbx
= round_up(nbx
, 64 * 8);
520 nby
= round_up(nby
, 64 * 8);
523 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
524 nbx
= round_up(nbx
, 64 * 8);
525 nby
= round_up(nby
, 32 * 8);
528 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
529 nbx
= round_up(nbx
, 32 * 8);
530 nby
= round_up(nby
, 32 * 8);
533 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
534 nbx
= round_up(nbx
, 32 * 8);
535 nby
= round_up(nby
, 16 * 8);
538 dev_warn(p
->dev
, "%s:%d invalid num pipes %d\n",
539 __func__
, __LINE__
, track
->npipes
);
543 /* compute number of htile */
546 /* size must be aligned on npipes * 2K boundary */
547 size
= roundup(nbx
* nby
* 4, track
->npipes
* (2 << 10));
548 size
+= track
->htile_offset
;
550 if (size
> radeon_bo_size(track
->htile_bo
)) {
551 dev_warn(p
->dev
, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
552 __func__
, __LINE__
, radeon_bo_size(track
->htile_bo
),
559 static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser
*p
)
561 struct evergreen_cs_track
*track
= p
->track
;
562 struct eg_surface surf
;
563 unsigned pitch
, slice
, mslice
;
564 unsigned long offset
;
567 mslice
= G_028008_SLICE_MAX(track
->db_depth_view
) + 1;
568 pitch
= G_028058_PITCH_TILE_MAX(track
->db_depth_size
);
569 slice
= track
->db_depth_slice
;
570 surf
.nbx
= (pitch
+ 1) * 8;
571 surf
.nby
= ((slice
+ 1) * 64) / surf
.nbx
;
572 surf
.mode
= G_028040_ARRAY_MODE(track
->db_z_info
);
573 surf
.format
= G_028044_FORMAT(track
->db_s_info
);
574 surf
.tsplit
= G_028044_TILE_SPLIT(track
->db_s_info
);
575 surf
.nbanks
= G_028040_NUM_BANKS(track
->db_z_info
);
576 surf
.bankw
= G_028040_BANK_WIDTH(track
->db_z_info
);
577 surf
.bankh
= G_028040_BANK_HEIGHT(track
->db_z_info
);
578 surf
.mtilea
= G_028040_MACRO_TILE_ASPECT(track
->db_z_info
);
581 if (surf
.format
!= 1) {
582 dev_warn(p
->dev
, "%s:%d stencil invalid format %d\n",
583 __func__
, __LINE__
, surf
.format
);
586 /* replace by color format so we can use same code */
587 surf
.format
= V_028C70_COLOR_8
;
589 r
= evergreen_surface_value_conv_check(p
, &surf
, "stencil");
594 r
= evergreen_surface_check(p
, &surf
, NULL
);
596 /* old userspace doesn't compute proper depth/stencil alignment
597 * check that alignment against a bigger byte per elements and
598 * only report if that alignment is wrong too.
600 surf
.format
= V_028C70_COLOR_8_8_8_8
;
601 r
= evergreen_surface_check(p
, &surf
, "stencil");
603 dev_warn(p
->dev
, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
604 __func__
, __LINE__
, track
->db_depth_size
,
605 track
->db_depth_slice
, track
->db_s_info
, track
->db_z_info
);
610 offset
= track
->db_s_read_offset
<< 8;
611 if (offset
& (surf
.base_align
- 1)) {
612 dev_warn(p
->dev
, "%s:%d stencil read bo base %ld not aligned with %ld\n",
613 __func__
, __LINE__
, offset
, surf
.base_align
);
616 offset
+= surf
.layer_size
* mslice
;
617 if (offset
> radeon_bo_size(track
->db_s_read_bo
)) {
618 dev_warn(p
->dev
, "%s:%d stencil read bo too small (layer size %d, "
619 "offset %ld, max layer %d, bo size %ld)\n",
620 __func__
, __LINE__
, surf
.layer_size
,
621 (unsigned long)track
->db_s_read_offset
<< 8, mslice
,
622 radeon_bo_size(track
->db_s_read_bo
));
623 dev_warn(p
->dev
, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
624 __func__
, __LINE__
, track
->db_depth_size
,
625 track
->db_depth_slice
, track
->db_s_info
, track
->db_z_info
);
629 offset
= track
->db_s_write_offset
<< 8;
630 if (offset
& (surf
.base_align
- 1)) {
631 dev_warn(p
->dev
, "%s:%d stencil write bo base %ld not aligned with %ld\n",
632 __func__
, __LINE__
, offset
, surf
.base_align
);
635 offset
+= surf
.layer_size
* mslice
;
636 if (offset
> radeon_bo_size(track
->db_s_write_bo
)) {
637 dev_warn(p
->dev
, "%s:%d stencil write bo too small (layer size %d, "
638 "offset %ld, max layer %d, bo size %ld)\n",
639 __func__
, __LINE__
, surf
.layer_size
,
640 (unsigned long)track
->db_s_write_offset
<< 8, mslice
,
641 radeon_bo_size(track
->db_s_write_bo
));
646 if (G_028040_TILE_SURFACE_ENABLE(track
->db_z_info
)) {
647 r
= evergreen_cs_track_validate_htile(p
, surf
.nbx
, surf
.nby
);
656 static int evergreen_cs_track_validate_depth(struct radeon_cs_parser
*p
)
658 struct evergreen_cs_track
*track
= p
->track
;
659 struct eg_surface surf
;
660 unsigned pitch
, slice
, mslice
;
661 unsigned long offset
;
664 mslice
= G_028008_SLICE_MAX(track
->db_depth_view
) + 1;
665 pitch
= G_028058_PITCH_TILE_MAX(track
->db_depth_size
);
666 slice
= track
->db_depth_slice
;
667 surf
.nbx
= (pitch
+ 1) * 8;
668 surf
.nby
= ((slice
+ 1) * 64) / surf
.nbx
;
669 surf
.mode
= G_028040_ARRAY_MODE(track
->db_z_info
);
670 surf
.format
= G_028040_FORMAT(track
->db_z_info
);
671 surf
.tsplit
= G_028040_TILE_SPLIT(track
->db_z_info
);
672 surf
.nbanks
= G_028040_NUM_BANKS(track
->db_z_info
);
673 surf
.bankw
= G_028040_BANK_WIDTH(track
->db_z_info
);
674 surf
.bankh
= G_028040_BANK_HEIGHT(track
->db_z_info
);
675 surf
.mtilea
= G_028040_MACRO_TILE_ASPECT(track
->db_z_info
);
678 switch (surf
.format
) {
680 surf
.format
= V_028C70_COLOR_16
;
683 case V_028040_Z_32_FLOAT
:
684 surf
.format
= V_028C70_COLOR_8_8_8_8
;
687 dev_warn(p
->dev
, "%s:%d depth invalid format %d\n",
688 __func__
, __LINE__
, surf
.format
);
692 r
= evergreen_surface_value_conv_check(p
, &surf
, "depth");
694 dev_warn(p
->dev
, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
695 __func__
, __LINE__
, track
->db_depth_size
,
696 track
->db_depth_slice
, track
->db_z_info
);
700 r
= evergreen_surface_check(p
, &surf
, "depth");
702 dev_warn(p
->dev
, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
703 __func__
, __LINE__
, track
->db_depth_size
,
704 track
->db_depth_slice
, track
->db_z_info
);
708 offset
= track
->db_z_read_offset
<< 8;
709 if (offset
& (surf
.base_align
- 1)) {
710 dev_warn(p
->dev
, "%s:%d stencil read bo base %ld not aligned with %ld\n",
711 __func__
, __LINE__
, offset
, surf
.base_align
);
714 offset
+= surf
.layer_size
* mslice
;
715 if (offset
> radeon_bo_size(track
->db_z_read_bo
)) {
716 dev_warn(p
->dev
, "%s:%d depth read bo too small (layer size %d, "
717 "offset %ld, max layer %d, bo size %ld)\n",
718 __func__
, __LINE__
, surf
.layer_size
,
719 (unsigned long)track
->db_z_read_offset
<< 8, mslice
,
720 radeon_bo_size(track
->db_z_read_bo
));
724 offset
= track
->db_z_write_offset
<< 8;
725 if (offset
& (surf
.base_align
- 1)) {
726 dev_warn(p
->dev
, "%s:%d stencil write bo base %ld not aligned with %ld\n",
727 __func__
, __LINE__
, offset
, surf
.base_align
);
730 offset
+= surf
.layer_size
* mslice
;
731 if (offset
> radeon_bo_size(track
->db_z_write_bo
)) {
732 dev_warn(p
->dev
, "%s:%d depth write bo too small (layer size %d, "
733 "offset %ld, max layer %d, bo size %ld)\n",
734 __func__
, __LINE__
, surf
.layer_size
,
735 (unsigned long)track
->db_z_write_offset
<< 8, mslice
,
736 radeon_bo_size(track
->db_z_write_bo
));
741 if (G_028040_TILE_SURFACE_ENABLE(track
->db_z_info
)) {
742 r
= evergreen_cs_track_validate_htile(p
, surf
.nbx
, surf
.nby
);
751 static int evergreen_cs_track_validate_texture(struct radeon_cs_parser
*p
,
752 struct radeon_bo
*texture
,
753 struct radeon_bo
*mipmap
,
756 struct eg_surface surf
;
757 unsigned long toffset
, moffset
;
758 unsigned dim
, llevel
, mslice
, width
, height
, depth
, i
;
762 texdw
[0] = radeon_get_ib_value(p
, idx
+ 0);
763 texdw
[1] = radeon_get_ib_value(p
, idx
+ 1);
764 texdw
[2] = radeon_get_ib_value(p
, idx
+ 2);
765 texdw
[3] = radeon_get_ib_value(p
, idx
+ 3);
766 texdw
[4] = radeon_get_ib_value(p
, idx
+ 4);
767 texdw
[5] = radeon_get_ib_value(p
, idx
+ 5);
768 texdw
[6] = radeon_get_ib_value(p
, idx
+ 6);
769 texdw
[7] = radeon_get_ib_value(p
, idx
+ 7);
770 dim
= G_030000_DIM(texdw
[0]);
771 llevel
= G_030014_LAST_LEVEL(texdw
[5]);
772 mslice
= G_030014_LAST_ARRAY(texdw
[5]) + 1;
773 width
= G_030000_TEX_WIDTH(texdw
[0]) + 1;
774 height
= G_030004_TEX_HEIGHT(texdw
[1]) + 1;
775 depth
= G_030004_TEX_DEPTH(texdw
[1]) + 1;
776 surf
.format
= G_03001C_DATA_FORMAT(texdw
[7]);
777 surf
.nbx
= (G_030000_PITCH(texdw
[0]) + 1) * 8;
778 surf
.nbx
= r600_fmt_get_nblocksx(surf
.format
, surf
.nbx
);
779 surf
.nby
= r600_fmt_get_nblocksy(surf
.format
, height
);
780 surf
.mode
= G_030004_ARRAY_MODE(texdw
[1]);
781 surf
.tsplit
= G_030018_TILE_SPLIT(texdw
[6]);
782 surf
.nbanks
= G_03001C_NUM_BANKS(texdw
[7]);
783 surf
.bankw
= G_03001C_BANK_WIDTH(texdw
[7]);
784 surf
.bankh
= G_03001C_BANK_HEIGHT(texdw
[7]);
785 surf
.mtilea
= G_03001C_MACRO_TILE_ASPECT(texdw
[7]);
787 toffset
= texdw
[2] << 8;
788 moffset
= texdw
[3] << 8;
790 if (!r600_fmt_is_valid_texture(surf
.format
, p
->family
)) {
791 dev_warn(p
->dev
, "%s:%d texture invalid format %d\n",
792 __func__
, __LINE__
, surf
.format
);
796 case V_030000_SQ_TEX_DIM_1D
:
797 case V_030000_SQ_TEX_DIM_2D
:
798 case V_030000_SQ_TEX_DIM_CUBEMAP
:
799 case V_030000_SQ_TEX_DIM_1D_ARRAY
:
800 case V_030000_SQ_TEX_DIM_2D_ARRAY
:
803 case V_030000_SQ_TEX_DIM_2D_MSAA
:
804 case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
805 surf
.nsamples
= 1 << llevel
;
809 case V_030000_SQ_TEX_DIM_3D
:
812 dev_warn(p
->dev
, "%s:%d texture invalid dimension %d\n",
813 __func__
, __LINE__
, dim
);
817 r
= evergreen_surface_value_conv_check(p
, &surf
, "texture");
823 evergreen_surface_check(p
, &surf
, NULL
);
824 surf
.nby
= ALIGN(surf
.nby
, surf
.halign
);
826 r
= evergreen_surface_check(p
, &surf
, "texture");
828 dev_warn(p
->dev
, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
829 __func__
, __LINE__
, texdw
[0], texdw
[1], texdw
[4],
830 texdw
[5], texdw
[6], texdw
[7]);
834 /* check texture size */
835 if (toffset
& (surf
.base_align
- 1)) {
836 dev_warn(p
->dev
, "%s:%d texture bo base %ld not aligned with %ld\n",
837 __func__
, __LINE__
, toffset
, surf
.base_align
);
840 if (moffset
& (surf
.base_align
- 1)) {
841 dev_warn(p
->dev
, "%s:%d mipmap bo base %ld not aligned with %ld\n",
842 __func__
, __LINE__
, moffset
, surf
.base_align
);
845 if (dim
== SQ_TEX_DIM_3D
) {
846 toffset
+= surf
.layer_size
* depth
;
848 toffset
+= surf
.layer_size
* mslice
;
850 if (toffset
> radeon_bo_size(texture
)) {
851 dev_warn(p
->dev
, "%s:%d texture bo too small (layer size %d, "
852 "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
853 __func__
, __LINE__
, surf
.layer_size
,
854 (unsigned long)texdw
[2] << 8, mslice
,
855 depth
, radeon_bo_size(texture
),
862 dev_warn(p
->dev
, "%s:%i got NULL MIP_ADDRESS relocation\n",
866 return 0; /* everything's ok */
870 /* check mipmap size */
871 for (i
= 1; i
<= llevel
; i
++) {
874 w
= r600_mip_minify(width
, i
);
875 h
= r600_mip_minify(height
, i
);
876 d
= r600_mip_minify(depth
, i
);
877 surf
.nbx
= r600_fmt_get_nblocksx(surf
.format
, w
);
878 surf
.nby
= r600_fmt_get_nblocksy(surf
.format
, h
);
881 case ARRAY_2D_TILED_THIN1
:
882 if (surf
.nbx
< surf
.palign
|| surf
.nby
< surf
.halign
) {
883 surf
.mode
= ARRAY_1D_TILED_THIN1
;
885 /* recompute alignment */
886 evergreen_surface_check(p
, &surf
, NULL
);
888 case ARRAY_LINEAR_GENERAL
:
889 case ARRAY_LINEAR_ALIGNED
:
890 case ARRAY_1D_TILED_THIN1
:
893 dev_warn(p
->dev
, "%s:%d invalid array mode %d\n",
894 __func__
, __LINE__
, surf
.mode
);
897 surf
.nbx
= ALIGN(surf
.nbx
, surf
.palign
);
898 surf
.nby
= ALIGN(surf
.nby
, surf
.halign
);
900 r
= evergreen_surface_check(p
, &surf
, "mipmap");
905 if (dim
== SQ_TEX_DIM_3D
) {
906 moffset
+= surf
.layer_size
* d
;
908 moffset
+= surf
.layer_size
* mslice
;
910 if (moffset
> radeon_bo_size(mipmap
)) {
911 dev_warn(p
->dev
, "%s:%d mipmap [%d] bo too small (layer size %d, "
912 "offset %ld, coffset %ld, max layer %d, depth %d, "
913 "bo size %ld) level0 (%d %d %d)\n",
914 __func__
, __LINE__
, i
, surf
.layer_size
,
915 (unsigned long)texdw
[3] << 8, moffset
, mslice
,
916 d
, radeon_bo_size(mipmap
),
917 width
, height
, depth
);
918 dev_warn(p
->dev
, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
919 __func__
, __LINE__
, surf
.nbx
, surf
.nby
,
920 surf
.mode
, surf
.bpe
, surf
.nsamples
,
921 surf
.bankw
, surf
.bankh
,
922 surf
.tsplit
, surf
.mtilea
);
930 static int evergreen_cs_track_check(struct radeon_cs_parser
*p
)
932 struct evergreen_cs_track
*track
= p
->track
;
935 unsigned buffer_mask
= 0;
937 /* check streamout */
938 if (track
->streamout_dirty
&& track
->vgt_strmout_config
) {
939 for (i
= 0; i
< 4; i
++) {
940 if (track
->vgt_strmout_config
& (1 << i
)) {
941 buffer_mask
|= (track
->vgt_strmout_buffer_config
>> (i
* 4)) & 0xf;
945 for (i
= 0; i
< 4; i
++) {
946 if (buffer_mask
& (1 << i
)) {
947 if (track
->vgt_strmout_bo
[i
]) {
948 u64 offset
= (u64
)track
->vgt_strmout_bo_offset
[i
] +
949 (u64
)track
->vgt_strmout_size
[i
];
950 if (offset
> radeon_bo_size(track
->vgt_strmout_bo
[i
])) {
951 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
953 radeon_bo_size(track
->vgt_strmout_bo
[i
]));
957 dev_warn(p
->dev
, "No buffer for streamout %d\n", i
);
962 track
->streamout_dirty
= false;
965 if (track
->sx_misc_kill_all_prims
)
968 /* check that we have a cb for each enabled target
970 if (track
->cb_dirty
) {
971 tmp
= track
->cb_target_mask
;
972 for (i
= 0; i
< 8; i
++) {
973 if ((tmp
>> (i
* 4)) & 0xF) {
974 /* at least one component is enabled */
975 if (track
->cb_color_bo
[i
] == NULL
) {
976 dev_warn(p
->dev
, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
977 __func__
, __LINE__
, track
->cb_target_mask
, track
->cb_shader_mask
, i
);
981 r
= evergreen_cs_track_validate_cb(p
, i
);
987 track
->cb_dirty
= false;
990 if (track
->db_dirty
) {
991 /* Check stencil buffer */
992 if (G_028044_FORMAT(track
->db_s_info
) != V_028044_STENCIL_INVALID
&&
993 G_028800_STENCIL_ENABLE(track
->db_depth_control
)) {
994 r
= evergreen_cs_track_validate_stencil(p
);
998 /* Check depth buffer */
999 if (G_028040_FORMAT(track
->db_z_info
) != V_028040_Z_INVALID
&&
1000 G_028800_Z_ENABLE(track
->db_depth_control
)) {
1001 r
= evergreen_cs_track_validate_depth(p
);
1005 track
->db_dirty
= false;
1012 * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
1013 * @parser: parser structure holding parsing context.
1014 * @pkt: where to store packet informations
1016 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1017 * if packet is bigger than remaining ib size. or if packets is unknown.
1019 static int evergreen_cs_packet_parse(struct radeon_cs_parser
*p
,
1020 struct radeon_cs_packet
*pkt
,
1023 struct radeon_cs_chunk
*ib_chunk
= &p
->chunks
[p
->chunk_ib_idx
];
1026 if (idx
>= ib_chunk
->length_dw
) {
1027 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1028 idx
, ib_chunk
->length_dw
);
1031 header
= radeon_get_ib_value(p
, idx
);
1033 pkt
->type
= CP_PACKET_GET_TYPE(header
);
1034 pkt
->count
= CP_PACKET_GET_COUNT(header
);
1035 pkt
->one_reg_wr
= 0;
1036 switch (pkt
->type
) {
1038 pkt
->reg
= CP_PACKET0_GET_REG(header
);
1041 pkt
->opcode
= CP_PACKET3_GET_OPCODE(header
);
1047 DRM_ERROR("Unknown packet type %d at %d !\n", pkt
->type
, idx
);
1050 if ((pkt
->count
+ 1 + pkt
->idx
) >= ib_chunk
->length_dw
) {
1051 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1052 pkt
->idx
, pkt
->type
, pkt
->count
, ib_chunk
->length_dw
);
1059 * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1060 * @parser: parser structure holding parsing context.
1061 * @data: pointer to relocation data
1062 * @offset_start: starting offset
1063 * @offset_mask: offset mask (to align start offset on)
1064 * @reloc: reloc informations
1066 * Check next packet is relocation packet3, do bo validation and compute
1067 * GPU offset using the provided start.
1069 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser
*p
,
1070 struct radeon_cs_reloc
**cs_reloc
)
1072 struct radeon_cs_chunk
*relocs_chunk
;
1073 struct radeon_cs_packet p3reloc
;
1077 if (p
->chunk_relocs_idx
== -1) {
1078 DRM_ERROR("No relocation chunk !\n");
1082 relocs_chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
1083 r
= evergreen_cs_packet_parse(p
, &p3reloc
, p
->idx
);
1087 p
->idx
+= p3reloc
.count
+ 2;
1088 if (p3reloc
.type
!= PACKET_TYPE3
|| p3reloc
.opcode
!= PACKET3_NOP
) {
1089 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1093 idx
= radeon_get_ib_value(p
, p3reloc
.idx
+ 1);
1094 if (idx
>= relocs_chunk
->length_dw
) {
1095 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1096 idx
, relocs_chunk
->length_dw
);
1099 /* FIXME: we assume reloc size is 4 dwords */
1100 *cs_reloc
= p
->relocs_ptr
[(idx
/ 4)];
1105 * evergreen_cs_packet_next_is_pkt3_nop() - test if the next packet is NOP
1106 * @p: structure holding the parser context.
1108 * Check if the next packet is a relocation packet3.
1110 static bool evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser
*p
)
1112 struct radeon_cs_packet p3reloc
;
1115 r
= evergreen_cs_packet_parse(p
, &p3reloc
, p
->idx
);
1119 if (p3reloc
.type
!= PACKET_TYPE3
|| p3reloc
.opcode
!= PACKET3_NOP
) {
1126 * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
1127 * @parser: parser structure holding parsing context.
1129 * Userspace sends a special sequence for VLINE waits.
1130 * PACKET0 - VLINE_START_END + value
1131 * PACKET3 - WAIT_REG_MEM poll vline status reg
1132 * RELOC (P3) - crtc_id in reloc.
1134 * This function parses this and relocates the VLINE START END
1135 * and WAIT_REG_MEM packets to the correct crtc.
1136 * It also detects a switched off crtc and nulls out the
1137 * wait in that case.
1139 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser
*p
)
1141 struct drm_mode_object
*obj
;
1142 struct drm_crtc
*crtc
;
1143 struct radeon_crtc
*radeon_crtc
;
1144 struct radeon_cs_packet p3reloc
, wait_reg_mem
;
1147 uint32_t header
, h_idx
, reg
, wait_reg_mem_info
;
1148 volatile uint32_t *ib
;
1152 /* parse the WAIT_REG_MEM */
1153 r
= evergreen_cs_packet_parse(p
, &wait_reg_mem
, p
->idx
);
1157 /* check its a WAIT_REG_MEM */
1158 if (wait_reg_mem
.type
!= PACKET_TYPE3
||
1159 wait_reg_mem
.opcode
!= PACKET3_WAIT_REG_MEM
) {
1160 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
1164 wait_reg_mem_info
= radeon_get_ib_value(p
, wait_reg_mem
.idx
+ 1);
1165 /* bit 4 is reg (0) or mem (1) */
1166 if (wait_reg_mem_info
& 0x10) {
1167 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
1170 /* waiting for value to be equal */
1171 if ((wait_reg_mem_info
& 0x7) != 0x3) {
1172 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1175 if ((radeon_get_ib_value(p
, wait_reg_mem
.idx
+ 2) << 2) != EVERGREEN_VLINE_STATUS
) {
1176 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1180 if (radeon_get_ib_value(p
, wait_reg_mem
.idx
+ 5) != EVERGREEN_VLINE_STAT
) {
1181 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1185 /* jump over the NOP */
1186 r
= evergreen_cs_packet_parse(p
, &p3reloc
, p
->idx
+ wait_reg_mem
.count
+ 2);
1191 p
->idx
+= wait_reg_mem
.count
+ 2;
1192 p
->idx
+= p3reloc
.count
+ 2;
1194 header
= radeon_get_ib_value(p
, h_idx
);
1195 crtc_id
= radeon_get_ib_value(p
, h_idx
+ 2 + 7 + 1);
1196 reg
= CP_PACKET0_GET_REG(header
);
1197 obj
= drm_mode_object_find(p
->rdev
->ddev
, crtc_id
, DRM_MODE_OBJECT_CRTC
);
1199 DRM_ERROR("cannot find crtc %d\n", crtc_id
);
1202 crtc
= obj_to_crtc(obj
);
1203 radeon_crtc
= to_radeon_crtc(crtc
);
1204 crtc_id
= radeon_crtc
->crtc_id
;
1206 if (!crtc
->enabled
) {
1207 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1208 ib
[h_idx
+ 2] = PACKET2(0);
1209 ib
[h_idx
+ 3] = PACKET2(0);
1210 ib
[h_idx
+ 4] = PACKET2(0);
1211 ib
[h_idx
+ 5] = PACKET2(0);
1212 ib
[h_idx
+ 6] = PACKET2(0);
1213 ib
[h_idx
+ 7] = PACKET2(0);
1214 ib
[h_idx
+ 8] = PACKET2(0);
1217 case EVERGREEN_VLINE_START_END
:
1218 header
&= ~R600_CP_PACKET0_REG_MASK
;
1219 header
|= (EVERGREEN_VLINE_START_END
+ radeon_crtc
->crtc_offset
) >> 2;
1221 ib
[h_idx
+ 4] = (EVERGREEN_VLINE_STATUS
+ radeon_crtc
->crtc_offset
) >> 2;
1224 DRM_ERROR("unknown crtc reloc\n");
1231 static int evergreen_packet0_check(struct radeon_cs_parser
*p
,
1232 struct radeon_cs_packet
*pkt
,
1233 unsigned idx
, unsigned reg
)
1238 case EVERGREEN_VLINE_START_END
:
1239 r
= evergreen_cs_packet_parse_vline(p
);
1241 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1247 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
1254 static int evergreen_cs_parse_packet0(struct radeon_cs_parser
*p
,
1255 struct radeon_cs_packet
*pkt
)
1263 for (i
= 0; i
<= pkt
->count
; i
++, idx
++, reg
+= 4) {
1264 r
= evergreen_packet0_check(p
, pkt
, idx
, reg
);
1273 * evergreen_cs_check_reg() - check if register is authorized or not
1274 * @parser: parser structure holding parsing context
1275 * @reg: register we are testing
1276 * @idx: index into the cs buffer
1278 * This function will test against evergreen_reg_safe_bm and return 0
1279 * if register is safe. If register is not flag as safe this function
1280 * will test it against a list of register needind special handling.
1282 static int evergreen_cs_check_reg(struct radeon_cs_parser
*p
, u32 reg
, u32 idx
)
1284 struct evergreen_cs_track
*track
= (struct evergreen_cs_track
*)p
->track
;
1285 struct radeon_cs_reloc
*reloc
;
1290 if (p
->rdev
->family
>= CHIP_CAYMAN
)
1291 last_reg
= ARRAY_SIZE(cayman_reg_safe_bm
);
1293 last_reg
= ARRAY_SIZE(evergreen_reg_safe_bm
);
1296 if (i
>= last_reg
) {
1297 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
1300 m
= 1 << ((reg
>> 2) & 31);
1301 if (p
->rdev
->family
>= CHIP_CAYMAN
) {
1302 if (!(cayman_reg_safe_bm
[i
] & m
))
1305 if (!(evergreen_reg_safe_bm
[i
] & m
))
1310 /* force following reg to 0 in an attempt to disable out buffer
1311 * which will need us to better understand how it works to perform
1312 * security check on it (Jerome)
1314 case SQ_ESGS_RING_SIZE
:
1315 case SQ_GSVS_RING_SIZE
:
1316 case SQ_ESTMP_RING_SIZE
:
1317 case SQ_GSTMP_RING_SIZE
:
1318 case SQ_HSTMP_RING_SIZE
:
1319 case SQ_LSTMP_RING_SIZE
:
1320 case SQ_PSTMP_RING_SIZE
:
1321 case SQ_VSTMP_RING_SIZE
:
1322 case SQ_ESGS_RING_ITEMSIZE
:
1323 case SQ_ESTMP_RING_ITEMSIZE
:
1324 case SQ_GSTMP_RING_ITEMSIZE
:
1325 case SQ_GSVS_RING_ITEMSIZE
:
1326 case SQ_GS_VERT_ITEMSIZE
:
1327 case SQ_GS_VERT_ITEMSIZE_1
:
1328 case SQ_GS_VERT_ITEMSIZE_2
:
1329 case SQ_GS_VERT_ITEMSIZE_3
:
1330 case SQ_GSVS_RING_OFFSET_1
:
1331 case SQ_GSVS_RING_OFFSET_2
:
1332 case SQ_GSVS_RING_OFFSET_3
:
1333 case SQ_HSTMP_RING_ITEMSIZE
:
1334 case SQ_LSTMP_RING_ITEMSIZE
:
1335 case SQ_PSTMP_RING_ITEMSIZE
:
1336 case SQ_VSTMP_RING_ITEMSIZE
:
1337 case VGT_TF_RING_SIZE
:
1338 /* get value to populate the IB don't remove */
1339 /*tmp =radeon_get_ib_value(p, idx);
1342 case SQ_ESGS_RING_BASE
:
1343 case SQ_GSVS_RING_BASE
:
1344 case SQ_ESTMP_RING_BASE
:
1345 case SQ_GSTMP_RING_BASE
:
1346 case SQ_HSTMP_RING_BASE
:
1347 case SQ_LSTMP_RING_BASE
:
1348 case SQ_PSTMP_RING_BASE
:
1349 case SQ_VSTMP_RING_BASE
:
1350 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1352 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1356 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1358 case DB_DEPTH_CONTROL
:
1359 track
->db_depth_control
= radeon_get_ib_value(p
, idx
);
1360 track
->db_dirty
= true;
1362 case CAYMAN_DB_EQAA
:
1363 if (p
->rdev
->family
< CHIP_CAYMAN
) {
1364 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1369 case CAYMAN_DB_DEPTH_INFO
:
1370 if (p
->rdev
->family
< CHIP_CAYMAN
) {
1371 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1377 track
->db_z_info
= radeon_get_ib_value(p
, idx
);
1378 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
1379 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1381 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1385 ib
[idx
] &= ~Z_ARRAY_MODE(0xf);
1386 track
->db_z_info
&= ~Z_ARRAY_MODE(0xf);
1387 ib
[idx
] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc
->lobj
.tiling_flags
));
1388 track
->db_z_info
|= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc
->lobj
.tiling_flags
));
1389 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
) {
1390 unsigned bankw
, bankh
, mtaspect
, tile_split
;
1392 evergreen_tiling_fields(reloc
->lobj
.tiling_flags
,
1393 &bankw
, &bankh
, &mtaspect
,
1395 ib
[idx
] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track
->nbanks
));
1396 ib
[idx
] |= DB_TILE_SPLIT(tile_split
) |
1397 DB_BANK_WIDTH(bankw
) |
1398 DB_BANK_HEIGHT(bankh
) |
1399 DB_MACRO_TILE_ASPECT(mtaspect
);
1402 track
->db_dirty
= true;
1404 case DB_STENCIL_INFO
:
1405 track
->db_s_info
= radeon_get_ib_value(p
, idx
);
1406 track
->db_dirty
= true;
1409 track
->db_depth_view
= radeon_get_ib_value(p
, idx
);
1410 track
->db_dirty
= true;
1413 track
->db_depth_size
= radeon_get_ib_value(p
, idx
);
1414 track
->db_dirty
= true;
1416 case R_02805C_DB_DEPTH_SLICE
:
1417 track
->db_depth_slice
= radeon_get_ib_value(p
, idx
);
1418 track
->db_dirty
= true;
1420 case DB_Z_READ_BASE
:
1421 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1423 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1427 track
->db_z_read_offset
= radeon_get_ib_value(p
, idx
);
1428 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1429 track
->db_z_read_bo
= reloc
->robj
;
1430 track
->db_dirty
= true;
1432 case DB_Z_WRITE_BASE
:
1433 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1435 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1439 track
->db_z_write_offset
= radeon_get_ib_value(p
, idx
);
1440 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1441 track
->db_z_write_bo
= reloc
->robj
;
1442 track
->db_dirty
= true;
1444 case DB_STENCIL_READ_BASE
:
1445 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1447 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1451 track
->db_s_read_offset
= radeon_get_ib_value(p
, idx
);
1452 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1453 track
->db_s_read_bo
= reloc
->robj
;
1454 track
->db_dirty
= true;
1456 case DB_STENCIL_WRITE_BASE
:
1457 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1459 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1463 track
->db_s_write_offset
= radeon_get_ib_value(p
, idx
);
1464 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1465 track
->db_s_write_bo
= reloc
->robj
;
1466 track
->db_dirty
= true;
1468 case VGT_STRMOUT_CONFIG
:
1469 track
->vgt_strmout_config
= radeon_get_ib_value(p
, idx
);
1470 track
->streamout_dirty
= true;
1472 case VGT_STRMOUT_BUFFER_CONFIG
:
1473 track
->vgt_strmout_buffer_config
= radeon_get_ib_value(p
, idx
);
1474 track
->streamout_dirty
= true;
1476 case VGT_STRMOUT_BUFFER_BASE_0
:
1477 case VGT_STRMOUT_BUFFER_BASE_1
:
1478 case VGT_STRMOUT_BUFFER_BASE_2
:
1479 case VGT_STRMOUT_BUFFER_BASE_3
:
1480 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1482 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1486 tmp
= (reg
- VGT_STRMOUT_BUFFER_BASE_0
) / 16;
1487 track
->vgt_strmout_bo_offset
[tmp
] = radeon_get_ib_value(p
, idx
) << 8;
1488 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1489 track
->vgt_strmout_bo
[tmp
] = reloc
->robj
;
1490 track
->streamout_dirty
= true;
1492 case VGT_STRMOUT_BUFFER_SIZE_0
:
1493 case VGT_STRMOUT_BUFFER_SIZE_1
:
1494 case VGT_STRMOUT_BUFFER_SIZE_2
:
1495 case VGT_STRMOUT_BUFFER_SIZE_3
:
1496 tmp
= (reg
- VGT_STRMOUT_BUFFER_SIZE_0
) / 16;
1497 /* size in register is DWs, convert to bytes */
1498 track
->vgt_strmout_size
[tmp
] = radeon_get_ib_value(p
, idx
) * 4;
1499 track
->streamout_dirty
= true;
1502 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1504 dev_warn(p
->dev
, "missing reloc for CP_COHER_BASE "
1508 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1509 case CB_TARGET_MASK
:
1510 track
->cb_target_mask
= radeon_get_ib_value(p
, idx
);
1511 track
->cb_dirty
= true;
1513 case CB_SHADER_MASK
:
1514 track
->cb_shader_mask
= radeon_get_ib_value(p
, idx
);
1515 track
->cb_dirty
= true;
1517 case PA_SC_AA_CONFIG
:
1518 if (p
->rdev
->family
>= CHIP_CAYMAN
) {
1519 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1523 tmp
= radeon_get_ib_value(p
, idx
) & MSAA_NUM_SAMPLES_MASK
;
1524 track
->nsamples
= 1 << tmp
;
1526 case CAYMAN_PA_SC_AA_CONFIG
:
1527 if (p
->rdev
->family
< CHIP_CAYMAN
) {
1528 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1532 tmp
= radeon_get_ib_value(p
, idx
) & CAYMAN_MSAA_NUM_SAMPLES_MASK
;
1533 track
->nsamples
= 1 << tmp
;
1535 case CB_COLOR0_VIEW
:
1536 case CB_COLOR1_VIEW
:
1537 case CB_COLOR2_VIEW
:
1538 case CB_COLOR3_VIEW
:
1539 case CB_COLOR4_VIEW
:
1540 case CB_COLOR5_VIEW
:
1541 case CB_COLOR6_VIEW
:
1542 case CB_COLOR7_VIEW
:
1543 tmp
= (reg
- CB_COLOR0_VIEW
) / 0x3c;
1544 track
->cb_color_view
[tmp
] = radeon_get_ib_value(p
, idx
);
1545 track
->cb_dirty
= true;
1547 case CB_COLOR8_VIEW
:
1548 case CB_COLOR9_VIEW
:
1549 case CB_COLOR10_VIEW
:
1550 case CB_COLOR11_VIEW
:
1551 tmp
= ((reg
- CB_COLOR8_VIEW
) / 0x1c) + 8;
1552 track
->cb_color_view
[tmp
] = radeon_get_ib_value(p
, idx
);
1553 track
->cb_dirty
= true;
1555 case CB_COLOR0_INFO
:
1556 case CB_COLOR1_INFO
:
1557 case CB_COLOR2_INFO
:
1558 case CB_COLOR3_INFO
:
1559 case CB_COLOR4_INFO
:
1560 case CB_COLOR5_INFO
:
1561 case CB_COLOR6_INFO
:
1562 case CB_COLOR7_INFO
:
1563 tmp
= (reg
- CB_COLOR0_INFO
) / 0x3c;
1564 track
->cb_color_info
[tmp
] = radeon_get_ib_value(p
, idx
);
1565 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
1566 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1568 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1572 ib
[idx
] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc
->lobj
.tiling_flags
));
1573 track
->cb_color_info
[tmp
] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc
->lobj
.tiling_flags
));
1575 track
->cb_dirty
= true;
1577 case CB_COLOR8_INFO
:
1578 case CB_COLOR9_INFO
:
1579 case CB_COLOR10_INFO
:
1580 case CB_COLOR11_INFO
:
1581 tmp
= ((reg
- CB_COLOR8_INFO
) / 0x1c) + 8;
1582 track
->cb_color_info
[tmp
] = radeon_get_ib_value(p
, idx
);
1583 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
1584 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1586 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1590 ib
[idx
] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc
->lobj
.tiling_flags
));
1591 track
->cb_color_info
[tmp
] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc
->lobj
.tiling_flags
));
1593 track
->cb_dirty
= true;
1595 case CB_COLOR0_PITCH
:
1596 case CB_COLOR1_PITCH
:
1597 case CB_COLOR2_PITCH
:
1598 case CB_COLOR3_PITCH
:
1599 case CB_COLOR4_PITCH
:
1600 case CB_COLOR5_PITCH
:
1601 case CB_COLOR6_PITCH
:
1602 case CB_COLOR7_PITCH
:
1603 tmp
= (reg
- CB_COLOR0_PITCH
) / 0x3c;
1604 track
->cb_color_pitch
[tmp
] = radeon_get_ib_value(p
, idx
);
1605 track
->cb_dirty
= true;
1607 case CB_COLOR8_PITCH
:
1608 case CB_COLOR9_PITCH
:
1609 case CB_COLOR10_PITCH
:
1610 case CB_COLOR11_PITCH
:
1611 tmp
= ((reg
- CB_COLOR8_PITCH
) / 0x1c) + 8;
1612 track
->cb_color_pitch
[tmp
] = radeon_get_ib_value(p
, idx
);
1613 track
->cb_dirty
= true;
1615 case CB_COLOR0_SLICE
:
1616 case CB_COLOR1_SLICE
:
1617 case CB_COLOR2_SLICE
:
1618 case CB_COLOR3_SLICE
:
1619 case CB_COLOR4_SLICE
:
1620 case CB_COLOR5_SLICE
:
1621 case CB_COLOR6_SLICE
:
1622 case CB_COLOR7_SLICE
:
1623 tmp
= (reg
- CB_COLOR0_SLICE
) / 0x3c;
1624 track
->cb_color_slice
[tmp
] = radeon_get_ib_value(p
, idx
);
1625 track
->cb_color_slice_idx
[tmp
] = idx
;
1626 track
->cb_dirty
= true;
1628 case CB_COLOR8_SLICE
:
1629 case CB_COLOR9_SLICE
:
1630 case CB_COLOR10_SLICE
:
1631 case CB_COLOR11_SLICE
:
1632 tmp
= ((reg
- CB_COLOR8_SLICE
) / 0x1c) + 8;
1633 track
->cb_color_slice
[tmp
] = radeon_get_ib_value(p
, idx
);
1634 track
->cb_color_slice_idx
[tmp
] = idx
;
1635 track
->cb_dirty
= true;
1637 case CB_COLOR0_ATTRIB
:
1638 case CB_COLOR1_ATTRIB
:
1639 case CB_COLOR2_ATTRIB
:
1640 case CB_COLOR3_ATTRIB
:
1641 case CB_COLOR4_ATTRIB
:
1642 case CB_COLOR5_ATTRIB
:
1643 case CB_COLOR6_ATTRIB
:
1644 case CB_COLOR7_ATTRIB
:
1645 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1647 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1651 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
1652 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
) {
1653 unsigned bankw
, bankh
, mtaspect
, tile_split
;
1655 evergreen_tiling_fields(reloc
->lobj
.tiling_flags
,
1656 &bankw
, &bankh
, &mtaspect
,
1658 ib
[idx
] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track
->nbanks
));
1659 ib
[idx
] |= CB_TILE_SPLIT(tile_split
) |
1660 CB_BANK_WIDTH(bankw
) |
1661 CB_BANK_HEIGHT(bankh
) |
1662 CB_MACRO_TILE_ASPECT(mtaspect
);
1665 tmp
= ((reg
- CB_COLOR0_ATTRIB
) / 0x3c);
1666 track
->cb_color_attrib
[tmp
] = ib
[idx
];
1667 track
->cb_dirty
= true;
1669 case CB_COLOR8_ATTRIB
:
1670 case CB_COLOR9_ATTRIB
:
1671 case CB_COLOR10_ATTRIB
:
1672 case CB_COLOR11_ATTRIB
:
1673 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1675 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1679 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
1680 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
) {
1681 unsigned bankw
, bankh
, mtaspect
, tile_split
;
1683 evergreen_tiling_fields(reloc
->lobj
.tiling_flags
,
1684 &bankw
, &bankh
, &mtaspect
,
1686 ib
[idx
] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track
->nbanks
));
1687 ib
[idx
] |= CB_TILE_SPLIT(tile_split
) |
1688 CB_BANK_WIDTH(bankw
) |
1689 CB_BANK_HEIGHT(bankh
) |
1690 CB_MACRO_TILE_ASPECT(mtaspect
);
1693 tmp
= ((reg
- CB_COLOR8_ATTRIB
) / 0x1c) + 8;
1694 track
->cb_color_attrib
[tmp
] = ib
[idx
];
1695 track
->cb_dirty
= true;
1697 case CB_COLOR0_FMASK
:
1698 case CB_COLOR1_FMASK
:
1699 case CB_COLOR2_FMASK
:
1700 case CB_COLOR3_FMASK
:
1701 case CB_COLOR4_FMASK
:
1702 case CB_COLOR5_FMASK
:
1703 case CB_COLOR6_FMASK
:
1704 case CB_COLOR7_FMASK
:
1705 tmp
= (reg
- CB_COLOR0_FMASK
) / 0x3c;
1706 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1708 dev_err(p
->dev
, "bad SET_CONTEXT_REG 0x%04X\n", reg
);
1711 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1712 track
->cb_color_fmask_bo
[tmp
] = reloc
->robj
;
1714 case CB_COLOR0_CMASK
:
1715 case CB_COLOR1_CMASK
:
1716 case CB_COLOR2_CMASK
:
1717 case CB_COLOR3_CMASK
:
1718 case CB_COLOR4_CMASK
:
1719 case CB_COLOR5_CMASK
:
1720 case CB_COLOR6_CMASK
:
1721 case CB_COLOR7_CMASK
:
1722 tmp
= (reg
- CB_COLOR0_CMASK
) / 0x3c;
1723 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1725 dev_err(p
->dev
, "bad SET_CONTEXT_REG 0x%04X\n", reg
);
1728 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1729 track
->cb_color_cmask_bo
[tmp
] = reloc
->robj
;
1731 case CB_COLOR0_FMASK_SLICE
:
1732 case CB_COLOR1_FMASK_SLICE
:
1733 case CB_COLOR2_FMASK_SLICE
:
1734 case CB_COLOR3_FMASK_SLICE
:
1735 case CB_COLOR4_FMASK_SLICE
:
1736 case CB_COLOR5_FMASK_SLICE
:
1737 case CB_COLOR6_FMASK_SLICE
:
1738 case CB_COLOR7_FMASK_SLICE
:
1739 tmp
= (reg
- CB_COLOR0_FMASK_SLICE
) / 0x3c;
1740 track
->cb_color_fmask_slice
[tmp
] = radeon_get_ib_value(p
, idx
);
1742 case CB_COLOR0_CMASK_SLICE
:
1743 case CB_COLOR1_CMASK_SLICE
:
1744 case CB_COLOR2_CMASK_SLICE
:
1745 case CB_COLOR3_CMASK_SLICE
:
1746 case CB_COLOR4_CMASK_SLICE
:
1747 case CB_COLOR5_CMASK_SLICE
:
1748 case CB_COLOR6_CMASK_SLICE
:
1749 case CB_COLOR7_CMASK_SLICE
:
1750 tmp
= (reg
- CB_COLOR0_CMASK_SLICE
) / 0x3c;
1751 track
->cb_color_cmask_slice
[tmp
] = radeon_get_ib_value(p
, idx
);
1753 case CB_COLOR0_BASE
:
1754 case CB_COLOR1_BASE
:
1755 case CB_COLOR2_BASE
:
1756 case CB_COLOR3_BASE
:
1757 case CB_COLOR4_BASE
:
1758 case CB_COLOR5_BASE
:
1759 case CB_COLOR6_BASE
:
1760 case CB_COLOR7_BASE
:
1761 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1763 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1767 tmp
= (reg
- CB_COLOR0_BASE
) / 0x3c;
1768 track
->cb_color_bo_offset
[tmp
] = radeon_get_ib_value(p
, idx
);
1769 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1770 track
->cb_color_bo
[tmp
] = reloc
->robj
;
1771 track
->cb_dirty
= true;
1773 case CB_COLOR8_BASE
:
1774 case CB_COLOR9_BASE
:
1775 case CB_COLOR10_BASE
:
1776 case CB_COLOR11_BASE
:
1777 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1779 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1783 tmp
= ((reg
- CB_COLOR8_BASE
) / 0x1c) + 8;
1784 track
->cb_color_bo_offset
[tmp
] = radeon_get_ib_value(p
, idx
);
1785 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1786 track
->cb_color_bo
[tmp
] = reloc
->robj
;
1787 track
->cb_dirty
= true;
1789 case DB_HTILE_DATA_BASE
:
1790 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1792 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1796 track
->htile_offset
= radeon_get_ib_value(p
, idx
);
1797 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1798 track
->htile_bo
= reloc
->robj
;
1799 track
->db_dirty
= true;
1801 case DB_HTILE_SURFACE
:
1803 track
->htile_surface
= radeon_get_ib_value(p
, idx
);
1804 /* force 8x8 htile width and height */
1806 track
->db_dirty
= true;
1808 case CB_IMMED0_BASE
:
1809 case CB_IMMED1_BASE
:
1810 case CB_IMMED2_BASE
:
1811 case CB_IMMED3_BASE
:
1812 case CB_IMMED4_BASE
:
1813 case CB_IMMED5_BASE
:
1814 case CB_IMMED6_BASE
:
1815 case CB_IMMED7_BASE
:
1816 case CB_IMMED8_BASE
:
1817 case CB_IMMED9_BASE
:
1818 case CB_IMMED10_BASE
:
1819 case CB_IMMED11_BASE
:
1820 case SQ_PGM_START_FS
:
1821 case SQ_PGM_START_ES
:
1822 case SQ_PGM_START_VS
:
1823 case SQ_PGM_START_GS
:
1824 case SQ_PGM_START_PS
:
1825 case SQ_PGM_START_HS
:
1826 case SQ_PGM_START_LS
:
1827 case SQ_CONST_MEM_BASE
:
1828 case SQ_ALU_CONST_CACHE_GS_0
:
1829 case SQ_ALU_CONST_CACHE_GS_1
:
1830 case SQ_ALU_CONST_CACHE_GS_2
:
1831 case SQ_ALU_CONST_CACHE_GS_3
:
1832 case SQ_ALU_CONST_CACHE_GS_4
:
1833 case SQ_ALU_CONST_CACHE_GS_5
:
1834 case SQ_ALU_CONST_CACHE_GS_6
:
1835 case SQ_ALU_CONST_CACHE_GS_7
:
1836 case SQ_ALU_CONST_CACHE_GS_8
:
1837 case SQ_ALU_CONST_CACHE_GS_9
:
1838 case SQ_ALU_CONST_CACHE_GS_10
:
1839 case SQ_ALU_CONST_CACHE_GS_11
:
1840 case SQ_ALU_CONST_CACHE_GS_12
:
1841 case SQ_ALU_CONST_CACHE_GS_13
:
1842 case SQ_ALU_CONST_CACHE_GS_14
:
1843 case SQ_ALU_CONST_CACHE_GS_15
:
1844 case SQ_ALU_CONST_CACHE_PS_0
:
1845 case SQ_ALU_CONST_CACHE_PS_1
:
1846 case SQ_ALU_CONST_CACHE_PS_2
:
1847 case SQ_ALU_CONST_CACHE_PS_3
:
1848 case SQ_ALU_CONST_CACHE_PS_4
:
1849 case SQ_ALU_CONST_CACHE_PS_5
:
1850 case SQ_ALU_CONST_CACHE_PS_6
:
1851 case SQ_ALU_CONST_CACHE_PS_7
:
1852 case SQ_ALU_CONST_CACHE_PS_8
:
1853 case SQ_ALU_CONST_CACHE_PS_9
:
1854 case SQ_ALU_CONST_CACHE_PS_10
:
1855 case SQ_ALU_CONST_CACHE_PS_11
:
1856 case SQ_ALU_CONST_CACHE_PS_12
:
1857 case SQ_ALU_CONST_CACHE_PS_13
:
1858 case SQ_ALU_CONST_CACHE_PS_14
:
1859 case SQ_ALU_CONST_CACHE_PS_15
:
1860 case SQ_ALU_CONST_CACHE_VS_0
:
1861 case SQ_ALU_CONST_CACHE_VS_1
:
1862 case SQ_ALU_CONST_CACHE_VS_2
:
1863 case SQ_ALU_CONST_CACHE_VS_3
:
1864 case SQ_ALU_CONST_CACHE_VS_4
:
1865 case SQ_ALU_CONST_CACHE_VS_5
:
1866 case SQ_ALU_CONST_CACHE_VS_6
:
1867 case SQ_ALU_CONST_CACHE_VS_7
:
1868 case SQ_ALU_CONST_CACHE_VS_8
:
1869 case SQ_ALU_CONST_CACHE_VS_9
:
1870 case SQ_ALU_CONST_CACHE_VS_10
:
1871 case SQ_ALU_CONST_CACHE_VS_11
:
1872 case SQ_ALU_CONST_CACHE_VS_12
:
1873 case SQ_ALU_CONST_CACHE_VS_13
:
1874 case SQ_ALU_CONST_CACHE_VS_14
:
1875 case SQ_ALU_CONST_CACHE_VS_15
:
1876 case SQ_ALU_CONST_CACHE_HS_0
:
1877 case SQ_ALU_CONST_CACHE_HS_1
:
1878 case SQ_ALU_CONST_CACHE_HS_2
:
1879 case SQ_ALU_CONST_CACHE_HS_3
:
1880 case SQ_ALU_CONST_CACHE_HS_4
:
1881 case SQ_ALU_CONST_CACHE_HS_5
:
1882 case SQ_ALU_CONST_CACHE_HS_6
:
1883 case SQ_ALU_CONST_CACHE_HS_7
:
1884 case SQ_ALU_CONST_CACHE_HS_8
:
1885 case SQ_ALU_CONST_CACHE_HS_9
:
1886 case SQ_ALU_CONST_CACHE_HS_10
:
1887 case SQ_ALU_CONST_CACHE_HS_11
:
1888 case SQ_ALU_CONST_CACHE_HS_12
:
1889 case SQ_ALU_CONST_CACHE_HS_13
:
1890 case SQ_ALU_CONST_CACHE_HS_14
:
1891 case SQ_ALU_CONST_CACHE_HS_15
:
1892 case SQ_ALU_CONST_CACHE_LS_0
:
1893 case SQ_ALU_CONST_CACHE_LS_1
:
1894 case SQ_ALU_CONST_CACHE_LS_2
:
1895 case SQ_ALU_CONST_CACHE_LS_3
:
1896 case SQ_ALU_CONST_CACHE_LS_4
:
1897 case SQ_ALU_CONST_CACHE_LS_5
:
1898 case SQ_ALU_CONST_CACHE_LS_6
:
1899 case SQ_ALU_CONST_CACHE_LS_7
:
1900 case SQ_ALU_CONST_CACHE_LS_8
:
1901 case SQ_ALU_CONST_CACHE_LS_9
:
1902 case SQ_ALU_CONST_CACHE_LS_10
:
1903 case SQ_ALU_CONST_CACHE_LS_11
:
1904 case SQ_ALU_CONST_CACHE_LS_12
:
1905 case SQ_ALU_CONST_CACHE_LS_13
:
1906 case SQ_ALU_CONST_CACHE_LS_14
:
1907 case SQ_ALU_CONST_CACHE_LS_15
:
1908 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1910 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1914 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1916 case SX_MEMORY_EXPORT_BASE
:
1917 if (p
->rdev
->family
>= CHIP_CAYMAN
) {
1918 dev_warn(p
->dev
, "bad SET_CONFIG_REG "
1922 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1924 dev_warn(p
->dev
, "bad SET_CONFIG_REG "
1928 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1930 case CAYMAN_SX_SCATTER_EXPORT_BASE
:
1931 if (p
->rdev
->family
< CHIP_CAYMAN
) {
1932 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1936 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
1938 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1942 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1945 track
->sx_misc_kill_all_prims
= (radeon_get_ib_value(p
, idx
) & 0x1) != 0;
1948 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
1954 static bool evergreen_is_safe_reg(struct radeon_cs_parser
*p
, u32 reg
, u32 idx
)
1958 if (p
->rdev
->family
>= CHIP_CAYMAN
)
1959 last_reg
= ARRAY_SIZE(cayman_reg_safe_bm
);
1961 last_reg
= ARRAY_SIZE(evergreen_reg_safe_bm
);
1964 if (i
>= last_reg
) {
1965 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
1968 m
= 1 << ((reg
>> 2) & 31);
1969 if (p
->rdev
->family
>= CHIP_CAYMAN
) {
1970 if (!(cayman_reg_safe_bm
[i
] & m
))
1973 if (!(evergreen_reg_safe_bm
[i
] & m
))
1976 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
1980 static int evergreen_packet3_check(struct radeon_cs_parser
*p
,
1981 struct radeon_cs_packet
*pkt
)
1983 struct radeon_cs_reloc
*reloc
;
1984 struct evergreen_cs_track
*track
;
1988 unsigned start_reg
, end_reg
, reg
;
1992 track
= (struct evergreen_cs_track
*)p
->track
;
1995 idx_value
= radeon_get_ib_value(p
, idx
);
1997 switch (pkt
->opcode
) {
1998 case PACKET3_SET_PREDICATION
:
2004 if (pkt
->count
!= 1) {
2005 DRM_ERROR("bad SET PREDICATION\n");
2009 tmp
= radeon_get_ib_value(p
, idx
+ 1);
2010 pred_op
= (tmp
>> 16) & 0x7;
2012 /* for the clear predicate operation */
2017 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op
);
2021 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2023 DRM_ERROR("bad SET PREDICATION\n");
2027 offset
= reloc
->lobj
.gpu_offset
+
2028 (idx_value
& 0xfffffff0) +
2029 ((u64
)(tmp
& 0xff) << 32);
2031 ib
[idx
+ 0] = offset
;
2032 ib
[idx
+ 1] = (tmp
& 0xffffff00) | (upper_32_bits(offset
) & 0xff);
2035 case PACKET3_CONTEXT_CONTROL
:
2036 if (pkt
->count
!= 1) {
2037 DRM_ERROR("bad CONTEXT_CONTROL\n");
2041 case PACKET3_INDEX_TYPE
:
2042 case PACKET3_NUM_INSTANCES
:
2043 case PACKET3_CLEAR_STATE
:
2045 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
2049 case CAYMAN_PACKET3_DEALLOC_STATE
:
2050 if (p
->rdev
->family
< CHIP_CAYMAN
) {
2051 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
2055 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
2059 case PACKET3_INDEX_BASE
:
2063 if (pkt
->count
!= 1) {
2064 DRM_ERROR("bad INDEX_BASE\n");
2067 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2069 DRM_ERROR("bad INDEX_BASE\n");
2073 offset
= reloc
->lobj
.gpu_offset
+
2075 ((u64
)(radeon_get_ib_value(p
, idx
+1) & 0xff) << 32);
2078 ib
[idx
+1] = upper_32_bits(offset
) & 0xff;
2080 r
= evergreen_cs_track_check(p
);
2082 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
2087 case PACKET3_DRAW_INDEX
:
2090 if (pkt
->count
!= 3) {
2091 DRM_ERROR("bad DRAW_INDEX\n");
2094 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2096 DRM_ERROR("bad DRAW_INDEX\n");
2100 offset
= reloc
->lobj
.gpu_offset
+
2102 ((u64
)(radeon_get_ib_value(p
, idx
+1) & 0xff) << 32);
2105 ib
[idx
+1] = upper_32_bits(offset
) & 0xff;
2107 r
= evergreen_cs_track_check(p
);
2109 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
2114 case PACKET3_DRAW_INDEX_2
:
2118 if (pkt
->count
!= 4) {
2119 DRM_ERROR("bad DRAW_INDEX_2\n");
2122 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2124 DRM_ERROR("bad DRAW_INDEX_2\n");
2128 offset
= reloc
->lobj
.gpu_offset
+
2129 radeon_get_ib_value(p
, idx
+1) +
2130 ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff) << 32);
2133 ib
[idx
+2] = upper_32_bits(offset
) & 0xff;
2135 r
= evergreen_cs_track_check(p
);
2137 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
2142 case PACKET3_DRAW_INDEX_AUTO
:
2143 if (pkt
->count
!= 1) {
2144 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
2147 r
= evergreen_cs_track_check(p
);
2149 dev_warn(p
->dev
, "%s:%d invalid cmd stream %d\n", __func__
, __LINE__
, idx
);
2153 case PACKET3_DRAW_INDEX_MULTI_AUTO
:
2154 if (pkt
->count
!= 2) {
2155 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
2158 r
= evergreen_cs_track_check(p
);
2160 dev_warn(p
->dev
, "%s:%d invalid cmd stream %d\n", __func__
, __LINE__
, idx
);
2164 case PACKET3_DRAW_INDEX_IMMD
:
2165 if (pkt
->count
< 2) {
2166 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
2169 r
= evergreen_cs_track_check(p
);
2171 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
2175 case PACKET3_DRAW_INDEX_OFFSET
:
2176 if (pkt
->count
!= 2) {
2177 DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
2180 r
= evergreen_cs_track_check(p
);
2182 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
2186 case PACKET3_DRAW_INDEX_OFFSET_2
:
2187 if (pkt
->count
!= 3) {
2188 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
2191 r
= evergreen_cs_track_check(p
);
2193 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
2197 case PACKET3_DISPATCH_DIRECT
:
2198 if (pkt
->count
!= 3) {
2199 DRM_ERROR("bad DISPATCH_DIRECT\n");
2202 r
= evergreen_cs_track_check(p
);
2204 dev_warn(p
->dev
, "%s:%d invalid cmd stream %d\n", __func__
, __LINE__
, idx
);
2208 case PACKET3_DISPATCH_INDIRECT
:
2209 if (pkt
->count
!= 1) {
2210 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2213 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2215 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2218 ib
[idx
+0] = idx_value
+ (u32
)(reloc
->lobj
.gpu_offset
& 0xffffffff);
2219 r
= evergreen_cs_track_check(p
);
2221 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
2225 case PACKET3_WAIT_REG_MEM
:
2226 if (pkt
->count
!= 5) {
2227 DRM_ERROR("bad WAIT_REG_MEM\n");
2230 /* bit 4 is reg (0) or mem (1) */
2231 if (idx_value
& 0x10) {
2234 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2236 DRM_ERROR("bad WAIT_REG_MEM\n");
2240 offset
= reloc
->lobj
.gpu_offset
+
2241 (radeon_get_ib_value(p
, idx
+1) & 0xfffffffc) +
2242 ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff) << 32);
2244 ib
[idx
+1] = (ib
[idx
+1] & 0x3) | (offset
& 0xfffffffc);
2245 ib
[idx
+2] = upper_32_bits(offset
) & 0xff;
2248 case PACKET3_CP_DMA
:
2250 u32 command
, size
, info
;
2252 if (pkt
->count
!= 4) {
2253 DRM_ERROR("bad CP DMA\n");
2256 command
= radeon_get_ib_value(p
, idx
+4);
2257 size
= command
& 0x1fffff;
2258 info
= radeon_get_ib_value(p
, idx
+1);
2259 if ((((info
& 0x60000000) >> 29) != 0) || /* src = GDS or DATA */
2260 (((info
& 0x00300000) >> 20) != 0) || /* dst = GDS */
2261 ((((info
& 0x00300000) >> 20) == 0) &&
2262 (command
& PACKET3_CP_DMA_CMD_DAS
)) || /* dst = register */
2263 ((((info
& 0x60000000) >> 29) == 0) &&
2264 (command
& PACKET3_CP_DMA_CMD_SAS
))) { /* src = register */
2265 /* non mem to mem copies requires dw aligned count */
2267 DRM_ERROR("CP DMA command requires dw count alignment\n");
2271 if (command
& PACKET3_CP_DMA_CMD_SAS
) {
2272 /* src address space is register */
2274 if (((info
& 0x60000000) >> 29) != 1) {
2275 DRM_ERROR("CP DMA SAS not supported\n");
2279 if (command
& PACKET3_CP_DMA_CMD_SAIC
) {
2280 DRM_ERROR("CP DMA SAIC only supported for registers\n");
2283 /* src address space is memory */
2284 if (((info
& 0x60000000) >> 29) == 0) {
2285 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2287 DRM_ERROR("bad CP DMA SRC\n");
2291 tmp
= radeon_get_ib_value(p
, idx
) +
2292 ((u64
)(radeon_get_ib_value(p
, idx
+1) & 0xff) << 32);
2294 offset
= reloc
->lobj
.gpu_offset
+ tmp
;
2296 if ((tmp
+ size
) > radeon_bo_size(reloc
->robj
)) {
2297 dev_warn(p
->dev
, "CP DMA src buffer too small (%llu %lu)\n",
2298 tmp
+ size
, radeon_bo_size(reloc
->robj
));
2303 ib
[idx
+1] = (ib
[idx
+1] & 0xffffff00) | (upper_32_bits(offset
) & 0xff);
2304 } else if (((info
& 0x60000000) >> 29) != 2) {
2305 DRM_ERROR("bad CP DMA SRC_SEL\n");
2309 if (command
& PACKET3_CP_DMA_CMD_DAS
) {
2310 /* dst address space is register */
2312 if (((info
& 0x00300000) >> 20) != 1) {
2313 DRM_ERROR("CP DMA DAS not supported\n");
2317 /* dst address space is memory */
2318 if (command
& PACKET3_CP_DMA_CMD_DAIC
) {
2319 DRM_ERROR("CP DMA DAIC only supported for registers\n");
2322 if (((info
& 0x00300000) >> 20) == 0) {
2323 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2325 DRM_ERROR("bad CP DMA DST\n");
2329 tmp
= radeon_get_ib_value(p
, idx
+2) +
2330 ((u64
)(radeon_get_ib_value(p
, idx
+3) & 0xff) << 32);
2332 offset
= reloc
->lobj
.gpu_offset
+ tmp
;
2334 if ((tmp
+ size
) > radeon_bo_size(reloc
->robj
)) {
2335 dev_warn(p
->dev
, "CP DMA dst buffer too small (%llu %lu)\n",
2336 tmp
+ size
, radeon_bo_size(reloc
->robj
));
2341 ib
[idx
+3] = upper_32_bits(offset
) & 0xff;
2343 DRM_ERROR("bad CP DMA DST_SEL\n");
2349 case PACKET3_SURFACE_SYNC
:
2350 if (pkt
->count
!= 3) {
2351 DRM_ERROR("bad SURFACE_SYNC\n");
2354 /* 0xffffffff/0x0 is flush all cache flag */
2355 if (radeon_get_ib_value(p
, idx
+ 1) != 0xffffffff ||
2356 radeon_get_ib_value(p
, idx
+ 2) != 0) {
2357 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2359 DRM_ERROR("bad SURFACE_SYNC\n");
2362 ib
[idx
+2] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
2365 case PACKET3_EVENT_WRITE
:
2366 if (pkt
->count
!= 2 && pkt
->count
!= 0) {
2367 DRM_ERROR("bad EVENT_WRITE\n");
2373 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2375 DRM_ERROR("bad EVENT_WRITE\n");
2378 offset
= reloc
->lobj
.gpu_offset
+
2379 (radeon_get_ib_value(p
, idx
+1) & 0xfffffff8) +
2380 ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff) << 32);
2382 ib
[idx
+1] = offset
& 0xfffffff8;
2383 ib
[idx
+2] = upper_32_bits(offset
) & 0xff;
2386 case PACKET3_EVENT_WRITE_EOP
:
2390 if (pkt
->count
!= 4) {
2391 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2394 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2396 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2400 offset
= reloc
->lobj
.gpu_offset
+
2401 (radeon_get_ib_value(p
, idx
+1) & 0xfffffffc) +
2402 ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff) << 32);
2404 ib
[idx
+1] = offset
& 0xfffffffc;
2405 ib
[idx
+2] = (ib
[idx
+2] & 0xffffff00) | (upper_32_bits(offset
) & 0xff);
2408 case PACKET3_EVENT_WRITE_EOS
:
2412 if (pkt
->count
!= 3) {
2413 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2416 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2418 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2422 offset
= reloc
->lobj
.gpu_offset
+
2423 (radeon_get_ib_value(p
, idx
+1) & 0xfffffffc) +
2424 ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff) << 32);
2426 ib
[idx
+1] = offset
& 0xfffffffc;
2427 ib
[idx
+2] = (ib
[idx
+2] & 0xffffff00) | (upper_32_bits(offset
) & 0xff);
2430 case PACKET3_SET_CONFIG_REG
:
2431 start_reg
= (idx_value
<< 2) + PACKET3_SET_CONFIG_REG_START
;
2432 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2433 if ((start_reg
< PACKET3_SET_CONFIG_REG_START
) ||
2434 (start_reg
>= PACKET3_SET_CONFIG_REG_END
) ||
2435 (end_reg
>= PACKET3_SET_CONFIG_REG_END
)) {
2436 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2439 for (i
= 0; i
< pkt
->count
; i
++) {
2440 reg
= start_reg
+ (4 * i
);
2441 r
= evergreen_cs_check_reg(p
, reg
, idx
+1+i
);
2446 case PACKET3_SET_CONTEXT_REG
:
2447 start_reg
= (idx_value
<< 2) + PACKET3_SET_CONTEXT_REG_START
;
2448 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2449 if ((start_reg
< PACKET3_SET_CONTEXT_REG_START
) ||
2450 (start_reg
>= PACKET3_SET_CONTEXT_REG_END
) ||
2451 (end_reg
>= PACKET3_SET_CONTEXT_REG_END
)) {
2452 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2455 for (i
= 0; i
< pkt
->count
; i
++) {
2456 reg
= start_reg
+ (4 * i
);
2457 r
= evergreen_cs_check_reg(p
, reg
, idx
+1+i
);
2462 case PACKET3_SET_RESOURCE
:
2463 if (pkt
->count
% 8) {
2464 DRM_ERROR("bad SET_RESOURCE\n");
2467 start_reg
= (idx_value
<< 2) + PACKET3_SET_RESOURCE_START
;
2468 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2469 if ((start_reg
< PACKET3_SET_RESOURCE_START
) ||
2470 (start_reg
>= PACKET3_SET_RESOURCE_END
) ||
2471 (end_reg
>= PACKET3_SET_RESOURCE_END
)) {
2472 DRM_ERROR("bad SET_RESOURCE\n");
2475 for (i
= 0; i
< (pkt
->count
/ 8); i
++) {
2476 struct radeon_bo
*texture
, *mipmap
;
2477 u32 toffset
, moffset
;
2478 u32 size
, offset
, mip_address
, tex_dim
;
2480 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p
, idx
+1+(i
*8)+7))) {
2481 case SQ_TEX_VTX_VALID_TEXTURE
:
2483 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2485 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2488 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
2489 ib
[idx
+1+(i
*8)+1] |=
2490 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc
->lobj
.tiling_flags
));
2491 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
) {
2492 unsigned bankw
, bankh
, mtaspect
, tile_split
;
2494 evergreen_tiling_fields(reloc
->lobj
.tiling_flags
,
2495 &bankw
, &bankh
, &mtaspect
,
2497 ib
[idx
+1+(i
*8)+6] |= TEX_TILE_SPLIT(tile_split
);
2498 ib
[idx
+1+(i
*8)+7] |=
2499 TEX_BANK_WIDTH(bankw
) |
2500 TEX_BANK_HEIGHT(bankh
) |
2501 MACRO_TILE_ASPECT(mtaspect
) |
2502 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track
->nbanks
));
2505 texture
= reloc
->robj
;
2506 toffset
= (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
2509 tex_dim
= ib
[idx
+1+(i
*8)+0] & 0x7;
2510 mip_address
= ib
[idx
+1+(i
*8)+3];
2512 if ((tex_dim
== SQ_TEX_DIM_2D_MSAA
|| tex_dim
== SQ_TEX_DIM_2D_ARRAY_MSAA
) &&
2514 !evergreen_cs_packet_next_is_pkt3_nop(p
)) {
2515 /* MIP_ADDRESS should point to FMASK for an MSAA texture.
2516 * It should be 0 if FMASK is disabled. */
2520 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2522 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2525 moffset
= (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
2526 mipmap
= reloc
->robj
;
2529 r
= evergreen_cs_track_validate_texture(p
, texture
, mipmap
, idx
+1+(i
*8));
2532 ib
[idx
+1+(i
*8)+2] += toffset
;
2533 ib
[idx
+1+(i
*8)+3] += moffset
;
2535 case SQ_TEX_VTX_VALID_BUFFER
:
2539 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2541 DRM_ERROR("bad SET_RESOURCE (vtx)\n");
2544 offset
= radeon_get_ib_value(p
, idx
+1+(i
*8)+0);
2545 size
= radeon_get_ib_value(p
, idx
+1+(i
*8)+1);
2546 if (p
->rdev
&& (size
+ offset
) > radeon_bo_size(reloc
->robj
)) {
2547 /* force size to size of the buffer */
2548 dev_warn(p
->dev
, "vbo resource seems too big for the bo\n");
2549 ib
[idx
+1+(i
*8)+1] = radeon_bo_size(reloc
->robj
) - offset
;
2552 offset64
= reloc
->lobj
.gpu_offset
+ offset
;
2553 ib
[idx
+1+(i
*8)+0] = offset64
;
2554 ib
[idx
+1+(i
*8)+2] = (ib
[idx
+1+(i
*8)+2] & 0xffffff00) |
2555 (upper_32_bits(offset64
) & 0xff);
2558 case SQ_TEX_VTX_INVALID_TEXTURE
:
2559 case SQ_TEX_VTX_INVALID_BUFFER
:
2561 DRM_ERROR("bad SET_RESOURCE\n");
2566 case PACKET3_SET_ALU_CONST
:
2567 /* XXX fix me ALU const buffers only */
2569 case PACKET3_SET_BOOL_CONST
:
2570 start_reg
= (idx_value
<< 2) + PACKET3_SET_BOOL_CONST_START
;
2571 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2572 if ((start_reg
< PACKET3_SET_BOOL_CONST_START
) ||
2573 (start_reg
>= PACKET3_SET_BOOL_CONST_END
) ||
2574 (end_reg
>= PACKET3_SET_BOOL_CONST_END
)) {
2575 DRM_ERROR("bad SET_BOOL_CONST\n");
2579 case PACKET3_SET_LOOP_CONST
:
2580 start_reg
= (idx_value
<< 2) + PACKET3_SET_LOOP_CONST_START
;
2581 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2582 if ((start_reg
< PACKET3_SET_LOOP_CONST_START
) ||
2583 (start_reg
>= PACKET3_SET_LOOP_CONST_END
) ||
2584 (end_reg
>= PACKET3_SET_LOOP_CONST_END
)) {
2585 DRM_ERROR("bad SET_LOOP_CONST\n");
2589 case PACKET3_SET_CTL_CONST
:
2590 start_reg
= (idx_value
<< 2) + PACKET3_SET_CTL_CONST_START
;
2591 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2592 if ((start_reg
< PACKET3_SET_CTL_CONST_START
) ||
2593 (start_reg
>= PACKET3_SET_CTL_CONST_END
) ||
2594 (end_reg
>= PACKET3_SET_CTL_CONST_END
)) {
2595 DRM_ERROR("bad SET_CTL_CONST\n");
2599 case PACKET3_SET_SAMPLER
:
2600 if (pkt
->count
% 3) {
2601 DRM_ERROR("bad SET_SAMPLER\n");
2604 start_reg
= (idx_value
<< 2) + PACKET3_SET_SAMPLER_START
;
2605 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2606 if ((start_reg
< PACKET3_SET_SAMPLER_START
) ||
2607 (start_reg
>= PACKET3_SET_SAMPLER_END
) ||
2608 (end_reg
>= PACKET3_SET_SAMPLER_END
)) {
2609 DRM_ERROR("bad SET_SAMPLER\n");
2613 case PACKET3_STRMOUT_BUFFER_UPDATE
:
2614 if (pkt
->count
!= 4) {
2615 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2618 /* Updating memory at DST_ADDRESS. */
2619 if (idx_value
& 0x1) {
2621 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2623 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2626 offset
= radeon_get_ib_value(p
, idx
+1);
2627 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff)) << 32;
2628 if ((offset
+ 4) > radeon_bo_size(reloc
->robj
)) {
2629 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2630 offset
+ 4, radeon_bo_size(reloc
->robj
));
2633 offset
+= reloc
->lobj
.gpu_offset
;
2635 ib
[idx
+2] = upper_32_bits(offset
) & 0xff;
2637 /* Reading data from SRC_ADDRESS. */
2638 if (((idx_value
>> 1) & 0x3) == 2) {
2640 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2642 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2645 offset
= radeon_get_ib_value(p
, idx
+3);
2646 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+4) & 0xff)) << 32;
2647 if ((offset
+ 4) > radeon_bo_size(reloc
->robj
)) {
2648 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2649 offset
+ 4, radeon_bo_size(reloc
->robj
));
2652 offset
+= reloc
->lobj
.gpu_offset
;
2654 ib
[idx
+4] = upper_32_bits(offset
) & 0xff;
2657 case PACKET3_MEM_WRITE
:
2661 if (pkt
->count
!= 3) {
2662 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2665 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2667 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2670 offset
= radeon_get_ib_value(p
, idx
+0);
2671 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+1) & 0xff)) << 32UL;
2673 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2676 if ((offset
+ 8) > radeon_bo_size(reloc
->robj
)) {
2677 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
2678 offset
+ 8, radeon_bo_size(reloc
->robj
));
2681 offset
+= reloc
->lobj
.gpu_offset
;
2683 ib
[idx
+1] = upper_32_bits(offset
) & 0xff;
2686 case PACKET3_COPY_DW
:
2687 if (pkt
->count
!= 4) {
2688 DRM_ERROR("bad COPY_DW (invalid count)\n");
2691 if (idx_value
& 0x1) {
2693 /* SRC is memory. */
2694 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2696 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2699 offset
= radeon_get_ib_value(p
, idx
+1);
2700 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff)) << 32;
2701 if ((offset
+ 4) > radeon_bo_size(reloc
->robj
)) {
2702 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2703 offset
+ 4, radeon_bo_size(reloc
->robj
));
2706 offset
+= reloc
->lobj
.gpu_offset
;
2708 ib
[idx
+2] = upper_32_bits(offset
) & 0xff;
2711 reg
= radeon_get_ib_value(p
, idx
+1) << 2;
2712 if (!evergreen_is_safe_reg(p
, reg
, idx
+1))
2715 if (idx_value
& 0x2) {
2717 /* DST is memory. */
2718 r
= evergreen_cs_packet_next_reloc(p
, &reloc
);
2720 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2723 offset
= radeon_get_ib_value(p
, idx
+3);
2724 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+4) & 0xff)) << 32;
2725 if ((offset
+ 4) > radeon_bo_size(reloc
->robj
)) {
2726 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2727 offset
+ 4, radeon_bo_size(reloc
->robj
));
2730 offset
+= reloc
->lobj
.gpu_offset
;
2732 ib
[idx
+4] = upper_32_bits(offset
) & 0xff;
2735 reg
= radeon_get_ib_value(p
, idx
+3) << 2;
2736 if (!evergreen_is_safe_reg(p
, reg
, idx
+3))
2743 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
2749 int evergreen_cs_parse(struct radeon_cs_parser
*p
)
2751 struct radeon_cs_packet pkt
;
2752 struct evergreen_cs_track
*track
;
2756 if (p
->track
== NULL
) {
2757 /* initialize tracker, we are in kms */
2758 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
2761 evergreen_cs_track_init(track
);
2762 if (p
->rdev
->family
>= CHIP_CAYMAN
)
2763 tmp
= p
->rdev
->config
.cayman
.tile_config
;
2765 tmp
= p
->rdev
->config
.evergreen
.tile_config
;
2767 switch (tmp
& 0xf) {
2783 switch ((tmp
& 0xf0) >> 4) {
2796 switch ((tmp
& 0xf00) >> 8) {
2798 track
->group_size
= 256;
2802 track
->group_size
= 512;
2806 switch ((tmp
& 0xf000) >> 12) {
2808 track
->row_size
= 1;
2812 track
->row_size
= 2;
2815 track
->row_size
= 4;
2822 r
= evergreen_cs_packet_parse(p
, &pkt
, p
->idx
);
2828 p
->idx
+= pkt
.count
+ 2;
2831 r
= evergreen_cs_parse_packet0(p
, &pkt
);
2836 r
= evergreen_packet3_check(p
, &pkt
);
2839 DRM_ERROR("Unknown packet type %d !\n", pkt
.type
);
2849 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
2851 for (r
= 0; r
< p
->ib
.length_dw
; r
++) {
2852 printk(KERN_INFO
"%05d 0x%08X\n", r
, p
->ib
.ptr
[r
]);
2865 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2866 #define GET_DMA_COUNT(h) ((h) & 0x000fffff)
2867 #define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2868 #define GET_DMA_NEW(h) (((h) & 0x04000000) >> 26)
2869 #define GET_DMA_MISC(h) (((h) & 0x0700000) >> 20)
2872 * evergreen_dma_cs_parse() - parse the DMA IB
2873 * @p: parser structure holding parsing context.
2875 * Parses the DMA IB from the CS ioctl and updates
2876 * the GPU addresses based on the reloc information and
2877 * checks for errors. (Evergreen-Cayman)
2878 * Returns 0 for success and an error on failure.
2880 int evergreen_dma_cs_parse(struct radeon_cs_parser
*p
)
2882 struct radeon_cs_chunk
*ib_chunk
= &p
->chunks
[p
->chunk_ib_idx
];
2883 struct radeon_cs_reloc
*src_reloc
, *dst_reloc
, *dst2_reloc
;
2884 u32 header
, cmd
, count
, tiled
, new_cmd
, misc
;
2885 volatile u32
*ib
= p
->ib
.ptr
;
2887 u64 src_offset
, dst_offset
, dst2_offset
;
2891 if (p
->idx
>= ib_chunk
->length_dw
) {
2892 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2893 p
->idx
, ib_chunk
->length_dw
);
2897 header
= radeon_get_ib_value(p
, idx
);
2898 cmd
= GET_DMA_CMD(header
);
2899 count
= GET_DMA_COUNT(header
);
2900 tiled
= GET_DMA_T(header
);
2901 new_cmd
= GET_DMA_NEW(header
);
2902 misc
= GET_DMA_MISC(header
);
2905 case DMA_PACKET_WRITE
:
2906 r
= r600_dma_cs_next_reloc(p
, &dst_reloc
);
2908 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2912 dst_offset
= ib
[idx
+1];
2915 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
2916 p
->idx
+= count
+ 7;
2918 dst_offset
= ib
[idx
+1];
2919 dst_offset
|= ((u64
)(ib
[idx
+2] & 0xff)) << 32;
2921 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2922 ib
[idx
+2] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
2923 p
->idx
+= count
+ 3;
2925 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
2926 dev_warn(p
->dev
, "DMA write buffer too small (%llu %lu)\n",
2927 dst_offset
, radeon_bo_size(dst_reloc
->robj
));
2931 case DMA_PACKET_COPY
:
2932 r
= r600_dma_cs_next_reloc(p
, &src_reloc
);
2934 DRM_ERROR("bad DMA_PACKET_COPY\n");
2937 r
= r600_dma_cs_next_reloc(p
, &dst_reloc
);
2939 DRM_ERROR("bad DMA_PACKET_COPY\n");
2943 idx_value
= radeon_get_ib_value(p
, idx
+ 2);
2947 /* L2T, frame to fields */
2948 if (idx_value
& (1 << 31)) {
2949 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
2952 r
= r600_dma_cs_next_reloc(p
, &dst2_reloc
);
2954 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
2957 dst_offset
= ib
[idx
+1];
2959 dst2_offset
= ib
[idx
+2];
2961 src_offset
= ib
[idx
+8];
2962 src_offset
|= ((u64
)(ib
[idx
+9] & 0xff)) << 32;
2963 if ((src_offset
+ (count
* 4)) > radeon_bo_size(src_reloc
->robj
)) {
2964 dev_warn(p
->dev
, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n",
2965 src_offset
+ (count
* 4), radeon_bo_size(src_reloc
->robj
));
2968 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
2969 dev_warn(p
->dev
, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
2970 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
2973 if ((dst2_offset
+ (count
* 4)) > radeon_bo_size(dst2_reloc
->robj
)) {
2974 dev_warn(p
->dev
, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
2975 dst2_offset
+ (count
* 4), radeon_bo_size(dst2_reloc
->robj
));
2978 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
2979 ib
[idx
+2] += (u32
)(dst2_reloc
->lobj
.gpu_offset
>> 8);
2980 ib
[idx
+8] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2981 ib
[idx
+9] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
2985 /* L2T, T2L partial */
2986 if (p
->family
< CHIP_CAYMAN
) {
2987 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
2991 if (idx_value
& (1 << 31)) {
2992 /* tiled src, linear dst */
2993 ib
[idx
+1] += (u32
)(src_reloc
->lobj
.gpu_offset
>> 8);
2995 ib
[idx
+7] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2996 ib
[idx
+8] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
2998 /* linear src, tiled dst */
2999 ib
[idx
+7] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3000 ib
[idx
+8] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
3002 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
3007 /* L2T, broadcast */
3008 if (idx_value
& (1 << 31)) {
3009 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3012 r
= r600_dma_cs_next_reloc(p
, &dst2_reloc
);
3014 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3017 dst_offset
= ib
[idx
+1];
3019 dst2_offset
= ib
[idx
+2];
3021 src_offset
= ib
[idx
+8];
3022 src_offset
|= ((u64
)(ib
[idx
+9] & 0xff)) << 32;
3023 if ((src_offset
+ (count
* 4)) > radeon_bo_size(src_reloc
->robj
)) {
3024 dev_warn(p
->dev
, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3025 src_offset
+ (count
* 4), radeon_bo_size(src_reloc
->robj
));
3028 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
3029 dev_warn(p
->dev
, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3030 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
3033 if ((dst2_offset
+ (count
* 4)) > radeon_bo_size(dst2_reloc
->robj
)) {
3034 dev_warn(p
->dev
, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
3035 dst2_offset
+ (count
* 4), radeon_bo_size(dst2_reloc
->robj
));
3038 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
3039 ib
[idx
+2] += (u32
)(dst2_reloc
->lobj
.gpu_offset
>> 8);
3040 ib
[idx
+8] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3041 ib
[idx
+9] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
3047 if (idx_value
& (1 << 31)) {
3048 /* tiled src, linear dst */
3049 src_offset
= ib
[idx
+1];
3051 ib
[idx
+1] += (u32
)(src_reloc
->lobj
.gpu_offset
>> 8);
3053 dst_offset
= ib
[idx
+7];
3054 dst_offset
|= ((u64
)(ib
[idx
+8] & 0xff)) << 32;
3055 ib
[idx
+7] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3056 ib
[idx
+8] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
3058 /* linear src, tiled dst */
3059 src_offset
= ib
[idx
+7];
3060 src_offset
|= ((u64
)(ib
[idx
+8] & 0xff)) << 32;
3061 ib
[idx
+7] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3062 ib
[idx
+8] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
3064 dst_offset
= ib
[idx
+1];
3066 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
3068 if ((src_offset
+ (count
* 4)) > radeon_bo_size(src_reloc
->robj
)) {
3069 dev_warn(p
->dev
, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
3070 src_offset
+ (count
* 4), radeon_bo_size(src_reloc
->robj
));
3073 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
3074 dev_warn(p
->dev
, "DMA L2T, T2L dst buffer too small (%llu %lu)\n",
3075 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
3082 if (p
->family
< CHIP_CAYMAN
) {
3083 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
3086 ib
[idx
+1] += (u32
)(src_reloc
->lobj
.gpu_offset
>> 8);
3087 ib
[idx
+4] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
3091 /* L2T, broadcast */
3092 if (idx_value
& (1 << 31)) {
3093 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3096 r
= r600_dma_cs_next_reloc(p
, &dst2_reloc
);
3098 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3101 dst_offset
= ib
[idx
+1];
3103 dst2_offset
= ib
[idx
+2];
3105 src_offset
= ib
[idx
+8];
3106 src_offset
|= ((u64
)(ib
[idx
+9] & 0xff)) << 32;
3107 if ((src_offset
+ (count
* 4)) > radeon_bo_size(src_reloc
->robj
)) {
3108 dev_warn(p
->dev
, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3109 src_offset
+ (count
* 4), radeon_bo_size(src_reloc
->robj
));
3112 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
3113 dev_warn(p
->dev
, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3114 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
3117 if ((dst2_offset
+ (count
* 4)) > radeon_bo_size(dst2_reloc
->robj
)) {
3118 dev_warn(p
->dev
, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
3119 dst2_offset
+ (count
* 4), radeon_bo_size(dst2_reloc
->robj
));
3122 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
3123 ib
[idx
+2] += (u32
)(dst2_reloc
->lobj
.gpu_offset
>> 8);
3124 ib
[idx
+8] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3125 ib
[idx
+9] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
3129 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc
);
3136 if (idx_value
& (1 << 31)) {
3137 /* tiled src, linear dst */
3138 src_offset
= ib
[idx
+1];
3140 ib
[idx
+1] += (u32
)(src_reloc
->lobj
.gpu_offset
>> 8);
3142 dst_offset
= ib
[idx
+7];
3143 dst_offset
|= ((u64
)(ib
[idx
+8] & 0xff)) << 32;
3144 ib
[idx
+7] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3145 ib
[idx
+8] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
3147 /* linear src, tiled dst */
3148 src_offset
= ib
[idx
+7];
3149 src_offset
|= ((u64
)(ib
[idx
+8] & 0xff)) << 32;
3150 ib
[idx
+7] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3151 ib
[idx
+8] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
3153 dst_offset
= ib
[idx
+1];
3155 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
3157 if ((src_offset
+ (count
* 4)) > radeon_bo_size(src_reloc
->robj
)) {
3158 dev_warn(p
->dev
, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3159 src_offset
+ (count
* 4), radeon_bo_size(src_reloc
->robj
));
3162 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
3163 dev_warn(p
->dev
, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3164 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
3170 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc
);
3179 src_offset
= ib
[idx
+2];
3180 src_offset
|= ((u64
)(ib
[idx
+4] & 0xff)) << 32;
3181 dst_offset
= ib
[idx
+1];
3182 dst_offset
|= ((u64
)(ib
[idx
+3] & 0xff)) << 32;
3183 if ((src_offset
+ count
) > radeon_bo_size(src_reloc
->robj
)) {
3184 dev_warn(p
->dev
, "DMA L2L, byte src buffer too small (%llu %lu)\n",
3185 src_offset
+ count
, radeon_bo_size(src_reloc
->robj
));
3188 if ((dst_offset
+ count
) > radeon_bo_size(dst_reloc
->robj
)) {
3189 dev_warn(p
->dev
, "DMA L2L, byte dst buffer too small (%llu %lu)\n",
3190 dst_offset
+ count
, radeon_bo_size(dst_reloc
->robj
));
3193 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xffffffff);
3194 ib
[idx
+2] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xffffffff);
3195 ib
[idx
+3] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
3196 ib
[idx
+4] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
3201 if (p
->family
< CHIP_CAYMAN
) {
3202 DRM_ERROR("L2L Partial is cayman only !\n");
3205 ib
[idx
+1] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xffffffff);
3206 ib
[idx
+2] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
3207 ib
[idx
+4] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xffffffff);
3208 ib
[idx
+5] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
3213 /* L2L, dw, broadcast */
3214 r
= r600_dma_cs_next_reloc(p
, &dst2_reloc
);
3216 DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n");
3219 dst_offset
= ib
[idx
+1];
3220 dst_offset
|= ((u64
)(ib
[idx
+4] & 0xff)) << 32;
3221 dst2_offset
= ib
[idx
+2];
3222 dst2_offset
|= ((u64
)(ib
[idx
+5] & 0xff)) << 32;
3223 src_offset
= ib
[idx
+3];
3224 src_offset
|= ((u64
)(ib
[idx
+6] & 0xff)) << 32;
3225 if ((src_offset
+ (count
* 4)) > radeon_bo_size(src_reloc
->robj
)) {
3226 dev_warn(p
->dev
, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n",
3227 src_offset
+ (count
* 4), radeon_bo_size(src_reloc
->robj
));
3230 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
3231 dev_warn(p
->dev
, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n",
3232 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
3235 if ((dst2_offset
+ (count
* 4)) > radeon_bo_size(dst2_reloc
->robj
)) {
3236 dev_warn(p
->dev
, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n",
3237 dst2_offset
+ (count
* 4), radeon_bo_size(dst2_reloc
->robj
));
3240 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3241 ib
[idx
+2] += (u32
)(dst2_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3242 ib
[idx
+3] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3243 ib
[idx
+4] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
3244 ib
[idx
+5] += upper_32_bits(dst2_reloc
->lobj
.gpu_offset
) & 0xff;
3245 ib
[idx
+6] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
3249 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc
);
3254 src_offset
= ib
[idx
+2];
3255 src_offset
|= ((u64
)(ib
[idx
+4] & 0xff)) << 32;
3256 dst_offset
= ib
[idx
+1];
3257 dst_offset
|= ((u64
)(ib
[idx
+3] & 0xff)) << 32;
3258 if ((src_offset
+ (count
* 4)) > radeon_bo_size(src_reloc
->robj
)) {
3259 dev_warn(p
->dev
, "DMA L2L, dw src buffer too small (%llu %lu)\n",
3260 src_offset
+ (count
* 4), radeon_bo_size(src_reloc
->robj
));
3263 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
3264 dev_warn(p
->dev
, "DMA L2L, dw dst buffer too small (%llu %lu)\n",
3265 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
3268 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3269 ib
[idx
+2] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3270 ib
[idx
+3] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
3271 ib
[idx
+4] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
3276 case DMA_PACKET_CONSTANT_FILL
:
3277 r
= r600_dma_cs_next_reloc(p
, &dst_reloc
);
3279 DRM_ERROR("bad DMA_PACKET_CONSTANT_FILL\n");
3282 dst_offset
= ib
[idx
+1];
3283 dst_offset
|= ((u64
)(ib
[idx
+3] & 0x00ff0000)) << 16;
3284 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
3285 dev_warn(p
->dev
, "DMA constant fill buffer too small (%llu %lu)\n",
3286 dst_offset
, radeon_bo_size(dst_reloc
->robj
));
3289 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
3290 ib
[idx
+3] += (upper_32_bits(dst_reloc
->lobj
.gpu_offset
) << 16) & 0x00ff0000;
3293 case DMA_PACKET_NOP
:
3297 DRM_ERROR("Unknown packet type %d at %d !\n", cmd
, idx
);
3300 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
3302 for (r
= 0; r
< p
->ib
->length_dw
; r
++) {
3303 printk(KERN_INFO
"%05d 0x%08X\n", r
, p
->ib
.ptr
[r
]);
3311 static bool evergreen_vm_reg_valid(u32 reg
)
3313 /* context regs are fine */
3317 /* check config regs */
3320 case GRBM_GFX_INDEX
:
3321 case CP_STRMOUT_CNTL
:
3324 case VGT_VTX_VECT_EJECT_REG
:
3325 case VGT_CACHE_INVALIDATION
:
3326 case VGT_GS_VERTEX_REUSE
:
3327 case VGT_PRIMITIVE_TYPE
:
3328 case VGT_INDEX_TYPE
:
3329 case VGT_NUM_INDICES
:
3330 case VGT_NUM_INSTANCES
:
3331 case VGT_COMPUTE_DIM_X
:
3332 case VGT_COMPUTE_DIM_Y
:
3333 case VGT_COMPUTE_DIM_Z
:
3334 case VGT_COMPUTE_START_X
:
3335 case VGT_COMPUTE_START_Y
:
3336 case VGT_COMPUTE_START_Z
:
3337 case VGT_COMPUTE_INDEX
:
3338 case VGT_COMPUTE_THREAD_GROUP_SIZE
:
3339 case VGT_HS_OFFCHIP_PARAM
:
3341 case PA_SU_LINE_STIPPLE_VALUE
:
3342 case PA_SC_LINE_STIPPLE_STATE
:
3344 case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
:
3345 case SQ_DYN_GPR_SIMD_LOCK_EN
:
3347 case SQ_GPR_RESOURCE_MGMT_1
:
3348 case SQ_GLOBAL_GPR_RESOURCE_MGMT_1
:
3349 case SQ_GLOBAL_GPR_RESOURCE_MGMT_2
:
3350 case SQ_CONST_MEM_BASE
:
3351 case SQ_STATIC_THREAD_MGMT_1
:
3352 case SQ_STATIC_THREAD_MGMT_2
:
3353 case SQ_STATIC_THREAD_MGMT_3
:
3354 case SPI_CONFIG_CNTL
:
3355 case SPI_CONFIG_CNTL_1
:
3362 case TD_PS_BORDER_COLOR_INDEX
:
3363 case TD_PS_BORDER_COLOR_RED
:
3364 case TD_PS_BORDER_COLOR_GREEN
:
3365 case TD_PS_BORDER_COLOR_BLUE
:
3366 case TD_PS_BORDER_COLOR_ALPHA
:
3367 case TD_VS_BORDER_COLOR_INDEX
:
3368 case TD_VS_BORDER_COLOR_RED
:
3369 case TD_VS_BORDER_COLOR_GREEN
:
3370 case TD_VS_BORDER_COLOR_BLUE
:
3371 case TD_VS_BORDER_COLOR_ALPHA
:
3372 case TD_GS_BORDER_COLOR_INDEX
:
3373 case TD_GS_BORDER_COLOR_RED
:
3374 case TD_GS_BORDER_COLOR_GREEN
:
3375 case TD_GS_BORDER_COLOR_BLUE
:
3376 case TD_GS_BORDER_COLOR_ALPHA
:
3377 case TD_HS_BORDER_COLOR_INDEX
:
3378 case TD_HS_BORDER_COLOR_RED
:
3379 case TD_HS_BORDER_COLOR_GREEN
:
3380 case TD_HS_BORDER_COLOR_BLUE
:
3381 case TD_HS_BORDER_COLOR_ALPHA
:
3382 case TD_LS_BORDER_COLOR_INDEX
:
3383 case TD_LS_BORDER_COLOR_RED
:
3384 case TD_LS_BORDER_COLOR_GREEN
:
3385 case TD_LS_BORDER_COLOR_BLUE
:
3386 case TD_LS_BORDER_COLOR_ALPHA
:
3387 case TD_CS_BORDER_COLOR_INDEX
:
3388 case TD_CS_BORDER_COLOR_RED
:
3389 case TD_CS_BORDER_COLOR_GREEN
:
3390 case TD_CS_BORDER_COLOR_BLUE
:
3391 case TD_CS_BORDER_COLOR_ALPHA
:
3392 case SQ_ESGS_RING_SIZE
:
3393 case SQ_GSVS_RING_SIZE
:
3394 case SQ_ESTMP_RING_SIZE
:
3395 case SQ_GSTMP_RING_SIZE
:
3396 case SQ_HSTMP_RING_SIZE
:
3397 case SQ_LSTMP_RING_SIZE
:
3398 case SQ_PSTMP_RING_SIZE
:
3399 case SQ_VSTMP_RING_SIZE
:
3400 case SQ_ESGS_RING_ITEMSIZE
:
3401 case SQ_ESTMP_RING_ITEMSIZE
:
3402 case SQ_GSTMP_RING_ITEMSIZE
:
3403 case SQ_GSVS_RING_ITEMSIZE
:
3404 case SQ_GS_VERT_ITEMSIZE
:
3405 case SQ_GS_VERT_ITEMSIZE_1
:
3406 case SQ_GS_VERT_ITEMSIZE_2
:
3407 case SQ_GS_VERT_ITEMSIZE_3
:
3408 case SQ_GSVS_RING_OFFSET_1
:
3409 case SQ_GSVS_RING_OFFSET_2
:
3410 case SQ_GSVS_RING_OFFSET_3
:
3411 case SQ_HSTMP_RING_ITEMSIZE
:
3412 case SQ_LSTMP_RING_ITEMSIZE
:
3413 case SQ_PSTMP_RING_ITEMSIZE
:
3414 case SQ_VSTMP_RING_ITEMSIZE
:
3415 case VGT_TF_RING_SIZE
:
3416 case SQ_ESGS_RING_BASE
:
3417 case SQ_GSVS_RING_BASE
:
3418 case SQ_ESTMP_RING_BASE
:
3419 case SQ_GSTMP_RING_BASE
:
3420 case SQ_HSTMP_RING_BASE
:
3421 case SQ_LSTMP_RING_BASE
:
3422 case SQ_PSTMP_RING_BASE
:
3423 case SQ_VSTMP_RING_BASE
:
3424 case CAYMAN_VGT_OFFCHIP_LDS_BASE
:
3425 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS
:
3428 DRM_ERROR("Invalid register 0x%x in CS\n", reg
);
3433 static int evergreen_vm_packet3_check(struct radeon_device
*rdev
,
3434 u32
*ib
, struct radeon_cs_packet
*pkt
)
3436 u32 idx
= pkt
->idx
+ 1;
3437 u32 idx_value
= ib
[idx
];
3438 u32 start_reg
, end_reg
, reg
, i
;
3441 switch (pkt
->opcode
) {
3443 case PACKET3_SET_BASE
:
3444 case PACKET3_CLEAR_STATE
:
3445 case PACKET3_INDEX_BUFFER_SIZE
:
3446 case PACKET3_DISPATCH_DIRECT
:
3447 case PACKET3_DISPATCH_INDIRECT
:
3448 case PACKET3_MODE_CONTROL
:
3449 case PACKET3_SET_PREDICATION
:
3450 case PACKET3_COND_EXEC
:
3451 case PACKET3_PRED_EXEC
:
3452 case PACKET3_DRAW_INDIRECT
:
3453 case PACKET3_DRAW_INDEX_INDIRECT
:
3454 case PACKET3_INDEX_BASE
:
3455 case PACKET3_DRAW_INDEX_2
:
3456 case PACKET3_CONTEXT_CONTROL
:
3457 case PACKET3_DRAW_INDEX_OFFSET
:
3458 case PACKET3_INDEX_TYPE
:
3459 case PACKET3_DRAW_INDEX
:
3460 case PACKET3_DRAW_INDEX_AUTO
:
3461 case PACKET3_DRAW_INDEX_IMMD
:
3462 case PACKET3_NUM_INSTANCES
:
3463 case PACKET3_DRAW_INDEX_MULTI_AUTO
:
3464 case PACKET3_STRMOUT_BUFFER_UPDATE
:
3465 case PACKET3_DRAW_INDEX_OFFSET_2
:
3466 case PACKET3_DRAW_INDEX_MULTI_ELEMENT
:
3467 case PACKET3_MPEG_INDEX
:
3468 case PACKET3_WAIT_REG_MEM
:
3469 case PACKET3_MEM_WRITE
:
3470 case PACKET3_SURFACE_SYNC
:
3471 case PACKET3_EVENT_WRITE
:
3472 case PACKET3_EVENT_WRITE_EOP
:
3473 case PACKET3_EVENT_WRITE_EOS
:
3474 case PACKET3_SET_CONTEXT_REG
:
3475 case PACKET3_SET_BOOL_CONST
:
3476 case PACKET3_SET_LOOP_CONST
:
3477 case PACKET3_SET_RESOURCE
:
3478 case PACKET3_SET_SAMPLER
:
3479 case PACKET3_SET_CTL_CONST
:
3480 case PACKET3_SET_RESOURCE_OFFSET
:
3481 case PACKET3_SET_CONTEXT_REG_INDIRECT
:
3482 case PACKET3_SET_RESOURCE_INDIRECT
:
3483 case CAYMAN_PACKET3_DEALLOC_STATE
:
3485 case PACKET3_COND_WRITE
:
3486 if (idx_value
& 0x100) {
3487 reg
= ib
[idx
+ 5] * 4;
3488 if (!evergreen_vm_reg_valid(reg
))
3492 case PACKET3_COPY_DW
:
3493 if (idx_value
& 0x2) {
3494 reg
= ib
[idx
+ 3] * 4;
3495 if (!evergreen_vm_reg_valid(reg
))
3499 case PACKET3_SET_CONFIG_REG
:
3500 start_reg
= (idx_value
<< 2) + PACKET3_SET_CONFIG_REG_START
;
3501 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
3502 if ((start_reg
< PACKET3_SET_CONFIG_REG_START
) ||
3503 (start_reg
>= PACKET3_SET_CONFIG_REG_END
) ||
3504 (end_reg
>= PACKET3_SET_CONFIG_REG_END
)) {
3505 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
3508 for (i
= 0; i
< pkt
->count
; i
++) {
3509 reg
= start_reg
+ (4 * i
);
3510 if (!evergreen_vm_reg_valid(reg
))
3514 case PACKET3_CP_DMA
:
3515 command
= ib
[idx
+ 4];
3517 if ((((info
& 0x60000000) >> 29) != 0) || /* src = GDS or DATA */
3518 (((info
& 0x00300000) >> 20) != 0) || /* dst = GDS */
3519 ((((info
& 0x00300000) >> 20) == 0) &&
3520 (command
& PACKET3_CP_DMA_CMD_DAS
)) || /* dst = register */
3521 ((((info
& 0x60000000) >> 29) == 0) &&
3522 (command
& PACKET3_CP_DMA_CMD_SAS
))) { /* src = register */
3523 /* non mem to mem copies requires dw aligned count */
3524 if ((command
& 0x1fffff) % 4) {
3525 DRM_ERROR("CP DMA command requires dw count alignment\n");
3529 if (command
& PACKET3_CP_DMA_CMD_SAS
) {
3530 /* src address space is register */
3531 if (((info
& 0x60000000) >> 29) == 0) {
3532 start_reg
= idx_value
<< 2;
3533 if (command
& PACKET3_CP_DMA_CMD_SAIC
) {
3535 if (!evergreen_vm_reg_valid(reg
)) {
3536 DRM_ERROR("CP DMA Bad SRC register\n");
3540 for (i
= 0; i
< (command
& 0x1fffff); i
++) {
3541 reg
= start_reg
+ (4 * i
);
3542 if (!evergreen_vm_reg_valid(reg
)) {
3543 DRM_ERROR("CP DMA Bad SRC register\n");
3550 if (command
& PACKET3_CP_DMA_CMD_DAS
) {
3551 /* dst address space is register */
3552 if (((info
& 0x00300000) >> 20) == 0) {
3553 start_reg
= ib
[idx
+ 2];
3554 if (command
& PACKET3_CP_DMA_CMD_DAIC
) {
3556 if (!evergreen_vm_reg_valid(reg
)) {
3557 DRM_ERROR("CP DMA Bad DST register\n");
3561 for (i
= 0; i
< (command
& 0x1fffff); i
++) {
3562 reg
= start_reg
+ (4 * i
);
3563 if (!evergreen_vm_reg_valid(reg
)) {
3564 DRM_ERROR("CP DMA Bad DST register\n");
3578 int evergreen_ib_parse(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3582 struct radeon_cs_packet pkt
;
3586 pkt
.type
= CP_PACKET_GET_TYPE(ib
->ptr
[idx
]);
3587 pkt
.count
= CP_PACKET_GET_COUNT(ib
->ptr
[idx
]);
3591 dev_err(rdev
->dev
, "Packet0 not allowed!\n");
3598 pkt
.opcode
= CP_PACKET3_GET_OPCODE(ib
->ptr
[idx
]);
3599 ret
= evergreen_vm_packet3_check(rdev
, ib
->ptr
, &pkt
);
3600 idx
+= pkt
.count
+ 2;
3603 dev_err(rdev
->dev
, "Unknown packet type %d !\n", pkt
.type
);
3609 } while (idx
< ib
->length_dw
);
3615 * evergreen_dma_ib_parse() - parse the DMA IB for VM
3616 * @rdev: radeon_device pointer
3617 * @ib: radeon_ib pointer
3619 * Parses the DMA IB from the VM CS ioctl
3620 * checks for errors. (Cayman-SI)
3621 * Returns 0 for success and an error on failure.
3623 int evergreen_dma_ib_parse(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3626 u32 header
, cmd
, count
, tiled
, new_cmd
, misc
;
3629 header
= ib
->ptr
[idx
];
3630 cmd
= GET_DMA_CMD(header
);
3631 count
= GET_DMA_COUNT(header
);
3632 tiled
= GET_DMA_T(header
);
3633 new_cmd
= GET_DMA_NEW(header
);
3634 misc
= GET_DMA_MISC(header
);
3637 case DMA_PACKET_WRITE
:
3643 case DMA_PACKET_COPY
:
3648 /* L2T, frame to fields */
3652 /* L2T, T2L partial */
3656 /* L2T, broadcast */
3668 /* L2T, broadcast */
3672 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc
);
3681 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc
);
3697 /* L2L, dw, broadcast */
3701 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc
);
3710 case DMA_PACKET_CONSTANT_FILL
:
3713 case DMA_PACKET_NOP
:
3717 DRM_ERROR("Unknown packet type %d at %d !\n", cmd
, idx
);
3720 } while (idx
< ib
->length_dw
);