2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/module.h>
33 #include <drm/radeon_drm.h>
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
40 #include "radeon_ucode.h"
43 MODULE_FIRMWARE("radeon/R600_pfp.bin");
44 MODULE_FIRMWARE("radeon/R600_me.bin");
45 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
46 MODULE_FIRMWARE("radeon/RV610_me.bin");
47 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
48 MODULE_FIRMWARE("radeon/RV630_me.bin");
49 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV620_me.bin");
51 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV635_me.bin");
53 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV670_me.bin");
55 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
56 MODULE_FIRMWARE("radeon/RS780_me.bin");
57 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV770_me.bin");
59 MODULE_FIRMWARE("radeon/RV770_smc.bin");
60 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
61 MODULE_FIRMWARE("radeon/RV730_me.bin");
62 MODULE_FIRMWARE("radeon/RV730_smc.bin");
63 MODULE_FIRMWARE("radeon/RV740_smc.bin");
64 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
65 MODULE_FIRMWARE("radeon/RV710_me.bin");
66 MODULE_FIRMWARE("radeon/RV710_smc.bin");
67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
69 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
70 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
71 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
72 MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
73 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
74 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
75 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
76 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
77 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
78 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
79 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
81 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
82 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
85 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
86 MODULE_FIRMWARE("radeon/PALM_me.bin");
87 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
88 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
89 MODULE_FIRMWARE("radeon/SUMO_me.bin");
90 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
91 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
93 static const u32 crtc_offsets
[2] =
96 AVIVO_D2CRTC_H_TOTAL
- AVIVO_D1CRTC_H_TOTAL
99 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
);
101 /* r600,rv610,rv630,rv620,rv635,rv670 */
102 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
103 static void r600_gpu_init(struct radeon_device
*rdev
);
104 void r600_fini(struct radeon_device
*rdev
);
105 void r600_irq_disable(struct radeon_device
*rdev
);
106 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
);
107 extern int evergreen_rlc_resume(struct radeon_device
*rdev
);
110 * r600_get_xclk - get the xclk
112 * @rdev: radeon_device pointer
114 * Returns the reference clock used by the gfx engine
115 * (r6xx, IGPs, APUs).
117 u32
r600_get_xclk(struct radeon_device
*rdev
)
119 return rdev
->clock
.spll
.reference_freq
;
122 /* get temperature in millidegrees */
123 int rv6xx_get_temp(struct radeon_device
*rdev
)
125 u32 temp
= (RREG32(CG_THERMAL_STATUS
) & ASIC_T_MASK
) >>
127 int actual_temp
= temp
& 0xff;
132 return actual_temp
* 1000;
135 void r600_pm_get_dynpm_state(struct radeon_device
*rdev
)
139 rdev
->pm
.dynpm_can_upclock
= true;
140 rdev
->pm
.dynpm_can_downclock
= true;
142 /* power state array is low to high, default is first */
143 if ((rdev
->flags
& RADEON_IS_IGP
) || (rdev
->family
== CHIP_R600
)) {
144 int min_power_state_index
= 0;
146 if (rdev
->pm
.num_power_states
> 2)
147 min_power_state_index
= 1;
149 switch (rdev
->pm
.dynpm_planned_action
) {
150 case DYNPM_ACTION_MINIMUM
:
151 rdev
->pm
.requested_power_state_index
= min_power_state_index
;
152 rdev
->pm
.requested_clock_mode_index
= 0;
153 rdev
->pm
.dynpm_can_downclock
= false;
155 case DYNPM_ACTION_DOWNCLOCK
:
156 if (rdev
->pm
.current_power_state_index
== min_power_state_index
) {
157 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
158 rdev
->pm
.dynpm_can_downclock
= false;
160 if (rdev
->pm
.active_crtc_count
> 1) {
161 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
162 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
164 else if (i
>= rdev
->pm
.current_power_state_index
) {
165 rdev
->pm
.requested_power_state_index
=
166 rdev
->pm
.current_power_state_index
;
169 rdev
->pm
.requested_power_state_index
= i
;
174 if (rdev
->pm
.current_power_state_index
== 0)
175 rdev
->pm
.requested_power_state_index
=
176 rdev
->pm
.num_power_states
- 1;
178 rdev
->pm
.requested_power_state_index
=
179 rdev
->pm
.current_power_state_index
- 1;
182 rdev
->pm
.requested_clock_mode_index
= 0;
183 /* don't use the power state if crtcs are active and no display flag is set */
184 if ((rdev
->pm
.active_crtc_count
> 0) &&
185 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
186 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
187 RADEON_PM_MODE_NO_DISPLAY
)) {
188 rdev
->pm
.requested_power_state_index
++;
191 case DYNPM_ACTION_UPCLOCK
:
192 if (rdev
->pm
.current_power_state_index
== (rdev
->pm
.num_power_states
- 1)) {
193 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
194 rdev
->pm
.dynpm_can_upclock
= false;
196 if (rdev
->pm
.active_crtc_count
> 1) {
197 for (i
= (rdev
->pm
.num_power_states
- 1); i
>= 0; i
--) {
198 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
200 else if (i
<= rdev
->pm
.current_power_state_index
) {
201 rdev
->pm
.requested_power_state_index
=
202 rdev
->pm
.current_power_state_index
;
205 rdev
->pm
.requested_power_state_index
= i
;
210 rdev
->pm
.requested_power_state_index
=
211 rdev
->pm
.current_power_state_index
+ 1;
213 rdev
->pm
.requested_clock_mode_index
= 0;
215 case DYNPM_ACTION_DEFAULT
:
216 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
217 rdev
->pm
.requested_clock_mode_index
= 0;
218 rdev
->pm
.dynpm_can_upclock
= false;
220 case DYNPM_ACTION_NONE
:
222 DRM_ERROR("Requested mode for not defined action\n");
226 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
227 /* for now just select the first power state and switch between clock modes */
228 /* power state array is low to high, default is first (0) */
229 if (rdev
->pm
.active_crtc_count
> 1) {
230 rdev
->pm
.requested_power_state_index
= -1;
231 /* start at 1 as we don't want the default mode */
232 for (i
= 1; i
< rdev
->pm
.num_power_states
; i
++) {
233 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
235 else if ((rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_PERFORMANCE
) ||
236 (rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_BATTERY
)) {
237 rdev
->pm
.requested_power_state_index
= i
;
241 /* if nothing selected, grab the default state. */
242 if (rdev
->pm
.requested_power_state_index
== -1)
243 rdev
->pm
.requested_power_state_index
= 0;
245 rdev
->pm
.requested_power_state_index
= 1;
247 switch (rdev
->pm
.dynpm_planned_action
) {
248 case DYNPM_ACTION_MINIMUM
:
249 rdev
->pm
.requested_clock_mode_index
= 0;
250 rdev
->pm
.dynpm_can_downclock
= false;
252 case DYNPM_ACTION_DOWNCLOCK
:
253 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
254 if (rdev
->pm
.current_clock_mode_index
== 0) {
255 rdev
->pm
.requested_clock_mode_index
= 0;
256 rdev
->pm
.dynpm_can_downclock
= false;
258 rdev
->pm
.requested_clock_mode_index
=
259 rdev
->pm
.current_clock_mode_index
- 1;
261 rdev
->pm
.requested_clock_mode_index
= 0;
262 rdev
->pm
.dynpm_can_downclock
= false;
264 /* don't use the power state if crtcs are active and no display flag is set */
265 if ((rdev
->pm
.active_crtc_count
> 0) &&
266 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
267 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
268 RADEON_PM_MODE_NO_DISPLAY
)) {
269 rdev
->pm
.requested_clock_mode_index
++;
272 case DYNPM_ACTION_UPCLOCK
:
273 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
274 if (rdev
->pm
.current_clock_mode_index
==
275 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1)) {
276 rdev
->pm
.requested_clock_mode_index
= rdev
->pm
.current_clock_mode_index
;
277 rdev
->pm
.dynpm_can_upclock
= false;
279 rdev
->pm
.requested_clock_mode_index
=
280 rdev
->pm
.current_clock_mode_index
+ 1;
282 rdev
->pm
.requested_clock_mode_index
=
283 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1;
284 rdev
->pm
.dynpm_can_upclock
= false;
287 case DYNPM_ACTION_DEFAULT
:
288 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
289 rdev
->pm
.requested_clock_mode_index
= 0;
290 rdev
->pm
.dynpm_can_upclock
= false;
292 case DYNPM_ACTION_NONE
:
294 DRM_ERROR("Requested mode for not defined action\n");
299 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
300 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
301 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
,
302 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
303 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
,
304 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
308 void rs780_pm_init_profile(struct radeon_device
*rdev
)
310 if (rdev
->pm
.num_power_states
== 2) {
312 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
313 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
314 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
315 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
317 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 0;
318 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 0;
319 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
320 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
322 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 0;
323 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 0;
324 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
325 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
327 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 0;
328 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
329 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
330 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
332 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 0;
333 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
334 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
335 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
337 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 0;
338 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
339 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
340 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
342 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 0;
343 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 1;
344 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
345 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
346 } else if (rdev
->pm
.num_power_states
== 3) {
348 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
349 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
350 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
351 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
353 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
354 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
355 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
356 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
358 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
359 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
360 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
361 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
363 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
364 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 2;
365 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
366 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
368 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 1;
369 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 1;
370 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
371 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
373 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 1;
374 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 1;
375 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
376 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
378 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 1;
379 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
380 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
381 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
384 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
385 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
386 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
387 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
389 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 2;
390 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 2;
391 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
392 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
394 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 2;
395 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 2;
396 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
397 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
399 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 2;
400 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 3;
401 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
402 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
404 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
405 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
406 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
407 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
409 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
410 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
411 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
412 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
414 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
415 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 3;
416 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
417 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
421 void r600_pm_init_profile(struct radeon_device
*rdev
)
425 if (rdev
->family
== CHIP_R600
) {
428 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
429 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
430 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
431 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
433 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
434 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
435 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
436 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
438 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
439 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
440 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
441 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
443 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
444 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
445 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
446 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
448 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
449 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
450 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
451 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
453 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
454 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
455 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
456 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
458 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
459 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
460 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
461 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
463 if (rdev
->pm
.num_power_states
< 4) {
465 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
466 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
467 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
468 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
470 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
471 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
472 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
473 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
475 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
476 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
477 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
478 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
480 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
481 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
482 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
483 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
485 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
486 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 2;
487 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
488 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
490 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
491 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 2;
492 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
493 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
495 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
496 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
497 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
498 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
501 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
502 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
503 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
504 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
506 if (rdev
->flags
& RADEON_IS_MOBILITY
)
507 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
509 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
510 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= idx
;
511 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= idx
;
512 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
513 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
515 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= idx
;
516 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= idx
;
517 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
518 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
520 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
521 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= idx
;
522 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= idx
;
523 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
524 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
526 if (rdev
->flags
& RADEON_IS_MOBILITY
)
527 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
529 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
530 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= idx
;
531 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= idx
;
532 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
533 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
535 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= idx
;
536 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= idx
;
537 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
538 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
540 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
541 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= idx
;
542 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= idx
;
543 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
544 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
549 void r600_pm_misc(struct radeon_device
*rdev
)
551 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
552 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
553 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
554 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
556 if ((voltage
->type
== VOLTAGE_SW
) && voltage
->voltage
) {
557 /* 0xff01 is a flag rather then an actual voltage */
558 if (voltage
->voltage
== 0xff01)
560 if (voltage
->voltage
!= rdev
->pm
.current_vddc
) {
561 radeon_atom_set_voltage(rdev
, voltage
->voltage
, SET_VOLTAGE_TYPE_ASIC_VDDC
);
562 rdev
->pm
.current_vddc
= voltage
->voltage
;
563 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage
->voltage
);
568 bool r600_gui_idle(struct radeon_device
*rdev
)
570 if (RREG32(GRBM_STATUS
) & GUI_ACTIVE
)
576 /* hpd for digital panel detect/disconnect */
577 bool r600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
579 bool connected
= false;
581 if (ASIC_IS_DCE3(rdev
)) {
584 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
588 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
592 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
596 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
601 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
605 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
614 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
618 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
622 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
632 void r600_hpd_set_polarity(struct radeon_device
*rdev
,
633 enum radeon_hpd_id hpd
)
636 bool connected
= r600_hpd_sense(rdev
, hpd
);
638 if (ASIC_IS_DCE3(rdev
)) {
641 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
643 tmp
&= ~DC_HPDx_INT_POLARITY
;
645 tmp
|= DC_HPDx_INT_POLARITY
;
646 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
649 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
651 tmp
&= ~DC_HPDx_INT_POLARITY
;
653 tmp
|= DC_HPDx_INT_POLARITY
;
654 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
657 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
659 tmp
&= ~DC_HPDx_INT_POLARITY
;
661 tmp
|= DC_HPDx_INT_POLARITY
;
662 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
665 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
667 tmp
&= ~DC_HPDx_INT_POLARITY
;
669 tmp
|= DC_HPDx_INT_POLARITY
;
670 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
673 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
675 tmp
&= ~DC_HPDx_INT_POLARITY
;
677 tmp
|= DC_HPDx_INT_POLARITY
;
678 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
682 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
684 tmp
&= ~DC_HPDx_INT_POLARITY
;
686 tmp
|= DC_HPDx_INT_POLARITY
;
687 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
695 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
697 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
699 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
700 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
703 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
705 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
707 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
708 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
711 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
713 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
715 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
716 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
724 void r600_hpd_init(struct radeon_device
*rdev
)
726 struct drm_device
*dev
= rdev
->ddev
;
727 struct drm_connector
*connector
;
730 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
731 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
733 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
734 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
735 /* don't try to enable hpd on eDP or LVDS avoid breaking the
736 * aux dp channel on imac and help (but not completely fix)
737 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
741 if (ASIC_IS_DCE3(rdev
)) {
742 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
743 if (ASIC_IS_DCE32(rdev
))
746 switch (radeon_connector
->hpd
.hpd
) {
748 WREG32(DC_HPD1_CONTROL
, tmp
);
751 WREG32(DC_HPD2_CONTROL
, tmp
);
754 WREG32(DC_HPD3_CONTROL
, tmp
);
757 WREG32(DC_HPD4_CONTROL
, tmp
);
761 WREG32(DC_HPD5_CONTROL
, tmp
);
764 WREG32(DC_HPD6_CONTROL
, tmp
);
770 switch (radeon_connector
->hpd
.hpd
) {
772 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
775 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
778 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
784 enable
|= 1 << radeon_connector
->hpd
.hpd
;
785 radeon_hpd_set_polarity(rdev
, radeon_connector
->hpd
.hpd
);
787 radeon_irq_kms_enable_hpd(rdev
, enable
);
790 void r600_hpd_fini(struct radeon_device
*rdev
)
792 struct drm_device
*dev
= rdev
->ddev
;
793 struct drm_connector
*connector
;
794 unsigned disable
= 0;
796 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
797 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
798 if (ASIC_IS_DCE3(rdev
)) {
799 switch (radeon_connector
->hpd
.hpd
) {
801 WREG32(DC_HPD1_CONTROL
, 0);
804 WREG32(DC_HPD2_CONTROL
, 0);
807 WREG32(DC_HPD3_CONTROL
, 0);
810 WREG32(DC_HPD4_CONTROL
, 0);
814 WREG32(DC_HPD5_CONTROL
, 0);
817 WREG32(DC_HPD6_CONTROL
, 0);
823 switch (radeon_connector
->hpd
.hpd
) {
825 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, 0);
828 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, 0);
831 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, 0);
837 disable
|= 1 << radeon_connector
->hpd
.hpd
;
839 radeon_irq_kms_disable_hpd(rdev
, disable
);
845 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
850 /* flush hdp cache so updates hit vram */
851 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
852 !(rdev
->flags
& RADEON_IS_AGP
)) {
853 void __iomem
*ptr
= (void *)rdev
->gart
.ptr
;
856 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
857 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
858 * This seems to cause problems on some AGP cards. Just use the old
861 WREG32(HDP_DEBUG1
, 0);
862 tmp
= readl((void __iomem
*)ptr
);
864 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
866 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR
, rdev
->mc
.gtt_start
>> 12);
867 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR
, (rdev
->mc
.gtt_end
- 1) >> 12);
868 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
869 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
871 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
872 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
874 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
884 int r600_pcie_gart_init(struct radeon_device
*rdev
)
888 if (rdev
->gart
.robj
) {
889 WARN(1, "R600 PCIE GART already initialized\n");
892 /* Initialize common gart structure */
893 r
= radeon_gart_init(rdev
);
896 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 8;
897 return radeon_gart_table_vram_alloc(rdev
);
900 static int r600_pcie_gart_enable(struct radeon_device
*rdev
)
905 if (rdev
->gart
.robj
== NULL
) {
906 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
909 r
= radeon_gart_table_vram_pin(rdev
);
912 radeon_gart_restore(rdev
);
915 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
916 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
917 EFFECTIVE_L2_QUEUE_SIZE(7));
918 WREG32(VM_L2_CNTL2
, 0);
919 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
920 /* Setup TLB control */
921 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
922 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
923 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
924 ENABLE_WAIT_L2_QUERY
;
925 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
926 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
927 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
928 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
929 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
930 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
931 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
932 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
933 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
934 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
935 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
936 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
937 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
938 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
939 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
940 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
941 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
942 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
943 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
944 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
945 (u32
)(rdev
->dummy_page
.addr
>> 12));
946 for (i
= 1; i
< 7; i
++)
947 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
949 r600_pcie_gart_tlb_flush(rdev
);
950 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
951 (unsigned)(rdev
->mc
.gtt_size
>> 20),
952 (unsigned long long)rdev
->gart
.table_addr
);
953 rdev
->gart
.ready
= true;
957 static void r600_pcie_gart_disable(struct radeon_device
*rdev
)
962 /* Disable all tables */
963 for (i
= 0; i
< 7; i
++)
964 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
966 /* Disable L2 cache */
967 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
968 EFFECTIVE_L2_QUEUE_SIZE(7));
969 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
970 /* Setup L1 TLB control */
971 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
972 ENABLE_WAIT_L2_QUERY
;
973 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
974 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
975 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
976 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
977 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
978 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
979 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
980 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
981 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
);
982 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
);
983 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
984 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
985 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
);
986 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
987 radeon_gart_table_vram_unpin(rdev
);
990 static void r600_pcie_gart_fini(struct radeon_device
*rdev
)
992 radeon_gart_fini(rdev
);
993 r600_pcie_gart_disable(rdev
);
994 radeon_gart_table_vram_free(rdev
);
997 static void r600_agp_enable(struct radeon_device
*rdev
)
1002 /* Setup L2 cache */
1003 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1004 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1005 EFFECTIVE_L2_QUEUE_SIZE(7));
1006 WREG32(VM_L2_CNTL2
, 0);
1007 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1008 /* Setup TLB control */
1009 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1010 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1011 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1012 ENABLE_WAIT_L2_QUERY
;
1013 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
1014 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
1015 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
1016 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
1017 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
1018 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
1019 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
1020 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
1021 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
1022 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
1023 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
1024 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
1025 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1026 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1027 for (i
= 0; i
< 7; i
++)
1028 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
1031 int r600_mc_wait_for_idle(struct radeon_device
*rdev
)
1036 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1037 /* read MC_STATUS */
1038 tmp
= RREG32(R_000E50_SRBM_STATUS
) & 0x3F00;
1046 uint32_t rs780_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
)
1050 WREG32(R_0028F8_MC_INDEX
, S_0028F8_MC_IND_ADDR(reg
));
1051 r
= RREG32(R_0028FC_MC_DATA
);
1052 WREG32(R_0028F8_MC_INDEX
, ~C_0028F8_MC_IND_ADDR
);
1056 void rs780_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
1058 WREG32(R_0028F8_MC_INDEX
, S_0028F8_MC_IND_ADDR(reg
) |
1059 S_0028F8_MC_IND_WR_EN(1));
1060 WREG32(R_0028FC_MC_DATA
, v
);
1061 WREG32(R_0028F8_MC_INDEX
, 0x7F);
1064 static void r600_mc_program(struct radeon_device
*rdev
)
1066 struct rv515_mc_save save
;
1070 /* Initialize HDP */
1071 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1072 WREG32((0x2c14 + j
), 0x00000000);
1073 WREG32((0x2c18 + j
), 0x00000000);
1074 WREG32((0x2c1c + j
), 0x00000000);
1075 WREG32((0x2c20 + j
), 0x00000000);
1076 WREG32((0x2c24 + j
), 0x00000000);
1078 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1080 rv515_mc_stop(rdev
, &save
);
1081 if (r600_mc_wait_for_idle(rdev
)) {
1082 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1084 /* Lockout access through VGA aperture (doesn't exist before R600) */
1085 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1086 /* Update configuration */
1087 if (rdev
->flags
& RADEON_IS_AGP
) {
1088 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1089 /* VRAM before AGP */
1090 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1091 rdev
->mc
.vram_start
>> 12);
1092 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1093 rdev
->mc
.gtt_end
>> 12);
1095 /* VRAM after AGP */
1096 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1097 rdev
->mc
.gtt_start
>> 12);
1098 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1099 rdev
->mc
.vram_end
>> 12);
1102 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.vram_start
>> 12);
1103 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, rdev
->mc
.vram_end
>> 12);
1105 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, rdev
->vram_scratch
.gpu_addr
>> 12);
1106 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1107 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1108 WREG32(MC_VM_FB_LOCATION
, tmp
);
1109 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1110 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
1111 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1112 if (rdev
->flags
& RADEON_IS_AGP
) {
1113 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 22);
1114 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 22);
1115 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1117 WREG32(MC_VM_AGP_BASE
, 0);
1118 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1119 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1121 if (r600_mc_wait_for_idle(rdev
)) {
1122 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1124 rv515_mc_resume(rdev
, &save
);
1125 /* we need to own VRAM, so turn off the VGA renderer here
1126 * to stop it overwriting our objects */
1127 rv515_vga_render_disable(rdev
);
1131 * r600_vram_gtt_location - try to find VRAM & GTT location
1132 * @rdev: radeon device structure holding all necessary informations
1133 * @mc: memory controller structure holding memory informations
1135 * Function will place try to place VRAM at same place as in CPU (PCI)
1136 * address space as some GPU seems to have issue when we reprogram at
1137 * different address space.
1139 * If there is not enough space to fit the unvisible VRAM after the
1140 * aperture then we limit the VRAM size to the aperture.
1142 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1143 * them to be in one from GPU point of view so that we can program GPU to
1144 * catch access outside them (weird GPU policy see ??).
1146 * This function will never fails, worst case are limiting VRAM or GTT.
1148 * Note: GTT start, end, size should be initialized before calling this
1149 * function on AGP platform.
1151 static void r600_vram_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
1153 u64 size_bf
, size_af
;
1155 if (mc
->mc_vram_size
> 0xE0000000) {
1156 /* leave room for at least 512M GTT */
1157 dev_warn(rdev
->dev
, "limiting VRAM\n");
1158 mc
->real_vram_size
= 0xE0000000;
1159 mc
->mc_vram_size
= 0xE0000000;
1161 if (rdev
->flags
& RADEON_IS_AGP
) {
1162 size_bf
= mc
->gtt_start
;
1163 size_af
= mc
->mc_mask
- mc
->gtt_end
;
1164 if (size_bf
> size_af
) {
1165 if (mc
->mc_vram_size
> size_bf
) {
1166 dev_warn(rdev
->dev
, "limiting VRAM\n");
1167 mc
->real_vram_size
= size_bf
;
1168 mc
->mc_vram_size
= size_bf
;
1170 mc
->vram_start
= mc
->gtt_start
- mc
->mc_vram_size
;
1172 if (mc
->mc_vram_size
> size_af
) {
1173 dev_warn(rdev
->dev
, "limiting VRAM\n");
1174 mc
->real_vram_size
= size_af
;
1175 mc
->mc_vram_size
= size_af
;
1177 mc
->vram_start
= mc
->gtt_end
+ 1;
1179 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
1180 dev_info(rdev
->dev
, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1181 mc
->mc_vram_size
>> 20, mc
->vram_start
,
1182 mc
->vram_end
, mc
->real_vram_size
>> 20);
1185 if (rdev
->flags
& RADEON_IS_IGP
) {
1186 base
= RREG32(MC_VM_FB_LOCATION
) & 0xFFFF;
1189 radeon_vram_location(rdev
, &rdev
->mc
, base
);
1190 rdev
->mc
.gtt_base_align
= 0;
1191 radeon_gtt_location(rdev
, mc
);
1195 static int r600_mc_init(struct radeon_device
*rdev
)
1198 int chansize
, numchan
;
1199 uint32_t h_addr
, l_addr
;
1200 unsigned long long k8_addr
;
1202 /* Get VRAM informations */
1203 rdev
->mc
.vram_is_ddr
= true;
1204 tmp
= RREG32(RAMCFG
);
1205 if (tmp
& CHANSIZE_OVERRIDE
) {
1207 } else if (tmp
& CHANSIZE_MASK
) {
1212 tmp
= RREG32(CHMAP
);
1213 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
1228 rdev
->mc
.vram_width
= numchan
* chansize
;
1229 /* Could aper size report 0 ? */
1230 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
1231 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
1232 /* Setup GPU memory space */
1233 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
1234 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
1235 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
1236 r600_vram_gtt_location(rdev
, &rdev
->mc
);
1238 if (rdev
->flags
& RADEON_IS_IGP
) {
1239 rs690_pm_info(rdev
);
1240 rdev
->mc
.igp_sideport_enabled
= radeon_atombios_sideport_present(rdev
);
1242 if (rdev
->family
== CHIP_RS780
|| rdev
->family
== CHIP_RS880
) {
1243 /* Use K8 direct mapping for fast fb access. */
1244 rdev
->fastfb_working
= false;
1245 h_addr
= G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL
));
1246 l_addr
= RREG32_MC(R_000011_K8_FB_LOCATION
);
1247 k8_addr
= ((unsigned long long)h_addr
) << 32 | l_addr
;
1248 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1249 if (k8_addr
+ rdev
->mc
.visible_vram_size
< 0x100000000ULL
)
1252 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1253 * memory is present.
1255 if (rdev
->mc
.igp_sideport_enabled
== false && radeon_fastfb
== 1) {
1256 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1257 (unsigned long long)rdev
->mc
.aper_base
, k8_addr
);
1258 rdev
->mc
.aper_base
= (resource_size_t
)k8_addr
;
1259 rdev
->fastfb_working
= true;
1265 radeon_update_bandwidth_info(rdev
);
1269 int r600_vram_scratch_init(struct radeon_device
*rdev
)
1273 if (rdev
->vram_scratch
.robj
== NULL
) {
1274 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
,
1275 PAGE_SIZE
, true, RADEON_GEM_DOMAIN_VRAM
,
1276 NULL
, &rdev
->vram_scratch
.robj
);
1282 r
= radeon_bo_reserve(rdev
->vram_scratch
.robj
, false);
1283 if (unlikely(r
!= 0))
1285 r
= radeon_bo_pin(rdev
->vram_scratch
.robj
,
1286 RADEON_GEM_DOMAIN_VRAM
, &rdev
->vram_scratch
.gpu_addr
);
1288 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
1291 r
= radeon_bo_kmap(rdev
->vram_scratch
.robj
,
1292 (void **)&rdev
->vram_scratch
.ptr
);
1294 radeon_bo_unpin(rdev
->vram_scratch
.robj
);
1295 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
1300 void r600_vram_scratch_fini(struct radeon_device
*rdev
)
1304 if (rdev
->vram_scratch
.robj
== NULL
) {
1307 r
= radeon_bo_reserve(rdev
->vram_scratch
.robj
, false);
1308 if (likely(r
== 0)) {
1309 radeon_bo_kunmap(rdev
->vram_scratch
.robj
);
1310 radeon_bo_unpin(rdev
->vram_scratch
.robj
);
1311 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
1313 radeon_bo_unref(&rdev
->vram_scratch
.robj
);
1316 void r600_set_bios_scratch_engine_hung(struct radeon_device
*rdev
, bool hung
)
1318 u32 tmp
= RREG32(R600_BIOS_3_SCRATCH
);
1321 tmp
|= ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
1323 tmp
&= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
1325 WREG32(R600_BIOS_3_SCRATCH
, tmp
);
1328 static void r600_print_gpu_status_regs(struct radeon_device
*rdev
)
1330 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS = 0x%08X\n",
1331 RREG32(R_008010_GRBM_STATUS
));
1332 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1333 RREG32(R_008014_GRBM_STATUS2
));
1334 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS = 0x%08X\n",
1335 RREG32(R_000E50_SRBM_STATUS
));
1336 dev_info(rdev
->dev
, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1337 RREG32(CP_STALLED_STAT1
));
1338 dev_info(rdev
->dev
, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1339 RREG32(CP_STALLED_STAT2
));
1340 dev_info(rdev
->dev
, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1341 RREG32(CP_BUSY_STAT
));
1342 dev_info(rdev
->dev
, " R_008680_CP_STAT = 0x%08X\n",
1344 dev_info(rdev
->dev
, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1345 RREG32(DMA_STATUS_REG
));
1348 static bool r600_is_display_hung(struct radeon_device
*rdev
)
1354 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1355 if (RREG32(AVIVO_D1CRTC_CONTROL
+ crtc_offsets
[i
]) & AVIVO_CRTC_EN
) {
1356 crtc_status
[i
] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
1357 crtc_hung
|= (1 << i
);
1361 for (j
= 0; j
< 10; j
++) {
1362 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1363 if (crtc_hung
& (1 << i
)) {
1364 tmp
= RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
1365 if (tmp
!= crtc_status
[i
])
1366 crtc_hung
&= ~(1 << i
);
1377 static u32
r600_gpu_check_soft_reset(struct radeon_device
*rdev
)
1383 tmp
= RREG32(R_008010_GRBM_STATUS
);
1384 if (rdev
->family
>= CHIP_RV770
) {
1385 if (G_008010_PA_BUSY(tmp
) | G_008010_SC_BUSY(tmp
) |
1386 G_008010_SH_BUSY(tmp
) | G_008010_SX_BUSY(tmp
) |
1387 G_008010_TA_BUSY(tmp
) | G_008010_VGT_BUSY(tmp
) |
1388 G_008010_DB03_BUSY(tmp
) | G_008010_CB03_BUSY(tmp
) |
1389 G_008010_SPI03_BUSY(tmp
) | G_008010_VGT_BUSY_NO_DMA(tmp
))
1390 reset_mask
|= RADEON_RESET_GFX
;
1392 if (G_008010_PA_BUSY(tmp
) | G_008010_SC_BUSY(tmp
) |
1393 G_008010_SH_BUSY(tmp
) | G_008010_SX_BUSY(tmp
) |
1394 G_008010_TA03_BUSY(tmp
) | G_008010_VGT_BUSY(tmp
) |
1395 G_008010_DB03_BUSY(tmp
) | G_008010_CB03_BUSY(tmp
) |
1396 G_008010_SPI03_BUSY(tmp
) | G_008010_VGT_BUSY_NO_DMA(tmp
))
1397 reset_mask
|= RADEON_RESET_GFX
;
1400 if (G_008010_CF_RQ_PENDING(tmp
) | G_008010_PF_RQ_PENDING(tmp
) |
1401 G_008010_CP_BUSY(tmp
) | G_008010_CP_COHERENCY_BUSY(tmp
))
1402 reset_mask
|= RADEON_RESET_CP
;
1404 if (G_008010_GRBM_EE_BUSY(tmp
))
1405 reset_mask
|= RADEON_RESET_GRBM
| RADEON_RESET_GFX
| RADEON_RESET_CP
;
1407 /* DMA_STATUS_REG */
1408 tmp
= RREG32(DMA_STATUS_REG
);
1409 if (!(tmp
& DMA_IDLE
))
1410 reset_mask
|= RADEON_RESET_DMA
;
1413 tmp
= RREG32(R_000E50_SRBM_STATUS
);
1414 if (G_000E50_RLC_RQ_PENDING(tmp
) | G_000E50_RLC_BUSY(tmp
))
1415 reset_mask
|= RADEON_RESET_RLC
;
1417 if (G_000E50_IH_BUSY(tmp
))
1418 reset_mask
|= RADEON_RESET_IH
;
1420 if (G_000E50_SEM_BUSY(tmp
))
1421 reset_mask
|= RADEON_RESET_SEM
;
1423 if (G_000E50_GRBM_RQ_PENDING(tmp
))
1424 reset_mask
|= RADEON_RESET_GRBM
;
1426 if (G_000E50_VMC_BUSY(tmp
))
1427 reset_mask
|= RADEON_RESET_VMC
;
1429 if (G_000E50_MCB_BUSY(tmp
) | G_000E50_MCDZ_BUSY(tmp
) |
1430 G_000E50_MCDY_BUSY(tmp
) | G_000E50_MCDX_BUSY(tmp
) |
1431 G_000E50_MCDW_BUSY(tmp
))
1432 reset_mask
|= RADEON_RESET_MC
;
1434 if (r600_is_display_hung(rdev
))
1435 reset_mask
|= RADEON_RESET_DISPLAY
;
1437 /* Skip MC reset as it's mostly likely not hung, just busy */
1438 if (reset_mask
& RADEON_RESET_MC
) {
1439 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask
);
1440 reset_mask
&= ~RADEON_RESET_MC
;
1446 static void r600_gpu_soft_reset(struct radeon_device
*rdev
, u32 reset_mask
)
1448 struct rv515_mc_save save
;
1449 u32 grbm_soft_reset
= 0, srbm_soft_reset
= 0;
1452 if (reset_mask
== 0)
1455 dev_info(rdev
->dev
, "GPU softreset: 0x%08X\n", reset_mask
);
1457 r600_print_gpu_status_regs(rdev
);
1459 /* Disable CP parsing/prefetching */
1460 if (rdev
->family
>= CHIP_RV770
)
1461 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1463 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
1465 /* disable the RLC */
1466 WREG32(RLC_CNTL
, 0);
1468 if (reset_mask
& RADEON_RESET_DMA
) {
1470 tmp
= RREG32(DMA_RB_CNTL
);
1471 tmp
&= ~DMA_RB_ENABLE
;
1472 WREG32(DMA_RB_CNTL
, tmp
);
1477 rv515_mc_stop(rdev
, &save
);
1478 if (r600_mc_wait_for_idle(rdev
)) {
1479 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1482 if (reset_mask
& (RADEON_RESET_GFX
| RADEON_RESET_COMPUTE
)) {
1483 if (rdev
->family
>= CHIP_RV770
)
1484 grbm_soft_reset
|= S_008020_SOFT_RESET_DB(1) |
1485 S_008020_SOFT_RESET_CB(1) |
1486 S_008020_SOFT_RESET_PA(1) |
1487 S_008020_SOFT_RESET_SC(1) |
1488 S_008020_SOFT_RESET_SPI(1) |
1489 S_008020_SOFT_RESET_SX(1) |
1490 S_008020_SOFT_RESET_SH(1) |
1491 S_008020_SOFT_RESET_TC(1) |
1492 S_008020_SOFT_RESET_TA(1) |
1493 S_008020_SOFT_RESET_VC(1) |
1494 S_008020_SOFT_RESET_VGT(1);
1496 grbm_soft_reset
|= S_008020_SOFT_RESET_CR(1) |
1497 S_008020_SOFT_RESET_DB(1) |
1498 S_008020_SOFT_RESET_CB(1) |
1499 S_008020_SOFT_RESET_PA(1) |
1500 S_008020_SOFT_RESET_SC(1) |
1501 S_008020_SOFT_RESET_SMX(1) |
1502 S_008020_SOFT_RESET_SPI(1) |
1503 S_008020_SOFT_RESET_SX(1) |
1504 S_008020_SOFT_RESET_SH(1) |
1505 S_008020_SOFT_RESET_TC(1) |
1506 S_008020_SOFT_RESET_TA(1) |
1507 S_008020_SOFT_RESET_VC(1) |
1508 S_008020_SOFT_RESET_VGT(1);
1511 if (reset_mask
& RADEON_RESET_CP
) {
1512 grbm_soft_reset
|= S_008020_SOFT_RESET_CP(1) |
1513 S_008020_SOFT_RESET_VGT(1);
1515 srbm_soft_reset
|= S_000E60_SOFT_RESET_GRBM(1);
1518 if (reset_mask
& RADEON_RESET_DMA
) {
1519 if (rdev
->family
>= CHIP_RV770
)
1520 srbm_soft_reset
|= RV770_SOFT_RESET_DMA
;
1522 srbm_soft_reset
|= SOFT_RESET_DMA
;
1525 if (reset_mask
& RADEON_RESET_RLC
)
1526 srbm_soft_reset
|= S_000E60_SOFT_RESET_RLC(1);
1528 if (reset_mask
& RADEON_RESET_SEM
)
1529 srbm_soft_reset
|= S_000E60_SOFT_RESET_SEM(1);
1531 if (reset_mask
& RADEON_RESET_IH
)
1532 srbm_soft_reset
|= S_000E60_SOFT_RESET_IH(1);
1534 if (reset_mask
& RADEON_RESET_GRBM
)
1535 srbm_soft_reset
|= S_000E60_SOFT_RESET_GRBM(1);
1537 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
1538 if (reset_mask
& RADEON_RESET_MC
)
1539 srbm_soft_reset
|= S_000E60_SOFT_RESET_MC(1);
1542 if (reset_mask
& RADEON_RESET_VMC
)
1543 srbm_soft_reset
|= S_000E60_SOFT_RESET_VMC(1);
1545 if (grbm_soft_reset
) {
1546 tmp
= RREG32(R_008020_GRBM_SOFT_RESET
);
1547 tmp
|= grbm_soft_reset
;
1548 dev_info(rdev
->dev
, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
1549 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1550 tmp
= RREG32(R_008020_GRBM_SOFT_RESET
);
1554 tmp
&= ~grbm_soft_reset
;
1555 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1556 tmp
= RREG32(R_008020_GRBM_SOFT_RESET
);
1559 if (srbm_soft_reset
) {
1560 tmp
= RREG32(SRBM_SOFT_RESET
);
1561 tmp
|= srbm_soft_reset
;
1562 dev_info(rdev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1563 WREG32(SRBM_SOFT_RESET
, tmp
);
1564 tmp
= RREG32(SRBM_SOFT_RESET
);
1568 tmp
&= ~srbm_soft_reset
;
1569 WREG32(SRBM_SOFT_RESET
, tmp
);
1570 tmp
= RREG32(SRBM_SOFT_RESET
);
1573 /* Wait a little for things to settle down */
1576 rv515_mc_resume(rdev
, &save
);
1579 r600_print_gpu_status_regs(rdev
);
1582 int r600_asic_reset(struct radeon_device
*rdev
)
1586 reset_mask
= r600_gpu_check_soft_reset(rdev
);
1589 r600_set_bios_scratch_engine_hung(rdev
, true);
1591 r600_gpu_soft_reset(rdev
, reset_mask
);
1593 reset_mask
= r600_gpu_check_soft_reset(rdev
);
1596 r600_set_bios_scratch_engine_hung(rdev
, false);
1602 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1604 * @rdev: radeon_device pointer
1605 * @ring: radeon_ring structure holding ring information
1607 * Check if the GFX engine is locked up.
1608 * Returns true if the engine appears to be locked up, false if not.
1610 bool r600_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
1612 u32 reset_mask
= r600_gpu_check_soft_reset(rdev
);
1614 if (!(reset_mask
& (RADEON_RESET_GFX
|
1615 RADEON_RESET_COMPUTE
|
1616 RADEON_RESET_CP
))) {
1617 radeon_ring_lockup_update(ring
);
1620 /* force CP activities */
1621 radeon_ring_force_activity(rdev
, ring
);
1622 return radeon_ring_test_lockup(rdev
, ring
);
1626 * r600_dma_is_lockup - Check if the DMA engine is locked up
1628 * @rdev: radeon_device pointer
1629 * @ring: radeon_ring structure holding ring information
1631 * Check if the async DMA engine is locked up.
1632 * Returns true if the engine appears to be locked up, false if not.
1634 bool r600_dma_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
1636 u32 reset_mask
= r600_gpu_check_soft_reset(rdev
);
1638 if (!(reset_mask
& RADEON_RESET_DMA
)) {
1639 radeon_ring_lockup_update(ring
);
1642 /* force ring activities */
1643 radeon_ring_force_activity(rdev
, ring
);
1644 return radeon_ring_test_lockup(rdev
, ring
);
1647 u32
r6xx_remap_render_backend(struct radeon_device
*rdev
,
1648 u32 tiling_pipe_num
,
1650 u32 total_max_rb_num
,
1651 u32 disabled_rb_mask
)
1653 u32 rendering_pipe_num
, rb_num_width
, req_rb_num
;
1654 u32 pipe_rb_ratio
, pipe_rb_remain
, tmp
;
1655 u32 data
= 0, mask
= 1 << (max_rb_num
- 1);
1658 /* mask out the RBs that don't exist on that asic */
1659 tmp
= disabled_rb_mask
| ((0xff << max_rb_num
) & 0xff);
1660 /* make sure at least one RB is available */
1661 if ((tmp
& 0xff) != 0xff)
1662 disabled_rb_mask
= tmp
;
1664 rendering_pipe_num
= 1 << tiling_pipe_num
;
1665 req_rb_num
= total_max_rb_num
- r600_count_pipe_bits(disabled_rb_mask
);
1666 BUG_ON(rendering_pipe_num
< req_rb_num
);
1668 pipe_rb_ratio
= rendering_pipe_num
/ req_rb_num
;
1669 pipe_rb_remain
= rendering_pipe_num
- pipe_rb_ratio
* req_rb_num
;
1671 if (rdev
->family
<= CHIP_RV740
) {
1679 for (i
= 0; i
< max_rb_num
; i
++) {
1680 if (!(mask
& disabled_rb_mask
)) {
1681 for (j
= 0; j
< pipe_rb_ratio
; j
++) {
1682 data
<<= rb_num_width
;
1683 data
|= max_rb_num
- i
- 1;
1685 if (pipe_rb_remain
) {
1686 data
<<= rb_num_width
;
1687 data
|= max_rb_num
- i
- 1;
1697 int r600_count_pipe_bits(uint32_t val
)
1699 return hweight32(val
);
1702 static void r600_gpu_init(struct radeon_device
*rdev
)
1706 u32 cc_rb_backend_disable
;
1707 u32 cc_gc_shader_pipe_config
;
1711 u32 sq_gpr_resource_mgmt_1
= 0;
1712 u32 sq_gpr_resource_mgmt_2
= 0;
1713 u32 sq_thread_resource_mgmt
= 0;
1714 u32 sq_stack_resource_mgmt_1
= 0;
1715 u32 sq_stack_resource_mgmt_2
= 0;
1716 u32 disabled_rb_mask
;
1718 rdev
->config
.r600
.tiling_group_size
= 256;
1719 switch (rdev
->family
) {
1721 rdev
->config
.r600
.max_pipes
= 4;
1722 rdev
->config
.r600
.max_tile_pipes
= 8;
1723 rdev
->config
.r600
.max_simds
= 4;
1724 rdev
->config
.r600
.max_backends
= 4;
1725 rdev
->config
.r600
.max_gprs
= 256;
1726 rdev
->config
.r600
.max_threads
= 192;
1727 rdev
->config
.r600
.max_stack_entries
= 256;
1728 rdev
->config
.r600
.max_hw_contexts
= 8;
1729 rdev
->config
.r600
.max_gs_threads
= 16;
1730 rdev
->config
.r600
.sx_max_export_size
= 128;
1731 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1732 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1733 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1737 rdev
->config
.r600
.max_pipes
= 2;
1738 rdev
->config
.r600
.max_tile_pipes
= 2;
1739 rdev
->config
.r600
.max_simds
= 3;
1740 rdev
->config
.r600
.max_backends
= 1;
1741 rdev
->config
.r600
.max_gprs
= 128;
1742 rdev
->config
.r600
.max_threads
= 192;
1743 rdev
->config
.r600
.max_stack_entries
= 128;
1744 rdev
->config
.r600
.max_hw_contexts
= 8;
1745 rdev
->config
.r600
.max_gs_threads
= 4;
1746 rdev
->config
.r600
.sx_max_export_size
= 128;
1747 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1748 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1749 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1755 rdev
->config
.r600
.max_pipes
= 1;
1756 rdev
->config
.r600
.max_tile_pipes
= 1;
1757 rdev
->config
.r600
.max_simds
= 2;
1758 rdev
->config
.r600
.max_backends
= 1;
1759 rdev
->config
.r600
.max_gprs
= 128;
1760 rdev
->config
.r600
.max_threads
= 192;
1761 rdev
->config
.r600
.max_stack_entries
= 128;
1762 rdev
->config
.r600
.max_hw_contexts
= 4;
1763 rdev
->config
.r600
.max_gs_threads
= 4;
1764 rdev
->config
.r600
.sx_max_export_size
= 128;
1765 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1766 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1767 rdev
->config
.r600
.sq_num_cf_insts
= 1;
1770 rdev
->config
.r600
.max_pipes
= 4;
1771 rdev
->config
.r600
.max_tile_pipes
= 4;
1772 rdev
->config
.r600
.max_simds
= 4;
1773 rdev
->config
.r600
.max_backends
= 4;
1774 rdev
->config
.r600
.max_gprs
= 192;
1775 rdev
->config
.r600
.max_threads
= 192;
1776 rdev
->config
.r600
.max_stack_entries
= 256;
1777 rdev
->config
.r600
.max_hw_contexts
= 8;
1778 rdev
->config
.r600
.max_gs_threads
= 16;
1779 rdev
->config
.r600
.sx_max_export_size
= 128;
1780 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1781 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1782 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1788 /* Initialize HDP */
1789 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1790 WREG32((0x2c14 + j
), 0x00000000);
1791 WREG32((0x2c18 + j
), 0x00000000);
1792 WREG32((0x2c1c + j
), 0x00000000);
1793 WREG32((0x2c20 + j
), 0x00000000);
1794 WREG32((0x2c24 + j
), 0x00000000);
1797 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1801 ramcfg
= RREG32(RAMCFG
);
1802 switch (rdev
->config
.r600
.max_tile_pipes
) {
1804 tiling_config
|= PIPE_TILING(0);
1807 tiling_config
|= PIPE_TILING(1);
1810 tiling_config
|= PIPE_TILING(2);
1813 tiling_config
|= PIPE_TILING(3);
1818 rdev
->config
.r600
.tiling_npipes
= rdev
->config
.r600
.max_tile_pipes
;
1819 rdev
->config
.r600
.tiling_nbanks
= 4 << ((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1820 tiling_config
|= BANK_TILING((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1821 tiling_config
|= GROUP_SIZE((ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
);
1823 tmp
= (ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
;
1825 tiling_config
|= ROW_TILING(3);
1826 tiling_config
|= SAMPLE_SPLIT(3);
1828 tiling_config
|= ROW_TILING(tmp
);
1829 tiling_config
|= SAMPLE_SPLIT(tmp
);
1831 tiling_config
|= BANK_SWAPS(1);
1833 cc_rb_backend_disable
= RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
1834 tmp
= R6XX_MAX_BACKENDS
-
1835 r600_count_pipe_bits((cc_rb_backend_disable
>> 16) & R6XX_MAX_BACKENDS_MASK
);
1836 if (tmp
< rdev
->config
.r600
.max_backends
) {
1837 rdev
->config
.r600
.max_backends
= tmp
;
1840 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0x00ffff00;
1841 tmp
= R6XX_MAX_PIPES
-
1842 r600_count_pipe_bits((cc_gc_shader_pipe_config
>> 8) & R6XX_MAX_PIPES_MASK
);
1843 if (tmp
< rdev
->config
.r600
.max_pipes
) {
1844 rdev
->config
.r600
.max_pipes
= tmp
;
1846 tmp
= R6XX_MAX_SIMDS
-
1847 r600_count_pipe_bits((cc_gc_shader_pipe_config
>> 16) & R6XX_MAX_SIMDS_MASK
);
1848 if (tmp
< rdev
->config
.r600
.max_simds
) {
1849 rdev
->config
.r600
.max_simds
= tmp
;
1852 disabled_rb_mask
= (RREG32(CC_RB_BACKEND_DISABLE
) >> 16) & R6XX_MAX_BACKENDS_MASK
;
1853 tmp
= (tiling_config
& PIPE_TILING__MASK
) >> PIPE_TILING__SHIFT
;
1854 tmp
= r6xx_remap_render_backend(rdev
, tmp
, rdev
->config
.r600
.max_backends
,
1855 R6XX_MAX_BACKENDS
, disabled_rb_mask
);
1856 tiling_config
|= tmp
<< 16;
1857 rdev
->config
.r600
.backend_map
= tmp
;
1859 rdev
->config
.r600
.tile_config
= tiling_config
;
1860 WREG32(GB_TILING_CONFIG
, tiling_config
);
1861 WREG32(DCP_TILING_CONFIG
, tiling_config
& 0xffff);
1862 WREG32(HDP_TILING_CONFIG
, tiling_config
& 0xffff);
1863 WREG32(DMA_TILING_CONFIG
, tiling_config
& 0xffff);
1865 tmp
= R6XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& INACTIVE_QD_PIPES_MASK
) >> 8);
1866 WREG32(VGT_OUT_DEALLOC_CNTL
, (tmp
* 4) & DEALLOC_DIST_MASK
);
1867 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((tmp
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
1869 /* Setup some CP states */
1870 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1871 WREG32(CP_MEQ_THRESHOLDS
, (MEQ_END(0x40) | ROQ_END(0x40)));
1873 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
| SYNC_GRADIENT
|
1874 SYNC_WALKER
| SYNC_ALIGNER
));
1875 /* Setup various GPU states */
1876 if (rdev
->family
== CHIP_RV670
)
1877 WREG32(ARB_GDEC_RD_CNTL
, 0x00000021);
1879 tmp
= RREG32(SX_DEBUG_1
);
1880 tmp
|= SMX_EVENT_RELEASE
;
1881 if ((rdev
->family
> CHIP_R600
))
1882 tmp
|= ENABLE_NEW_SMX_ADDRESS
;
1883 WREG32(SX_DEBUG_1
, tmp
);
1885 if (((rdev
->family
) == CHIP_R600
) ||
1886 ((rdev
->family
) == CHIP_RV630
) ||
1887 ((rdev
->family
) == CHIP_RV610
) ||
1888 ((rdev
->family
) == CHIP_RV620
) ||
1889 ((rdev
->family
) == CHIP_RS780
) ||
1890 ((rdev
->family
) == CHIP_RS880
)) {
1891 WREG32(DB_DEBUG
, PREZ_MUST_WAIT_FOR_POSTZ_DONE
);
1893 WREG32(DB_DEBUG
, 0);
1895 WREG32(DB_WATERMARKS
, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1896 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1898 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1899 WREG32(VGT_NUM_INSTANCES
, 0);
1901 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
1902 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(0));
1904 tmp
= RREG32(SQ_MS_FIFO_SIZES
);
1905 if (((rdev
->family
) == CHIP_RV610
) ||
1906 ((rdev
->family
) == CHIP_RV620
) ||
1907 ((rdev
->family
) == CHIP_RS780
) ||
1908 ((rdev
->family
) == CHIP_RS880
)) {
1909 tmp
= (CACHE_FIFO_SIZE(0xa) |
1910 FETCH_FIFO_HIWATER(0xa) |
1911 DONE_FIFO_HIWATER(0xe0) |
1912 ALU_UPDATE_FIFO_HIWATER(0x8));
1913 } else if (((rdev
->family
) == CHIP_R600
) ||
1914 ((rdev
->family
) == CHIP_RV630
)) {
1915 tmp
&= ~DONE_FIFO_HIWATER(0xff);
1916 tmp
|= DONE_FIFO_HIWATER(0x4);
1918 WREG32(SQ_MS_FIFO_SIZES
, tmp
);
1920 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1921 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1923 sq_config
= RREG32(SQ_CONFIG
);
1924 sq_config
&= ~(PS_PRIO(3) |
1928 sq_config
|= (DX9_CONSTS
|
1935 if ((rdev
->family
) == CHIP_R600
) {
1936 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(124) |
1938 NUM_CLAUSE_TEMP_GPRS(4));
1939 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(0) |
1941 sq_thread_resource_mgmt
= (NUM_PS_THREADS(136) |
1942 NUM_VS_THREADS(48) |
1945 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(128) |
1946 NUM_VS_STACK_ENTRIES(128));
1947 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(0) |
1948 NUM_ES_STACK_ENTRIES(0));
1949 } else if (((rdev
->family
) == CHIP_RV610
) ||
1950 ((rdev
->family
) == CHIP_RV620
) ||
1951 ((rdev
->family
) == CHIP_RS780
) ||
1952 ((rdev
->family
) == CHIP_RS880
)) {
1953 /* no vertex cache */
1954 sq_config
&= ~VC_ENABLE
;
1956 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1958 NUM_CLAUSE_TEMP_GPRS(2));
1959 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1961 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1962 NUM_VS_THREADS(78) |
1964 NUM_ES_THREADS(31));
1965 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1966 NUM_VS_STACK_ENTRIES(40));
1967 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1968 NUM_ES_STACK_ENTRIES(16));
1969 } else if (((rdev
->family
) == CHIP_RV630
) ||
1970 ((rdev
->family
) == CHIP_RV635
)) {
1971 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1973 NUM_CLAUSE_TEMP_GPRS(2));
1974 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(18) |
1976 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1977 NUM_VS_THREADS(78) |
1979 NUM_ES_THREADS(31));
1980 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1981 NUM_VS_STACK_ENTRIES(40));
1982 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1983 NUM_ES_STACK_ENTRIES(16));
1984 } else if ((rdev
->family
) == CHIP_RV670
) {
1985 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1987 NUM_CLAUSE_TEMP_GPRS(2));
1988 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1990 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1991 NUM_VS_THREADS(78) |
1993 NUM_ES_THREADS(31));
1994 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(64) |
1995 NUM_VS_STACK_ENTRIES(64));
1996 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(64) |
1997 NUM_ES_STACK_ENTRIES(64));
2000 WREG32(SQ_CONFIG
, sq_config
);
2001 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
2002 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
2003 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
2004 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
2005 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
2007 if (((rdev
->family
) == CHIP_RV610
) ||
2008 ((rdev
->family
) == CHIP_RV620
) ||
2009 ((rdev
->family
) == CHIP_RS780
) ||
2010 ((rdev
->family
) == CHIP_RS880
)) {
2011 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(TC_ONLY
));
2013 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(VC_AND_TC
));
2016 /* More default values. 2D/3D driver should adjust as needed */
2017 WREG32(PA_SC_AA_SAMPLE_LOCS_2S
, (S0_X(0xc) | S0_Y(0x4) |
2018 S1_X(0x4) | S1_Y(0xc)));
2019 WREG32(PA_SC_AA_SAMPLE_LOCS_4S
, (S0_X(0xe) | S0_Y(0xe) |
2020 S1_X(0x2) | S1_Y(0x2) |
2021 S2_X(0xa) | S2_Y(0x6) |
2022 S3_X(0x6) | S3_Y(0xa)));
2023 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0
, (S0_X(0xe) | S0_Y(0xb) |
2024 S1_X(0x4) | S1_Y(0xc) |
2025 S2_X(0x1) | S2_Y(0x6) |
2026 S3_X(0xa) | S3_Y(0xe)));
2027 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1
, (S4_X(0x6) | S4_Y(0x1) |
2028 S5_X(0x0) | S5_Y(0x0) |
2029 S6_X(0xb) | S6_Y(0x4) |
2030 S7_X(0x7) | S7_Y(0x8)));
2032 WREG32(VGT_STRMOUT_EN
, 0);
2033 tmp
= rdev
->config
.r600
.max_pipes
* 16;
2034 switch (rdev
->family
) {
2050 WREG32(VGT_ES_PER_GS
, 128);
2051 WREG32(VGT_GS_PER_ES
, tmp
);
2052 WREG32(VGT_GS_PER_VS
, 2);
2053 WREG32(VGT_GS_VERTEX_REUSE
, 16);
2055 /* more default values. 2D/3D driver should adjust as needed */
2056 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
2057 WREG32(VGT_STRMOUT_EN
, 0);
2059 WREG32(PA_SC_MODE_CNTL
, 0);
2060 WREG32(PA_SC_AA_CONFIG
, 0);
2061 WREG32(PA_SC_LINE_STIPPLE
, 0);
2062 WREG32(SPI_INPUT_Z
, 0);
2063 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
2064 WREG32(CB_COLOR7_FRAG
, 0);
2066 /* Clear render buffer base addresses */
2067 WREG32(CB_COLOR0_BASE
, 0);
2068 WREG32(CB_COLOR1_BASE
, 0);
2069 WREG32(CB_COLOR2_BASE
, 0);
2070 WREG32(CB_COLOR3_BASE
, 0);
2071 WREG32(CB_COLOR4_BASE
, 0);
2072 WREG32(CB_COLOR5_BASE
, 0);
2073 WREG32(CB_COLOR6_BASE
, 0);
2074 WREG32(CB_COLOR7_BASE
, 0);
2075 WREG32(CB_COLOR7_FRAG
, 0);
2077 switch (rdev
->family
) {
2082 tmp
= TC_L2_SIZE(8);
2086 tmp
= TC_L2_SIZE(4);
2089 tmp
= TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT
;
2092 tmp
= TC_L2_SIZE(0);
2095 WREG32(TC_CNTL
, tmp
);
2097 tmp
= RREG32(HDP_HOST_PATH_CNTL
);
2098 WREG32(HDP_HOST_PATH_CNTL
, tmp
);
2100 tmp
= RREG32(ARB_POP
);
2101 tmp
|= ENABLE_TC128
;
2102 WREG32(ARB_POP
, tmp
);
2104 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
2105 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
2107 WREG32(PA_SC_ENHANCE
, FORCE_EOV_MAX_CLK_CNT(4095));
2108 WREG32(VC_ENHANCE
, 0);
2113 * Indirect registers accessor
2115 u32
r600_pciep_rreg(struct radeon_device
*rdev
, u32 reg
)
2119 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
2120 (void)RREG32(PCIE_PORT_INDEX
);
2121 r
= RREG32(PCIE_PORT_DATA
);
2125 void r600_pciep_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
2127 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
2128 (void)RREG32(PCIE_PORT_INDEX
);
2129 WREG32(PCIE_PORT_DATA
, (v
));
2130 (void)RREG32(PCIE_PORT_DATA
);
2136 void r600_cp_stop(struct radeon_device
*rdev
)
2138 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.visible_vram_size
);
2139 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
2140 WREG32(SCRATCH_UMSK
, 0);
2141 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= false;
2144 int r600_init_microcode(struct radeon_device
*rdev
)
2146 const char *chip_name
;
2147 const char *rlc_chip_name
;
2148 const char *smc_chip_name
= "RV770";
2149 size_t pfp_req_size
, me_req_size
, rlc_req_size
, smc_req_size
= 0;
2155 switch (rdev
->family
) {
2158 rlc_chip_name
= "R600";
2161 chip_name
= "RV610";
2162 rlc_chip_name
= "R600";
2165 chip_name
= "RV630";
2166 rlc_chip_name
= "R600";
2169 chip_name
= "RV620";
2170 rlc_chip_name
= "R600";
2173 chip_name
= "RV635";
2174 rlc_chip_name
= "R600";
2177 chip_name
= "RV670";
2178 rlc_chip_name
= "R600";
2182 chip_name
= "RS780";
2183 rlc_chip_name
= "R600";
2186 chip_name
= "RV770";
2187 rlc_chip_name
= "R700";
2188 smc_chip_name
= "RV770";
2189 smc_req_size
= ALIGN(RV770_SMC_UCODE_SIZE
, 4);
2192 chip_name
= "RV730";
2193 rlc_chip_name
= "R700";
2194 smc_chip_name
= "RV730";
2195 smc_req_size
= ALIGN(RV730_SMC_UCODE_SIZE
, 4);
2198 chip_name
= "RV710";
2199 rlc_chip_name
= "R700";
2200 smc_chip_name
= "RV710";
2201 smc_req_size
= ALIGN(RV710_SMC_UCODE_SIZE
, 4);
2204 chip_name
= "RV730";
2205 rlc_chip_name
= "R700";
2206 smc_chip_name
= "RV740";
2207 smc_req_size
= ALIGN(RV740_SMC_UCODE_SIZE
, 4);
2210 chip_name
= "CEDAR";
2211 rlc_chip_name
= "CEDAR";
2212 smc_chip_name
= "CEDAR";
2213 smc_req_size
= ALIGN(CEDAR_SMC_UCODE_SIZE
, 4);
2216 chip_name
= "REDWOOD";
2217 rlc_chip_name
= "REDWOOD";
2218 smc_chip_name
= "REDWOOD";
2219 smc_req_size
= ALIGN(REDWOOD_SMC_UCODE_SIZE
, 4);
2222 chip_name
= "JUNIPER";
2223 rlc_chip_name
= "JUNIPER";
2224 smc_chip_name
= "JUNIPER";
2225 smc_req_size
= ALIGN(JUNIPER_SMC_UCODE_SIZE
, 4);
2229 chip_name
= "CYPRESS";
2230 rlc_chip_name
= "CYPRESS";
2231 smc_chip_name
= "CYPRESS";
2232 smc_req_size
= ALIGN(CYPRESS_SMC_UCODE_SIZE
, 4);
2236 rlc_chip_name
= "SUMO";
2240 rlc_chip_name
= "SUMO";
2243 chip_name
= "SUMO2";
2244 rlc_chip_name
= "SUMO";
2249 if (rdev
->family
>= CHIP_CEDAR
) {
2250 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
2251 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
2252 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
2253 } else if (rdev
->family
>= CHIP_RV770
) {
2254 pfp_req_size
= R700_PFP_UCODE_SIZE
* 4;
2255 me_req_size
= R700_PM4_UCODE_SIZE
* 4;
2256 rlc_req_size
= R700_RLC_UCODE_SIZE
* 4;
2258 pfp_req_size
= R600_PFP_UCODE_SIZE
* 4;
2259 me_req_size
= R600_PM4_UCODE_SIZE
* 12;
2260 rlc_req_size
= R600_RLC_UCODE_SIZE
* 4;
2263 DRM_INFO("Loading %s Microcode\n", chip_name
);
2265 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
2266 err
= request_firmware(&rdev
->pfp_fw
, fw_name
, rdev
->dev
);
2269 if (rdev
->pfp_fw
->size
!= pfp_req_size
) {
2271 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2272 rdev
->pfp_fw
->size
, fw_name
);
2277 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
2278 err
= request_firmware(&rdev
->me_fw
, fw_name
, rdev
->dev
);
2281 if (rdev
->me_fw
->size
!= me_req_size
) {
2283 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2284 rdev
->me_fw
->size
, fw_name
);
2288 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", rlc_chip_name
);
2289 err
= request_firmware(&rdev
->rlc_fw
, fw_name
, rdev
->dev
);
2292 if (rdev
->rlc_fw
->size
!= rlc_req_size
) {
2294 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2295 rdev
->rlc_fw
->size
, fw_name
);
2299 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_HEMLOCK
)) {
2300 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_smc.bin", smc_chip_name
);
2301 err
= request_firmware(&rdev
->smc_fw
, fw_name
, rdev
->dev
);
2304 "smc: error loading firmware \"%s\"\n",
2306 release_firmware(rdev
->smc_fw
);
2307 rdev
->smc_fw
= NULL
;
2308 } else if (rdev
->smc_fw
->size
!= smc_req_size
) {
2310 "smc: Bogus length %zu in firmware \"%s\"\n",
2311 rdev
->smc_fw
->size
, fw_name
);
2320 "r600_cp: Failed to load firmware \"%s\"\n",
2322 release_firmware(rdev
->pfp_fw
);
2323 rdev
->pfp_fw
= NULL
;
2324 release_firmware(rdev
->me_fw
);
2326 release_firmware(rdev
->rlc_fw
);
2327 rdev
->rlc_fw
= NULL
;
2328 release_firmware(rdev
->smc_fw
);
2329 rdev
->smc_fw
= NULL
;
2334 static int r600_cp_load_microcode(struct radeon_device
*rdev
)
2336 const __be32
*fw_data
;
2339 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
2348 RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
2351 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2352 RREG32(GRBM_SOFT_RESET
);
2354 WREG32(GRBM_SOFT_RESET
, 0);
2356 WREG32(CP_ME_RAM_WADDR
, 0);
2358 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
2359 WREG32(CP_ME_RAM_WADDR
, 0);
2360 for (i
= 0; i
< R600_PM4_UCODE_SIZE
* 3; i
++)
2361 WREG32(CP_ME_RAM_DATA
,
2362 be32_to_cpup(fw_data
++));
2364 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
2365 WREG32(CP_PFP_UCODE_ADDR
, 0);
2366 for (i
= 0; i
< R600_PFP_UCODE_SIZE
; i
++)
2367 WREG32(CP_PFP_UCODE_DATA
,
2368 be32_to_cpup(fw_data
++));
2370 WREG32(CP_PFP_UCODE_ADDR
, 0);
2371 WREG32(CP_ME_RAM_WADDR
, 0);
2372 WREG32(CP_ME_RAM_RADDR
, 0);
2376 int r600_cp_start(struct radeon_device
*rdev
)
2378 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2382 r
= radeon_ring_lock(rdev
, ring
, 7);
2384 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
2387 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
2388 radeon_ring_write(ring
, 0x1);
2389 if (rdev
->family
>= CHIP_RV770
) {
2390 radeon_ring_write(ring
, 0x0);
2391 radeon_ring_write(ring
, rdev
->config
.rv770
.max_hw_contexts
- 1);
2393 radeon_ring_write(ring
, 0x3);
2394 radeon_ring_write(ring
, rdev
->config
.r600
.max_hw_contexts
- 1);
2396 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2397 radeon_ring_write(ring
, 0);
2398 radeon_ring_write(ring
, 0);
2399 radeon_ring_unlock_commit(rdev
, ring
);
2402 WREG32(R_0086D8_CP_ME_CNTL
, cp_me
);
2406 int r600_cp_resume(struct radeon_device
*rdev
)
2408 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2414 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2415 RREG32(GRBM_SOFT_RESET
);
2417 WREG32(GRBM_SOFT_RESET
, 0);
2419 /* Set ring buffer size */
2420 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
2421 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2423 tmp
|= BUF_SWAP_32BIT
;
2425 WREG32(CP_RB_CNTL
, tmp
);
2426 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
2428 /* Set the write pointer delay */
2429 WREG32(CP_RB_WPTR_DELAY
, 0);
2431 /* Initialize the ring buffer's read and write pointers */
2432 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
2433 WREG32(CP_RB_RPTR_WR
, 0);
2435 WREG32(CP_RB_WPTR
, ring
->wptr
);
2437 /* set the wb address whether it's enabled or not */
2438 WREG32(CP_RB_RPTR_ADDR
,
2439 ((rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC));
2440 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
2441 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
2443 if (rdev
->wb
.enabled
)
2444 WREG32(SCRATCH_UMSK
, 0xff);
2446 tmp
|= RB_NO_UPDATE
;
2447 WREG32(SCRATCH_UMSK
, 0);
2451 WREG32(CP_RB_CNTL
, tmp
);
2453 WREG32(CP_RB_BASE
, ring
->gpu_addr
>> 8);
2454 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
2456 ring
->rptr
= RREG32(CP_RB_RPTR
);
2458 r600_cp_start(rdev
);
2460 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, ring
);
2462 ring
->ready
= false;
2468 void r600_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ring_size
)
2473 /* Align ring size */
2474 rb_bufsz
= drm_order(ring_size
/ 8);
2475 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
2476 ring
->ring_size
= ring_size
;
2477 ring
->align_mask
= 16 - 1;
2479 if (radeon_ring_supports_scratch_reg(rdev
, ring
)) {
2480 r
= radeon_scratch_get(rdev
, &ring
->rptr_save_reg
);
2482 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r
);
2483 ring
->rptr_save_reg
= 0;
2488 void r600_cp_fini(struct radeon_device
*rdev
)
2490 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2492 radeon_ring_fini(rdev
, ring
);
2493 radeon_scratch_free(rdev
, ring
->rptr_save_reg
);
2498 * Starting with R600, the GPU has an asynchronous
2499 * DMA engine. The programming model is very similar
2500 * to the 3D engine (ring buffer, IBs, etc.), but the
2501 * DMA controller has it's own packet format that is
2502 * different form the PM4 format used by the 3D engine.
2503 * It supports copying data, writing embedded data,
2504 * solid fills, and a number of other things. It also
2505 * has support for tiling/detiling of buffers.
2508 * r600_dma_stop - stop the async dma engine
2510 * @rdev: radeon_device pointer
2512 * Stop the async dma engine (r6xx-evergreen).
2514 void r600_dma_stop(struct radeon_device
*rdev
)
2516 u32 rb_cntl
= RREG32(DMA_RB_CNTL
);
2518 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.visible_vram_size
);
2520 rb_cntl
&= ~DMA_RB_ENABLE
;
2521 WREG32(DMA_RB_CNTL
, rb_cntl
);
2523 rdev
->ring
[R600_RING_TYPE_DMA_INDEX
].ready
= false;
2527 * r600_dma_resume - setup and start the async dma engine
2529 * @rdev: radeon_device pointer
2531 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2532 * Returns 0 for success, error for failure.
2534 int r600_dma_resume(struct radeon_device
*rdev
)
2536 struct radeon_ring
*ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
2537 u32 rb_cntl
, dma_cntl
, ib_cntl
;
2542 if (rdev
->family
>= CHIP_RV770
)
2543 WREG32(SRBM_SOFT_RESET
, RV770_SOFT_RESET_DMA
);
2545 WREG32(SRBM_SOFT_RESET
, SOFT_RESET_DMA
);
2546 RREG32(SRBM_SOFT_RESET
);
2548 WREG32(SRBM_SOFT_RESET
, 0);
2550 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL
, 0);
2551 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL
, 0);
2553 /* Set ring buffer size in dwords */
2554 rb_bufsz
= drm_order(ring
->ring_size
/ 4);
2555 rb_cntl
= rb_bufsz
<< 1;
2557 rb_cntl
|= DMA_RB_SWAP_ENABLE
| DMA_RPTR_WRITEBACK_SWAP_ENABLE
;
2559 WREG32(DMA_RB_CNTL
, rb_cntl
);
2561 /* Initialize the ring buffer's read and write pointers */
2562 WREG32(DMA_RB_RPTR
, 0);
2563 WREG32(DMA_RB_WPTR
, 0);
2565 /* set the wb address whether it's enabled or not */
2566 WREG32(DMA_RB_RPTR_ADDR_HI
,
2567 upper_32_bits(rdev
->wb
.gpu_addr
+ R600_WB_DMA_RPTR_OFFSET
) & 0xFF);
2568 WREG32(DMA_RB_RPTR_ADDR_LO
,
2569 ((rdev
->wb
.gpu_addr
+ R600_WB_DMA_RPTR_OFFSET
) & 0xFFFFFFFC));
2571 if (rdev
->wb
.enabled
)
2572 rb_cntl
|= DMA_RPTR_WRITEBACK_ENABLE
;
2574 WREG32(DMA_RB_BASE
, ring
->gpu_addr
>> 8);
2576 /* enable DMA IBs */
2577 ib_cntl
= DMA_IB_ENABLE
;
2579 ib_cntl
|= DMA_IB_SWAP_ENABLE
;
2581 WREG32(DMA_IB_CNTL
, ib_cntl
);
2583 dma_cntl
= RREG32(DMA_CNTL
);
2584 dma_cntl
&= ~CTXEMPTY_INT_ENABLE
;
2585 WREG32(DMA_CNTL
, dma_cntl
);
2587 if (rdev
->family
>= CHIP_RV770
)
2588 WREG32(DMA_MODE
, 1);
2591 WREG32(DMA_RB_WPTR
, ring
->wptr
<< 2);
2593 ring
->rptr
= RREG32(DMA_RB_RPTR
) >> 2;
2595 WREG32(DMA_RB_CNTL
, rb_cntl
| DMA_RB_ENABLE
);
2599 r
= radeon_ring_test(rdev
, R600_RING_TYPE_DMA_INDEX
, ring
);
2601 ring
->ready
= false;
2605 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.real_vram_size
);
2611 * r600_dma_fini - tear down the async dma engine
2613 * @rdev: radeon_device pointer
2615 * Stop the async dma engine and free the ring (r6xx-evergreen).
2617 void r600_dma_fini(struct radeon_device
*rdev
)
2619 r600_dma_stop(rdev
);
2620 radeon_ring_fini(rdev
, &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
]);
2626 int r600_uvd_rbc_start(struct radeon_device
*rdev
)
2628 struct radeon_ring
*ring
= &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
];
2630 uint32_t rb_bufsz
, tmp
;
2633 rptr_addr
= rdev
->wb
.gpu_addr
+ R600_WB_UVD_RPTR_OFFSET
;
2635 if (upper_32_bits(rptr_addr
) != upper_32_bits(ring
->gpu_addr
)) {
2636 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n");
2640 /* force RBC into idle state */
2641 WREG32(UVD_RBC_RB_CNTL
, 0x11010101);
2643 /* Set the write pointer delay */
2644 WREG32(UVD_RBC_RB_WPTR_CNTL
, 0);
2646 /* set the wb address */
2647 WREG32(UVD_RBC_RB_RPTR_ADDR
, rptr_addr
>> 2);
2649 /* programm the 4GB memory segment for rptr and ring buffer */
2650 WREG32(UVD_LMI_EXT40_ADDR
, upper_32_bits(rptr_addr
) |
2651 (0x7 << 16) | (0x1 << 31));
2653 /* Initialize the ring buffer's read and write pointers */
2654 WREG32(UVD_RBC_RB_RPTR
, 0x0);
2656 ring
->wptr
= ring
->rptr
= RREG32(UVD_RBC_RB_RPTR
);
2657 WREG32(UVD_RBC_RB_WPTR
, ring
->wptr
);
2659 /* set the ring address */
2660 WREG32(UVD_RBC_RB_BASE
, ring
->gpu_addr
);
2662 /* Set ring buffer size */
2663 rb_bufsz
= drm_order(ring
->ring_size
);
2664 rb_bufsz
= (0x1 << 8) | rb_bufsz
;
2665 WREG32(UVD_RBC_RB_CNTL
, rb_bufsz
);
2668 r
= radeon_ring_test(rdev
, R600_RING_TYPE_UVD_INDEX
, ring
);
2670 ring
->ready
= false;
2674 r
= radeon_ring_lock(rdev
, ring
, 10);
2676 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r
);
2680 tmp
= PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
, 0);
2681 radeon_ring_write(ring
, tmp
);
2682 radeon_ring_write(ring
, 0xFFFFF);
2684 tmp
= PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
, 0);
2685 radeon_ring_write(ring
, tmp
);
2686 radeon_ring_write(ring
, 0xFFFFF);
2688 tmp
= PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
, 0);
2689 radeon_ring_write(ring
, tmp
);
2690 radeon_ring_write(ring
, 0xFFFFF);
2692 /* Clear timeout status bits */
2693 radeon_ring_write(ring
, PACKET0(UVD_SEMA_TIMEOUT_STATUS
, 0));
2694 radeon_ring_write(ring
, 0x8);
2696 radeon_ring_write(ring
, PACKET0(UVD_SEMA_CNTL
, 0));
2697 radeon_ring_write(ring
, 3);
2699 radeon_ring_unlock_commit(rdev
, ring
);
2704 void r600_uvd_stop(struct radeon_device
*rdev
)
2706 struct radeon_ring
*ring
= &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
];
2708 /* force RBC into idle state */
2709 WREG32(UVD_RBC_RB_CNTL
, 0x11010101);
2711 /* Stall UMC and register bus before resetting VCPU */
2712 WREG32_P(UVD_LMI_CTRL2
, 1 << 8, ~(1 << 8));
2713 WREG32_P(UVD_RB_ARB_CTRL
, 1 << 3, ~(1 << 3));
2716 /* put VCPU into reset */
2717 WREG32(UVD_SOFT_RESET
, VCPU_SOFT_RESET
);
2720 /* disable VCPU clock */
2721 WREG32(UVD_VCPU_CNTL
, 0x0);
2723 /* Unstall UMC and register bus */
2724 WREG32_P(UVD_LMI_CTRL2
, 0, ~(1 << 8));
2725 WREG32_P(UVD_RB_ARB_CTRL
, 0, ~(1 << 3));
2727 ring
->ready
= false;
2730 int r600_uvd_init(struct radeon_device
*rdev
)
2733 /* disable byte swapping */
2734 u32 lmi_swap_cntl
= 0;
2735 u32 mp_swap_cntl
= 0;
2737 /* raise clocks while booting up the VCPU */
2738 radeon_set_uvd_clocks(rdev
, 53300, 40000);
2740 /* disable clock gating */
2741 WREG32(UVD_CGC_GATE
, 0);
2743 /* disable interupt */
2744 WREG32_P(UVD_MASTINT_EN
, 0, ~(1 << 1));
2746 /* Stall UMC and register bus before resetting VCPU */
2747 WREG32_P(UVD_LMI_CTRL2
, 1 << 8, ~(1 << 8));
2748 WREG32_P(UVD_RB_ARB_CTRL
, 1 << 3, ~(1 << 3));
2751 /* put LMI, VCPU, RBC etc... into reset */
2752 WREG32(UVD_SOFT_RESET
, LMI_SOFT_RESET
| VCPU_SOFT_RESET
|
2753 LBSI_SOFT_RESET
| RBC_SOFT_RESET
| CSM_SOFT_RESET
|
2754 CXW_SOFT_RESET
| TAP_SOFT_RESET
| LMI_UMC_SOFT_RESET
);
2757 /* take UVD block out of reset */
2758 WREG32_P(SRBM_SOFT_RESET
, 0, ~SOFT_RESET_UVD
);
2761 /* initialize UVD memory controller */
2762 WREG32(UVD_LMI_CTRL
, 0x40 | (1 << 8) | (1 << 13) |
2763 (1 << 21) | (1 << 9) | (1 << 20));
2766 /* swap (8 in 32) RB and IB */
2767 lmi_swap_cntl
= 0xa;
2770 WREG32(UVD_LMI_SWAP_CNTL
, lmi_swap_cntl
);
2771 WREG32(UVD_MP_SWAP_CNTL
, mp_swap_cntl
);
2773 WREG32(UVD_MPC_SET_MUXA0
, 0x40c2040);
2774 WREG32(UVD_MPC_SET_MUXA1
, 0x0);
2775 WREG32(UVD_MPC_SET_MUXB0
, 0x40c2040);
2776 WREG32(UVD_MPC_SET_MUXB1
, 0x0);
2777 WREG32(UVD_MPC_SET_ALU
, 0);
2778 WREG32(UVD_MPC_SET_MUX
, 0x88);
2780 /* take all subblocks out of reset, except VCPU */
2781 WREG32(UVD_SOFT_RESET
, VCPU_SOFT_RESET
);
2784 /* enable VCPU clock */
2785 WREG32(UVD_VCPU_CNTL
, 1 << 9);
2788 WREG32_P(UVD_LMI_CTRL2
, 0, ~(1 << 8));
2790 /* boot up the VCPU */
2791 WREG32(UVD_SOFT_RESET
, 0);
2794 WREG32_P(UVD_RB_ARB_CTRL
, 0, ~(1 << 3));
2796 for (i
= 0; i
< 10; ++i
) {
2798 for (j
= 0; j
< 100; ++j
) {
2799 status
= RREG32(UVD_STATUS
);
2808 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
2809 WREG32_P(UVD_SOFT_RESET
, VCPU_SOFT_RESET
, ~VCPU_SOFT_RESET
);
2811 WREG32_P(UVD_SOFT_RESET
, 0, ~VCPU_SOFT_RESET
);
2817 DRM_ERROR("UVD not responding, giving up!!!\n");
2818 radeon_set_uvd_clocks(rdev
, 0, 0);
2822 /* enable interupt */
2823 WREG32_P(UVD_MASTINT_EN
, 3<<1, ~(3 << 1));
2825 r
= r600_uvd_rbc_start(rdev
);
2827 DRM_INFO("UVD initialized successfully.\n");
2829 /* lower clocks again */
2830 radeon_set_uvd_clocks(rdev
, 0, 0);
2836 * GPU scratch registers helpers function.
2838 void r600_scratch_init(struct radeon_device
*rdev
)
2842 rdev
->scratch
.num_reg
= 7;
2843 rdev
->scratch
.reg_base
= SCRATCH_REG0
;
2844 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
2845 rdev
->scratch
.free
[i
] = true;
2846 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
2850 int r600_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2857 r
= radeon_scratch_get(rdev
, &scratch
);
2859 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
2862 WREG32(scratch
, 0xCAFEDEAD);
2863 r
= radeon_ring_lock(rdev
, ring
, 3);
2865 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring
->idx
, r
);
2866 radeon_scratch_free(rdev
, scratch
);
2869 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2870 radeon_ring_write(ring
, ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2871 radeon_ring_write(ring
, 0xDEADBEEF);
2872 radeon_ring_unlock_commit(rdev
, ring
);
2873 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2874 tmp
= RREG32(scratch
);
2875 if (tmp
== 0xDEADBEEF)
2879 if (i
< rdev
->usec_timeout
) {
2880 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
2882 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2883 ring
->idx
, scratch
, tmp
);
2886 radeon_scratch_free(rdev
, scratch
);
2891 * r600_dma_ring_test - simple async dma engine test
2893 * @rdev: radeon_device pointer
2894 * @ring: radeon_ring structure holding ring information
2896 * Test the DMA engine by writing using it to write an
2897 * value to memory. (r6xx-SI).
2898 * Returns 0 for success, error for failure.
2900 int r600_dma_ring_test(struct radeon_device
*rdev
,
2901 struct radeon_ring
*ring
)
2905 void __iomem
*ptr
= (void *)rdev
->vram_scratch
.ptr
;
2909 DRM_ERROR("invalid vram scratch pointer\n");
2916 r
= radeon_ring_lock(rdev
, ring
, 4);
2918 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
2921 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_WRITE
, 0, 0, 1));
2922 radeon_ring_write(ring
, rdev
->vram_scratch
.gpu_addr
& 0xfffffffc);
2923 radeon_ring_write(ring
, upper_32_bits(rdev
->vram_scratch
.gpu_addr
) & 0xff);
2924 radeon_ring_write(ring
, 0xDEADBEEF);
2925 radeon_ring_unlock_commit(rdev
, ring
);
2927 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2929 if (tmp
== 0xDEADBEEF)
2934 if (i
< rdev
->usec_timeout
) {
2935 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
2937 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2944 int r600_uvd_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2950 WREG32(UVD_CONTEXT_ID
, 0xCAFEDEAD);
2951 r
= radeon_ring_lock(rdev
, ring
, 3);
2953 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
2957 radeon_ring_write(ring
, PACKET0(UVD_CONTEXT_ID
, 0));
2958 radeon_ring_write(ring
, 0xDEADBEEF);
2959 radeon_ring_unlock_commit(rdev
, ring
);
2960 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2961 tmp
= RREG32(UVD_CONTEXT_ID
);
2962 if (tmp
== 0xDEADBEEF)
2967 if (i
< rdev
->usec_timeout
) {
2968 DRM_INFO("ring test on %d succeeded in %d usecs\n",
2971 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2979 * CP fences/semaphores
2982 void r600_fence_ring_emit(struct radeon_device
*rdev
,
2983 struct radeon_fence
*fence
)
2985 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
2987 if (rdev
->wb
.use_event
) {
2988 u64 addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
2989 /* flush read cache over gart */
2990 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
2991 radeon_ring_write(ring
, PACKET3_TC_ACTION_ENA
|
2992 PACKET3_VC_ACTION_ENA
|
2993 PACKET3_SH_ACTION_ENA
);
2994 radeon_ring_write(ring
, 0xFFFFFFFF);
2995 radeon_ring_write(ring
, 0);
2996 radeon_ring_write(ring
, 10); /* poll interval */
2997 /* EVENT_WRITE_EOP - flush caches, send int */
2998 radeon_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
2999 radeon_ring_write(ring
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS
) | EVENT_INDEX(5));
3000 radeon_ring_write(ring
, addr
& 0xffffffff);
3001 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3002 radeon_ring_write(ring
, fence
->seq
);
3003 radeon_ring_write(ring
, 0);
3005 /* flush read cache over gart */
3006 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
3007 radeon_ring_write(ring
, PACKET3_TC_ACTION_ENA
|
3008 PACKET3_VC_ACTION_ENA
|
3009 PACKET3_SH_ACTION_ENA
);
3010 radeon_ring_write(ring
, 0xFFFFFFFF);
3011 radeon_ring_write(ring
, 0);
3012 radeon_ring_write(ring
, 10); /* poll interval */
3013 radeon_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE
, 0));
3014 radeon_ring_write(ring
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0));
3015 /* wait for 3D idle clean */
3016 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
3017 radeon_ring_write(ring
, (WAIT_UNTIL
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
3018 radeon_ring_write(ring
, WAIT_3D_IDLE_bit
| WAIT_3D_IDLECLEAN_bit
);
3019 /* Emit fence sequence & fire IRQ */
3020 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
3021 radeon_ring_write(ring
, ((rdev
->fence_drv
[fence
->ring
].scratch_reg
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
3022 radeon_ring_write(ring
, fence
->seq
);
3023 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
3024 radeon_ring_write(ring
, PACKET0(CP_INT_STATUS
, 0));
3025 radeon_ring_write(ring
, RB_INT_STAT
);
3029 void r600_uvd_fence_emit(struct radeon_device
*rdev
,
3030 struct radeon_fence
*fence
)
3032 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
3033 uint64_t addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
3035 radeon_ring_write(ring
, PACKET0(UVD_CONTEXT_ID
, 0));
3036 radeon_ring_write(ring
, fence
->seq
);
3037 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA0
, 0));
3038 radeon_ring_write(ring
, addr
& 0xffffffff);
3039 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA1
, 0));
3040 radeon_ring_write(ring
, upper_32_bits(addr
) & 0xff);
3041 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_CMD
, 0));
3042 radeon_ring_write(ring
, 0);
3044 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA0
, 0));
3045 radeon_ring_write(ring
, 0);
3046 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA1
, 0));
3047 radeon_ring_write(ring
, 0);
3048 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_CMD
, 0));
3049 radeon_ring_write(ring
, 2);
3053 void r600_semaphore_ring_emit(struct radeon_device
*rdev
,
3054 struct radeon_ring
*ring
,
3055 struct radeon_semaphore
*semaphore
,
3058 uint64_t addr
= semaphore
->gpu_addr
;
3059 unsigned sel
= emit_wait
? PACKET3_SEM_SEL_WAIT
: PACKET3_SEM_SEL_SIGNAL
;
3061 if (rdev
->family
< CHIP_CAYMAN
)
3062 sel
|= PACKET3_SEM_WAIT_ON_SIGNAL
;
3064 radeon_ring_write(ring
, PACKET3(PACKET3_MEM_SEMAPHORE
, 1));
3065 radeon_ring_write(ring
, addr
& 0xffffffff);
3066 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff) | sel
);
3070 * DMA fences/semaphores
3074 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
3076 * @rdev: radeon_device pointer
3077 * @fence: radeon fence object
3079 * Add a DMA fence packet to the ring to write
3080 * the fence seq number and DMA trap packet to generate
3081 * an interrupt if needed (r6xx-r7xx).
3083 void r600_dma_fence_ring_emit(struct radeon_device
*rdev
,
3084 struct radeon_fence
*fence
)
3086 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
3087 u64 addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
3089 /* write the fence */
3090 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_FENCE
, 0, 0, 0));
3091 radeon_ring_write(ring
, addr
& 0xfffffffc);
3092 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff));
3093 radeon_ring_write(ring
, lower_32_bits(fence
->seq
));
3094 /* generate an interrupt */
3095 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_TRAP
, 0, 0, 0));
3099 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
3101 * @rdev: radeon_device pointer
3102 * @ring: radeon_ring structure holding ring information
3103 * @semaphore: radeon semaphore object
3104 * @emit_wait: wait or signal semaphore
3106 * Add a DMA semaphore packet to the ring wait on or signal
3107 * other rings (r6xx-SI).
3109 void r600_dma_semaphore_ring_emit(struct radeon_device
*rdev
,
3110 struct radeon_ring
*ring
,
3111 struct radeon_semaphore
*semaphore
,
3114 u64 addr
= semaphore
->gpu_addr
;
3115 u32 s
= emit_wait
? 0 : 1;
3117 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_SEMAPHORE
, 0, s
, 0));
3118 radeon_ring_write(ring
, addr
& 0xfffffffc);
3119 radeon_ring_write(ring
, upper_32_bits(addr
) & 0xff);
3122 void r600_uvd_semaphore_emit(struct radeon_device
*rdev
,
3123 struct radeon_ring
*ring
,
3124 struct radeon_semaphore
*semaphore
,
3127 uint64_t addr
= semaphore
->gpu_addr
;
3129 radeon_ring_write(ring
, PACKET0(UVD_SEMA_ADDR_LOW
, 0));
3130 radeon_ring_write(ring
, (addr
>> 3) & 0x000FFFFF);
3132 radeon_ring_write(ring
, PACKET0(UVD_SEMA_ADDR_HIGH
, 0));
3133 radeon_ring_write(ring
, (addr
>> 23) & 0x000FFFFF);
3135 radeon_ring_write(ring
, PACKET0(UVD_SEMA_CMD
, 0));
3136 radeon_ring_write(ring
, emit_wait
? 1 : 0);
3139 int r600_copy_blit(struct radeon_device
*rdev
,
3140 uint64_t src_offset
,
3141 uint64_t dst_offset
,
3142 unsigned num_gpu_pages
,
3143 struct radeon_fence
**fence
)
3145 struct radeon_semaphore
*sem
= NULL
;
3146 struct radeon_sa_bo
*vb
= NULL
;
3149 r
= r600_blit_prepare_copy(rdev
, num_gpu_pages
, fence
, &vb
, &sem
);
3153 r600_kms_blit_copy(rdev
, src_offset
, dst_offset
, num_gpu_pages
, vb
);
3154 r600_blit_done_copy(rdev
, fence
, vb
, sem
);
3159 * r600_copy_cpdma - copy pages using the CP DMA engine
3161 * @rdev: radeon_device pointer
3162 * @src_offset: src GPU address
3163 * @dst_offset: dst GPU address
3164 * @num_gpu_pages: number of GPU pages to xfer
3165 * @fence: radeon fence object
3167 * Copy GPU paging using the CP DMA engine (r6xx+).
3168 * Used by the radeon ttm implementation to move pages if
3169 * registered as the asic copy callback.
3171 int r600_copy_cpdma(struct radeon_device
*rdev
,
3172 uint64_t src_offset
, uint64_t dst_offset
,
3173 unsigned num_gpu_pages
,
3174 struct radeon_fence
**fence
)
3176 struct radeon_semaphore
*sem
= NULL
;
3177 int ring_index
= rdev
->asic
->copy
.blit_ring_index
;
3178 struct radeon_ring
*ring
= &rdev
->ring
[ring_index
];
3179 u32 size_in_bytes
, cur_size_in_bytes
, tmp
;
3183 r
= radeon_semaphore_create(rdev
, &sem
);
3185 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3189 size_in_bytes
= (num_gpu_pages
<< RADEON_GPU_PAGE_SHIFT
);
3190 num_loops
= DIV_ROUND_UP(size_in_bytes
, 0x1fffff);
3191 r
= radeon_ring_lock(rdev
, ring
, num_loops
* 6 + 24);
3193 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3194 radeon_semaphore_free(rdev
, &sem
, NULL
);
3198 if (radeon_fence_need_sync(*fence
, ring
->idx
)) {
3199 radeon_semaphore_sync_rings(rdev
, sem
, (*fence
)->ring
,
3201 radeon_fence_note_sync(*fence
, ring
->idx
);
3203 radeon_semaphore_free(rdev
, &sem
, NULL
);
3206 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
3207 radeon_ring_write(ring
, (WAIT_UNTIL
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
3208 radeon_ring_write(ring
, WAIT_3D_IDLE_bit
);
3209 for (i
= 0; i
< num_loops
; i
++) {
3210 cur_size_in_bytes
= size_in_bytes
;
3211 if (cur_size_in_bytes
> 0x1fffff)
3212 cur_size_in_bytes
= 0x1fffff;
3213 size_in_bytes
-= cur_size_in_bytes
;
3214 tmp
= upper_32_bits(src_offset
) & 0xff;
3215 if (size_in_bytes
== 0)
3216 tmp
|= PACKET3_CP_DMA_CP_SYNC
;
3217 radeon_ring_write(ring
, PACKET3(PACKET3_CP_DMA
, 4));
3218 radeon_ring_write(ring
, src_offset
& 0xffffffff);
3219 radeon_ring_write(ring
, tmp
);
3220 radeon_ring_write(ring
, dst_offset
& 0xffffffff);
3221 radeon_ring_write(ring
, upper_32_bits(dst_offset
) & 0xff);
3222 radeon_ring_write(ring
, cur_size_in_bytes
);
3223 src_offset
+= cur_size_in_bytes
;
3224 dst_offset
+= cur_size_in_bytes
;
3226 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
3227 radeon_ring_write(ring
, (WAIT_UNTIL
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
3228 radeon_ring_write(ring
, WAIT_CP_DMA_IDLE_bit
);
3230 r
= radeon_fence_emit(rdev
, fence
, ring
->idx
);
3232 radeon_ring_unlock_undo(rdev
, ring
);
3236 radeon_ring_unlock_commit(rdev
, ring
);
3237 radeon_semaphore_free(rdev
, &sem
, *fence
);
3243 * r600_copy_dma - copy pages using the DMA engine
3245 * @rdev: radeon_device pointer
3246 * @src_offset: src GPU address
3247 * @dst_offset: dst GPU address
3248 * @num_gpu_pages: number of GPU pages to xfer
3249 * @fence: radeon fence object
3251 * Copy GPU paging using the DMA engine (r6xx).
3252 * Used by the radeon ttm implementation to move pages if
3253 * registered as the asic copy callback.
3255 int r600_copy_dma(struct radeon_device
*rdev
,
3256 uint64_t src_offset
, uint64_t dst_offset
,
3257 unsigned num_gpu_pages
,
3258 struct radeon_fence
**fence
)
3260 struct radeon_semaphore
*sem
= NULL
;
3261 int ring_index
= rdev
->asic
->copy
.dma_ring_index
;
3262 struct radeon_ring
*ring
= &rdev
->ring
[ring_index
];
3263 u32 size_in_dw
, cur_size_in_dw
;
3267 r
= radeon_semaphore_create(rdev
, &sem
);
3269 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3273 size_in_dw
= (num_gpu_pages
<< RADEON_GPU_PAGE_SHIFT
) / 4;
3274 num_loops
= DIV_ROUND_UP(size_in_dw
, 0xFFFE);
3275 r
= radeon_ring_lock(rdev
, ring
, num_loops
* 4 + 8);
3277 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3278 radeon_semaphore_free(rdev
, &sem
, NULL
);
3282 if (radeon_fence_need_sync(*fence
, ring
->idx
)) {
3283 radeon_semaphore_sync_rings(rdev
, sem
, (*fence
)->ring
,
3285 radeon_fence_note_sync(*fence
, ring
->idx
);
3287 radeon_semaphore_free(rdev
, &sem
, NULL
);
3290 for (i
= 0; i
< num_loops
; i
++) {
3291 cur_size_in_dw
= size_in_dw
;
3292 if (cur_size_in_dw
> 0xFFFE)
3293 cur_size_in_dw
= 0xFFFE;
3294 size_in_dw
-= cur_size_in_dw
;
3295 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_COPY
, 0, 0, cur_size_in_dw
));
3296 radeon_ring_write(ring
, dst_offset
& 0xfffffffc);
3297 radeon_ring_write(ring
, src_offset
& 0xfffffffc);
3298 radeon_ring_write(ring
, (((upper_32_bits(dst_offset
) & 0xff) << 16) |
3299 (upper_32_bits(src_offset
) & 0xff)));
3300 src_offset
+= cur_size_in_dw
* 4;
3301 dst_offset
+= cur_size_in_dw
* 4;
3304 r
= radeon_fence_emit(rdev
, fence
, ring
->idx
);
3306 radeon_ring_unlock_undo(rdev
, ring
);
3310 radeon_ring_unlock_commit(rdev
, ring
);
3311 radeon_semaphore_free(rdev
, &sem
, *fence
);
3316 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
3317 uint32_t tiling_flags
, uint32_t pitch
,
3318 uint32_t offset
, uint32_t obj_size
)
3320 /* FIXME: implement */
3324 void r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
3326 /* FIXME: implement */
3329 static int r600_startup(struct radeon_device
*rdev
)
3331 struct radeon_ring
*ring
;
3334 /* enable pcie gen2 link */
3335 r600_pcie_gen2_enable(rdev
);
3337 r600_mc_program(rdev
);
3339 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
3340 r
= r600_init_microcode(rdev
);
3342 DRM_ERROR("Failed to load firmware!\n");
3347 r
= r600_vram_scratch_init(rdev
);
3351 if (rdev
->flags
& RADEON_IS_AGP
) {
3352 r600_agp_enable(rdev
);
3354 r
= r600_pcie_gart_enable(rdev
);
3358 r600_gpu_init(rdev
);
3359 r
= r600_blit_init(rdev
);
3361 r600_blit_fini(rdev
);
3362 rdev
->asic
->copy
.copy
= NULL
;
3363 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
3366 /* allocate wb buffer */
3367 r
= radeon_wb_init(rdev
);
3371 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3373 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
3377 r
= radeon_fence_driver_start_ring(rdev
, R600_RING_TYPE_DMA_INDEX
);
3379 dev_err(rdev
->dev
, "failed initializing DMA fences (%d).\n", r
);
3384 if (!rdev
->irq
.installed
) {
3385 r
= radeon_irq_kms_init(rdev
);
3390 r
= r600_irq_init(rdev
);
3392 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
3393 radeon_irq_kms_fini(rdev
);
3398 ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
3399 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
3400 R600_CP_RB_RPTR
, R600_CP_RB_WPTR
,
3401 0, 0xfffff, RADEON_CP_PACKET2
);
3405 ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
3406 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, R600_WB_DMA_RPTR_OFFSET
,
3407 DMA_RB_RPTR
, DMA_RB_WPTR
,
3408 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0));
3412 r
= r600_cp_load_microcode(rdev
);
3415 r
= r600_cp_resume(rdev
);
3419 r
= r600_dma_resume(rdev
);
3423 r
= radeon_ib_pool_init(rdev
);
3425 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
3429 r
= r600_audio_init(rdev
);
3431 DRM_ERROR("radeon: audio init failed\n");
3438 void r600_vga_set_state(struct radeon_device
*rdev
, bool state
)
3442 temp
= RREG32(CONFIG_CNTL
);
3443 if (state
== false) {
3449 WREG32(CONFIG_CNTL
, temp
);
3452 int r600_resume(struct radeon_device
*rdev
)
3456 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3457 * posting will perform necessary task to bring back GPU into good
3461 atom_asic_init(rdev
->mode_info
.atom_context
);
3463 rdev
->accel_working
= true;
3464 r
= r600_startup(rdev
);
3466 DRM_ERROR("r600 startup failed on resume\n");
3467 rdev
->accel_working
= false;
3474 int r600_suspend(struct radeon_device
*rdev
)
3476 r600_audio_fini(rdev
);
3478 r600_dma_stop(rdev
);
3479 r600_irq_suspend(rdev
);
3480 radeon_wb_disable(rdev
);
3481 r600_pcie_gart_disable(rdev
);
3486 /* Plan is to move initialization in that function and use
3487 * helper function so that radeon_device_init pretty much
3488 * do nothing more than calling asic specific function. This
3489 * should also allow to remove a bunch of callback function
3492 int r600_init(struct radeon_device
*rdev
)
3496 if (r600_debugfs_mc_info_init(rdev
)) {
3497 DRM_ERROR("Failed to register debugfs file for mc !\n");
3500 if (!radeon_get_bios(rdev
)) {
3501 if (ASIC_IS_AVIVO(rdev
))
3504 /* Must be an ATOMBIOS */
3505 if (!rdev
->is_atom_bios
) {
3506 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
3509 r
= radeon_atombios_init(rdev
);
3512 /* Post card if necessary */
3513 if (!radeon_card_posted(rdev
)) {
3515 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
3518 DRM_INFO("GPU not posted. posting now...\n");
3519 atom_asic_init(rdev
->mode_info
.atom_context
);
3521 /* Initialize scratch registers */
3522 r600_scratch_init(rdev
);
3523 /* Initialize surface registers */
3524 radeon_surface_init(rdev
);
3525 /* Initialize clocks */
3526 radeon_get_clock_info(rdev
->ddev
);
3528 r
= radeon_fence_driver_init(rdev
);
3531 if (rdev
->flags
& RADEON_IS_AGP
) {
3532 r
= radeon_agp_init(rdev
);
3534 radeon_agp_disable(rdev
);
3536 r
= r600_mc_init(rdev
);
3539 /* Memory manager */
3540 r
= radeon_bo_init(rdev
);
3544 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ring_obj
= NULL
;
3545 r600_ring_init(rdev
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
], 1024 * 1024);
3547 rdev
->ring
[R600_RING_TYPE_DMA_INDEX
].ring_obj
= NULL
;
3548 r600_ring_init(rdev
, &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
], 64 * 1024);
3550 rdev
->ih
.ring_obj
= NULL
;
3551 r600_ih_ring_init(rdev
, 64 * 1024);
3553 r
= r600_pcie_gart_init(rdev
);
3557 rdev
->accel_working
= true;
3558 r
= r600_startup(rdev
);
3560 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
3562 r600_dma_fini(rdev
);
3563 r600_irq_fini(rdev
);
3564 radeon_wb_fini(rdev
);
3565 radeon_ib_pool_fini(rdev
);
3566 radeon_irq_kms_fini(rdev
);
3567 r600_pcie_gart_fini(rdev
);
3568 rdev
->accel_working
= false;
3574 void r600_fini(struct radeon_device
*rdev
)
3576 r600_audio_fini(rdev
);
3577 r600_blit_fini(rdev
);
3579 r600_dma_fini(rdev
);
3580 r600_irq_fini(rdev
);
3581 radeon_wb_fini(rdev
);
3582 radeon_ib_pool_fini(rdev
);
3583 radeon_irq_kms_fini(rdev
);
3584 r600_pcie_gart_fini(rdev
);
3585 r600_vram_scratch_fini(rdev
);
3586 radeon_agp_fini(rdev
);
3587 radeon_gem_fini(rdev
);
3588 radeon_fence_driver_fini(rdev
);
3589 radeon_bo_fini(rdev
);
3590 radeon_atombios_fini(rdev
);
3599 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3601 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
3604 if (ring
->rptr_save_reg
) {
3605 next_rptr
= ring
->wptr
+ 3 + 4;
3606 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
3607 radeon_ring_write(ring
, ((ring
->rptr_save_reg
-
3608 PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
3609 radeon_ring_write(ring
, next_rptr
);
3610 } else if (rdev
->wb
.enabled
) {
3611 next_rptr
= ring
->wptr
+ 5 + 4;
3612 radeon_ring_write(ring
, PACKET3(PACKET3_MEM_WRITE
, 3));
3613 radeon_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
3614 radeon_ring_write(ring
, (upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xff) | (1 << 18));
3615 radeon_ring_write(ring
, next_rptr
);
3616 radeon_ring_write(ring
, 0);
3619 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
3620 radeon_ring_write(ring
,
3624 (ib
->gpu_addr
& 0xFFFFFFFC));
3625 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
3626 radeon_ring_write(ring
, ib
->length_dw
);
3629 void r600_uvd_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3631 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
3633 radeon_ring_write(ring
, PACKET0(UVD_RBC_IB_BASE
, 0));
3634 radeon_ring_write(ring
, ib
->gpu_addr
);
3635 radeon_ring_write(ring
, PACKET0(UVD_RBC_IB_SIZE
, 0));
3636 radeon_ring_write(ring
, ib
->length_dw
);
3639 int r600_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
3641 struct radeon_ib ib
;
3647 r
= radeon_scratch_get(rdev
, &scratch
);
3649 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
3652 WREG32(scratch
, 0xCAFEDEAD);
3653 r
= radeon_ib_get(rdev
, ring
->idx
, &ib
, NULL
, 256);
3655 DRM_ERROR("radeon: failed to get ib (%d).\n", r
);
3658 ib
.ptr
[0] = PACKET3(PACKET3_SET_CONFIG_REG
, 1);
3659 ib
.ptr
[1] = ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
3660 ib
.ptr
[2] = 0xDEADBEEF;
3662 r
= radeon_ib_schedule(rdev
, &ib
, NULL
);
3664 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r
);
3667 r
= radeon_fence_wait(ib
.fence
, false);
3669 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
3672 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3673 tmp
= RREG32(scratch
);
3674 if (tmp
== 0xDEADBEEF)
3678 if (i
< rdev
->usec_timeout
) {
3679 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib
.fence
->ring
, i
);
3681 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3686 radeon_ib_free(rdev
, &ib
);
3688 radeon_scratch_free(rdev
, scratch
);
3693 * r600_dma_ib_test - test an IB on the DMA engine
3695 * @rdev: radeon_device pointer
3696 * @ring: radeon_ring structure holding ring information
3698 * Test a simple IB in the DMA ring (r6xx-SI).
3699 * Returns 0 on success, error on failure.
3701 int r600_dma_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
3703 struct radeon_ib ib
;
3706 void __iomem
*ptr
= (void *)rdev
->vram_scratch
.ptr
;
3710 DRM_ERROR("invalid vram scratch pointer\n");
3717 r
= radeon_ib_get(rdev
, ring
->idx
, &ib
, NULL
, 256);
3719 DRM_ERROR("radeon: failed to get ib (%d).\n", r
);
3723 ib
.ptr
[0] = DMA_PACKET(DMA_PACKET_WRITE
, 0, 0, 1);
3724 ib
.ptr
[1] = rdev
->vram_scratch
.gpu_addr
& 0xfffffffc;
3725 ib
.ptr
[2] = upper_32_bits(rdev
->vram_scratch
.gpu_addr
) & 0xff;
3726 ib
.ptr
[3] = 0xDEADBEEF;
3729 r
= radeon_ib_schedule(rdev
, &ib
, NULL
);
3731 radeon_ib_free(rdev
, &ib
);
3732 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r
);
3735 r
= radeon_fence_wait(ib
.fence
, false);
3737 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
3740 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3742 if (tmp
== 0xDEADBEEF)
3746 if (i
< rdev
->usec_timeout
) {
3747 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib
.fence
->ring
, i
);
3749 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp
);
3752 radeon_ib_free(rdev
, &ib
);
3756 int r600_uvd_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
3758 struct radeon_fence
*fence
= NULL
;
3761 r
= radeon_set_uvd_clocks(rdev
, 53300, 40000);
3763 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r
);
3767 r
= radeon_uvd_get_create_msg(rdev
, ring
->idx
, 1, NULL
);
3769 DRM_ERROR("radeon: failed to get create msg (%d).\n", r
);
3773 r
= radeon_uvd_get_destroy_msg(rdev
, ring
->idx
, 1, &fence
);
3775 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r
);
3779 r
= radeon_fence_wait(fence
, false);
3781 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
3784 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
3786 radeon_fence_unref(&fence
);
3787 radeon_set_uvd_clocks(rdev
, 0, 0);
3792 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3794 * @rdev: radeon_device pointer
3795 * @ib: IB object to schedule
3797 * Schedule an IB in the DMA ring (r6xx-r7xx).
3799 void r600_dma_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3801 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
3803 if (rdev
->wb
.enabled
) {
3804 u32 next_rptr
= ring
->wptr
+ 4;
3805 while ((next_rptr
& 7) != 5)
3808 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_WRITE
, 0, 0, 1));
3809 radeon_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
3810 radeon_ring_write(ring
, upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xff);
3811 radeon_ring_write(ring
, next_rptr
);
3814 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3815 * Pad as necessary with NOPs.
3817 while ((ring
->wptr
& 7) != 5)
3818 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0));
3819 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER
, 0, 0, 0));
3820 radeon_ring_write(ring
, (ib
->gpu_addr
& 0xFFFFFFE0));
3821 radeon_ring_write(ring
, (ib
->length_dw
<< 16) | (upper_32_bits(ib
->gpu_addr
) & 0xFF));
3828 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3829 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3830 * writing to the ring and the GPU consuming, the GPU writes to the ring
3831 * and host consumes. As the host irq handler processes interrupts, it
3832 * increments the rptr. When the rptr catches up with the wptr, all the
3833 * current interrupts have been processed.
3836 void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
)
3840 /* Align ring size */
3841 rb_bufsz
= drm_order(ring_size
/ 4);
3842 ring_size
= (1 << rb_bufsz
) * 4;
3843 rdev
->ih
.ring_size
= ring_size
;
3844 rdev
->ih
.ptr_mask
= rdev
->ih
.ring_size
- 1;
3848 int r600_ih_ring_alloc(struct radeon_device
*rdev
)
3852 /* Allocate ring buffer */
3853 if (rdev
->ih
.ring_obj
== NULL
) {
3854 r
= radeon_bo_create(rdev
, rdev
->ih
.ring_size
,
3856 RADEON_GEM_DOMAIN_GTT
,
3857 NULL
, &rdev
->ih
.ring_obj
);
3859 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r
);
3862 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
3863 if (unlikely(r
!= 0))
3865 r
= radeon_bo_pin(rdev
->ih
.ring_obj
,
3866 RADEON_GEM_DOMAIN_GTT
,
3867 &rdev
->ih
.gpu_addr
);
3869 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
3870 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r
);
3873 r
= radeon_bo_kmap(rdev
->ih
.ring_obj
,
3874 (void **)&rdev
->ih
.ring
);
3875 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
3877 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r
);
3884 void r600_ih_ring_fini(struct radeon_device
*rdev
)
3887 if (rdev
->ih
.ring_obj
) {
3888 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
3889 if (likely(r
== 0)) {
3890 radeon_bo_kunmap(rdev
->ih
.ring_obj
);
3891 radeon_bo_unpin(rdev
->ih
.ring_obj
);
3892 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
3894 radeon_bo_unref(&rdev
->ih
.ring_obj
);
3895 rdev
->ih
.ring
= NULL
;
3896 rdev
->ih
.ring_obj
= NULL
;
3900 void r600_rlc_stop(struct radeon_device
*rdev
)
3903 if ((rdev
->family
>= CHIP_RV770
) &&
3904 (rdev
->family
<= CHIP_RV740
)) {
3905 /* r7xx asics need to soft reset RLC before halting */
3906 WREG32(SRBM_SOFT_RESET
, SOFT_RESET_RLC
);
3907 RREG32(SRBM_SOFT_RESET
);
3909 WREG32(SRBM_SOFT_RESET
, 0);
3910 RREG32(SRBM_SOFT_RESET
);
3913 WREG32(RLC_CNTL
, 0);
3916 static void r600_rlc_start(struct radeon_device
*rdev
)
3918 WREG32(RLC_CNTL
, RLC_ENABLE
);
3921 static int r600_rlc_resume(struct radeon_device
*rdev
)
3924 const __be32
*fw_data
;
3929 r600_rlc_stop(rdev
);
3931 WREG32(RLC_HB_CNTL
, 0);
3933 WREG32(RLC_HB_BASE
, 0);
3934 WREG32(RLC_HB_RPTR
, 0);
3935 WREG32(RLC_HB_WPTR
, 0);
3936 WREG32(RLC_HB_WPTR_LSB_ADDR
, 0);
3937 WREG32(RLC_HB_WPTR_MSB_ADDR
, 0);
3938 WREG32(RLC_MC_CNTL
, 0);
3939 WREG32(RLC_UCODE_CNTL
, 0);
3941 fw_data
= (const __be32
*)rdev
->rlc_fw
->data
;
3942 if (rdev
->family
>= CHIP_RV770
) {
3943 for (i
= 0; i
< R700_RLC_UCODE_SIZE
; i
++) {
3944 WREG32(RLC_UCODE_ADDR
, i
);
3945 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
3948 for (i
= 0; i
< R600_RLC_UCODE_SIZE
; i
++) {
3949 WREG32(RLC_UCODE_ADDR
, i
);
3950 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
3953 WREG32(RLC_UCODE_ADDR
, 0);
3955 r600_rlc_start(rdev
);
3960 static void r600_enable_interrupts(struct radeon_device
*rdev
)
3962 u32 ih_cntl
= RREG32(IH_CNTL
);
3963 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
3965 ih_cntl
|= ENABLE_INTR
;
3966 ih_rb_cntl
|= IH_RB_ENABLE
;
3967 WREG32(IH_CNTL
, ih_cntl
);
3968 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
3969 rdev
->ih
.enabled
= true;
3972 void r600_disable_interrupts(struct radeon_device
*rdev
)
3974 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
3975 u32 ih_cntl
= RREG32(IH_CNTL
);
3977 ih_rb_cntl
&= ~IH_RB_ENABLE
;
3978 ih_cntl
&= ~ENABLE_INTR
;
3979 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
3980 WREG32(IH_CNTL
, ih_cntl
);
3981 /* set rptr, wptr to 0 */
3982 WREG32(IH_RB_RPTR
, 0);
3983 WREG32(IH_RB_WPTR
, 0);
3984 rdev
->ih
.enabled
= false;
3988 static void r600_disable_interrupt_state(struct radeon_device
*rdev
)
3992 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
3993 tmp
= RREG32(DMA_CNTL
) & ~TRAP_ENABLE
;
3994 WREG32(DMA_CNTL
, tmp
);
3995 WREG32(GRBM_INT_CNTL
, 0);
3996 WREG32(DxMODE_INT_MASK
, 0);
3997 WREG32(D1GRPH_INTERRUPT_CONTROL
, 0);
3998 WREG32(D2GRPH_INTERRUPT_CONTROL
, 0);
3999 if (ASIC_IS_DCE3(rdev
)) {
4000 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL
, 0);
4001 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL
, 0);
4002 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
4003 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
4004 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
4005 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
4006 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
4007 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
4008 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
4009 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
4010 if (ASIC_IS_DCE32(rdev
)) {
4011 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
4012 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
4013 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
4014 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
4015 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4016 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
, tmp
);
4017 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4018 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
, tmp
);
4020 tmp
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4021 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, tmp
);
4022 tmp
= RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4023 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
4026 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
4027 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
4028 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
4029 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
4030 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
4031 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
4032 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
4033 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
4034 tmp
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4035 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, tmp
);
4036 tmp
= RREG32(HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4037 WREG32(HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
4041 int r600_irq_init(struct radeon_device
*rdev
)
4045 u32 interrupt_cntl
, ih_cntl
, ih_rb_cntl
;
4048 ret
= r600_ih_ring_alloc(rdev
);
4053 r600_disable_interrupts(rdev
);
4056 if (rdev
->family
>= CHIP_CEDAR
)
4057 ret
= evergreen_rlc_resume(rdev
);
4059 ret
= r600_rlc_resume(rdev
);
4061 r600_ih_ring_fini(rdev
);
4065 /* setup interrupt control */
4066 /* set dummy read address to ring address */
4067 WREG32(INTERRUPT_CNTL2
, rdev
->ih
.gpu_addr
>> 8);
4068 interrupt_cntl
= RREG32(INTERRUPT_CNTL
);
4069 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
4070 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
4072 interrupt_cntl
&= ~IH_DUMMY_RD_OVERRIDE
;
4073 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
4074 interrupt_cntl
&= ~IH_REQ_NONSNOOP_EN
;
4075 WREG32(INTERRUPT_CNTL
, interrupt_cntl
);
4077 WREG32(IH_RB_BASE
, rdev
->ih
.gpu_addr
>> 8);
4078 rb_bufsz
= drm_order(rdev
->ih
.ring_size
/ 4);
4080 ih_rb_cntl
= (IH_WPTR_OVERFLOW_ENABLE
|
4081 IH_WPTR_OVERFLOW_CLEAR
|
4084 if (rdev
->wb
.enabled
)
4085 ih_rb_cntl
|= IH_WPTR_WRITEBACK_ENABLE
;
4087 /* set the writeback address whether it's enabled or not */
4088 WREG32(IH_RB_WPTR_ADDR_LO
, (rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFFFFFFFC);
4089 WREG32(IH_RB_WPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFF);
4091 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
4093 /* set rptr, wptr to 0 */
4094 WREG32(IH_RB_RPTR
, 0);
4095 WREG32(IH_RB_WPTR
, 0);
4097 /* Default settings for IH_CNTL (disabled at first) */
4098 ih_cntl
= MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
4099 /* RPTR_REARM only works if msi's are enabled */
4100 if (rdev
->msi_enabled
)
4101 ih_cntl
|= RPTR_REARM
;
4102 WREG32(IH_CNTL
, ih_cntl
);
4104 /* force the active interrupt state to all disabled */
4105 if (rdev
->family
>= CHIP_CEDAR
)
4106 evergreen_disable_interrupt_state(rdev
);
4108 r600_disable_interrupt_state(rdev
);
4110 /* at this point everything should be setup correctly to enable master */
4111 pci_set_master(rdev
->pdev
);
4114 r600_enable_interrupts(rdev
);
4119 void r600_irq_suspend(struct radeon_device
*rdev
)
4121 r600_irq_disable(rdev
);
4122 r600_rlc_stop(rdev
);
4125 void r600_irq_fini(struct radeon_device
*rdev
)
4127 r600_irq_suspend(rdev
);
4128 r600_ih_ring_fini(rdev
);
4131 int r600_irq_set(struct radeon_device
*rdev
)
4133 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
4135 u32 hpd1
, hpd2
, hpd3
, hpd4
= 0, hpd5
= 0, hpd6
= 0;
4136 u32 grbm_int_cntl
= 0;
4138 u32 d1grph
= 0, d2grph
= 0;
4140 u32 thermal_int
= 0;
4142 if (!rdev
->irq
.installed
) {
4143 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
4146 /* don't enable anything if the ih is disabled */
4147 if (!rdev
->ih
.enabled
) {
4148 r600_disable_interrupts(rdev
);
4149 /* force the active interrupt state to all disabled */
4150 r600_disable_interrupt_state(rdev
);
4154 if (ASIC_IS_DCE3(rdev
)) {
4155 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4156 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4157 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4158 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4159 if (ASIC_IS_DCE32(rdev
)) {
4160 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4161 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4162 hdmi0
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
4163 hdmi1
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
4165 hdmi0
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4166 hdmi1
= RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4169 hpd1
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4170 hpd2
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4171 hpd3
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4172 hdmi0
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4173 hdmi1
= RREG32(HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4176 dma_cntl
= RREG32(DMA_CNTL
) & ~TRAP_ENABLE
;
4178 if ((rdev
->family
> CHIP_R600
) && (rdev
->family
< CHIP_RV770
)) {
4179 thermal_int
= RREG32(CG_THERMAL_INT
) &
4180 ~(THERM_INT_MASK_HIGH
| THERM_INT_MASK_LOW
);
4181 } else if (rdev
->family
>= CHIP_RV770
) {
4182 thermal_int
= RREG32(RV770_CG_THERMAL_INT
) &
4183 ~(THERM_INT_MASK_HIGH
| THERM_INT_MASK_LOW
);
4185 if (rdev
->irq
.dpm_thermal
) {
4186 DRM_DEBUG("dpm thermal\n");
4187 thermal_int
|= THERM_INT_MASK_HIGH
| THERM_INT_MASK_LOW
;
4190 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
4191 DRM_DEBUG("r600_irq_set: sw int\n");
4192 cp_int_cntl
|= RB_INT_ENABLE
;
4193 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
4196 if (atomic_read(&rdev
->irq
.ring_int
[R600_RING_TYPE_DMA_INDEX
])) {
4197 DRM_DEBUG("r600_irq_set: sw int dma\n");
4198 dma_cntl
|= TRAP_ENABLE
;
4201 if (rdev
->irq
.crtc_vblank_int
[0] ||
4202 atomic_read(&rdev
->irq
.pflip
[0])) {
4203 DRM_DEBUG("r600_irq_set: vblank 0\n");
4204 mode_int
|= D1MODE_VBLANK_INT_MASK
;
4206 if (rdev
->irq
.crtc_vblank_int
[1] ||
4207 atomic_read(&rdev
->irq
.pflip
[1])) {
4208 DRM_DEBUG("r600_irq_set: vblank 1\n");
4209 mode_int
|= D2MODE_VBLANK_INT_MASK
;
4211 if (rdev
->irq
.hpd
[0]) {
4212 DRM_DEBUG("r600_irq_set: hpd 1\n");
4213 hpd1
|= DC_HPDx_INT_EN
;
4215 if (rdev
->irq
.hpd
[1]) {
4216 DRM_DEBUG("r600_irq_set: hpd 2\n");
4217 hpd2
|= DC_HPDx_INT_EN
;
4219 if (rdev
->irq
.hpd
[2]) {
4220 DRM_DEBUG("r600_irq_set: hpd 3\n");
4221 hpd3
|= DC_HPDx_INT_EN
;
4223 if (rdev
->irq
.hpd
[3]) {
4224 DRM_DEBUG("r600_irq_set: hpd 4\n");
4225 hpd4
|= DC_HPDx_INT_EN
;
4227 if (rdev
->irq
.hpd
[4]) {
4228 DRM_DEBUG("r600_irq_set: hpd 5\n");
4229 hpd5
|= DC_HPDx_INT_EN
;
4231 if (rdev
->irq
.hpd
[5]) {
4232 DRM_DEBUG("r600_irq_set: hpd 6\n");
4233 hpd6
|= DC_HPDx_INT_EN
;
4235 if (rdev
->irq
.afmt
[0]) {
4236 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4237 hdmi0
|= HDMI0_AZ_FORMAT_WTRIG_MASK
;
4239 if (rdev
->irq
.afmt
[1]) {
4240 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4241 hdmi1
|= HDMI0_AZ_FORMAT_WTRIG_MASK
;
4244 WREG32(CP_INT_CNTL
, cp_int_cntl
);
4245 WREG32(DMA_CNTL
, dma_cntl
);
4246 WREG32(DxMODE_INT_MASK
, mode_int
);
4247 WREG32(D1GRPH_INTERRUPT_CONTROL
, d1grph
);
4248 WREG32(D2GRPH_INTERRUPT_CONTROL
, d2grph
);
4249 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
4250 if (ASIC_IS_DCE3(rdev
)) {
4251 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
4252 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
4253 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
4254 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
4255 if (ASIC_IS_DCE32(rdev
)) {
4256 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
4257 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
4258 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
, hdmi0
);
4259 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
, hdmi1
);
4261 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, hdmi0
);
4262 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
, hdmi1
);
4265 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, hpd1
);
4266 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, hpd2
);
4267 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, hpd3
);
4268 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, hdmi0
);
4269 WREG32(HDMI1_AUDIO_PACKET_CONTROL
, hdmi1
);
4271 if ((rdev
->family
> CHIP_R600
) && (rdev
->family
< CHIP_RV770
)) {
4272 WREG32(CG_THERMAL_INT
, thermal_int
);
4273 } else if (rdev
->family
>= CHIP_RV770
) {
4274 WREG32(RV770_CG_THERMAL_INT
, thermal_int
);
4280 static void r600_irq_ack(struct radeon_device
*rdev
)
4284 if (ASIC_IS_DCE3(rdev
)) {
4285 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DCE3_DISP_INTERRUPT_STATUS
);
4286 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE
);
4287 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2
);
4288 if (ASIC_IS_DCE32(rdev
)) {
4289 rdev
->irq
.stat_regs
.r600
.hdmi0_status
= RREG32(AFMT_STATUS
+ DCE3_HDMI_OFFSET0
);
4290 rdev
->irq
.stat_regs
.r600
.hdmi1_status
= RREG32(AFMT_STATUS
+ DCE3_HDMI_OFFSET1
);
4292 rdev
->irq
.stat_regs
.r600
.hdmi0_status
= RREG32(HDMI0_STATUS
);
4293 rdev
->irq
.stat_regs
.r600
.hdmi1_status
= RREG32(DCE3_HDMI1_STATUS
);
4296 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
4297 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
4298 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= 0;
4299 rdev
->irq
.stat_regs
.r600
.hdmi0_status
= RREG32(HDMI0_STATUS
);
4300 rdev
->irq
.stat_regs
.r600
.hdmi1_status
= RREG32(HDMI1_STATUS
);
4302 rdev
->irq
.stat_regs
.r600
.d1grph_int
= RREG32(D1GRPH_INTERRUPT_STATUS
);
4303 rdev
->irq
.stat_regs
.r600
.d2grph_int
= RREG32(D2GRPH_INTERRUPT_STATUS
);
4305 if (rdev
->irq
.stat_regs
.r600
.d1grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
4306 WREG32(D1GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
4307 if (rdev
->irq
.stat_regs
.r600
.d2grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
4308 WREG32(D2GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
4309 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
4310 WREG32(D1MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
4311 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
)
4312 WREG32(D1MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
4313 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
)
4314 WREG32(D2MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
4315 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
)
4316 WREG32(D2MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
4317 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
4318 if (ASIC_IS_DCE3(rdev
)) {
4319 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
4320 tmp
|= DC_HPDx_INT_ACK
;
4321 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
4323 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
4324 tmp
|= DC_HPDx_INT_ACK
;
4325 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
4328 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
4329 if (ASIC_IS_DCE3(rdev
)) {
4330 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
4331 tmp
|= DC_HPDx_INT_ACK
;
4332 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
4334 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
4335 tmp
|= DC_HPDx_INT_ACK
;
4336 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
4339 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
4340 if (ASIC_IS_DCE3(rdev
)) {
4341 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
4342 tmp
|= DC_HPDx_INT_ACK
;
4343 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
4345 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
4346 tmp
|= DC_HPDx_INT_ACK
;
4347 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
4350 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
4351 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
4352 tmp
|= DC_HPDx_INT_ACK
;
4353 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
4355 if (ASIC_IS_DCE32(rdev
)) {
4356 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
4357 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
4358 tmp
|= DC_HPDx_INT_ACK
;
4359 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
4361 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
4362 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
4363 tmp
|= DC_HPDx_INT_ACK
;
4364 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
4366 if (rdev
->irq
.stat_regs
.r600
.hdmi0_status
& AFMT_AZ_FORMAT_WTRIG
) {
4367 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
);
4368 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
4369 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
, tmp
);
4371 if (rdev
->irq
.stat_regs
.r600
.hdmi1_status
& AFMT_AZ_FORMAT_WTRIG
) {
4372 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
);
4373 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
4374 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
, tmp
);
4377 if (rdev
->irq
.stat_regs
.r600
.hdmi0_status
& HDMI0_AZ_FORMAT_WTRIG
) {
4378 tmp
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
);
4379 tmp
|= HDMI0_AZ_FORMAT_WTRIG_ACK
;
4380 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, tmp
);
4382 if (rdev
->irq
.stat_regs
.r600
.hdmi1_status
& HDMI0_AZ_FORMAT_WTRIG
) {
4383 if (ASIC_IS_DCE3(rdev
)) {
4384 tmp
= RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
);
4385 tmp
|= HDMI0_AZ_FORMAT_WTRIG_ACK
;
4386 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
4388 tmp
= RREG32(HDMI1_AUDIO_PACKET_CONTROL
);
4389 tmp
|= HDMI0_AZ_FORMAT_WTRIG_ACK
;
4390 WREG32(HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
4396 void r600_irq_disable(struct radeon_device
*rdev
)
4398 r600_disable_interrupts(rdev
);
4399 /* Wait and acknowledge irq */
4402 r600_disable_interrupt_state(rdev
);
4405 static u32
r600_get_ih_wptr(struct radeon_device
*rdev
)
4409 if (rdev
->wb
.enabled
)
4410 wptr
= le32_to_cpu(rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4]);
4412 wptr
= RREG32(IH_RB_WPTR
);
4414 if (wptr
& RB_OVERFLOW
) {
4415 /* When a ring buffer overflow happen start parsing interrupt
4416 * from the last not overwritten vector (wptr + 16). Hopefully
4417 * this should allow us to catchup.
4419 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
4420 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
4421 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
4422 tmp
= RREG32(IH_RB_CNTL
);
4423 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
4424 WREG32(IH_RB_CNTL
, tmp
);
4426 return (wptr
& rdev
->ih
.ptr_mask
);
4430 * Each IV ring entry is 128 bits:
4431 * [7:0] - interrupt source id
4433 * [59:32] - interrupt source data
4434 * [127:60] - reserved
4436 * The basic interrupt vector entries
4437 * are decoded as follows:
4438 * src_id src_data description
4443 * 19 0 FP Hot plug detection A
4444 * 19 1 FP Hot plug detection B
4445 * 19 2 DAC A auto-detection
4446 * 19 3 DAC B auto-detection
4452 * 181 - EOP Interrupt
4455 * Note, these are based on r600 and may need to be
4456 * adjusted or added to on newer asics
4459 int r600_irq_process(struct radeon_device
*rdev
)
4463 u32 src_id
, src_data
;
4465 bool queue_hotplug
= false;
4466 bool queue_hdmi
= false;
4467 bool queue_thermal
= false;
4469 if (!rdev
->ih
.enabled
|| rdev
->shutdown
)
4472 /* No MSIs, need a dummy read to flush PCI DMAs */
4473 if (!rdev
->msi_enabled
)
4476 wptr
= r600_get_ih_wptr(rdev
);
4479 /* is somebody else already processing irqs? */
4480 if (atomic_xchg(&rdev
->ih
.lock
, 1))
4483 rptr
= rdev
->ih
.rptr
;
4484 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
4486 /* Order reading of wptr vs. reading of IH ring data */
4489 /* display interrupts */
4492 while (rptr
!= wptr
) {
4493 /* wptr/rptr are in bytes! */
4494 ring_index
= rptr
/ 4;
4495 src_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
]) & 0xff;
4496 src_data
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 1]) & 0xfffffff;
4499 case 1: /* D1 vblank/vline */
4501 case 0: /* D1 vblank */
4502 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
4503 if (rdev
->irq
.crtc_vblank_int
[0]) {
4504 drm_handle_vblank(rdev
->ddev
, 0);
4505 rdev
->pm
.vblank_sync
= true;
4506 wake_up(&rdev
->irq
.vblank_queue
);
4508 if (atomic_read(&rdev
->irq
.pflip
[0]))
4509 radeon_crtc_handle_flip(rdev
, 0);
4510 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
4511 DRM_DEBUG("IH: D1 vblank\n");
4514 case 1: /* D1 vline */
4515 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
4516 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
4517 DRM_DEBUG("IH: D1 vline\n");
4521 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4525 case 5: /* D2 vblank/vline */
4527 case 0: /* D2 vblank */
4528 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
) {
4529 if (rdev
->irq
.crtc_vblank_int
[1]) {
4530 drm_handle_vblank(rdev
->ddev
, 1);
4531 rdev
->pm
.vblank_sync
= true;
4532 wake_up(&rdev
->irq
.vblank_queue
);
4534 if (atomic_read(&rdev
->irq
.pflip
[1]))
4535 radeon_crtc_handle_flip(rdev
, 1);
4536 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VBLANK_INTERRUPT
;
4537 DRM_DEBUG("IH: D2 vblank\n");
4540 case 1: /* D1 vline */
4541 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
) {
4542 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VLINE_INTERRUPT
;
4543 DRM_DEBUG("IH: D2 vline\n");
4547 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4551 case 19: /* HPD/DAC hotplug */
4554 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
4555 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD1_INTERRUPT
;
4556 queue_hotplug
= true;
4557 DRM_DEBUG("IH: HPD1\n");
4561 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
4562 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD2_INTERRUPT
;
4563 queue_hotplug
= true;
4564 DRM_DEBUG("IH: HPD2\n");
4568 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
4569 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD3_INTERRUPT
;
4570 queue_hotplug
= true;
4571 DRM_DEBUG("IH: HPD3\n");
4575 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
4576 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD4_INTERRUPT
;
4577 queue_hotplug
= true;
4578 DRM_DEBUG("IH: HPD4\n");
4582 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
4583 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD5_INTERRUPT
;
4584 queue_hotplug
= true;
4585 DRM_DEBUG("IH: HPD5\n");
4589 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
4590 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD6_INTERRUPT
;
4591 queue_hotplug
= true;
4592 DRM_DEBUG("IH: HPD6\n");
4596 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4603 if (rdev
->irq
.stat_regs
.r600
.hdmi0_status
& HDMI0_AZ_FORMAT_WTRIG
) {
4604 rdev
->irq
.stat_regs
.r600
.hdmi0_status
&= ~HDMI0_AZ_FORMAT_WTRIG
;
4606 DRM_DEBUG("IH: HDMI0\n");
4610 if (rdev
->irq
.stat_regs
.r600
.hdmi1_status
& HDMI0_AZ_FORMAT_WTRIG
) {
4611 rdev
->irq
.stat_regs
.r600
.hdmi1_status
&= ~HDMI0_AZ_FORMAT_WTRIG
;
4613 DRM_DEBUG("IH: HDMI1\n");
4617 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4621 case 176: /* CP_INT in ring buffer */
4622 case 177: /* CP_INT in IB1 */
4623 case 178: /* CP_INT in IB2 */
4624 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
4625 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
4627 case 181: /* CP EOP event */
4628 DRM_DEBUG("IH: CP EOP\n");
4629 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
4631 case 224: /* DMA trap event */
4632 DRM_DEBUG("IH: DMA trap\n");
4633 radeon_fence_process(rdev
, R600_RING_TYPE_DMA_INDEX
);
4635 case 230: /* thermal low to high */
4636 DRM_DEBUG("IH: thermal low to high\n");
4637 rdev
->pm
.dpm
.thermal
.high_to_low
= false;
4638 queue_thermal
= true;
4640 case 231: /* thermal high to low */
4641 DRM_DEBUG("IH: thermal high to low\n");
4642 rdev
->pm
.dpm
.thermal
.high_to_low
= true;
4643 queue_thermal
= true;
4645 case 233: /* GUI IDLE */
4646 DRM_DEBUG("IH: GUI idle\n");
4649 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4653 /* wptr/rptr are in bytes! */
4655 rptr
&= rdev
->ih
.ptr_mask
;
4658 schedule_work(&rdev
->hotplug_work
);
4660 schedule_work(&rdev
->audio_work
);
4661 if (queue_thermal
&& rdev
->pm
.dpm_enabled
)
4662 schedule_work(&rdev
->pm
.dpm
.thermal
.work
);
4663 rdev
->ih
.rptr
= rptr
;
4664 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
4665 atomic_set(&rdev
->ih
.lock
, 0);
4667 /* make sure wptr hasn't changed while processing */
4668 wptr
= r600_get_ih_wptr(rdev
);
4678 #if defined(CONFIG_DEBUG_FS)
4680 static int r600_debugfs_mc_info(struct seq_file
*m
, void *data
)
4682 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
4683 struct drm_device
*dev
= node
->minor
->dev
;
4684 struct radeon_device
*rdev
= dev
->dev_private
;
4686 DREG32_SYS(m
, rdev
, R_000E50_SRBM_STATUS
);
4687 DREG32_SYS(m
, rdev
, VM_L2_STATUS
);
4691 static struct drm_info_list r600_mc_info_list
[] = {
4692 {"r600_mc_info", r600_debugfs_mc_info
, 0, NULL
},
4696 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
)
4698 #if defined(CONFIG_DEBUG_FS)
4699 return radeon_debugfs_add_files(rdev
, r600_mc_info_list
, ARRAY_SIZE(r600_mc_info_list
));
4706 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4707 * rdev: radeon device structure
4708 * bo: buffer object struct which userspace is waiting for idle
4710 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4711 * through ring buffer, this leads to corruption in rendering, see
4712 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4713 * directly perform HDP flush by writing register through MMIO.
4715 void r600_ioctl_wait_idle(struct radeon_device
*rdev
, struct radeon_bo
*bo
)
4717 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
4718 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4719 * This seems to cause problems on some AGP cards. Just use the old
4722 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
4723 rdev
->vram_scratch
.ptr
&& !(rdev
->flags
& RADEON_IS_AGP
)) {
4724 void __iomem
*ptr
= (void *)rdev
->vram_scratch
.ptr
;
4727 WREG32(HDP_DEBUG1
, 0);
4728 tmp
= readl((void __iomem
*)ptr
);
4730 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
4733 void r600_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
)
4735 u32 link_width_cntl
, mask
;
4737 if (rdev
->flags
& RADEON_IS_IGP
)
4740 if (!(rdev
->flags
& RADEON_IS_PCIE
))
4743 /* x2 cards have a special sequence */
4744 if (ASIC_IS_X2(rdev
))
4747 radeon_gui_idle(rdev
);
4751 mask
= RADEON_PCIE_LC_LINK_WIDTH_X0
;
4754 mask
= RADEON_PCIE_LC_LINK_WIDTH_X1
;
4757 mask
= RADEON_PCIE_LC_LINK_WIDTH_X2
;
4760 mask
= RADEON_PCIE_LC_LINK_WIDTH_X4
;
4763 mask
= RADEON_PCIE_LC_LINK_WIDTH_X8
;
4766 /* not actually supported */
4767 mask
= RADEON_PCIE_LC_LINK_WIDTH_X12
;
4770 mask
= RADEON_PCIE_LC_LINK_WIDTH_X16
;
4773 DRM_ERROR("invalid pcie lane request: %d\n", lanes
);
4777 link_width_cntl
= RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
4778 link_width_cntl
&= ~RADEON_PCIE_LC_LINK_WIDTH_MASK
;
4779 link_width_cntl
|= mask
<< RADEON_PCIE_LC_LINK_WIDTH_SHIFT
;
4780 link_width_cntl
|= (RADEON_PCIE_LC_RECONFIG_NOW
|
4781 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE
);
4783 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4786 int r600_get_pcie_lanes(struct radeon_device
*rdev
)
4788 u32 link_width_cntl
;
4790 if (rdev
->flags
& RADEON_IS_IGP
)
4793 if (!(rdev
->flags
& RADEON_IS_PCIE
))
4796 /* x2 cards have a special sequence */
4797 if (ASIC_IS_X2(rdev
))
4800 radeon_gui_idle(rdev
);
4802 link_width_cntl
= RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
4804 switch ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
) {
4805 case RADEON_PCIE_LC_LINK_WIDTH_X1
:
4807 case RADEON_PCIE_LC_LINK_WIDTH_X2
:
4809 case RADEON_PCIE_LC_LINK_WIDTH_X4
:
4811 case RADEON_PCIE_LC_LINK_WIDTH_X8
:
4813 case RADEON_PCIE_LC_LINK_WIDTH_X12
:
4814 /* not actually supported */
4816 case RADEON_PCIE_LC_LINK_WIDTH_X0
:
4817 case RADEON_PCIE_LC_LINK_WIDTH_X16
:
4823 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
)
4825 u32 link_width_cntl
, lanes
, speed_cntl
, training_cntl
, tmp
;
4828 if (radeon_pcie_gen2
== 0)
4831 if (rdev
->flags
& RADEON_IS_IGP
)
4834 if (!(rdev
->flags
& RADEON_IS_PCIE
))
4837 /* x2 cards have a special sequence */
4838 if (ASIC_IS_X2(rdev
))
4841 /* only RV6xx+ chips are supported */
4842 if (rdev
->family
<= CHIP_R600
)
4845 if ((rdev
->pdev
->bus
->max_bus_speed
!= PCIE_SPEED_5_0GT
) &&
4846 (rdev
->pdev
->bus
->max_bus_speed
!= PCIE_SPEED_8_0GT
))
4849 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
4850 if (speed_cntl
& LC_CURRENT_DATA_RATE
) {
4851 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4855 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4857 /* 55 nm r6xx asics */
4858 if ((rdev
->family
== CHIP_RV670
) ||
4859 (rdev
->family
== CHIP_RV620
) ||
4860 (rdev
->family
== CHIP_RV635
)) {
4861 /* advertise upconfig capability */
4862 link_width_cntl
= RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
);
4863 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
4864 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4865 link_width_cntl
= RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
);
4866 if (link_width_cntl
& LC_RENEGOTIATION_SUPPORT
) {
4867 lanes
= (link_width_cntl
& LC_LINK_WIDTH_RD_MASK
) >> LC_LINK_WIDTH_RD_SHIFT
;
4868 link_width_cntl
&= ~(LC_LINK_WIDTH_MASK
|
4869 LC_RECONFIG_ARC_MISSING_ESCAPE
);
4870 link_width_cntl
|= lanes
| LC_RECONFIG_NOW
| LC_RENEGOTIATE_EN
;
4871 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4873 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
4874 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4878 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
4879 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) &&
4880 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
4882 /* 55 nm r6xx asics */
4883 if ((rdev
->family
== CHIP_RV670
) ||
4884 (rdev
->family
== CHIP_RV620
) ||
4885 (rdev
->family
== CHIP_RV635
)) {
4886 WREG32(MM_CFGREGS_CNTL
, 0x8);
4887 link_cntl2
= RREG32(0x4088);
4888 WREG32(MM_CFGREGS_CNTL
, 0);
4889 /* not supported yet */
4890 if (link_cntl2
& SELECTABLE_DEEMPHASIS
)
4894 speed_cntl
&= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
;
4895 speed_cntl
|= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT
);
4896 speed_cntl
&= ~LC_VOLTAGE_TIMER_SEL_MASK
;
4897 speed_cntl
&= ~LC_FORCE_DIS_HW_SPEED_CHANGE
;
4898 speed_cntl
|= LC_FORCE_EN_HW_SPEED_CHANGE
;
4899 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
, speed_cntl
);
4901 tmp
= RREG32(0x541c);
4902 WREG32(0x541c, tmp
| 0x8);
4903 WREG32(MM_CFGREGS_CNTL
, MM_WR_TO_CFG_EN
);
4904 link_cntl2
= RREG16(0x4088);
4905 link_cntl2
&= ~TARGET_LINK_SPEED_MASK
;
4907 WREG16(0x4088, link_cntl2
);
4908 WREG32(MM_CFGREGS_CNTL
, 0);
4910 if ((rdev
->family
== CHIP_RV670
) ||
4911 (rdev
->family
== CHIP_RV620
) ||
4912 (rdev
->family
== CHIP_RV635
)) {
4913 training_cntl
= RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL
);
4914 training_cntl
&= ~LC_POINT_7_PLUS_EN
;
4915 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL
, training_cntl
);
4917 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
4918 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
4919 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
, speed_cntl
);
4922 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
4923 speed_cntl
|= LC_GEN2_EN_STRAP
;
4924 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
, speed_cntl
);
4927 link_width_cntl
= RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
);
4928 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4930 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
4932 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
4933 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4938 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4940 * @rdev: radeon_device pointer
4942 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4943 * Returns the 64 bit clock counter snapshot.
4945 uint64_t r600_get_gpu_clock_counter(struct radeon_device
*rdev
)
4949 mutex_lock(&rdev
->gpu_clock_mutex
);
4950 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT
, 1);
4951 clock
= (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB
) |
4952 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB
) << 32ULL);
4953 mutex_unlock(&rdev
->gpu_clock_mutex
);