2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kernel.h>
32 #include "r600_reg_safe.h"
35 extern void r600_cs_legacy_get_tiling_conf(struct drm_device
*dev
, u32
*npipes
, u32
*nbanks
, u32
*group_size
);
38 struct r600_cs_track
{
39 /* configuration we miror so that we use same code btw kms/ums */
47 u32 cb_color_base_last
[8];
48 struct radeon_bo
*cb_color_bo
[8];
49 u64 cb_color_bo_mc
[8];
50 u64 cb_color_bo_offset
[8];
51 struct radeon_bo
*cb_color_frag_bo
[8];
52 u64 cb_color_frag_offset
[8];
53 struct radeon_bo
*cb_color_tile_bo
[8];
54 u64 cb_color_tile_offset
[8];
58 u32 cb_color_size_idx
[8]; /* unused */
60 u32 cb_shader_mask
; /* unused */
64 u32 vgt_strmout_buffer_en
;
65 struct radeon_bo
*vgt_strmout_bo
[4];
66 u64 vgt_strmout_bo_mc
[4]; /* unused */
67 u32 vgt_strmout_bo_offset
[4];
68 u32 vgt_strmout_size
[4];
71 u32 db_depth_size_idx
;
75 struct radeon_bo
*db_bo
;
77 bool sx_misc_kill_all_prims
;
81 struct radeon_bo
*htile_bo
;
86 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
87 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
88 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
89 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
90 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
91 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
92 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
93 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
100 enum radeon_family min_family
;
103 static const struct gpu_formats color_formats_table
[] = {
105 FMT_8_BIT(V_038004_COLOR_8
, 1),
106 FMT_8_BIT(V_038004_COLOR_4_4
, 1),
107 FMT_8_BIT(V_038004_COLOR_3_3_2
, 1),
108 FMT_8_BIT(V_038004_FMT_1
, 0),
111 FMT_16_BIT(V_038004_COLOR_16
, 1),
112 FMT_16_BIT(V_038004_COLOR_16_FLOAT
, 1),
113 FMT_16_BIT(V_038004_COLOR_8_8
, 1),
114 FMT_16_BIT(V_038004_COLOR_5_6_5
, 1),
115 FMT_16_BIT(V_038004_COLOR_6_5_5
, 1),
116 FMT_16_BIT(V_038004_COLOR_1_5_5_5
, 1),
117 FMT_16_BIT(V_038004_COLOR_4_4_4_4
, 1),
118 FMT_16_BIT(V_038004_COLOR_5_5_5_1
, 1),
121 FMT_24_BIT(V_038004_FMT_8_8_8
),
124 FMT_32_BIT(V_038004_COLOR_32
, 1),
125 FMT_32_BIT(V_038004_COLOR_32_FLOAT
, 1),
126 FMT_32_BIT(V_038004_COLOR_16_16
, 1),
127 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT
, 1),
128 FMT_32_BIT(V_038004_COLOR_8_24
, 1),
129 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT
, 1),
130 FMT_32_BIT(V_038004_COLOR_24_8
, 1),
131 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT
, 1),
132 FMT_32_BIT(V_038004_COLOR_10_11_11
, 1),
133 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT
, 1),
134 FMT_32_BIT(V_038004_COLOR_11_11_10
, 1),
135 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT
, 1),
136 FMT_32_BIT(V_038004_COLOR_2_10_10_10
, 1),
137 FMT_32_BIT(V_038004_COLOR_8_8_8_8
, 1),
138 FMT_32_BIT(V_038004_COLOR_10_10_10_2
, 1),
139 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP
, 0),
140 FMT_32_BIT(V_038004_FMT_32_AS_8
, 0),
141 FMT_32_BIT(V_038004_FMT_32_AS_8_8
, 0),
144 FMT_48_BIT(V_038004_FMT_16_16_16
),
145 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT
),
148 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT
, 1),
149 FMT_64_BIT(V_038004_COLOR_32_32
, 1),
150 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT
, 1),
151 FMT_64_BIT(V_038004_COLOR_16_16_16_16
, 1),
152 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT
, 1),
154 FMT_96_BIT(V_038004_FMT_32_32_32
),
155 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT
),
158 FMT_128_BIT(V_038004_COLOR_32_32_32_32
, 1),
159 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT
, 1),
161 [V_038004_FMT_GB_GR
] = { 2, 1, 4, 0 },
162 [V_038004_FMT_BG_RG
] = { 2, 1, 4, 0 },
164 /* block compressed formats */
165 [V_038004_FMT_BC1
] = { 4, 4, 8, 0 },
166 [V_038004_FMT_BC2
] = { 4, 4, 16, 0 },
167 [V_038004_FMT_BC3
] = { 4, 4, 16, 0 },
168 [V_038004_FMT_BC4
] = { 4, 4, 8, 0 },
169 [V_038004_FMT_BC5
] = { 4, 4, 16, 0},
170 [V_038004_FMT_BC6
] = { 4, 4, 16, 0, CHIP_CEDAR
}, /* Evergreen-only */
171 [V_038004_FMT_BC7
] = { 4, 4, 16, 0, CHIP_CEDAR
}, /* Evergreen-only */
173 /* The other Evergreen formats */
174 [V_038004_FMT_32_AS_32_32_32_32
] = { 1, 1, 4, 0, CHIP_CEDAR
},
177 bool r600_fmt_is_valid_color(u32 format
)
179 if (format
>= ARRAY_SIZE(color_formats_table
))
182 if (color_formats_table
[format
].valid_color
)
188 bool r600_fmt_is_valid_texture(u32 format
, enum radeon_family family
)
190 if (format
>= ARRAY_SIZE(color_formats_table
))
193 if (family
< color_formats_table
[format
].min_family
)
196 if (color_formats_table
[format
].blockwidth
> 0)
202 int r600_fmt_get_blocksize(u32 format
)
204 if (format
>= ARRAY_SIZE(color_formats_table
))
207 return color_formats_table
[format
].blocksize
;
210 int r600_fmt_get_nblocksx(u32 format
, u32 w
)
214 if (format
>= ARRAY_SIZE(color_formats_table
))
217 bw
= color_formats_table
[format
].blockwidth
;
221 return (w
+ bw
- 1) / bw
;
224 int r600_fmt_get_nblocksy(u32 format
, u32 h
)
228 if (format
>= ARRAY_SIZE(color_formats_table
))
231 bh
= color_formats_table
[format
].blockheight
;
235 return (h
+ bh
- 1) / bh
;
238 struct array_mode_checker
{
247 /* returns alignment in pixels for pitch/height/depth and bytes for base */
248 static int r600_get_array_mode_alignment(struct array_mode_checker
*values
,
256 u32 macro_tile_width
= values
->nbanks
;
257 u32 macro_tile_height
= values
->npipes
;
258 u32 tile_bytes
= tile_width
* tile_height
* values
->blocksize
* values
->nsamples
;
259 u32 macro_tile_bytes
= macro_tile_width
* macro_tile_height
* tile_bytes
;
261 switch (values
->array_mode
) {
262 case ARRAY_LINEAR_GENERAL
:
263 /* technically tile_width/_height for pitch/height */
264 *pitch_align
= 1; /* tile_width */
265 *height_align
= 1; /* tile_height */
269 case ARRAY_LINEAR_ALIGNED
:
270 *pitch_align
= max((u32
)64, (u32
)(values
->group_size
/ values
->blocksize
));
273 *base_align
= values
->group_size
;
275 case ARRAY_1D_TILED_THIN1
:
276 *pitch_align
= max((u32
)tile_width
,
277 (u32
)(values
->group_size
/
278 (tile_height
* values
->blocksize
* values
->nsamples
)));
279 *height_align
= tile_height
;
281 *base_align
= values
->group_size
;
283 case ARRAY_2D_TILED_THIN1
:
284 *pitch_align
= max((u32
)macro_tile_width
* tile_width
,
285 (u32
)((values
->group_size
* values
->nbanks
) /
286 (values
->blocksize
* values
->nsamples
* tile_width
)));
287 *height_align
= macro_tile_height
* tile_height
;
289 *base_align
= max(macro_tile_bytes
,
290 (*pitch_align
) * values
->blocksize
* (*height_align
) * values
->nsamples
);
299 static void r600_cs_track_init(struct r600_cs_track
*track
)
303 /* assume DX9 mode */
304 track
->sq_config
= DX9_CONSTS
;
305 for (i
= 0; i
< 8; i
++) {
306 track
->cb_color_base_last
[i
] = 0;
307 track
->cb_color_size
[i
] = 0;
308 track
->cb_color_size_idx
[i
] = 0;
309 track
->cb_color_info
[i
] = 0;
310 track
->cb_color_view
[i
] = 0xFFFFFFFF;
311 track
->cb_color_bo
[i
] = NULL
;
312 track
->cb_color_bo_offset
[i
] = 0xFFFFFFFF;
313 track
->cb_color_bo_mc
[i
] = 0xFFFFFFFF;
314 track
->cb_color_frag_bo
[i
] = NULL
;
315 track
->cb_color_frag_offset
[i
] = 0xFFFFFFFF;
316 track
->cb_color_tile_bo
[i
] = NULL
;
317 track
->cb_color_tile_offset
[i
] = 0xFFFFFFFF;
318 track
->cb_color_mask
[i
] = 0xFFFFFFFF;
320 track
->is_resolve
= false;
321 track
->nsamples
= 16;
322 track
->log_nsamples
= 4;
323 track
->cb_target_mask
= 0xFFFFFFFF;
324 track
->cb_shader_mask
= 0xFFFFFFFF;
325 track
->cb_dirty
= true;
327 track
->db_bo_mc
= 0xFFFFFFFF;
328 /* assume the biggest format and that htile is enabled */
329 track
->db_depth_info
= 7 | (1 << 25);
330 track
->db_depth_view
= 0xFFFFC000;
331 track
->db_depth_size
= 0xFFFFFFFF;
332 track
->db_depth_size_idx
= 0;
333 track
->db_depth_control
= 0xFFFFFFFF;
334 track
->db_dirty
= true;
335 track
->htile_bo
= NULL
;
336 track
->htile_offset
= 0xFFFFFFFF;
337 track
->htile_surface
= 0;
339 for (i
= 0; i
< 4; i
++) {
340 track
->vgt_strmout_size
[i
] = 0;
341 track
->vgt_strmout_bo
[i
] = NULL
;
342 track
->vgt_strmout_bo_offset
[i
] = 0xFFFFFFFF;
343 track
->vgt_strmout_bo_mc
[i
] = 0xFFFFFFFF;
345 track
->streamout_dirty
= true;
346 track
->sx_misc_kill_all_prims
= false;
349 static int r600_cs_track_validate_cb(struct radeon_cs_parser
*p
, int i
)
351 struct r600_cs_track
*track
= p
->track
;
352 u32 slice_tile_max
, size
, tmp
;
353 u32 height
, height_align
, pitch
, pitch_align
, depth_align
;
354 u64 base_offset
, base_align
;
355 struct array_mode_checker array_check
;
356 volatile u32
*ib
= p
->ib
.ptr
;
359 /* When resolve is used, the second colorbuffer has always 1 sample. */
360 unsigned nsamples
= track
->is_resolve
&& i
== 1 ? 1 : track
->nsamples
;
362 size
= radeon_bo_size(track
->cb_color_bo
[i
]) - track
->cb_color_bo_offset
[i
];
363 format
= G_0280A0_FORMAT(track
->cb_color_info
[i
]);
364 if (!r600_fmt_is_valid_color(format
)) {
365 dev_warn(p
->dev
, "%s:%d cb invalid format %d for %d (0x%08X)\n",
366 __func__
, __LINE__
, format
,
367 i
, track
->cb_color_info
[i
]);
370 /* pitch in pixels */
371 pitch
= (G_028060_PITCH_TILE_MAX(track
->cb_color_size
[i
]) + 1) * 8;
372 slice_tile_max
= G_028060_SLICE_TILE_MAX(track
->cb_color_size
[i
]) + 1;
373 slice_tile_max
*= 64;
374 height
= slice_tile_max
/ pitch
;
377 array_mode
= G_0280A0_ARRAY_MODE(track
->cb_color_info
[i
]);
379 base_offset
= track
->cb_color_bo_mc
[i
] + track
->cb_color_bo_offset
[i
];
380 array_check
.array_mode
= array_mode
;
381 array_check
.group_size
= track
->group_size
;
382 array_check
.nbanks
= track
->nbanks
;
383 array_check
.npipes
= track
->npipes
;
384 array_check
.nsamples
= nsamples
;
385 array_check
.blocksize
= r600_fmt_get_blocksize(format
);
386 if (r600_get_array_mode_alignment(&array_check
,
387 &pitch_align
, &height_align
, &depth_align
, &base_align
)) {
388 dev_warn(p
->dev
, "%s invalid tiling %d for %d (0x%08X)\n", __func__
,
389 G_0280A0_ARRAY_MODE(track
->cb_color_info
[i
]), i
,
390 track
->cb_color_info
[i
]);
393 switch (array_mode
) {
394 case V_0280A0_ARRAY_LINEAR_GENERAL
:
396 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
398 case V_0280A0_ARRAY_1D_TILED_THIN1
:
399 /* avoid breaking userspace */
403 case V_0280A0_ARRAY_2D_TILED_THIN1
:
406 dev_warn(p
->dev
, "%s invalid tiling %d for %d (0x%08X)\n", __func__
,
407 G_0280A0_ARRAY_MODE(track
->cb_color_info
[i
]), i
,
408 track
->cb_color_info
[i
]);
412 if (!IS_ALIGNED(pitch
, pitch_align
)) {
413 dev_warn(p
->dev
, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
414 __func__
, __LINE__
, pitch
, pitch_align
, array_mode
);
417 if (!IS_ALIGNED(height
, height_align
)) {
418 dev_warn(p
->dev
, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
419 __func__
, __LINE__
, height
, height_align
, array_mode
);
422 if (!IS_ALIGNED(base_offset
, base_align
)) {
423 dev_warn(p
->dev
, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__
, i
,
424 base_offset
, base_align
, array_mode
);
429 tmp
= r600_fmt_get_nblocksy(format
, height
) * r600_fmt_get_nblocksx(format
, pitch
) *
430 r600_fmt_get_blocksize(format
) * nsamples
;
431 switch (array_mode
) {
433 case V_0280A0_ARRAY_LINEAR_GENERAL
:
434 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
435 tmp
+= track
->cb_color_view
[i
] & 0xFF;
437 case V_0280A0_ARRAY_1D_TILED_THIN1
:
438 case V_0280A0_ARRAY_2D_TILED_THIN1
:
439 tmp
+= G_028080_SLICE_MAX(track
->cb_color_view
[i
]) * tmp
;
442 if ((tmp
+ track
->cb_color_bo_offset
[i
]) > radeon_bo_size(track
->cb_color_bo
[i
])) {
443 if (array_mode
== V_0280A0_ARRAY_LINEAR_GENERAL
) {
444 /* the initial DDX does bad things with the CB size occasionally */
445 /* it rounds up height too far for slice tile max but the BO is smaller */
446 /* r600c,g also seem to flush at bad times in some apps resulting in
447 * bogus values here. So for linear just allow anything to avoid breaking
451 dev_warn(p
->dev
, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
452 __func__
, i
, array_mode
,
453 track
->cb_color_bo_offset
[i
], tmp
,
454 radeon_bo_size(track
->cb_color_bo
[i
]),
455 pitch
, height
, r600_fmt_get_nblocksx(format
, pitch
),
456 r600_fmt_get_nblocksy(format
, height
),
457 r600_fmt_get_blocksize(format
));
462 tmp
= (height
* pitch
) >> 6;
463 if (tmp
< slice_tile_max
)
464 slice_tile_max
= tmp
;
465 tmp
= S_028060_PITCH_TILE_MAX((pitch
/ 8) - 1) |
466 S_028060_SLICE_TILE_MAX(slice_tile_max
- 1);
467 ib
[track
->cb_color_size_idx
[i
]] = tmp
;
470 switch (G_0280A0_TILE_MODE(track
->cb_color_info
[i
])) {
471 case V_0280A0_TILE_DISABLE
:
473 case V_0280A0_FRAG_ENABLE
:
474 if (track
->nsamples
> 1) {
475 uint32_t tile_max
= G_028100_FMASK_TILE_MAX(track
->cb_color_mask
[i
]);
476 /* the tile size is 8x8, but the size is in units of bits.
477 * for bytes, do just * 8. */
478 uint32_t bytes
= track
->nsamples
* track
->log_nsamples
* 8 * (tile_max
+ 1);
480 if (bytes
+ track
->cb_color_frag_offset
[i
] >
481 radeon_bo_size(track
->cb_color_frag_bo
[i
])) {
482 dev_warn(p
->dev
, "%s FMASK_TILE_MAX too large "
483 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
484 __func__
, tile_max
, bytes
,
485 track
->cb_color_frag_offset
[i
],
486 radeon_bo_size(track
->cb_color_frag_bo
[i
]));
491 case V_0280A0_CLEAR_ENABLE
:
493 uint32_t block_max
= G_028100_CMASK_BLOCK_MAX(track
->cb_color_mask
[i
]);
494 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
495 * (128*128) / (8*8) / 2 = 128 bytes per block. */
496 uint32_t bytes
= (block_max
+ 1) * 128;
498 if (bytes
+ track
->cb_color_tile_offset
[i
] >
499 radeon_bo_size(track
->cb_color_tile_bo
[i
])) {
500 dev_warn(p
->dev
, "%s CMASK_BLOCK_MAX too large "
501 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
502 __func__
, block_max
, bytes
,
503 track
->cb_color_tile_offset
[i
],
504 radeon_bo_size(track
->cb_color_tile_bo
[i
]));
510 dev_warn(p
->dev
, "%s invalid tile mode\n", __func__
);
516 static int r600_cs_track_validate_db(struct radeon_cs_parser
*p
)
518 struct r600_cs_track
*track
= p
->track
;
519 u32 nviews
, bpe
, ntiles
, size
, slice_tile_max
, tmp
;
520 u32 height_align
, pitch_align
, depth_align
;
523 u64 base_offset
, base_align
;
524 struct array_mode_checker array_check
;
526 volatile u32
*ib
= p
->ib
.ptr
;
529 if (track
->db_bo
== NULL
) {
530 dev_warn(p
->dev
, "z/stencil with no depth buffer\n");
533 switch (G_028010_FORMAT(track
->db_depth_info
)) {
534 case V_028010_DEPTH_16
:
537 case V_028010_DEPTH_X8_24
:
538 case V_028010_DEPTH_8_24
:
539 case V_028010_DEPTH_X8_24_FLOAT
:
540 case V_028010_DEPTH_8_24_FLOAT
:
541 case V_028010_DEPTH_32_FLOAT
:
544 case V_028010_DEPTH_X24_8_32_FLOAT
:
548 dev_warn(p
->dev
, "z/stencil with invalid format %d\n", G_028010_FORMAT(track
->db_depth_info
));
551 if ((track
->db_depth_size
& 0xFFFFFC00) == 0xFFFFFC00) {
552 if (!track
->db_depth_size_idx
) {
553 dev_warn(p
->dev
, "z/stencil buffer size not set\n");
556 tmp
= radeon_bo_size(track
->db_bo
) - track
->db_offset
;
557 tmp
= (tmp
/ bpe
) >> 6;
559 dev_warn(p
->dev
, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
560 track
->db_depth_size
, bpe
, track
->db_offset
,
561 radeon_bo_size(track
->db_bo
));
564 ib
[track
->db_depth_size_idx
] = S_028000_SLICE_TILE_MAX(tmp
- 1) | (track
->db_depth_size
& 0x3FF);
566 size
= radeon_bo_size(track
->db_bo
);
567 /* pitch in pixels */
568 pitch
= (G_028000_PITCH_TILE_MAX(track
->db_depth_size
) + 1) * 8;
569 slice_tile_max
= G_028000_SLICE_TILE_MAX(track
->db_depth_size
) + 1;
570 slice_tile_max
*= 64;
571 height
= slice_tile_max
/ pitch
;
574 base_offset
= track
->db_bo_mc
+ track
->db_offset
;
575 array_mode
= G_028010_ARRAY_MODE(track
->db_depth_info
);
576 array_check
.array_mode
= array_mode
;
577 array_check
.group_size
= track
->group_size
;
578 array_check
.nbanks
= track
->nbanks
;
579 array_check
.npipes
= track
->npipes
;
580 array_check
.nsamples
= track
->nsamples
;
581 array_check
.blocksize
= bpe
;
582 if (r600_get_array_mode_alignment(&array_check
,
583 &pitch_align
, &height_align
, &depth_align
, &base_align
)) {
584 dev_warn(p
->dev
, "%s invalid tiling %d (0x%08X)\n", __func__
,
585 G_028010_ARRAY_MODE(track
->db_depth_info
),
586 track
->db_depth_info
);
589 switch (array_mode
) {
590 case V_028010_ARRAY_1D_TILED_THIN1
:
591 /* don't break userspace */
594 case V_028010_ARRAY_2D_TILED_THIN1
:
597 dev_warn(p
->dev
, "%s invalid tiling %d (0x%08X)\n", __func__
,
598 G_028010_ARRAY_MODE(track
->db_depth_info
),
599 track
->db_depth_info
);
603 if (!IS_ALIGNED(pitch
, pitch_align
)) {
604 dev_warn(p
->dev
, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
605 __func__
, __LINE__
, pitch
, pitch_align
, array_mode
);
608 if (!IS_ALIGNED(height
, height_align
)) {
609 dev_warn(p
->dev
, "%s:%d db height (%d, 0x%x, %d) invalid\n",
610 __func__
, __LINE__
, height
, height_align
, array_mode
);
613 if (!IS_ALIGNED(base_offset
, base_align
)) {
614 dev_warn(p
->dev
, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__
,
615 base_offset
, base_align
, array_mode
);
619 ntiles
= G_028000_SLICE_TILE_MAX(track
->db_depth_size
) + 1;
620 nviews
= G_028004_SLICE_MAX(track
->db_depth_view
) + 1;
621 tmp
= ntiles
* bpe
* 64 * nviews
* track
->nsamples
;
622 if ((tmp
+ track
->db_offset
) > radeon_bo_size(track
->db_bo
)) {
623 dev_warn(p
->dev
, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
625 track
->db_depth_size
, ntiles
, nviews
, bpe
, tmp
+ track
->db_offset
,
626 radeon_bo_size(track
->db_bo
));
632 if (G_028010_TILE_SURFACE_ENABLE(track
->db_depth_info
)) {
636 if (track
->htile_bo
== NULL
) {
637 dev_warn(p
->dev
, "%s:%d htile enabled without htile surface 0x%08x\n",
638 __func__
, __LINE__
, track
->db_depth_info
);
641 if ((track
->db_depth_size
& 0xFFFFFC00) == 0xFFFFFC00) {
642 dev_warn(p
->dev
, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
643 __func__
, __LINE__
, track
->db_depth_size
);
649 if (G_028D24_LINEAR(track
->htile_surface
)) {
650 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
651 nbx
= round_up(nbx
, 16 * 8);
652 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
653 nby
= round_up(nby
, track
->npipes
* 8);
655 /* always assume 8x8 htile */
656 /* align is htile align * 8, htile align vary according to
657 * number of pipe and tile width and nby
659 switch (track
->npipes
) {
661 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
662 nbx
= round_up(nbx
, 64 * 8);
663 nby
= round_up(nby
, 64 * 8);
666 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
667 nbx
= round_up(nbx
, 64 * 8);
668 nby
= round_up(nby
, 32 * 8);
671 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
672 nbx
= round_up(nbx
, 32 * 8);
673 nby
= round_up(nby
, 32 * 8);
676 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
677 nbx
= round_up(nbx
, 32 * 8);
678 nby
= round_up(nby
, 16 * 8);
681 dev_warn(p
->dev
, "%s:%d invalid num pipes %d\n",
682 __func__
, __LINE__
, track
->npipes
);
686 /* compute number of htile */
689 /* size must be aligned on npipes * 2K boundary */
690 size
= roundup(nbx
* nby
* 4, track
->npipes
* (2 << 10));
691 size
+= track
->htile_offset
;
693 if (size
> radeon_bo_size(track
->htile_bo
)) {
694 dev_warn(p
->dev
, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
695 __func__
, __LINE__
, radeon_bo_size(track
->htile_bo
),
701 track
->db_dirty
= false;
705 static int r600_cs_track_check(struct radeon_cs_parser
*p
)
707 struct r600_cs_track
*track
= p
->track
;
711 /* on legacy kernel we don't perform advanced check */
715 /* check streamout */
716 if (track
->streamout_dirty
&& track
->vgt_strmout_en
) {
717 for (i
= 0; i
< 4; i
++) {
718 if (track
->vgt_strmout_buffer_en
& (1 << i
)) {
719 if (track
->vgt_strmout_bo
[i
]) {
720 u64 offset
= (u64
)track
->vgt_strmout_bo_offset
[i
] +
721 (u64
)track
->vgt_strmout_size
[i
];
722 if (offset
> radeon_bo_size(track
->vgt_strmout_bo
[i
])) {
723 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
725 radeon_bo_size(track
->vgt_strmout_bo
[i
]));
729 dev_warn(p
->dev
, "No buffer for streamout %d\n", i
);
734 track
->streamout_dirty
= false;
737 if (track
->sx_misc_kill_all_prims
)
740 /* check that we have a cb for each enabled target, we don't check
741 * shader_mask because it seems mesa isn't always setting it :(
743 if (track
->cb_dirty
) {
744 tmp
= track
->cb_target_mask
;
746 /* We must check both colorbuffers for RESOLVE. */
747 if (track
->is_resolve
) {
751 for (i
= 0; i
< 8; i
++) {
752 if ((tmp
>> (i
* 4)) & 0xF) {
753 /* at least one component is enabled */
754 if (track
->cb_color_bo
[i
] == NULL
) {
755 dev_warn(p
->dev
, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
756 __func__
, __LINE__
, track
->cb_target_mask
, track
->cb_shader_mask
, i
);
759 /* perform rewrite of CB_COLOR[0-7]_SIZE */
760 r
= r600_cs_track_validate_cb(p
, i
);
765 track
->cb_dirty
= false;
768 /* Check depth buffer */
769 if (track
->db_dirty
&&
770 G_028010_FORMAT(track
->db_depth_info
) != V_028010_DEPTH_INVALID
&&
771 (G_028800_STENCIL_ENABLE(track
->db_depth_control
) ||
772 G_028800_Z_ENABLE(track
->db_depth_control
))) {
773 r
= r600_cs_track_validate_db(p
);
782 * r600_cs_packet_parse_vline() - parse userspace VLINE packet
783 * @parser: parser structure holding parsing context.
785 * This is an R600-specific function for parsing VLINE packets.
786 * Real work is done by r600_cs_common_vline_parse function.
787 * Here we just set up ASIC-specific register table and call
788 * the common implementation function.
790 static int r600_cs_packet_parse_vline(struct radeon_cs_parser
*p
)
792 static uint32_t vline_start_end
[2] = {AVIVO_D1MODE_VLINE_START_END
,
793 AVIVO_D2MODE_VLINE_START_END
};
794 static uint32_t vline_status
[2] = {AVIVO_D1MODE_VLINE_STATUS
,
795 AVIVO_D2MODE_VLINE_STATUS
};
797 return r600_cs_common_vline_parse(p
, vline_start_end
, vline_status
);
801 * r600_cs_common_vline_parse() - common vline parser
802 * @parser: parser structure holding parsing context.
803 * @vline_start_end: table of vline_start_end registers
804 * @vline_status: table of vline_status registers
806 * Userspace sends a special sequence for VLINE waits.
807 * PACKET0 - VLINE_START_END + value
808 * PACKET3 - WAIT_REG_MEM poll vline status reg
809 * RELOC (P3) - crtc_id in reloc.
811 * This function parses this and relocates the VLINE START END
812 * and WAIT_REG_MEM packets to the correct crtc.
813 * It also detects a switched off crtc and nulls out the
814 * wait in that case. This function is common for all ASICs that
815 * are R600 and newer. The parsing algorithm is the same, and only
816 * differs in which registers are used.
818 * Caller is the ASIC-specific function which passes the parser
819 * context and ASIC-specific register table
821 int r600_cs_common_vline_parse(struct radeon_cs_parser
*p
,
822 uint32_t *vline_start_end
,
823 uint32_t *vline_status
)
825 struct drm_mode_object
*obj
;
826 struct drm_crtc
*crtc
;
827 struct radeon_crtc
*radeon_crtc
;
828 struct radeon_cs_packet p3reloc
, wait_reg_mem
;
831 uint32_t header
, h_idx
, reg
, wait_reg_mem_info
;
832 volatile uint32_t *ib
;
836 /* parse the WAIT_REG_MEM */
837 r
= radeon_cs_packet_parse(p
, &wait_reg_mem
, p
->idx
);
841 /* check its a WAIT_REG_MEM */
842 if (wait_reg_mem
.type
!= RADEON_PACKET_TYPE3
||
843 wait_reg_mem
.opcode
!= PACKET3_WAIT_REG_MEM
) {
844 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
848 wait_reg_mem_info
= radeon_get_ib_value(p
, wait_reg_mem
.idx
+ 1);
849 /* bit 4 is reg (0) or mem (1) */
850 if (wait_reg_mem_info
& 0x10) {
851 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n");
854 /* bit 8 is me (0) or pfp (1) */
855 if (wait_reg_mem_info
& 0x100) {
856 DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n");
859 /* waiting for value to be equal */
860 if ((wait_reg_mem_info
& 0x7) != 0x3) {
861 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
864 if ((radeon_get_ib_value(p
, wait_reg_mem
.idx
+ 2) << 2) != vline_status
[0]) {
865 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
869 if (radeon_get_ib_value(p
, wait_reg_mem
.idx
+ 5) != RADEON_VLINE_STAT
) {
870 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
874 /* jump over the NOP */
875 r
= radeon_cs_packet_parse(p
, &p3reloc
, p
->idx
+ wait_reg_mem
.count
+ 2);
880 p
->idx
+= wait_reg_mem
.count
+ 2;
881 p
->idx
+= p3reloc
.count
+ 2;
883 header
= radeon_get_ib_value(p
, h_idx
);
884 crtc_id
= radeon_get_ib_value(p
, h_idx
+ 2 + 7 + 1);
885 reg
= R600_CP_PACKET0_GET_REG(header
);
887 obj
= drm_mode_object_find(p
->rdev
->ddev
, crtc_id
, DRM_MODE_OBJECT_CRTC
);
889 DRM_ERROR("cannot find crtc %d\n", crtc_id
);
892 crtc
= obj_to_crtc(obj
);
893 radeon_crtc
= to_radeon_crtc(crtc
);
894 crtc_id
= radeon_crtc
->crtc_id
;
896 if (!crtc
->enabled
) {
897 /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
898 ib
[h_idx
+ 2] = PACKET2(0);
899 ib
[h_idx
+ 3] = PACKET2(0);
900 ib
[h_idx
+ 4] = PACKET2(0);
901 ib
[h_idx
+ 5] = PACKET2(0);
902 ib
[h_idx
+ 6] = PACKET2(0);
903 ib
[h_idx
+ 7] = PACKET2(0);
904 ib
[h_idx
+ 8] = PACKET2(0);
905 } else if (reg
== vline_start_end
[0]) {
906 header
&= ~R600_CP_PACKET0_REG_MASK
;
907 header
|= vline_start_end
[crtc_id
] >> 2;
909 ib
[h_idx
+ 4] = vline_status
[crtc_id
] >> 2;
911 DRM_ERROR("unknown crtc reloc\n");
917 static int r600_packet0_check(struct radeon_cs_parser
*p
,
918 struct radeon_cs_packet
*pkt
,
919 unsigned idx
, unsigned reg
)
924 case AVIVO_D1MODE_VLINE_START_END
:
925 r
= r600_cs_packet_parse_vline(p
);
927 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
933 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
940 static int r600_cs_parse_packet0(struct radeon_cs_parser
*p
,
941 struct radeon_cs_packet
*pkt
)
949 for (i
= 0; i
<= pkt
->count
; i
++, idx
++, reg
+= 4) {
950 r
= r600_packet0_check(p
, pkt
, idx
, reg
);
959 * r600_cs_check_reg() - check if register is authorized or not
960 * @parser: parser structure holding parsing context
961 * @reg: register we are testing
962 * @idx: index into the cs buffer
964 * This function will test against r600_reg_safe_bm and return 0
965 * if register is safe. If register is not flag as safe this function
966 * will test it against a list of register needind special handling.
968 static int r600_cs_check_reg(struct radeon_cs_parser
*p
, u32 reg
, u32 idx
)
970 struct r600_cs_track
*track
= (struct r600_cs_track
*)p
->track
;
971 struct radeon_cs_reloc
*reloc
;
976 if (i
>= ARRAY_SIZE(r600_reg_safe_bm
)) {
977 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
980 m
= 1 << ((reg
>> 2) & 31);
981 if (!(r600_reg_safe_bm
[i
] & m
))
985 /* force following reg to 0 in an attempt to disable out buffer
986 * which will need us to better understand how it works to perform
987 * security check on it (Jerome)
989 case R_0288A8_SQ_ESGS_RING_ITEMSIZE
:
990 case R_008C44_SQ_ESGS_RING_SIZE
:
991 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE
:
992 case R_008C54_SQ_ESTMP_RING_SIZE
:
993 case R_0288C0_SQ_FBUF_RING_ITEMSIZE
:
994 case R_008C74_SQ_FBUF_RING_SIZE
:
995 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE
:
996 case R_008C5C_SQ_GSTMP_RING_SIZE
:
997 case R_0288AC_SQ_GSVS_RING_ITEMSIZE
:
998 case R_008C4C_SQ_GSVS_RING_SIZE
:
999 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE
:
1000 case R_008C6C_SQ_PSTMP_RING_SIZE
:
1001 case R_0288C4_SQ_REDUC_RING_ITEMSIZE
:
1002 case R_008C7C_SQ_REDUC_RING_SIZE
:
1003 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE
:
1004 case R_008C64_SQ_VSTMP_RING_SIZE
:
1005 case R_0288C8_SQ_GS_VERT_ITEMSIZE
:
1006 /* get value to populate the IB don't remove */
1007 tmp
=radeon_get_ib_value(p
, idx
);
1011 track
->sq_config
= radeon_get_ib_value(p
, idx
);
1013 case R_028800_DB_DEPTH_CONTROL
:
1014 track
->db_depth_control
= radeon_get_ib_value(p
, idx
);
1015 track
->db_dirty
= true;
1017 case R_028010_DB_DEPTH_INFO
:
1018 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
) &&
1019 radeon_cs_packet_next_is_pkt3_nop(p
)) {
1020 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1022 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1026 track
->db_depth_info
= radeon_get_ib_value(p
, idx
);
1027 ib
[idx
] &= C_028010_ARRAY_MODE
;
1028 track
->db_depth_info
&= C_028010_ARRAY_MODE
;
1029 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
) {
1030 ib
[idx
] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1
);
1031 track
->db_depth_info
|= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1
);
1033 ib
[idx
] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1
);
1034 track
->db_depth_info
|= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1
);
1037 track
->db_depth_info
= radeon_get_ib_value(p
, idx
);
1039 track
->db_dirty
= true;
1041 case R_028004_DB_DEPTH_VIEW
:
1042 track
->db_depth_view
= radeon_get_ib_value(p
, idx
);
1043 track
->db_dirty
= true;
1045 case R_028000_DB_DEPTH_SIZE
:
1046 track
->db_depth_size
= radeon_get_ib_value(p
, idx
);
1047 track
->db_depth_size_idx
= idx
;
1048 track
->db_dirty
= true;
1050 case R_028AB0_VGT_STRMOUT_EN
:
1051 track
->vgt_strmout_en
= radeon_get_ib_value(p
, idx
);
1052 track
->streamout_dirty
= true;
1054 case R_028B20_VGT_STRMOUT_BUFFER_EN
:
1055 track
->vgt_strmout_buffer_en
= radeon_get_ib_value(p
, idx
);
1056 track
->streamout_dirty
= true;
1058 case VGT_STRMOUT_BUFFER_BASE_0
:
1059 case VGT_STRMOUT_BUFFER_BASE_1
:
1060 case VGT_STRMOUT_BUFFER_BASE_2
:
1061 case VGT_STRMOUT_BUFFER_BASE_3
:
1062 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1064 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1068 tmp
= (reg
- VGT_STRMOUT_BUFFER_BASE_0
) / 16;
1069 track
->vgt_strmout_bo_offset
[tmp
] = radeon_get_ib_value(p
, idx
) << 8;
1070 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1071 track
->vgt_strmout_bo
[tmp
] = reloc
->robj
;
1072 track
->vgt_strmout_bo_mc
[tmp
] = reloc
->lobj
.gpu_offset
;
1073 track
->streamout_dirty
= true;
1075 case VGT_STRMOUT_BUFFER_SIZE_0
:
1076 case VGT_STRMOUT_BUFFER_SIZE_1
:
1077 case VGT_STRMOUT_BUFFER_SIZE_2
:
1078 case VGT_STRMOUT_BUFFER_SIZE_3
:
1079 tmp
= (reg
- VGT_STRMOUT_BUFFER_SIZE_0
) / 16;
1080 /* size in register is DWs, convert to bytes */
1081 track
->vgt_strmout_size
[tmp
] = radeon_get_ib_value(p
, idx
) * 4;
1082 track
->streamout_dirty
= true;
1085 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1087 dev_warn(p
->dev
, "missing reloc for CP_COHER_BASE "
1091 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1093 case R_028238_CB_TARGET_MASK
:
1094 track
->cb_target_mask
= radeon_get_ib_value(p
, idx
);
1095 track
->cb_dirty
= true;
1097 case R_02823C_CB_SHADER_MASK
:
1098 track
->cb_shader_mask
= radeon_get_ib_value(p
, idx
);
1100 case R_028C04_PA_SC_AA_CONFIG
:
1101 tmp
= G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p
, idx
));
1102 track
->log_nsamples
= tmp
;
1103 track
->nsamples
= 1 << tmp
;
1104 track
->cb_dirty
= true;
1106 case R_028808_CB_COLOR_CONTROL
:
1107 tmp
= G_028808_SPECIAL_OP(radeon_get_ib_value(p
, idx
));
1108 track
->is_resolve
= tmp
== V_028808_SPECIAL_RESOLVE_BOX
;
1109 track
->cb_dirty
= true;
1111 case R_0280A0_CB_COLOR0_INFO
:
1112 case R_0280A4_CB_COLOR1_INFO
:
1113 case R_0280A8_CB_COLOR2_INFO
:
1114 case R_0280AC_CB_COLOR3_INFO
:
1115 case R_0280B0_CB_COLOR4_INFO
:
1116 case R_0280B4_CB_COLOR5_INFO
:
1117 case R_0280B8_CB_COLOR6_INFO
:
1118 case R_0280BC_CB_COLOR7_INFO
:
1119 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
) &&
1120 radeon_cs_packet_next_is_pkt3_nop(p
)) {
1121 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1123 dev_err(p
->dev
, "bad SET_CONTEXT_REG 0x%04X\n", reg
);
1126 tmp
= (reg
- R_0280A0_CB_COLOR0_INFO
) / 4;
1127 track
->cb_color_info
[tmp
] = radeon_get_ib_value(p
, idx
);
1128 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
) {
1129 ib
[idx
] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1
);
1130 track
->cb_color_info
[tmp
] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1
);
1131 } else if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
) {
1132 ib
[idx
] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1
);
1133 track
->cb_color_info
[tmp
] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1
);
1136 tmp
= (reg
- R_0280A0_CB_COLOR0_INFO
) / 4;
1137 track
->cb_color_info
[tmp
] = radeon_get_ib_value(p
, idx
);
1139 track
->cb_dirty
= true;
1141 case R_028080_CB_COLOR0_VIEW
:
1142 case R_028084_CB_COLOR1_VIEW
:
1143 case R_028088_CB_COLOR2_VIEW
:
1144 case R_02808C_CB_COLOR3_VIEW
:
1145 case R_028090_CB_COLOR4_VIEW
:
1146 case R_028094_CB_COLOR5_VIEW
:
1147 case R_028098_CB_COLOR6_VIEW
:
1148 case R_02809C_CB_COLOR7_VIEW
:
1149 tmp
= (reg
- R_028080_CB_COLOR0_VIEW
) / 4;
1150 track
->cb_color_view
[tmp
] = radeon_get_ib_value(p
, idx
);
1151 track
->cb_dirty
= true;
1153 case R_028060_CB_COLOR0_SIZE
:
1154 case R_028064_CB_COLOR1_SIZE
:
1155 case R_028068_CB_COLOR2_SIZE
:
1156 case R_02806C_CB_COLOR3_SIZE
:
1157 case R_028070_CB_COLOR4_SIZE
:
1158 case R_028074_CB_COLOR5_SIZE
:
1159 case R_028078_CB_COLOR6_SIZE
:
1160 case R_02807C_CB_COLOR7_SIZE
:
1161 tmp
= (reg
- R_028060_CB_COLOR0_SIZE
) / 4;
1162 track
->cb_color_size
[tmp
] = radeon_get_ib_value(p
, idx
);
1163 track
->cb_color_size_idx
[tmp
] = idx
;
1164 track
->cb_dirty
= true;
1166 /* This register were added late, there is userspace
1167 * which does provide relocation for those but set
1168 * 0 offset. In order to avoid breaking old userspace
1169 * we detect this and set address to point to last
1170 * CB_COLOR0_BASE, note that if userspace doesn't set
1171 * CB_COLOR0_BASE before this register we will report
1172 * error. Old userspace always set CB_COLOR0_BASE
1173 * before any of this.
1175 case R_0280E0_CB_COLOR0_FRAG
:
1176 case R_0280E4_CB_COLOR1_FRAG
:
1177 case R_0280E8_CB_COLOR2_FRAG
:
1178 case R_0280EC_CB_COLOR3_FRAG
:
1179 case R_0280F0_CB_COLOR4_FRAG
:
1180 case R_0280F4_CB_COLOR5_FRAG
:
1181 case R_0280F8_CB_COLOR6_FRAG
:
1182 case R_0280FC_CB_COLOR7_FRAG
:
1183 tmp
= (reg
- R_0280E0_CB_COLOR0_FRAG
) / 4;
1184 if (!radeon_cs_packet_next_is_pkt3_nop(p
)) {
1185 if (!track
->cb_color_base_last
[tmp
]) {
1186 dev_err(p
->dev
, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg
);
1189 track
->cb_color_frag_bo
[tmp
] = track
->cb_color_bo
[tmp
];
1190 track
->cb_color_frag_offset
[tmp
] = track
->cb_color_bo_offset
[tmp
];
1191 ib
[idx
] = track
->cb_color_base_last
[tmp
];
1193 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1195 dev_err(p
->dev
, "bad SET_CONTEXT_REG 0x%04X\n", reg
);
1198 track
->cb_color_frag_bo
[tmp
] = reloc
->robj
;
1199 track
->cb_color_frag_offset
[tmp
] = (u64
)ib
[idx
] << 8;
1200 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1202 if (G_0280A0_TILE_MODE(track
->cb_color_info
[tmp
])) {
1203 track
->cb_dirty
= true;
1206 case R_0280C0_CB_COLOR0_TILE
:
1207 case R_0280C4_CB_COLOR1_TILE
:
1208 case R_0280C8_CB_COLOR2_TILE
:
1209 case R_0280CC_CB_COLOR3_TILE
:
1210 case R_0280D0_CB_COLOR4_TILE
:
1211 case R_0280D4_CB_COLOR5_TILE
:
1212 case R_0280D8_CB_COLOR6_TILE
:
1213 case R_0280DC_CB_COLOR7_TILE
:
1214 tmp
= (reg
- R_0280C0_CB_COLOR0_TILE
) / 4;
1215 if (!radeon_cs_packet_next_is_pkt3_nop(p
)) {
1216 if (!track
->cb_color_base_last
[tmp
]) {
1217 dev_err(p
->dev
, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg
);
1220 track
->cb_color_tile_bo
[tmp
] = track
->cb_color_bo
[tmp
];
1221 track
->cb_color_tile_offset
[tmp
] = track
->cb_color_bo_offset
[tmp
];
1222 ib
[idx
] = track
->cb_color_base_last
[tmp
];
1224 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1226 dev_err(p
->dev
, "bad SET_CONTEXT_REG 0x%04X\n", reg
);
1229 track
->cb_color_tile_bo
[tmp
] = reloc
->robj
;
1230 track
->cb_color_tile_offset
[tmp
] = (u64
)ib
[idx
] << 8;
1231 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1233 if (G_0280A0_TILE_MODE(track
->cb_color_info
[tmp
])) {
1234 track
->cb_dirty
= true;
1237 case R_028100_CB_COLOR0_MASK
:
1238 case R_028104_CB_COLOR1_MASK
:
1239 case R_028108_CB_COLOR2_MASK
:
1240 case R_02810C_CB_COLOR3_MASK
:
1241 case R_028110_CB_COLOR4_MASK
:
1242 case R_028114_CB_COLOR5_MASK
:
1243 case R_028118_CB_COLOR6_MASK
:
1244 case R_02811C_CB_COLOR7_MASK
:
1245 tmp
= (reg
- R_028100_CB_COLOR0_MASK
) / 4;
1246 track
->cb_color_mask
[tmp
] = radeon_get_ib_value(p
, idx
);
1247 if (G_0280A0_TILE_MODE(track
->cb_color_info
[tmp
])) {
1248 track
->cb_dirty
= true;
1251 case CB_COLOR0_BASE
:
1252 case CB_COLOR1_BASE
:
1253 case CB_COLOR2_BASE
:
1254 case CB_COLOR3_BASE
:
1255 case CB_COLOR4_BASE
:
1256 case CB_COLOR5_BASE
:
1257 case CB_COLOR6_BASE
:
1258 case CB_COLOR7_BASE
:
1259 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1261 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1265 tmp
= (reg
- CB_COLOR0_BASE
) / 4;
1266 track
->cb_color_bo_offset
[tmp
] = radeon_get_ib_value(p
, idx
) << 8;
1267 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1268 track
->cb_color_base_last
[tmp
] = ib
[idx
];
1269 track
->cb_color_bo
[tmp
] = reloc
->robj
;
1270 track
->cb_color_bo_mc
[tmp
] = reloc
->lobj
.gpu_offset
;
1271 track
->cb_dirty
= true;
1274 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1276 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1280 track
->db_offset
= radeon_get_ib_value(p
, idx
) << 8;
1281 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1282 track
->db_bo
= reloc
->robj
;
1283 track
->db_bo_mc
= reloc
->lobj
.gpu_offset
;
1284 track
->db_dirty
= true;
1286 case DB_HTILE_DATA_BASE
:
1287 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1289 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1293 track
->htile_offset
= radeon_get_ib_value(p
, idx
) << 8;
1294 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1295 track
->htile_bo
= reloc
->robj
;
1296 track
->db_dirty
= true;
1298 case DB_HTILE_SURFACE
:
1299 track
->htile_surface
= radeon_get_ib_value(p
, idx
);
1300 /* force 8x8 htile width and height */
1302 track
->db_dirty
= true;
1304 case SQ_PGM_START_FS
:
1305 case SQ_PGM_START_ES
:
1306 case SQ_PGM_START_VS
:
1307 case SQ_PGM_START_GS
:
1308 case SQ_PGM_START_PS
:
1309 case SQ_ALU_CONST_CACHE_GS_0
:
1310 case SQ_ALU_CONST_CACHE_GS_1
:
1311 case SQ_ALU_CONST_CACHE_GS_2
:
1312 case SQ_ALU_CONST_CACHE_GS_3
:
1313 case SQ_ALU_CONST_CACHE_GS_4
:
1314 case SQ_ALU_CONST_CACHE_GS_5
:
1315 case SQ_ALU_CONST_CACHE_GS_6
:
1316 case SQ_ALU_CONST_CACHE_GS_7
:
1317 case SQ_ALU_CONST_CACHE_GS_8
:
1318 case SQ_ALU_CONST_CACHE_GS_9
:
1319 case SQ_ALU_CONST_CACHE_GS_10
:
1320 case SQ_ALU_CONST_CACHE_GS_11
:
1321 case SQ_ALU_CONST_CACHE_GS_12
:
1322 case SQ_ALU_CONST_CACHE_GS_13
:
1323 case SQ_ALU_CONST_CACHE_GS_14
:
1324 case SQ_ALU_CONST_CACHE_GS_15
:
1325 case SQ_ALU_CONST_CACHE_PS_0
:
1326 case SQ_ALU_CONST_CACHE_PS_1
:
1327 case SQ_ALU_CONST_CACHE_PS_2
:
1328 case SQ_ALU_CONST_CACHE_PS_3
:
1329 case SQ_ALU_CONST_CACHE_PS_4
:
1330 case SQ_ALU_CONST_CACHE_PS_5
:
1331 case SQ_ALU_CONST_CACHE_PS_6
:
1332 case SQ_ALU_CONST_CACHE_PS_7
:
1333 case SQ_ALU_CONST_CACHE_PS_8
:
1334 case SQ_ALU_CONST_CACHE_PS_9
:
1335 case SQ_ALU_CONST_CACHE_PS_10
:
1336 case SQ_ALU_CONST_CACHE_PS_11
:
1337 case SQ_ALU_CONST_CACHE_PS_12
:
1338 case SQ_ALU_CONST_CACHE_PS_13
:
1339 case SQ_ALU_CONST_CACHE_PS_14
:
1340 case SQ_ALU_CONST_CACHE_PS_15
:
1341 case SQ_ALU_CONST_CACHE_VS_0
:
1342 case SQ_ALU_CONST_CACHE_VS_1
:
1343 case SQ_ALU_CONST_CACHE_VS_2
:
1344 case SQ_ALU_CONST_CACHE_VS_3
:
1345 case SQ_ALU_CONST_CACHE_VS_4
:
1346 case SQ_ALU_CONST_CACHE_VS_5
:
1347 case SQ_ALU_CONST_CACHE_VS_6
:
1348 case SQ_ALU_CONST_CACHE_VS_7
:
1349 case SQ_ALU_CONST_CACHE_VS_8
:
1350 case SQ_ALU_CONST_CACHE_VS_9
:
1351 case SQ_ALU_CONST_CACHE_VS_10
:
1352 case SQ_ALU_CONST_CACHE_VS_11
:
1353 case SQ_ALU_CONST_CACHE_VS_12
:
1354 case SQ_ALU_CONST_CACHE_VS_13
:
1355 case SQ_ALU_CONST_CACHE_VS_14
:
1356 case SQ_ALU_CONST_CACHE_VS_15
:
1357 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1359 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1363 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1365 case SX_MEMORY_EXPORT_BASE
:
1366 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1368 dev_warn(p
->dev
, "bad SET_CONFIG_REG "
1372 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1375 track
->sx_misc_kill_all_prims
= (radeon_get_ib_value(p
, idx
) & 0x1) != 0;
1378 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
1384 unsigned r600_mip_minify(unsigned size
, unsigned level
)
1388 val
= max(1U, size
>> level
);
1390 val
= roundup_pow_of_two(val
);
1394 static void r600_texture_size(unsigned nfaces
, unsigned blevel
, unsigned llevel
,
1395 unsigned w0
, unsigned h0
, unsigned d0
, unsigned nsamples
, unsigned format
,
1396 unsigned block_align
, unsigned height_align
, unsigned base_align
,
1397 unsigned *l0_size
, unsigned *mipmap_size
)
1399 unsigned offset
, i
, level
;
1400 unsigned width
, height
, depth
, size
;
1403 unsigned nlevels
= llevel
- blevel
+ 1;
1406 blocksize
= r600_fmt_get_blocksize(format
);
1408 w0
= r600_mip_minify(w0
, 0);
1409 h0
= r600_mip_minify(h0
, 0);
1410 d0
= r600_mip_minify(d0
, 0);
1411 for(i
= 0, offset
= 0, level
= blevel
; i
< nlevels
; i
++, level
++) {
1412 width
= r600_mip_minify(w0
, i
);
1413 nbx
= r600_fmt_get_nblocksx(format
, width
);
1415 nbx
= round_up(nbx
, block_align
);
1417 height
= r600_mip_minify(h0
, i
);
1418 nby
= r600_fmt_get_nblocksy(format
, height
);
1419 nby
= round_up(nby
, height_align
);
1421 depth
= r600_mip_minify(d0
, i
);
1423 size
= nbx
* nby
* blocksize
* nsamples
;
1432 if (i
== 0 || i
== 1)
1433 offset
= round_up(offset
, base_align
);
1437 *mipmap_size
= offset
;
1439 *mipmap_size
= *l0_size
;
1441 *mipmap_size
-= *l0_size
;
1445 * r600_check_texture_resource() - check if register is authorized or not
1446 * @p: parser structure holding parsing context
1447 * @idx: index into the cs buffer
1448 * @texture: texture's bo structure
1449 * @mipmap: mipmap's bo structure
1451 * This function will check that the resource has valid field and that
1452 * the texture and mipmap bo object are big enough to cover this resource.
1454 static int r600_check_texture_resource(struct radeon_cs_parser
*p
, u32 idx
,
1455 struct radeon_bo
*texture
,
1456 struct radeon_bo
*mipmap
,
1461 struct r600_cs_track
*track
= p
->track
;
1462 u32 dim
, nfaces
, llevel
, blevel
, w0
, h0
, d0
;
1463 u32 word0
, word1
, l0_size
, mipmap_size
, word2
, word3
, word4
, word5
;
1464 u32 height_align
, pitch
, pitch_align
, depth_align
;
1467 struct array_mode_checker array_check
;
1471 /* on legacy kernel we don't perform advanced check */
1472 if (p
->rdev
== NULL
)
1475 /* convert to bytes */
1479 word0
= radeon_get_ib_value(p
, idx
+ 0);
1480 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
1481 if (tiling_flags
& RADEON_TILING_MACRO
)
1482 word0
|= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1483 else if (tiling_flags
& RADEON_TILING_MICRO
)
1484 word0
|= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1486 word1
= radeon_get_ib_value(p
, idx
+ 1);
1487 word2
= radeon_get_ib_value(p
, idx
+ 2) << 8;
1488 word3
= radeon_get_ib_value(p
, idx
+ 3) << 8;
1489 word4
= radeon_get_ib_value(p
, idx
+ 4);
1490 word5
= radeon_get_ib_value(p
, idx
+ 5);
1491 dim
= G_038000_DIM(word0
);
1492 w0
= G_038000_TEX_WIDTH(word0
) + 1;
1493 pitch
= (G_038000_PITCH(word0
) + 1) * 8;
1494 h0
= G_038004_TEX_HEIGHT(word1
) + 1;
1495 d0
= G_038004_TEX_DEPTH(word1
);
1496 format
= G_038004_DATA_FORMAT(word1
);
1497 blevel
= G_038010_BASE_LEVEL(word4
);
1498 llevel
= G_038014_LAST_LEVEL(word5
);
1499 /* pitch in texels */
1500 array_check
.array_mode
= G_038000_TILE_MODE(word0
);
1501 array_check
.group_size
= track
->group_size
;
1502 array_check
.nbanks
= track
->nbanks
;
1503 array_check
.npipes
= track
->npipes
;
1504 array_check
.nsamples
= 1;
1505 array_check
.blocksize
= r600_fmt_get_blocksize(format
);
1509 case V_038000_SQ_TEX_DIM_1D
:
1510 case V_038000_SQ_TEX_DIM_2D
:
1511 case V_038000_SQ_TEX_DIM_3D
:
1513 case V_038000_SQ_TEX_DIM_CUBEMAP
:
1514 if (p
->family
>= CHIP_RV770
)
1519 case V_038000_SQ_TEX_DIM_1D_ARRAY
:
1520 case V_038000_SQ_TEX_DIM_2D_ARRAY
:
1523 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
1526 case V_038000_SQ_TEX_DIM_2D_MSAA
:
1527 array_check
.nsamples
= 1 << llevel
;
1531 dev_warn(p
->dev
, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0
));
1534 if (!r600_fmt_is_valid_texture(format
, p
->family
)) {
1535 dev_warn(p
->dev
, "%s:%d texture invalid format %d\n",
1536 __func__
, __LINE__
, format
);
1540 if (r600_get_array_mode_alignment(&array_check
,
1541 &pitch_align
, &height_align
, &depth_align
, &base_align
)) {
1542 dev_warn(p
->dev
, "%s:%d tex array mode (%d) invalid\n",
1543 __func__
, __LINE__
, G_038000_TILE_MODE(word0
));
1547 /* XXX check height as well... */
1549 if (!IS_ALIGNED(pitch
, pitch_align
)) {
1550 dev_warn(p
->dev
, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1551 __func__
, __LINE__
, pitch
, pitch_align
, G_038000_TILE_MODE(word0
));
1554 if (!IS_ALIGNED(base_offset
, base_align
)) {
1555 dev_warn(p
->dev
, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1556 __func__
, __LINE__
, base_offset
, base_align
, G_038000_TILE_MODE(word0
));
1559 if (!IS_ALIGNED(mip_offset
, base_align
)) {
1560 dev_warn(p
->dev
, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1561 __func__
, __LINE__
, mip_offset
, base_align
, G_038000_TILE_MODE(word0
));
1565 if (blevel
> llevel
) {
1566 dev_warn(p
->dev
, "texture blevel %d > llevel %d\n",
1570 barray
= G_038014_BASE_ARRAY(word5
);
1571 larray
= G_038014_LAST_ARRAY(word5
);
1573 nfaces
= larray
- barray
+ 1;
1575 r600_texture_size(nfaces
, blevel
, llevel
, w0
, h0
, d0
, array_check
.nsamples
, format
,
1576 pitch_align
, height_align
, base_align
,
1577 &l0_size
, &mipmap_size
);
1578 /* using get ib will give us the offset into the texture bo */
1579 if ((l0_size
+ word2
) > radeon_bo_size(texture
)) {
1580 dev_warn(p
->dev
, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1581 w0
, h0
, pitch_align
, height_align
,
1582 array_check
.array_mode
, format
, word2
,
1583 l0_size
, radeon_bo_size(texture
));
1584 dev_warn(p
->dev
, "alignments %d %d %d %lld\n", pitch
, pitch_align
, height_align
, base_align
);
1587 /* using get ib will give us the offset into the mipmap bo */
1588 if ((mipmap_size
+ word3
) > radeon_bo_size(mipmap
)) {
1589 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1590 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1595 static bool r600_is_safe_reg(struct radeon_cs_parser
*p
, u32 reg
, u32 idx
)
1600 if (i
>= ARRAY_SIZE(r600_reg_safe_bm
)) {
1601 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
1604 m
= 1 << ((reg
>> 2) & 31);
1605 if (!(r600_reg_safe_bm
[i
] & m
))
1607 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
1611 static int r600_packet3_check(struct radeon_cs_parser
*p
,
1612 struct radeon_cs_packet
*pkt
)
1614 struct radeon_cs_reloc
*reloc
;
1615 struct r600_cs_track
*track
;
1619 unsigned start_reg
, end_reg
, reg
;
1623 track
= (struct r600_cs_track
*)p
->track
;
1626 idx_value
= radeon_get_ib_value(p
, idx
);
1628 switch (pkt
->opcode
) {
1629 case PACKET3_SET_PREDICATION
:
1635 if (pkt
->count
!= 1) {
1636 DRM_ERROR("bad SET PREDICATION\n");
1640 tmp
= radeon_get_ib_value(p
, idx
+ 1);
1641 pred_op
= (tmp
>> 16) & 0x7;
1643 /* for the clear predicate operation */
1648 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op
);
1652 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1654 DRM_ERROR("bad SET PREDICATION\n");
1658 offset
= reloc
->lobj
.gpu_offset
+
1659 (idx_value
& 0xfffffff0) +
1660 ((u64
)(tmp
& 0xff) << 32);
1662 ib
[idx
+ 0] = offset
;
1663 ib
[idx
+ 1] = (tmp
& 0xffffff00) | (upper_32_bits(offset
) & 0xff);
1667 case PACKET3_START_3D_CMDBUF
:
1668 if (p
->family
>= CHIP_RV770
|| pkt
->count
) {
1669 DRM_ERROR("bad START_3D\n");
1673 case PACKET3_CONTEXT_CONTROL
:
1674 if (pkt
->count
!= 1) {
1675 DRM_ERROR("bad CONTEXT_CONTROL\n");
1679 case PACKET3_INDEX_TYPE
:
1680 case PACKET3_NUM_INSTANCES
:
1682 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1686 case PACKET3_DRAW_INDEX
:
1689 if (pkt
->count
!= 3) {
1690 DRM_ERROR("bad DRAW_INDEX\n");
1693 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1695 DRM_ERROR("bad DRAW_INDEX\n");
1699 offset
= reloc
->lobj
.gpu_offset
+
1701 ((u64
)(radeon_get_ib_value(p
, idx
+1) & 0xff) << 32);
1704 ib
[idx
+1] = upper_32_bits(offset
) & 0xff;
1706 r
= r600_cs_track_check(p
);
1708 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
1713 case PACKET3_DRAW_INDEX_AUTO
:
1714 if (pkt
->count
!= 1) {
1715 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1718 r
= r600_cs_track_check(p
);
1720 dev_warn(p
->dev
, "%s:%d invalid cmd stream %d\n", __func__
, __LINE__
, idx
);
1724 case PACKET3_DRAW_INDEX_IMMD_BE
:
1725 case PACKET3_DRAW_INDEX_IMMD
:
1726 if (pkt
->count
< 2) {
1727 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1730 r
= r600_cs_track_check(p
);
1732 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
1736 case PACKET3_WAIT_REG_MEM
:
1737 if (pkt
->count
!= 5) {
1738 DRM_ERROR("bad WAIT_REG_MEM\n");
1741 /* bit 4 is reg (0) or mem (1) */
1742 if (idx_value
& 0x10) {
1745 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1747 DRM_ERROR("bad WAIT_REG_MEM\n");
1751 offset
= reloc
->lobj
.gpu_offset
+
1752 (radeon_get_ib_value(p
, idx
+1) & 0xfffffff0) +
1753 ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff) << 32);
1755 ib
[idx
+1] = (ib
[idx
+1] & 0x3) | (offset
& 0xfffffff0);
1756 ib
[idx
+2] = upper_32_bits(offset
) & 0xff;
1757 } else if (idx_value
& 0x100) {
1758 DRM_ERROR("cannot use PFP on REG wait\n");
1762 case PACKET3_CP_DMA
:
1766 if (pkt
->count
!= 4) {
1767 DRM_ERROR("bad CP DMA\n");
1770 command
= radeon_get_ib_value(p
, idx
+4);
1771 size
= command
& 0x1fffff;
1772 if (command
& PACKET3_CP_DMA_CMD_SAS
) {
1773 /* src address space is register */
1774 DRM_ERROR("CP DMA SAS not supported\n");
1777 if (command
& PACKET3_CP_DMA_CMD_SAIC
) {
1778 DRM_ERROR("CP DMA SAIC only supported for registers\n");
1781 /* src address space is memory */
1782 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1784 DRM_ERROR("bad CP DMA SRC\n");
1788 tmp
= radeon_get_ib_value(p
, idx
) +
1789 ((u64
)(radeon_get_ib_value(p
, idx
+1) & 0xff) << 32);
1791 offset
= reloc
->lobj
.gpu_offset
+ tmp
;
1793 if ((tmp
+ size
) > radeon_bo_size(reloc
->robj
)) {
1794 dev_warn(p
->dev
, "CP DMA src buffer too small (%llu %lu)\n",
1795 tmp
+ size
, radeon_bo_size(reloc
->robj
));
1800 ib
[idx
+1] = (ib
[idx
+1] & 0xffffff00) | (upper_32_bits(offset
) & 0xff);
1802 if (command
& PACKET3_CP_DMA_CMD_DAS
) {
1803 /* dst address space is register */
1804 DRM_ERROR("CP DMA DAS not supported\n");
1807 /* dst address space is memory */
1808 if (command
& PACKET3_CP_DMA_CMD_DAIC
) {
1809 DRM_ERROR("CP DMA DAIC only supported for registers\n");
1812 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1814 DRM_ERROR("bad CP DMA DST\n");
1818 tmp
= radeon_get_ib_value(p
, idx
+2) +
1819 ((u64
)(radeon_get_ib_value(p
, idx
+3) & 0xff) << 32);
1821 offset
= reloc
->lobj
.gpu_offset
+ tmp
;
1823 if ((tmp
+ size
) > radeon_bo_size(reloc
->robj
)) {
1824 dev_warn(p
->dev
, "CP DMA dst buffer too small (%llu %lu)\n",
1825 tmp
+ size
, radeon_bo_size(reloc
->robj
));
1830 ib
[idx
+3] = upper_32_bits(offset
) & 0xff;
1834 case PACKET3_SURFACE_SYNC
:
1835 if (pkt
->count
!= 3) {
1836 DRM_ERROR("bad SURFACE_SYNC\n");
1839 /* 0xffffffff/0x0 is flush all cache flag */
1840 if (radeon_get_ib_value(p
, idx
+ 1) != 0xffffffff ||
1841 radeon_get_ib_value(p
, idx
+ 2) != 0) {
1842 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1844 DRM_ERROR("bad SURFACE_SYNC\n");
1847 ib
[idx
+2] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1850 case PACKET3_EVENT_WRITE
:
1851 if (pkt
->count
!= 2 && pkt
->count
!= 0) {
1852 DRM_ERROR("bad EVENT_WRITE\n");
1858 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1860 DRM_ERROR("bad EVENT_WRITE\n");
1863 offset
= reloc
->lobj
.gpu_offset
+
1864 (radeon_get_ib_value(p
, idx
+1) & 0xfffffff8) +
1865 ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff) << 32);
1867 ib
[idx
+1] = offset
& 0xfffffff8;
1868 ib
[idx
+2] = upper_32_bits(offset
) & 0xff;
1871 case PACKET3_EVENT_WRITE_EOP
:
1875 if (pkt
->count
!= 4) {
1876 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1879 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1881 DRM_ERROR("bad EVENT_WRITE\n");
1885 offset
= reloc
->lobj
.gpu_offset
+
1886 (radeon_get_ib_value(p
, idx
+1) & 0xfffffffc) +
1887 ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff) << 32);
1889 ib
[idx
+1] = offset
& 0xfffffffc;
1890 ib
[idx
+2] = (ib
[idx
+2] & 0xffffff00) | (upper_32_bits(offset
) & 0xff);
1893 case PACKET3_SET_CONFIG_REG
:
1894 start_reg
= (idx_value
<< 2) + PACKET3_SET_CONFIG_REG_OFFSET
;
1895 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1896 if ((start_reg
< PACKET3_SET_CONFIG_REG_OFFSET
) ||
1897 (start_reg
>= PACKET3_SET_CONFIG_REG_END
) ||
1898 (end_reg
>= PACKET3_SET_CONFIG_REG_END
)) {
1899 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1902 for (i
= 0; i
< pkt
->count
; i
++) {
1903 reg
= start_reg
+ (4 * i
);
1904 r
= r600_cs_check_reg(p
, reg
, idx
+1+i
);
1909 case PACKET3_SET_CONTEXT_REG
:
1910 start_reg
= (idx_value
<< 2) + PACKET3_SET_CONTEXT_REG_OFFSET
;
1911 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1912 if ((start_reg
< PACKET3_SET_CONTEXT_REG_OFFSET
) ||
1913 (start_reg
>= PACKET3_SET_CONTEXT_REG_END
) ||
1914 (end_reg
>= PACKET3_SET_CONTEXT_REG_END
)) {
1915 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1918 for (i
= 0; i
< pkt
->count
; i
++) {
1919 reg
= start_reg
+ (4 * i
);
1920 r
= r600_cs_check_reg(p
, reg
, idx
+1+i
);
1925 case PACKET3_SET_RESOURCE
:
1926 if (pkt
->count
% 7) {
1927 DRM_ERROR("bad SET_RESOURCE\n");
1930 start_reg
= (idx_value
<< 2) + PACKET3_SET_RESOURCE_OFFSET
;
1931 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1932 if ((start_reg
< PACKET3_SET_RESOURCE_OFFSET
) ||
1933 (start_reg
>= PACKET3_SET_RESOURCE_END
) ||
1934 (end_reg
>= PACKET3_SET_RESOURCE_END
)) {
1935 DRM_ERROR("bad SET_RESOURCE\n");
1938 for (i
= 0; i
< (pkt
->count
/ 7); i
++) {
1939 struct radeon_bo
*texture
, *mipmap
;
1940 u32 size
, offset
, base_offset
, mip_offset
;
1942 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p
, idx
+(i
*7)+6+1))) {
1943 case SQ_TEX_VTX_VALID_TEXTURE
:
1945 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1947 DRM_ERROR("bad SET_RESOURCE\n");
1950 base_offset
= (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1951 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
1952 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
1953 ib
[idx
+1+(i
*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1954 else if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
1955 ib
[idx
+1+(i
*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1957 texture
= reloc
->robj
;
1959 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1961 DRM_ERROR("bad SET_RESOURCE\n");
1964 mip_offset
= (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1965 mipmap
= reloc
->robj
;
1966 r
= r600_check_texture_resource(p
, idx
+(i
*7)+1,
1968 base_offset
+ radeon_get_ib_value(p
, idx
+1+(i
*7)+2),
1969 mip_offset
+ radeon_get_ib_value(p
, idx
+1+(i
*7)+3),
1970 reloc
->lobj
.tiling_flags
);
1973 ib
[idx
+1+(i
*7)+2] += base_offset
;
1974 ib
[idx
+1+(i
*7)+3] += mip_offset
;
1976 case SQ_TEX_VTX_VALID_BUFFER
:
1980 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
1982 DRM_ERROR("bad SET_RESOURCE\n");
1985 offset
= radeon_get_ib_value(p
, idx
+1+(i
*7)+0);
1986 size
= radeon_get_ib_value(p
, idx
+1+(i
*7)+1) + 1;
1987 if (p
->rdev
&& (size
+ offset
) > radeon_bo_size(reloc
->robj
)) {
1988 /* force size to size of the buffer */
1989 dev_warn(p
->dev
, "vbo resource seems too big (%d) for the bo (%ld)\n",
1990 size
+ offset
, radeon_bo_size(reloc
->robj
));
1991 ib
[idx
+1+(i
*7)+1] = radeon_bo_size(reloc
->robj
) - offset
;
1994 offset64
= reloc
->lobj
.gpu_offset
+ offset
;
1995 ib
[idx
+1+(i
*8)+0] = offset64
;
1996 ib
[idx
+1+(i
*8)+2] = (ib
[idx
+1+(i
*8)+2] & 0xffffff00) |
1997 (upper_32_bits(offset64
) & 0xff);
2000 case SQ_TEX_VTX_INVALID_TEXTURE
:
2001 case SQ_TEX_VTX_INVALID_BUFFER
:
2003 DRM_ERROR("bad SET_RESOURCE\n");
2008 case PACKET3_SET_ALU_CONST
:
2009 if (track
->sq_config
& DX9_CONSTS
) {
2010 start_reg
= (idx_value
<< 2) + PACKET3_SET_ALU_CONST_OFFSET
;
2011 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2012 if ((start_reg
< PACKET3_SET_ALU_CONST_OFFSET
) ||
2013 (start_reg
>= PACKET3_SET_ALU_CONST_END
) ||
2014 (end_reg
>= PACKET3_SET_ALU_CONST_END
)) {
2015 DRM_ERROR("bad SET_ALU_CONST\n");
2020 case PACKET3_SET_BOOL_CONST
:
2021 start_reg
= (idx_value
<< 2) + PACKET3_SET_BOOL_CONST_OFFSET
;
2022 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2023 if ((start_reg
< PACKET3_SET_BOOL_CONST_OFFSET
) ||
2024 (start_reg
>= PACKET3_SET_BOOL_CONST_END
) ||
2025 (end_reg
>= PACKET3_SET_BOOL_CONST_END
)) {
2026 DRM_ERROR("bad SET_BOOL_CONST\n");
2030 case PACKET3_SET_LOOP_CONST
:
2031 start_reg
= (idx_value
<< 2) + PACKET3_SET_LOOP_CONST_OFFSET
;
2032 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2033 if ((start_reg
< PACKET3_SET_LOOP_CONST_OFFSET
) ||
2034 (start_reg
>= PACKET3_SET_LOOP_CONST_END
) ||
2035 (end_reg
>= PACKET3_SET_LOOP_CONST_END
)) {
2036 DRM_ERROR("bad SET_LOOP_CONST\n");
2040 case PACKET3_SET_CTL_CONST
:
2041 start_reg
= (idx_value
<< 2) + PACKET3_SET_CTL_CONST_OFFSET
;
2042 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2043 if ((start_reg
< PACKET3_SET_CTL_CONST_OFFSET
) ||
2044 (start_reg
>= PACKET3_SET_CTL_CONST_END
) ||
2045 (end_reg
>= PACKET3_SET_CTL_CONST_END
)) {
2046 DRM_ERROR("bad SET_CTL_CONST\n");
2050 case PACKET3_SET_SAMPLER
:
2051 if (pkt
->count
% 3) {
2052 DRM_ERROR("bad SET_SAMPLER\n");
2055 start_reg
= (idx_value
<< 2) + PACKET3_SET_SAMPLER_OFFSET
;
2056 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2057 if ((start_reg
< PACKET3_SET_SAMPLER_OFFSET
) ||
2058 (start_reg
>= PACKET3_SET_SAMPLER_END
) ||
2059 (end_reg
>= PACKET3_SET_SAMPLER_END
)) {
2060 DRM_ERROR("bad SET_SAMPLER\n");
2064 case PACKET3_STRMOUT_BASE_UPDATE
:
2065 /* RS780 and RS880 also need this */
2066 if (p
->family
< CHIP_RS780
) {
2067 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2070 if (pkt
->count
!= 1) {
2071 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2074 if (idx_value
> 3) {
2075 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2081 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
2083 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2087 if (reloc
->robj
!= track
->vgt_strmout_bo
[idx_value
]) {
2088 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2092 offset
= radeon_get_ib_value(p
, idx
+1) << 8;
2093 if (offset
!= track
->vgt_strmout_bo_offset
[idx_value
]) {
2094 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2095 offset
, track
->vgt_strmout_bo_offset
[idx_value
]);
2099 if ((offset
+ 4) > radeon_bo_size(reloc
->robj
)) {
2100 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2101 offset
+ 4, radeon_bo_size(reloc
->robj
));
2104 ib
[idx
+1] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
2107 case PACKET3_SURFACE_BASE_UPDATE
:
2108 if (p
->family
>= CHIP_RV770
|| p
->family
== CHIP_R600
) {
2109 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2113 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2117 case PACKET3_STRMOUT_BUFFER_UPDATE
:
2118 if (pkt
->count
!= 4) {
2119 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2122 /* Updating memory at DST_ADDRESS. */
2123 if (idx_value
& 0x1) {
2125 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
2127 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2130 offset
= radeon_get_ib_value(p
, idx
+1);
2131 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff)) << 32;
2132 if ((offset
+ 4) > radeon_bo_size(reloc
->robj
)) {
2133 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2134 offset
+ 4, radeon_bo_size(reloc
->robj
));
2137 offset
+= reloc
->lobj
.gpu_offset
;
2139 ib
[idx
+2] = upper_32_bits(offset
) & 0xff;
2141 /* Reading data from SRC_ADDRESS. */
2142 if (((idx_value
>> 1) & 0x3) == 2) {
2144 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
2146 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2149 offset
= radeon_get_ib_value(p
, idx
+3);
2150 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+4) & 0xff)) << 32;
2151 if ((offset
+ 4) > radeon_bo_size(reloc
->robj
)) {
2152 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2153 offset
+ 4, radeon_bo_size(reloc
->robj
));
2156 offset
+= reloc
->lobj
.gpu_offset
;
2158 ib
[idx
+4] = upper_32_bits(offset
) & 0xff;
2161 case PACKET3_MEM_WRITE
:
2165 if (pkt
->count
!= 3) {
2166 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2169 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
2171 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2174 offset
= radeon_get_ib_value(p
, idx
+0);
2175 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+1) & 0xff)) << 32UL;
2177 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2180 if ((offset
+ 8) > radeon_bo_size(reloc
->robj
)) {
2181 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
2182 offset
+ 8, radeon_bo_size(reloc
->robj
));
2185 offset
+= reloc
->lobj
.gpu_offset
;
2187 ib
[idx
+1] = upper_32_bits(offset
) & 0xff;
2190 case PACKET3_COPY_DW
:
2191 if (pkt
->count
!= 4) {
2192 DRM_ERROR("bad COPY_DW (invalid count)\n");
2195 if (idx_value
& 0x1) {
2197 /* SRC is memory. */
2198 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
2200 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2203 offset
= radeon_get_ib_value(p
, idx
+1);
2204 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff)) << 32;
2205 if ((offset
+ 4) > radeon_bo_size(reloc
->robj
)) {
2206 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2207 offset
+ 4, radeon_bo_size(reloc
->robj
));
2210 offset
+= reloc
->lobj
.gpu_offset
;
2212 ib
[idx
+2] = upper_32_bits(offset
) & 0xff;
2215 reg
= radeon_get_ib_value(p
, idx
+1) << 2;
2216 if (!r600_is_safe_reg(p
, reg
, idx
+1))
2219 if (idx_value
& 0x2) {
2221 /* DST is memory. */
2222 r
= radeon_cs_packet_next_reloc(p
, &reloc
, r600_nomm
);
2224 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2227 offset
= radeon_get_ib_value(p
, idx
+3);
2228 offset
+= ((u64
)(radeon_get_ib_value(p
, idx
+4) & 0xff)) << 32;
2229 if ((offset
+ 4) > radeon_bo_size(reloc
->robj
)) {
2230 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2231 offset
+ 4, radeon_bo_size(reloc
->robj
));
2234 offset
+= reloc
->lobj
.gpu_offset
;
2236 ib
[idx
+4] = upper_32_bits(offset
) & 0xff;
2239 reg
= radeon_get_ib_value(p
, idx
+3) << 2;
2240 if (!r600_is_safe_reg(p
, reg
, idx
+3))
2247 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
2253 int r600_cs_parse(struct radeon_cs_parser
*p
)
2255 struct radeon_cs_packet pkt
;
2256 struct r600_cs_track
*track
;
2259 if (p
->track
== NULL
) {
2260 /* initialize tracker, we are in kms */
2261 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
2264 r600_cs_track_init(track
);
2265 if (p
->rdev
->family
< CHIP_RV770
) {
2266 track
->npipes
= p
->rdev
->config
.r600
.tiling_npipes
;
2267 track
->nbanks
= p
->rdev
->config
.r600
.tiling_nbanks
;
2268 track
->group_size
= p
->rdev
->config
.r600
.tiling_group_size
;
2269 } else if (p
->rdev
->family
<= CHIP_RV740
) {
2270 track
->npipes
= p
->rdev
->config
.rv770
.tiling_npipes
;
2271 track
->nbanks
= p
->rdev
->config
.rv770
.tiling_nbanks
;
2272 track
->group_size
= p
->rdev
->config
.rv770
.tiling_group_size
;
2277 r
= radeon_cs_packet_parse(p
, &pkt
, p
->idx
);
2283 p
->idx
+= pkt
.count
+ 2;
2285 case RADEON_PACKET_TYPE0
:
2286 r
= r600_cs_parse_packet0(p
, &pkt
);
2288 case RADEON_PACKET_TYPE2
:
2290 case RADEON_PACKET_TYPE3
:
2291 r
= r600_packet3_check(p
, &pkt
);
2294 DRM_ERROR("Unknown packet type %d !\n", pkt
.type
);
2304 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
2306 for (r
= 0; r
< p
->ib
.length_dw
; r
++) {
2307 printk(KERN_INFO
"%05d 0x%08X\n", r
, p
->ib
.ptr
[r
]);
2316 #ifdef CONFIG_DRM_RADEON_UMS
2319 * cs_parser_fini() - clean parser states
2320 * @parser: parser structure holding parsing context.
2321 * @error: error number
2323 * If error is set than unvalidate buffer, otherwise just free memory
2324 * used by parsing context.
2326 static void r600_cs_parser_fini(struct radeon_cs_parser
*parser
, int error
)
2330 kfree(parser
->relocs
);
2331 for (i
= 0; i
< parser
->nchunks
; i
++) {
2332 kfree(parser
->chunks
[i
].kdata
);
2333 if (parser
->rdev
&& (parser
->rdev
->flags
& RADEON_IS_AGP
)) {
2334 kfree(parser
->chunks
[i
].kpage
[0]);
2335 kfree(parser
->chunks
[i
].kpage
[1]);
2338 kfree(parser
->chunks
);
2339 kfree(parser
->chunks_array
);
2342 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser
*p
)
2344 if (p
->chunk_relocs_idx
== -1) {
2347 p
->relocs
= kzalloc(sizeof(struct radeon_cs_reloc
), GFP_KERNEL
);
2348 if (p
->relocs
== NULL
) {
2354 int r600_cs_legacy(struct drm_device
*dev
, void *data
, struct drm_file
*filp
,
2355 unsigned family
, u32
*ib
, int *l
)
2357 struct radeon_cs_parser parser
;
2358 struct radeon_cs_chunk
*ib_chunk
;
2359 struct r600_cs_track
*track
;
2362 /* initialize tracker */
2363 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
2366 r600_cs_track_init(track
);
2367 r600_cs_legacy_get_tiling_conf(dev
, &track
->npipes
, &track
->nbanks
, &track
->group_size
);
2368 /* initialize parser */
2369 memset(&parser
, 0, sizeof(struct radeon_cs_parser
));
2371 parser
.dev
= &dev
->pdev
->dev
;
2373 parser
.family
= family
;
2374 parser
.track
= track
;
2376 r
= radeon_cs_parser_init(&parser
, data
);
2378 DRM_ERROR("Failed to initialize parser !\n");
2379 r600_cs_parser_fini(&parser
, r
);
2382 r
= r600_cs_parser_relocs_legacy(&parser
);
2384 DRM_ERROR("Failed to parse relocation !\n");
2385 r600_cs_parser_fini(&parser
, r
);
2388 /* Copy the packet into the IB, the parser will read from the
2389 * input memory (cached) and write to the IB (which can be
2391 ib_chunk
= &parser
.chunks
[parser
.chunk_ib_idx
];
2392 parser
.ib
.length_dw
= ib_chunk
->length_dw
;
2393 *l
= parser
.ib
.length_dw
;
2394 r
= r600_cs_parse(&parser
);
2396 DRM_ERROR("Invalid command stream !\n");
2397 r600_cs_parser_fini(&parser
, r
);
2400 r
= radeon_cs_finish_pages(&parser
);
2402 DRM_ERROR("Invalid command stream !\n");
2403 r600_cs_parser_fini(&parser
, r
);
2406 r600_cs_parser_fini(&parser
, r
);
2410 void r600_cs_legacy_init(void)
2421 * r600_dma_cs_next_reloc() - parse next reloc
2422 * @p: parser structure holding parsing context.
2423 * @cs_reloc: reloc informations
2425 * Return the next reloc, do bo validation and compute
2426 * GPU offset using the provided start.
2428 int r600_dma_cs_next_reloc(struct radeon_cs_parser
*p
,
2429 struct radeon_cs_reloc
**cs_reloc
)
2431 struct radeon_cs_chunk
*relocs_chunk
;
2435 if (p
->chunk_relocs_idx
== -1) {
2436 DRM_ERROR("No relocation chunk !\n");
2439 relocs_chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
2440 idx
= p
->dma_reloc_idx
;
2441 if (idx
>= p
->nrelocs
) {
2442 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
2446 *cs_reloc
= p
->relocs_ptr
[idx
];
2451 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2452 #define GET_DMA_COUNT(h) ((h) & 0x0000ffff)
2453 #define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2456 * r600_dma_cs_parse() - parse the DMA IB
2457 * @p: parser structure holding parsing context.
2459 * Parses the DMA IB from the CS ioctl and updates
2460 * the GPU addresses based on the reloc information and
2461 * checks for errors. (R6xx-R7xx)
2462 * Returns 0 for success and an error on failure.
2464 int r600_dma_cs_parse(struct radeon_cs_parser
*p
)
2466 struct radeon_cs_chunk
*ib_chunk
= &p
->chunks
[p
->chunk_ib_idx
];
2467 struct radeon_cs_reloc
*src_reloc
, *dst_reloc
;
2468 u32 header
, cmd
, count
, tiled
;
2469 volatile u32
*ib
= p
->ib
.ptr
;
2471 u64 src_offset
, dst_offset
;
2475 if (p
->idx
>= ib_chunk
->length_dw
) {
2476 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2477 p
->idx
, ib_chunk
->length_dw
);
2481 header
= radeon_get_ib_value(p
, idx
);
2482 cmd
= GET_DMA_CMD(header
);
2483 count
= GET_DMA_COUNT(header
);
2484 tiled
= GET_DMA_T(header
);
2487 case DMA_PACKET_WRITE
:
2488 r
= r600_dma_cs_next_reloc(p
, &dst_reloc
);
2490 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2494 dst_offset
= radeon_get_ib_value(p
, idx
+1);
2497 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
2498 p
->idx
+= count
+ 5;
2500 dst_offset
= radeon_get_ib_value(p
, idx
+1);
2501 dst_offset
|= ((u64
)(radeon_get_ib_value(p
, idx
+2) & 0xff)) << 32;
2503 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2504 ib
[idx
+2] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
2505 p
->idx
+= count
+ 3;
2507 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
2508 dev_warn(p
->dev
, "DMA write buffer too small (%llu %lu)\n",
2509 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
2513 case DMA_PACKET_COPY
:
2514 r
= r600_dma_cs_next_reloc(p
, &src_reloc
);
2516 DRM_ERROR("bad DMA_PACKET_COPY\n");
2519 r
= r600_dma_cs_next_reloc(p
, &dst_reloc
);
2521 DRM_ERROR("bad DMA_PACKET_COPY\n");
2525 idx_value
= radeon_get_ib_value(p
, idx
+ 2);
2527 if (idx_value
& (1 << 31)) {
2528 /* tiled src, linear dst */
2529 src_offset
= radeon_get_ib_value(p
, idx
+1);
2531 ib
[idx
+1] += (u32
)(src_reloc
->lobj
.gpu_offset
>> 8);
2533 dst_offset
= radeon_get_ib_value(p
, idx
+5);
2534 dst_offset
|= ((u64
)(radeon_get_ib_value(p
, idx
+6) & 0xff)) << 32;
2535 ib
[idx
+5] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2536 ib
[idx
+6] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
2538 /* linear src, tiled dst */
2539 src_offset
= radeon_get_ib_value(p
, idx
+5);
2540 src_offset
|= ((u64
)(radeon_get_ib_value(p
, idx
+6) & 0xff)) << 32;
2541 ib
[idx
+5] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2542 ib
[idx
+6] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
2544 dst_offset
= radeon_get_ib_value(p
, idx
+1);
2546 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
>> 8);
2550 if (p
->family
>= CHIP_RV770
) {
2551 src_offset
= radeon_get_ib_value(p
, idx
+2);
2552 src_offset
|= ((u64
)(radeon_get_ib_value(p
, idx
+4) & 0xff)) << 32;
2553 dst_offset
= radeon_get_ib_value(p
, idx
+1);
2554 dst_offset
|= ((u64
)(radeon_get_ib_value(p
, idx
+3) & 0xff)) << 32;
2556 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2557 ib
[idx
+2] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2558 ib
[idx
+3] += upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff;
2559 ib
[idx
+4] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
2562 src_offset
= radeon_get_ib_value(p
, idx
+2);
2563 src_offset
|= ((u64
)(radeon_get_ib_value(p
, idx
+3) & 0xff)) << 32;
2564 dst_offset
= radeon_get_ib_value(p
, idx
+1);
2565 dst_offset
|= ((u64
)(radeon_get_ib_value(p
, idx
+3) & 0xff0000)) << 16;
2567 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2568 ib
[idx
+2] += (u32
)(src_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2569 ib
[idx
+3] += upper_32_bits(src_reloc
->lobj
.gpu_offset
) & 0xff;
2570 ib
[idx
+3] += (upper_32_bits(dst_reloc
->lobj
.gpu_offset
) & 0xff) << 16;
2574 if ((src_offset
+ (count
* 4)) > radeon_bo_size(src_reloc
->robj
)) {
2575 dev_warn(p
->dev
, "DMA copy src buffer too small (%llu %lu)\n",
2576 src_offset
+ (count
* 4), radeon_bo_size(src_reloc
->robj
));
2579 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
2580 dev_warn(p
->dev
, "DMA write dst buffer too small (%llu %lu)\n",
2581 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
2585 case DMA_PACKET_CONSTANT_FILL
:
2586 if (p
->family
< CHIP_RV770
) {
2587 DRM_ERROR("Constant Fill is 7xx only !\n");
2590 r
= r600_dma_cs_next_reloc(p
, &dst_reloc
);
2592 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2595 dst_offset
= radeon_get_ib_value(p
, idx
+1);
2596 dst_offset
|= ((u64
)(radeon_get_ib_value(p
, idx
+3) & 0x00ff0000)) << 16;
2597 if ((dst_offset
+ (count
* 4)) > radeon_bo_size(dst_reloc
->robj
)) {
2598 dev_warn(p
->dev
, "DMA constant fill buffer too small (%llu %lu)\n",
2599 dst_offset
+ (count
* 4), radeon_bo_size(dst_reloc
->robj
));
2602 ib
[idx
+1] += (u32
)(dst_reloc
->lobj
.gpu_offset
& 0xfffffffc);
2603 ib
[idx
+3] += (upper_32_bits(dst_reloc
->lobj
.gpu_offset
) << 16) & 0x00ff0000;
2606 case DMA_PACKET_NOP
:
2610 DRM_ERROR("Unknown packet type %d at %d !\n", cmd
, idx
);
2613 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
2615 for (r
= 0; r
< p
->ib
->length_dw
; r
++) {
2616 printk(KERN_INFO
"%05d 0x%08X\n", r
, p
->ib
.ptr
[r
]);