2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
31 const u32 r600_utc
[R600_PM_NUMBER_OF_TC
] =
50 const u32 r600_dtc
[R600_PM_NUMBER_OF_TC
] =
69 void r600_dpm_print_class_info(u32
class, u32 class2
)
71 printk("\tui class: ");
72 switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
73 case ATOM_PPLIB_CLASSIFICATION_UI_NONE
:
77 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
80 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
:
83 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
84 printk("performance\n");
87 printk("\tinternal class: ");
88 if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK
) == 0) &&
92 if (class & ATOM_PPLIB_CLASSIFICATION_BOOT
)
94 if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
96 if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE
)
97 printk("limited_pwr ");
98 if (class & ATOM_PPLIB_CLASSIFICATION_REST
)
100 if (class & ATOM_PPLIB_CLASSIFICATION_FORCED
)
102 if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
104 if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE
)
106 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
)
108 if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW
)
110 if (class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
112 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
114 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
116 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
118 if (class2
& ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2
)
119 printk("limited_pwr2 ");
120 if (class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
122 if (class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
128 void r600_dpm_print_cap_info(u32 caps
)
131 if (caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
)
132 printk("single_disp ");
133 if (caps
& ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK
)
135 if (caps
& ATOM_PPLIB_DISALLOW_ON_DC
)
140 void r600_dpm_print_ps_status(struct radeon_device
*rdev
,
141 struct radeon_ps
*rps
)
143 printk("\tstatus: ");
144 if (rps
== rdev
->pm
.dpm
.current_ps
)
146 if (rps
== rdev
->pm
.dpm
.requested_ps
)
148 if (rps
== rdev
->pm
.dpm
.boot_ps
)
153 u32
r600_dpm_get_vblank_time(struct radeon_device
*rdev
)
155 struct drm_device
*dev
= rdev
->ddev
;
156 struct drm_crtc
*crtc
;
157 struct radeon_crtc
*radeon_crtc
;
158 u32 line_time_us
, vblank_lines
;
159 u32 vblank_time_us
= 0xffffffff; /* if the displays are off, vblank time is max */
161 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
162 radeon_crtc
= to_radeon_crtc(crtc
);
163 if (crtc
->enabled
&& radeon_crtc
->enabled
&& radeon_crtc
->hw_mode
.clock
) {
164 line_time_us
= (radeon_crtc
->hw_mode
.crtc_htotal
* 1000) /
165 radeon_crtc
->hw_mode
.clock
;
166 vblank_lines
= radeon_crtc
->hw_mode
.crtc_vblank_end
-
167 radeon_crtc
->hw_mode
.crtc_vdisplay
+
168 (radeon_crtc
->v_border
* 2);
169 vblank_time_us
= vblank_lines
* line_time_us
;
174 return vblank_time_us
;
177 void r600_calculate_u_and_p(u32 i
, u32 r_c
, u32 p_b
,
184 i_c
= (i
* r_c
) / 100;
193 *p
= i_c
/ (1 << (2 * (*u
)));
196 int r600_calculate_at(u32 t
, u32 h
, u32 fh
, u32 fl
, u32
*tl
, u32
*th
)
201 if ((fl
== 0) || (fh
== 0) || (fl
> fh
))
205 t1
= (t
* (k
- 100));
206 a
= (1000 * (100 * h
+ t1
)) / (10000 + (t1
/ 100));
208 ah
= ((a
* t
) + 5000) / 10000;
217 void r600_gfx_clockgating_enable(struct radeon_device
*rdev
, bool enable
)
222 WREG32_P(SCLK_PWRMGT_CNTL
, DYN_GFX_CLK_OFF_EN
, ~DYN_GFX_CLK_OFF_EN
);
224 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~DYN_GFX_CLK_OFF_EN
);
226 WREG32(CG_RLC_REQ_AND_RSP
, 0x2);
228 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
229 if (((RREG32(CG_RLC_REQ_AND_RSP
) & CG_RLC_RSP_TYPE_MASK
) >> CG_RLC_RSP_TYPE_SHIFT
) == 1)
234 WREG32(CG_RLC_REQ_AND_RSP
, 0x0);
236 WREG32(GRBM_PWR_CNTL
, 0x1);
237 RREG32(GRBM_PWR_CNTL
);
241 void r600_dynamicpm_enable(struct radeon_device
*rdev
, bool enable
)
244 WREG32_P(GENERAL_PWRMGT
, GLOBAL_PWRMGT_EN
, ~GLOBAL_PWRMGT_EN
);
246 WREG32_P(GENERAL_PWRMGT
, 0, ~GLOBAL_PWRMGT_EN
);
249 void r600_enable_thermal_protection(struct radeon_device
*rdev
, bool enable
)
252 WREG32_P(GENERAL_PWRMGT
, 0, ~THERMAL_PROTECTION_DIS
);
254 WREG32_P(GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, ~THERMAL_PROTECTION_DIS
);
257 void r600_enable_acpi_pm(struct radeon_device
*rdev
)
259 WREG32_P(GENERAL_PWRMGT
, STATIC_PM_EN
, ~STATIC_PM_EN
);
262 void r600_enable_dynamic_pcie_gen2(struct radeon_device
*rdev
, bool enable
)
265 WREG32_P(GENERAL_PWRMGT
, ENABLE_GEN2PCIE
, ~ENABLE_GEN2PCIE
);
267 WREG32_P(GENERAL_PWRMGT
, 0, ~ENABLE_GEN2PCIE
);
270 bool r600_dynamicpm_enabled(struct radeon_device
*rdev
)
272 if (RREG32(GENERAL_PWRMGT
) & GLOBAL_PWRMGT_EN
)
278 void r600_enable_sclk_control(struct radeon_device
*rdev
, bool enable
)
281 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~SCLK_PWRMGT_OFF
);
283 WREG32_P(SCLK_PWRMGT_CNTL
, SCLK_PWRMGT_OFF
, ~SCLK_PWRMGT_OFF
);
286 void r600_enable_mclk_control(struct radeon_device
*rdev
, bool enable
)
289 WREG32_P(MCLK_PWRMGT_CNTL
, 0, ~MPLL_PWRMGT_OFF
);
291 WREG32_P(MCLK_PWRMGT_CNTL
, MPLL_PWRMGT_OFF
, ~MPLL_PWRMGT_OFF
);
294 void r600_enable_spll_bypass(struct radeon_device
*rdev
, bool enable
)
297 WREG32_P(CG_SPLL_FUNC_CNTL
, SPLL_BYPASS_EN
, ~SPLL_BYPASS_EN
);
299 WREG32_P(CG_SPLL_FUNC_CNTL
, 0, ~SPLL_BYPASS_EN
);
302 void r600_wait_for_spll_change(struct radeon_device
*rdev
)
306 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
307 if (RREG32(CG_SPLL_FUNC_CNTL
) & SPLL_CHG_STATUS
)
313 void r600_set_bsp(struct radeon_device
*rdev
, u32 u
, u32 p
)
315 WREG32(CG_BSP
, BSP(p
) | BSU(u
));
318 void r600_set_at(struct radeon_device
*rdev
,
319 u32 l_to_m
, u32 m_to_h
,
320 u32 h_to_m
, u32 m_to_l
)
322 WREG32(CG_RT
, FLS(l_to_m
) | FMS(m_to_h
));
323 WREG32(CG_LT
, FHS(h_to_m
) | FMS(m_to_l
));
326 void r600_set_tc(struct radeon_device
*rdev
,
327 u32 index
, u32 u_t
, u32 d_t
)
329 WREG32(CG_FFCT_0
+ (index
* 4), UTC_0(u_t
) | DTC_0(d_t
));
332 void r600_select_td(struct radeon_device
*rdev
,
335 if (td
== R600_TD_AUTO
)
336 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_FORCE_TREND_SEL
);
338 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_FORCE_TREND_SEL
, ~FIR_FORCE_TREND_SEL
);
339 if (td
== R600_TD_UP
)
340 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_TREND_MODE
);
341 if (td
== R600_TD_DOWN
)
342 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_TREND_MODE
, ~FIR_TREND_MODE
);
345 void r600_set_vrc(struct radeon_device
*rdev
, u32 vrv
)
350 void r600_set_tpu(struct radeon_device
*rdev
, u32 u
)
352 WREG32_P(CG_TPC
, TPU(u
), ~TPU_MASK
);
355 void r600_set_tpc(struct radeon_device
*rdev
, u32 c
)
357 WREG32_P(CG_TPC
, TPCC(c
), ~TPCC_MASK
);
360 void r600_set_sstu(struct radeon_device
*rdev
, u32 u
)
362 WREG32_P(CG_SSP
, CG_SSTU(u
), ~CG_SSTU_MASK
);
365 void r600_set_sst(struct radeon_device
*rdev
, u32 t
)
367 WREG32_P(CG_SSP
, CG_SST(t
), ~CG_SST_MASK
);
370 void r600_set_git(struct radeon_device
*rdev
, u32 t
)
372 WREG32_P(CG_GIT
, CG_GICST(t
), ~CG_GICST_MASK
);
375 void r600_set_fctu(struct radeon_device
*rdev
, u32 u
)
377 WREG32_P(CG_FC_T
, FC_TU(u
), ~FC_TU_MASK
);
380 void r600_set_fct(struct radeon_device
*rdev
, u32 t
)
382 WREG32_P(CG_FC_T
, FC_T(t
), ~FC_T_MASK
);
385 void r600_set_ctxcgtt3d_rphc(struct radeon_device
*rdev
, u32 p
)
387 WREG32_P(CG_CTX_CGTT3D_R
, PHC(p
), ~PHC_MASK
);
390 void r600_set_ctxcgtt3d_rsdc(struct radeon_device
*rdev
, u32 s
)
392 WREG32_P(CG_CTX_CGTT3D_R
, SDC(s
), ~SDC_MASK
);
395 void r600_set_vddc3d_oorsu(struct radeon_device
*rdev
, u32 u
)
397 WREG32_P(CG_VDDC3D_OOR
, SU(u
), ~SU_MASK
);
400 void r600_set_vddc3d_oorphc(struct radeon_device
*rdev
, u32 p
)
402 WREG32_P(CG_VDDC3D_OOR
, PHC(p
), ~PHC_MASK
);
405 void r600_set_vddc3d_oorsdc(struct radeon_device
*rdev
, u32 s
)
407 WREG32_P(CG_VDDC3D_OOR
, SDC(s
), ~SDC_MASK
);
410 void r600_set_mpll_lock_time(struct radeon_device
*rdev
, u32 lock_time
)
412 WREG32_P(MPLL_TIME
, MPLL_LOCK_TIME(lock_time
), ~MPLL_LOCK_TIME_MASK
);
415 void r600_set_mpll_reset_time(struct radeon_device
*rdev
, u32 reset_time
)
417 WREG32_P(MPLL_TIME
, MPLL_RESET_TIME(reset_time
), ~MPLL_RESET_TIME_MASK
);
420 void r600_engine_clock_entry_enable(struct radeon_device
*rdev
,
421 u32 index
, bool enable
)
424 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2
+ (index
* 4 * 2),
425 STEP_0_SPLL_ENTRY_VALID
, ~STEP_0_SPLL_ENTRY_VALID
);
427 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2
+ (index
* 4 * 2),
428 0, ~STEP_0_SPLL_ENTRY_VALID
);
431 void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device
*rdev
,
432 u32 index
, bool enable
)
435 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2
+ (index
* 4 * 2),
436 STEP_0_SPLL_STEP_ENABLE
, ~STEP_0_SPLL_STEP_ENABLE
);
438 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2
+ (index
* 4 * 2),
439 0, ~STEP_0_SPLL_STEP_ENABLE
);
442 void r600_engine_clock_entry_enable_post_divider(struct radeon_device
*rdev
,
443 u32 index
, bool enable
)
446 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2
+ (index
* 4 * 2),
447 STEP_0_POST_DIV_EN
, ~STEP_0_POST_DIV_EN
);
449 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2
+ (index
* 4 * 2),
450 0, ~STEP_0_POST_DIV_EN
);
453 void r600_engine_clock_entry_set_post_divider(struct radeon_device
*rdev
,
454 u32 index
, u32 divider
)
456 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1
+ (index
* 4 * 2),
457 STEP_0_SPLL_POST_DIV(divider
), ~STEP_0_SPLL_POST_DIV_MASK
);
460 void r600_engine_clock_entry_set_reference_divider(struct radeon_device
*rdev
,
461 u32 index
, u32 divider
)
463 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1
+ (index
* 4 * 2),
464 STEP_0_SPLL_REF_DIV(divider
), ~STEP_0_SPLL_REF_DIV_MASK
);
467 void r600_engine_clock_entry_set_feedback_divider(struct radeon_device
*rdev
,
468 u32 index
, u32 divider
)
470 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1
+ (index
* 4 * 2),
471 STEP_0_SPLL_FB_DIV(divider
), ~STEP_0_SPLL_FB_DIV_MASK
);
474 void r600_engine_clock_entry_set_step_time(struct radeon_device
*rdev
,
475 u32 index
, u32 step_time
)
477 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1
+ (index
* 4 * 2),
478 STEP_0_SPLL_STEP_TIME(step_time
), ~STEP_0_SPLL_STEP_TIME_MASK
);
481 void r600_vid_rt_set_ssu(struct radeon_device
*rdev
, u32 u
)
483 WREG32_P(VID_RT
, SSTU(u
), ~SSTU_MASK
);
486 void r600_vid_rt_set_vru(struct radeon_device
*rdev
, u32 u
)
488 WREG32_P(VID_RT
, VID_CRTU(u
), ~VID_CRTU_MASK
);
491 void r600_vid_rt_set_vrt(struct radeon_device
*rdev
, u32 rt
)
493 WREG32_P(VID_RT
, VID_CRT(rt
), ~VID_CRT_MASK
);
496 void r600_voltage_control_enable_pins(struct radeon_device
*rdev
,
499 WREG32(LOWER_GPIO_ENABLE
, mask
& 0xffffffff);
500 WREG32(UPPER_GPIO_ENABLE
, upper_32_bits(mask
));
504 void r600_voltage_control_program_voltages(struct radeon_device
*rdev
,
505 enum r600_power_level index
, u64 pins
)
508 u32 ix
= 3 - (3 & index
);
510 WREG32(CTXSW_VID_LOWER_GPIO_CNTL
+ (ix
* 4), pins
& 0xffffffff);
512 mask
= 7 << (3 * ix
);
513 tmp
= RREG32(VID_UPPER_GPIO_CNTL
);
514 tmp
= (tmp
& ~mask
) | ((pins
>> (32 - (3 * ix
))) & mask
);
515 WREG32(VID_UPPER_GPIO_CNTL
, tmp
);
518 void r600_voltage_control_deactivate_static_control(struct radeon_device
*rdev
,
523 gpio
= RREG32(GPIOPAD_MASK
);
525 WREG32(GPIOPAD_MASK
, gpio
);
527 gpio
= RREG32(GPIOPAD_EN
);
529 WREG32(GPIOPAD_EN
, gpio
);
531 gpio
= RREG32(GPIOPAD_A
);
533 WREG32(GPIOPAD_A
, gpio
);
536 void r600_power_level_enable(struct radeon_device
*rdev
,
537 enum r600_power_level index
, bool enable
)
539 u32 ix
= 3 - (3 & index
);
542 WREG32_P(CTXSW_PROFILE_INDEX
+ (ix
* 4), CTXSW_FREQ_STATE_ENABLE
,
543 ~CTXSW_FREQ_STATE_ENABLE
);
545 WREG32_P(CTXSW_PROFILE_INDEX
+ (ix
* 4), 0,
546 ~CTXSW_FREQ_STATE_ENABLE
);
549 void r600_power_level_set_voltage_index(struct radeon_device
*rdev
,
550 enum r600_power_level index
, u32 voltage_index
)
552 u32 ix
= 3 - (3 & index
);
554 WREG32_P(CTXSW_PROFILE_INDEX
+ (ix
* 4),
555 CTXSW_FREQ_VIDS_CFG_INDEX(voltage_index
), ~CTXSW_FREQ_VIDS_CFG_INDEX_MASK
);
558 void r600_power_level_set_mem_clock_index(struct radeon_device
*rdev
,
559 enum r600_power_level index
, u32 mem_clock_index
)
561 u32 ix
= 3 - (3 & index
);
563 WREG32_P(CTXSW_PROFILE_INDEX
+ (ix
* 4),
564 CTXSW_FREQ_MCLK_CFG_INDEX(mem_clock_index
), ~CTXSW_FREQ_MCLK_CFG_INDEX_MASK
);
567 void r600_power_level_set_eng_clock_index(struct radeon_device
*rdev
,
568 enum r600_power_level index
, u32 eng_clock_index
)
570 u32 ix
= 3 - (3 & index
);
572 WREG32_P(CTXSW_PROFILE_INDEX
+ (ix
* 4),
573 CTXSW_FREQ_SCLK_CFG_INDEX(eng_clock_index
), ~CTXSW_FREQ_SCLK_CFG_INDEX_MASK
);
576 void r600_power_level_set_watermark_id(struct radeon_device
*rdev
,
577 enum r600_power_level index
,
578 enum r600_display_watermark watermark_id
)
580 u32 ix
= 3 - (3 & index
);
583 if (watermark_id
== R600_DISPLAY_WATERMARK_HIGH
)
584 tmp
= CTXSW_FREQ_DISPLAY_WATERMARK
;
585 WREG32_P(CTXSW_PROFILE_INDEX
+ (ix
* 4), tmp
, ~CTXSW_FREQ_DISPLAY_WATERMARK
);
588 void r600_power_level_set_pcie_gen2(struct radeon_device
*rdev
,
589 enum r600_power_level index
, bool compatible
)
591 u32 ix
= 3 - (3 & index
);
595 tmp
= CTXSW_FREQ_GEN2PCIE_VOLT
;
596 WREG32_P(CTXSW_PROFILE_INDEX
+ (ix
* 4), tmp
, ~CTXSW_FREQ_GEN2PCIE_VOLT
);
599 enum r600_power_level
r600_power_level_get_current_index(struct radeon_device
*rdev
)
603 tmp
= RREG32(TARGET_AND_CURRENT_PROFILE_INDEX
) & CURRENT_PROFILE_INDEX_MASK
;
604 tmp
>>= CURRENT_PROFILE_INDEX_SHIFT
;
608 enum r600_power_level
r600_power_level_get_target_index(struct radeon_device
*rdev
)
612 tmp
= RREG32(TARGET_AND_CURRENT_PROFILE_INDEX
) & TARGET_PROFILE_INDEX_MASK
;
613 tmp
>>= TARGET_PROFILE_INDEX_SHIFT
;
617 void r600_power_level_set_enter_index(struct radeon_device
*rdev
,
618 enum r600_power_level index
)
620 WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX
, DYN_PWR_ENTER_INDEX(index
),
621 ~DYN_PWR_ENTER_INDEX_MASK
);
624 void r600_wait_for_power_level_unequal(struct radeon_device
*rdev
,
625 enum r600_power_level index
)
629 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
630 if (r600_power_level_get_target_index(rdev
) != index
)
635 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
636 if (r600_power_level_get_current_index(rdev
) != index
)
642 void r600_wait_for_power_level(struct radeon_device
*rdev
,
643 enum r600_power_level index
)
647 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
648 if (r600_power_level_get_target_index(rdev
) == index
)
653 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
654 if (r600_power_level_get_current_index(rdev
) == index
)
660 void r600_start_dpm(struct radeon_device
*rdev
)
662 r600_enable_sclk_control(rdev
, false);
663 r600_enable_mclk_control(rdev
, false);
665 r600_dynamicpm_enable(rdev
, true);
667 radeon_wait_for_vblank(rdev
, 0);
668 radeon_wait_for_vblank(rdev
, 1);
670 r600_enable_spll_bypass(rdev
, true);
671 r600_wait_for_spll_change(rdev
);
672 r600_enable_spll_bypass(rdev
, false);
673 r600_wait_for_spll_change(rdev
);
675 r600_enable_spll_bypass(rdev
, true);
676 r600_wait_for_spll_change(rdev
);
677 r600_enable_spll_bypass(rdev
, false);
678 r600_wait_for_spll_change(rdev
);
680 r600_enable_sclk_control(rdev
, true);
681 r600_enable_mclk_control(rdev
, true);
684 void r600_stop_dpm(struct radeon_device
*rdev
)
686 r600_dynamicpm_enable(rdev
, false);
689 int r600_dpm_pre_set_power_state(struct radeon_device
*rdev
)
694 void r600_dpm_post_set_power_state(struct radeon_device
*rdev
)
699 bool r600_is_uvd_state(u32
class, u32 class2
)
701 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
)
703 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
705 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
707 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
709 if (class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
714 int r600_set_thermal_temperature_range(struct radeon_device
*rdev
,
715 int min_temp
, int max_temp
)
717 int low_temp
= 0 * 1000;
718 int high_temp
= 255 * 1000;
720 if (low_temp
< min_temp
)
722 if (high_temp
> max_temp
)
723 high_temp
= max_temp
;
724 if (high_temp
< low_temp
) {
725 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp
, high_temp
);
729 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTH(high_temp
/ 1000), ~DIG_THERM_INTH_MASK
);
730 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTL(low_temp
/ 1000), ~DIG_THERM_INTL_MASK
);
731 WREG32_P(CG_THERMAL_CTRL
, DIG_THERM_DPM(high_temp
/ 1000), ~DIG_THERM_DPM_MASK
);
733 rdev
->pm
.dpm
.thermal
.min_temp
= low_temp
;
734 rdev
->pm
.dpm
.thermal
.max_temp
= high_temp
;
739 bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor
)
742 case THERMAL_TYPE_RV6XX
:
743 case THERMAL_TYPE_RV770
:
744 case THERMAL_TYPE_EVERGREEN
:
745 case THERMAL_TYPE_SUMO
:
746 case THERMAL_TYPE_NI
:
747 case THERMAL_TYPE_SI
:
748 case THERMAL_TYPE_CI
:
749 case THERMAL_TYPE_KV
:
751 case THERMAL_TYPE_ADT7473_WITH_INTERNAL
:
752 case THERMAL_TYPE_EMC2103_WITH_INTERNAL
:
753 return false; /* need special handling */
754 case THERMAL_TYPE_NONE
:
755 case THERMAL_TYPE_EXTERNAL
:
756 case THERMAL_TYPE_EXTERNAL_GPIO
:
763 struct _ATOM_POWERPLAY_INFO info
;
764 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
765 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
766 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
767 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
768 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
769 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4
;
770 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5
;
774 struct _ATOM_PPLIB_FANTABLE fan
;
775 struct _ATOM_PPLIB_FANTABLE2 fan2
;
778 static int r600_parse_clk_voltage_dep_table(struct radeon_clock_voltage_dependency_table
*radeon_table
,
779 ATOM_PPLIB_Clock_Voltage_Dependency_Table
*atom_table
)
781 u32 size
= atom_table
->ucNumEntries
*
782 sizeof(struct radeon_clock_voltage_dependency_entry
);
785 radeon_table
->entries
= kzalloc(size
, GFP_KERNEL
);
786 if (!radeon_table
->entries
)
789 for (i
= 0; i
< atom_table
->ucNumEntries
; i
++) {
790 radeon_table
->entries
[i
].clk
= le16_to_cpu(atom_table
->entries
[i
].usClockLow
) |
791 (atom_table
->entries
[i
].ucClockHigh
<< 16);
792 radeon_table
->entries
[i
].v
= le16_to_cpu(atom_table
->entries
[i
].usVoltage
);
794 radeon_table
->count
= atom_table
->ucNumEntries
;
799 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
800 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
801 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
802 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
803 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
804 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
805 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
807 int r600_parse_extended_power_table(struct radeon_device
*rdev
)
809 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
810 union power_info
*power_info
;
811 union fan_info
*fan_info
;
812 ATOM_PPLIB_Clock_Voltage_Dependency_Table
*dep_table
;
813 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
818 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
819 &frev
, &crev
, &data_offset
))
821 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
824 if (le16_to_cpu(power_info
->pplib
.usTableSize
) >=
825 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3
)) {
826 if (power_info
->pplib3
.usFanTableOffset
) {
827 fan_info
= (union fan_info
*)(mode_info
->atom_context
->bios
+ data_offset
+
828 le16_to_cpu(power_info
->pplib3
.usFanTableOffset
));
829 rdev
->pm
.dpm
.fan
.t_hyst
= fan_info
->fan
.ucTHyst
;
830 rdev
->pm
.dpm
.fan
.t_min
= le16_to_cpu(fan_info
->fan
.usTMin
);
831 rdev
->pm
.dpm
.fan
.t_med
= le16_to_cpu(fan_info
->fan
.usTMed
);
832 rdev
->pm
.dpm
.fan
.t_high
= le16_to_cpu(fan_info
->fan
.usTHigh
);
833 rdev
->pm
.dpm
.fan
.pwm_min
= le16_to_cpu(fan_info
->fan
.usPWMMin
);
834 rdev
->pm
.dpm
.fan
.pwm_med
= le16_to_cpu(fan_info
->fan
.usPWMMed
);
835 rdev
->pm
.dpm
.fan
.pwm_high
= le16_to_cpu(fan_info
->fan
.usPWMHigh
);
836 if (fan_info
->fan
.ucFanTableFormat
>= 2)
837 rdev
->pm
.dpm
.fan
.t_max
= le16_to_cpu(fan_info
->fan2
.usTMax
);
839 rdev
->pm
.dpm
.fan
.t_max
= 10900;
840 rdev
->pm
.dpm
.fan
.cycle_delay
= 100000;
841 rdev
->pm
.dpm
.fan
.ucode_fan_control
= true;
845 /* clock dependancy tables, shedding tables */
846 if (le16_to_cpu(power_info
->pplib
.usTableSize
) >=
847 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4
)) {
848 if (power_info
->pplib4
.usVddcDependencyOnSCLKOffset
) {
849 dep_table
= (ATOM_PPLIB_Clock_Voltage_Dependency_Table
*)
850 (mode_info
->atom_context
->bios
+ data_offset
+
851 le16_to_cpu(power_info
->pplib4
.usVddcDependencyOnSCLKOffset
));
852 ret
= r600_parse_clk_voltage_dep_table(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
,
857 if (power_info
->pplib4
.usVddciDependencyOnMCLKOffset
) {
858 dep_table
= (ATOM_PPLIB_Clock_Voltage_Dependency_Table
*)
859 (mode_info
->atom_context
->bios
+ data_offset
+
860 le16_to_cpu(power_info
->pplib4
.usVddciDependencyOnMCLKOffset
));
861 ret
= r600_parse_clk_voltage_dep_table(&rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
,
864 kfree(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
);
868 if (power_info
->pplib4
.usVddcDependencyOnMCLKOffset
) {
869 dep_table
= (ATOM_PPLIB_Clock_Voltage_Dependency_Table
*)
870 (mode_info
->atom_context
->bios
+ data_offset
+
871 le16_to_cpu(power_info
->pplib4
.usVddcDependencyOnMCLKOffset
));
872 ret
= r600_parse_clk_voltage_dep_table(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
,
875 kfree(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
);
876 kfree(rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
.entries
);
880 if (power_info
->pplib4
.usMvddDependencyOnMCLKOffset
) {
881 dep_table
= (ATOM_PPLIB_Clock_Voltage_Dependency_Table
*)
882 (mode_info
->atom_context
->bios
+ data_offset
+
883 le16_to_cpu(power_info
->pplib4
.usMvddDependencyOnMCLKOffset
));
884 ret
= r600_parse_clk_voltage_dep_table(&rdev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
,
887 kfree(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
);
888 kfree(rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
.entries
);
889 kfree(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
.entries
);
893 if (power_info
->pplib4
.usMaxClockVoltageOnDCOffset
) {
894 ATOM_PPLIB_Clock_Voltage_Limit_Table
*clk_v
=
895 (ATOM_PPLIB_Clock_Voltage_Limit_Table
*)
896 (mode_info
->atom_context
->bios
+ data_offset
+
897 le16_to_cpu(power_info
->pplib4
.usMaxClockVoltageOnDCOffset
));
898 if (clk_v
->ucNumEntries
) {
899 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.sclk
=
900 le16_to_cpu(clk_v
->entries
[0].usSclkLow
) |
901 (clk_v
->entries
[0].ucSclkHigh
<< 16);
902 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.mclk
=
903 le16_to_cpu(clk_v
->entries
[0].usMclkLow
) |
904 (clk_v
->entries
[0].ucMclkHigh
<< 16);
905 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.vddc
=
906 le16_to_cpu(clk_v
->entries
[0].usVddc
);
907 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.vddci
=
908 le16_to_cpu(clk_v
->entries
[0].usVddci
);
911 if (power_info
->pplib4
.usVddcPhaseShedLimitsTableOffset
) {
912 ATOM_PPLIB_PhaseSheddingLimits_Table
*psl
=
913 (ATOM_PPLIB_PhaseSheddingLimits_Table
*)
914 (mode_info
->atom_context
->bios
+ data_offset
+
915 le16_to_cpu(power_info
->pplib4
.usVddcPhaseShedLimitsTableOffset
));
917 rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
.entries
=
918 kzalloc(psl
->ucNumEntries
*
919 sizeof(struct radeon_phase_shedding_limits_entry
),
921 if (!rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
.entries
) {
922 r600_free_extended_power_table(rdev
);
926 for (i
= 0; i
< psl
->ucNumEntries
; i
++) {
927 rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
.entries
[i
].sclk
=
928 le16_to_cpu(psl
->entries
[i
].usSclkLow
) |
929 (psl
->entries
[i
].ucSclkHigh
<< 16);
930 rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
.entries
[i
].mclk
=
931 le16_to_cpu(psl
->entries
[i
].usMclkLow
) |
932 (psl
->entries
[i
].ucMclkHigh
<< 16);
933 rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
.entries
[i
].voltage
=
934 le16_to_cpu(psl
->entries
[i
].usVoltage
);
936 rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
.count
=
942 if (le16_to_cpu(power_info
->pplib
.usTableSize
) >=
943 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5
)) {
944 rdev
->pm
.dpm
.tdp_limit
= le32_to_cpu(power_info
->pplib5
.ulTDPLimit
);
945 rdev
->pm
.dpm
.near_tdp_limit
= le32_to_cpu(power_info
->pplib5
.ulNearTDPLimit
);
946 rdev
->pm
.dpm
.near_tdp_limit_adjusted
= rdev
->pm
.dpm
.near_tdp_limit
;
947 rdev
->pm
.dpm
.tdp_od_limit
= le16_to_cpu(power_info
->pplib5
.usTDPODLimit
);
948 if (rdev
->pm
.dpm
.tdp_od_limit
)
949 rdev
->pm
.dpm
.power_control
= true;
951 rdev
->pm
.dpm
.power_control
= false;
952 rdev
->pm
.dpm
.tdp_adjustment
= 0;
953 rdev
->pm
.dpm
.sq_ramping_threshold
= le32_to_cpu(power_info
->pplib5
.ulSQRampingThreshold
);
954 rdev
->pm
.dpm
.cac_leakage
= le32_to_cpu(power_info
->pplib5
.ulCACLeakage
);
955 rdev
->pm
.dpm
.load_line_slope
= le16_to_cpu(power_info
->pplib5
.usLoadLineSlope
);
956 if (power_info
->pplib5
.usCACLeakageTableOffset
) {
957 ATOM_PPLIB_CAC_Leakage_Table
*cac_table
=
958 (ATOM_PPLIB_CAC_Leakage_Table
*)
959 (mode_info
->atom_context
->bios
+ data_offset
+
960 le16_to_cpu(power_info
->pplib5
.usCACLeakageTableOffset
));
961 u32 size
= cac_table
->ucNumEntries
* sizeof(struct radeon_cac_leakage_table
);
962 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
= kzalloc(size
, GFP_KERNEL
);
963 if (!rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
) {
964 r600_free_extended_power_table(rdev
);
967 for (i
= 0; i
< cac_table
->ucNumEntries
; i
++) {
968 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_EVV
) {
969 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].vddc1
=
970 le16_to_cpu(cac_table
->entries
[i
].usVddc1
);
971 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].vddc2
=
972 le16_to_cpu(cac_table
->entries
[i
].usVddc2
);
973 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].vddc3
=
974 le16_to_cpu(cac_table
->entries
[i
].usVddc3
);
976 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].vddc
=
977 le16_to_cpu(cac_table
->entries
[i
].usVddc
);
978 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].leakage
=
979 le32_to_cpu(cac_table
->entries
[i
].ulLeakageValue
);
982 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
= cac_table
->ucNumEntries
;
987 if (le16_to_cpu(power_info
->pplib
.usTableSize
) >=
988 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3
)) {
989 ATOM_PPLIB_EXTENDEDHEADER
*ext_hdr
= (ATOM_PPLIB_EXTENDEDHEADER
*)
990 (mode_info
->atom_context
->bios
+ data_offset
+
991 le16_to_cpu(power_info
->pplib3
.usExtendendedHeaderOffset
));
992 if ((le16_to_cpu(ext_hdr
->usSize
) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2
) &&
993 ext_hdr
->usVCETableOffset
) {
994 VCEClockInfoArray
*array
= (VCEClockInfoArray
*)
995 (mode_info
->atom_context
->bios
+ data_offset
+
996 le16_to_cpu(ext_hdr
->usVCETableOffset
) + 1);
997 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
*limits
=
998 (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
*)
999 (mode_info
->atom_context
->bios
+ data_offset
+
1000 le16_to_cpu(ext_hdr
->usVCETableOffset
) + 1 +
1001 1 + array
->ucNumEntries
* sizeof(VCEClockInfo
));
1002 u32 size
= limits
->numEntries
*
1003 sizeof(struct radeon_vce_clock_voltage_dependency_entry
);
1004 rdev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
=
1005 kzalloc(size
, GFP_KERNEL
);
1006 if (!rdev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
) {
1007 r600_free_extended_power_table(rdev
);
1010 rdev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.count
=
1012 for (i
= 0; i
< limits
->numEntries
; i
++) {
1013 VCEClockInfo
*vce_clk
=
1014 &array
->entries
[limits
->entries
[i
].ucVCEClockInfoIndex
];
1015 rdev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
[i
].evclk
=
1016 le16_to_cpu(vce_clk
->usEVClkLow
) | (vce_clk
->ucEVClkHigh
<< 16);
1017 rdev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
[i
].ecclk
=
1018 le16_to_cpu(vce_clk
->usECClkLow
) | (vce_clk
->ucECClkHigh
<< 16);
1019 rdev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
[i
].v
=
1020 le16_to_cpu(limits
->entries
[i
].usVoltage
);
1023 if ((le16_to_cpu(ext_hdr
->usSize
) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3
) &&
1024 ext_hdr
->usUVDTableOffset
) {
1025 UVDClockInfoArray
*array
= (UVDClockInfoArray
*)
1026 (mode_info
->atom_context
->bios
+ data_offset
+
1027 le16_to_cpu(ext_hdr
->usUVDTableOffset
) + 1);
1028 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
*limits
=
1029 (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
*)
1030 (mode_info
->atom_context
->bios
+ data_offset
+
1031 le16_to_cpu(ext_hdr
->usUVDTableOffset
) + 1 +
1032 1 + (array
->ucNumEntries
* sizeof (UVDClockInfo
)));
1033 u32 size
= limits
->numEntries
*
1034 sizeof(struct radeon_uvd_clock_voltage_dependency_entry
);
1035 rdev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
=
1036 kzalloc(size
, GFP_KERNEL
);
1037 if (!rdev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
) {
1038 r600_free_extended_power_table(rdev
);
1041 rdev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.count
=
1043 for (i
= 0; i
< limits
->numEntries
; i
++) {
1044 UVDClockInfo
*uvd_clk
=
1045 &array
->entries
[limits
->entries
[i
].ucUVDClockInfoIndex
];
1046 rdev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
[i
].vclk
=
1047 le16_to_cpu(uvd_clk
->usVClkLow
) | (uvd_clk
->ucVClkHigh
<< 16);
1048 rdev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
[i
].dclk
=
1049 le16_to_cpu(uvd_clk
->usDClkLow
) | (uvd_clk
->ucDClkHigh
<< 16);
1050 rdev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
[i
].v
=
1051 le16_to_cpu(limits
->entries
[i
].usVoltage
);
1054 if ((le16_to_cpu(ext_hdr
->usSize
) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4
) &&
1055 ext_hdr
->usSAMUTableOffset
) {
1056 ATOM_PPLIB_SAMClk_Voltage_Limit_Table
*limits
=
1057 (ATOM_PPLIB_SAMClk_Voltage_Limit_Table
*)
1058 (mode_info
->atom_context
->bios
+ data_offset
+
1059 le16_to_cpu(ext_hdr
->usSAMUTableOffset
) + 1);
1060 u32 size
= limits
->numEntries
*
1061 sizeof(struct radeon_clock_voltage_dependency_entry
);
1062 rdev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.entries
=
1063 kzalloc(size
, GFP_KERNEL
);
1064 if (!rdev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.entries
) {
1065 r600_free_extended_power_table(rdev
);
1068 rdev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.count
=
1070 for (i
= 0; i
< limits
->numEntries
; i
++) {
1071 rdev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.entries
[i
].clk
=
1072 le16_to_cpu(limits
->entries
[i
].usSAMClockLow
) |
1073 (limits
->entries
[i
].ucSAMClockHigh
<< 16);
1074 rdev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.entries
[i
].v
=
1075 le16_to_cpu(limits
->entries
[i
].usVoltage
);
1078 if ((le16_to_cpu(ext_hdr
->usSize
) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5
) &&
1079 ext_hdr
->usPPMTableOffset
) {
1080 ATOM_PPLIB_PPM_Table
*ppm
= (ATOM_PPLIB_PPM_Table
*)
1081 (mode_info
->atom_context
->bios
+ data_offset
+
1082 le16_to_cpu(ext_hdr
->usPPMTableOffset
));
1083 rdev
->pm
.dpm
.dyn_state
.ppm_table
=
1084 kzalloc(sizeof(struct radeon_ppm_table
), GFP_KERNEL
);
1085 if (!rdev
->pm
.dpm
.dyn_state
.ppm_table
) {
1086 r600_free_extended_power_table(rdev
);
1089 rdev
->pm
.dpm
.dyn_state
.ppm_table
->ppm_design
= ppm
->ucPpmDesign
;
1090 rdev
->pm
.dpm
.dyn_state
.ppm_table
->cpu_core_number
=
1091 le16_to_cpu(ppm
->usCpuCoreNumber
);
1092 rdev
->pm
.dpm
.dyn_state
.ppm_table
->platform_tdp
=
1093 le32_to_cpu(ppm
->ulPlatformTDP
);
1094 rdev
->pm
.dpm
.dyn_state
.ppm_table
->small_ac_platform_tdp
=
1095 le32_to_cpu(ppm
->ulSmallACPlatformTDP
);
1096 rdev
->pm
.dpm
.dyn_state
.ppm_table
->platform_tdc
=
1097 le32_to_cpu(ppm
->ulPlatformTDC
);
1098 rdev
->pm
.dpm
.dyn_state
.ppm_table
->small_ac_platform_tdc
=
1099 le32_to_cpu(ppm
->ulSmallACPlatformTDC
);
1100 rdev
->pm
.dpm
.dyn_state
.ppm_table
->apu_tdp
=
1101 le32_to_cpu(ppm
->ulApuTDP
);
1102 rdev
->pm
.dpm
.dyn_state
.ppm_table
->dgpu_tdp
=
1103 le32_to_cpu(ppm
->ulDGpuTDP
);
1104 rdev
->pm
.dpm
.dyn_state
.ppm_table
->dgpu_ulv_power
=
1105 le32_to_cpu(ppm
->ulDGpuUlvPower
);
1106 rdev
->pm
.dpm
.dyn_state
.ppm_table
->tj_max
=
1107 le32_to_cpu(ppm
->ulTjmax
);
1109 if ((le16_to_cpu(ext_hdr
->usSize
) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6
) &&
1110 ext_hdr
->usACPTableOffset
) {
1111 ATOM_PPLIB_ACPClk_Voltage_Limit_Table
*limits
=
1112 (ATOM_PPLIB_ACPClk_Voltage_Limit_Table
*)
1113 (mode_info
->atom_context
->bios
+ data_offset
+
1114 le16_to_cpu(ext_hdr
->usACPTableOffset
) + 1);
1115 u32 size
= limits
->numEntries
*
1116 sizeof(struct radeon_clock_voltage_dependency_entry
);
1117 rdev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.entries
=
1118 kzalloc(size
, GFP_KERNEL
);
1119 if (!rdev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.entries
) {
1120 r600_free_extended_power_table(rdev
);
1123 rdev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.count
=
1125 for (i
= 0; i
< limits
->numEntries
; i
++) {
1126 rdev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.entries
[i
].clk
=
1127 le16_to_cpu(limits
->entries
[i
].usACPClockLow
) |
1128 (limits
->entries
[i
].ucACPClockHigh
<< 16);
1129 rdev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.entries
[i
].v
=
1130 le16_to_cpu(limits
->entries
[i
].usVoltage
);
1133 if ((le16_to_cpu(ext_hdr
->usSize
) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7
) &&
1134 ext_hdr
->usPowerTuneTableOffset
) {
1135 u8 rev
= *(u8
*)(mode_info
->atom_context
->bios
+ data_offset
+
1136 le16_to_cpu(ext_hdr
->usPowerTuneTableOffset
));
1137 ATOM_PowerTune_Table
*pt
;
1138 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
=
1139 kzalloc(sizeof(struct radeon_cac_tdp_table
), GFP_KERNEL
);
1140 if (!rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
) {
1141 r600_free_extended_power_table(rdev
);
1145 ATOM_PPLIB_POWERTUNE_Table_V1
*ppt
= (ATOM_PPLIB_POWERTUNE_Table_V1
*)
1146 (mode_info
->atom_context
->bios
+ data_offset
+
1147 le16_to_cpu(ext_hdr
->usPowerTuneTableOffset
));
1148 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
->maximum_power_delivery_limit
=
1149 ppt
->usMaximumPowerDeliveryLimit
;
1150 pt
= &ppt
->power_tune_table
;
1152 ATOM_PPLIB_POWERTUNE_Table
*ppt
= (ATOM_PPLIB_POWERTUNE_Table
*)
1153 (mode_info
->atom_context
->bios
+ data_offset
+
1154 le16_to_cpu(ext_hdr
->usPowerTuneTableOffset
));
1155 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
->maximum_power_delivery_limit
= 255;
1156 pt
= &ppt
->power_tune_table
;
1158 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
->tdp
= le16_to_cpu(pt
->usTDP
);
1159 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
->configurable_tdp
=
1160 le16_to_cpu(pt
->usConfigurableTDP
);
1161 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
->tdc
= le16_to_cpu(pt
->usTDC
);
1162 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
->battery_power_limit
=
1163 le16_to_cpu(pt
->usBatteryPowerLimit
);
1164 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
->small_power_limit
=
1165 le16_to_cpu(pt
->usSmallPowerLimit
);
1166 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
->low_cac_leakage
=
1167 le16_to_cpu(pt
->usLowCACLeakage
);
1168 rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
->high_cac_leakage
=
1169 le16_to_cpu(pt
->usHighCACLeakage
);
1176 void r600_free_extended_power_table(struct radeon_device
*rdev
)
1178 if (rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
)
1179 kfree(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
);
1180 if (rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
.entries
)
1181 kfree(rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
.entries
);
1182 if (rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
.entries
)
1183 kfree(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
.entries
);
1184 if (rdev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
.entries
)
1185 kfree(rdev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
.entries
);
1186 if (rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
)
1187 kfree(rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
);
1188 if (rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
.entries
)
1189 kfree(rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
.entries
);
1190 if (rdev
->pm
.dpm
.dyn_state
.ppm_table
)
1191 kfree(rdev
->pm
.dpm
.dyn_state
.ppm_table
);
1192 if (rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
)
1193 kfree(rdev
->pm
.dpm
.dyn_state
.cac_tdp_table
);
1194 if (rdev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
)
1195 kfree(rdev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
);
1196 if (rdev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
)
1197 kfree(rdev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
);
1198 if (rdev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.entries
)
1199 kfree(rdev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.entries
);
1200 if (rdev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.entries
)
1201 kfree(rdev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.entries
);
1204 enum radeon_pcie_gen
r600_get_pcie_gen_support(struct radeon_device
*rdev
,
1206 enum radeon_pcie_gen asic_gen
,
1207 enum radeon_pcie_gen default_gen
)
1210 case RADEON_PCIE_GEN1
:
1211 return RADEON_PCIE_GEN1
;
1212 case RADEON_PCIE_GEN2
:
1213 return RADEON_PCIE_GEN2
;
1214 case RADEON_PCIE_GEN3
:
1215 return RADEON_PCIE_GEN3
;
1217 if ((sys_mask
& DRM_PCIE_SPEED_80
) && (default_gen
== RADEON_PCIE_GEN3
))
1218 return RADEON_PCIE_GEN3
;
1219 else if ((sys_mask
& DRM_PCIE_SPEED_50
) && (default_gen
== RADEON_PCIE_GEN2
))
1220 return RADEON_PCIE_GEN2
;
1222 return RADEON_PCIE_GEN1
;
1224 return RADEON_PCIE_GEN1
;
1227 u16
r600_get_pcie_lane_support(struct radeon_device
*rdev
,
1231 switch (asic_lanes
) {
1234 return default_lanes
;