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[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
102 extern int radeon_hard_reset;
103
104 /*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
108 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
110 /* RADEON_IB_POOL_SIZE must be a power of 2 */
111 #define RADEON_IB_POOL_SIZE 16
112 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
113 #define RADEONFB_CONN_LIMIT 4
114 #define RADEON_BIOS_NUM_SCRATCH 8
115
116 /* fence seq are set to this number when signaled */
117 #define RADEON_FENCE_SIGNALED_SEQ 0LL
118
119 /* internal ring indices */
120 /* r1xx+ has gfx CP ring */
121 #define RADEON_RING_TYPE_GFX_INDEX 0
122
123 /* cayman has 2 compute CP rings */
124 #define CAYMAN_RING_TYPE_CP1_INDEX 1
125 #define CAYMAN_RING_TYPE_CP2_INDEX 2
126
127 /* R600+ has an async dma ring */
128 #define R600_RING_TYPE_DMA_INDEX 3
129 /* cayman add a second async dma ring */
130 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
131
132 /* R600+ */
133 #define R600_RING_TYPE_UVD_INDEX 5
134
135 /* TN+ */
136 #define TN_RING_TYPE_VCE1_INDEX 6
137 #define TN_RING_TYPE_VCE2_INDEX 7
138
139 /* max number of rings */
140 #define RADEON_NUM_RINGS 8
141
142 /* number of hw syncs before falling back on blocking */
143 #define RADEON_NUM_SYNCS 4
144
145 /* number of hw syncs before falling back on blocking */
146 #define RADEON_NUM_SYNCS 4
147
148 /* hardcode those limit for now */
149 #define RADEON_VA_IB_OFFSET (1 << 20)
150 #define RADEON_VA_RESERVED_SIZE (8 << 20)
151 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
152
153 /* hard reset data */
154 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
155
156 /* reset flags */
157 #define RADEON_RESET_GFX (1 << 0)
158 #define RADEON_RESET_COMPUTE (1 << 1)
159 #define RADEON_RESET_DMA (1 << 2)
160 #define RADEON_RESET_CP (1 << 3)
161 #define RADEON_RESET_GRBM (1 << 4)
162 #define RADEON_RESET_DMA1 (1 << 5)
163 #define RADEON_RESET_RLC (1 << 6)
164 #define RADEON_RESET_SEM (1 << 7)
165 #define RADEON_RESET_IH (1 << 8)
166 #define RADEON_RESET_VMC (1 << 9)
167 #define RADEON_RESET_MC (1 << 10)
168 #define RADEON_RESET_DISPLAY (1 << 11)
169
170 /* CG block flags */
171 #define RADEON_CG_BLOCK_GFX (1 << 0)
172 #define RADEON_CG_BLOCK_MC (1 << 1)
173 #define RADEON_CG_BLOCK_SDMA (1 << 2)
174 #define RADEON_CG_BLOCK_UVD (1 << 3)
175 #define RADEON_CG_BLOCK_VCE (1 << 4)
176 #define RADEON_CG_BLOCK_HDP (1 << 5)
177 #define RADEON_CG_BLOCK_BIF (1 << 6)
178
179 /* CG flags */
180 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
181 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
182 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
183 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
184 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
185 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
186 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
187 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
188 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
189 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
190 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
191 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
192 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
193 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
194 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
195 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
196 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
197
198 /* PG flags */
199 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
200 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
201 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
202 #define RADEON_PG_SUPPORT_UVD (1 << 3)
203 #define RADEON_PG_SUPPORT_VCE (1 << 4)
204 #define RADEON_PG_SUPPORT_CP (1 << 5)
205 #define RADEON_PG_SUPPORT_GDS (1 << 6)
206 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
207 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
208 #define RADEON_PG_SUPPORT_ACP (1 << 9)
209 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
210
211 /* max cursor sizes (in pixels) */
212 #define CURSOR_WIDTH 64
213 #define CURSOR_HEIGHT 64
214
215 #define CIK_CURSOR_WIDTH 128
216 #define CIK_CURSOR_HEIGHT 128
217
218 /*
219 * Errata workarounds.
220 */
221 enum radeon_pll_errata {
222 CHIP_ERRATA_R300_CG = 0x00000001,
223 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
224 CHIP_ERRATA_PLL_DELAY = 0x00000004
225 };
226
227
228 struct radeon_device;
229
230
231 /*
232 * BIOS.
233 */
234 bool radeon_get_bios(struct radeon_device *rdev);
235
236 /*
237 * Dummy page
238 */
239 struct radeon_dummy_page {
240 struct page *page;
241 dma_addr_t addr;
242 };
243 int radeon_dummy_page_init(struct radeon_device *rdev);
244 void radeon_dummy_page_fini(struct radeon_device *rdev);
245
246
247 /*
248 * Clocks
249 */
250 struct radeon_clock {
251 struct radeon_pll p1pll;
252 struct radeon_pll p2pll;
253 struct radeon_pll dcpll;
254 struct radeon_pll spll;
255 struct radeon_pll mpll;
256 /* 10 Khz units */
257 uint32_t default_mclk;
258 uint32_t default_sclk;
259 uint32_t default_dispclk;
260 uint32_t current_dispclk;
261 uint32_t dp_extclk;
262 uint32_t max_pixel_clock;
263 };
264
265 /*
266 * Power management
267 */
268 int radeon_pm_init(struct radeon_device *rdev);
269 int radeon_pm_late_init(struct radeon_device *rdev);
270 void radeon_pm_fini(struct radeon_device *rdev);
271 void radeon_pm_compute_clocks(struct radeon_device *rdev);
272 void radeon_pm_suspend(struct radeon_device *rdev);
273 void radeon_pm_resume(struct radeon_device *rdev);
274 void radeon_combios_get_power_modes(struct radeon_device *rdev);
275 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
276 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
277 u8 clock_type,
278 u32 clock,
279 bool strobe_mode,
280 struct atom_clock_dividers *dividers);
281 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
282 u32 clock,
283 bool strobe_mode,
284 struct atom_mpll_param *mpll_param);
285 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
286 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
287 u16 voltage_level, u8 voltage_type,
288 u32 *gpio_value, u32 *gpio_mask);
289 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
290 u32 eng_clock, u32 mem_clock);
291 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
292 u8 voltage_type, u16 *voltage_step);
293 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
294 u16 voltage_id, u16 *voltage);
295 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
296 u16 *voltage,
297 u16 leakage_idx);
298 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
299 u16 *leakage_id);
300 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
301 u16 *vddc, u16 *vddci,
302 u16 virtual_voltage_id,
303 u16 vbios_voltage_id);
304 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
305 u8 voltage_type,
306 u16 nominal_voltage,
307 u16 *true_voltage);
308 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
309 u8 voltage_type, u16 *min_voltage);
310 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
311 u8 voltage_type, u16 *max_voltage);
312 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
313 u8 voltage_type, u8 voltage_mode,
314 struct atom_voltage_table *voltage_table);
315 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode);
317 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
318 u32 mem_clock);
319 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
320 u32 mem_clock);
321 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
322 u8 module_index,
323 struct atom_mc_reg_table *reg_table);
324 int radeon_atom_get_memory_info(struct radeon_device *rdev,
325 u8 module_index, struct atom_memory_info *mem_info);
326 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
327 bool gddr5, u8 module_index,
328 struct atom_memory_clock_range_table *mclk_range_table);
329 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
330 u16 voltage_id, u16 *voltage);
331 void rs690_pm_info(struct radeon_device *rdev);
332 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
333 unsigned *bankh, unsigned *mtaspect,
334 unsigned *tile_split);
335
336 /*
337 * Fences.
338 */
339 struct radeon_fence_driver {
340 uint32_t scratch_reg;
341 uint64_t gpu_addr;
342 volatile uint32_t *cpu_addr;
343 /* sync_seq is protected by ring emission lock */
344 uint64_t sync_seq[RADEON_NUM_RINGS];
345 atomic64_t last_seq;
346 bool initialized;
347 };
348
349 struct radeon_fence {
350 struct radeon_device *rdev;
351 struct kref kref;
352 /* protected by radeon_fence.lock */
353 uint64_t seq;
354 /* RB, DMA, etc. */
355 unsigned ring;
356 };
357
358 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
359 int radeon_fence_driver_init(struct radeon_device *rdev);
360 void radeon_fence_driver_fini(struct radeon_device *rdev);
361 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
362 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
363 void radeon_fence_process(struct radeon_device *rdev, int ring);
364 bool radeon_fence_signaled(struct radeon_fence *fence);
365 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
366 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
367 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
368 int radeon_fence_wait_any(struct radeon_device *rdev,
369 struct radeon_fence **fences,
370 bool intr);
371 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
372 void radeon_fence_unref(struct radeon_fence **fence);
373 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
374 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
375 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
376 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
377 struct radeon_fence *b)
378 {
379 if (!a) {
380 return b;
381 }
382
383 if (!b) {
384 return a;
385 }
386
387 BUG_ON(a->ring != b->ring);
388
389 if (a->seq > b->seq) {
390 return a;
391 } else {
392 return b;
393 }
394 }
395
396 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
397 struct radeon_fence *b)
398 {
399 if (!a) {
400 return false;
401 }
402
403 if (!b) {
404 return true;
405 }
406
407 BUG_ON(a->ring != b->ring);
408
409 return a->seq < b->seq;
410 }
411
412 /*
413 * Tiling registers
414 */
415 struct radeon_surface_reg {
416 struct radeon_bo *bo;
417 };
418
419 #define RADEON_GEM_MAX_SURFACES 8
420
421 /*
422 * TTM.
423 */
424 struct radeon_mman {
425 struct ttm_bo_global_ref bo_global_ref;
426 struct drm_global_reference mem_global_ref;
427 struct ttm_bo_device bdev;
428 bool mem_global_referenced;
429 bool initialized;
430
431 #if defined(CONFIG_DEBUG_FS)
432 struct dentry *vram;
433 struct dentry *gtt;
434 #endif
435 };
436
437 /* bo virtual address in a specific vm */
438 struct radeon_bo_va {
439 /* protected by bo being reserved */
440 struct list_head bo_list;
441 uint64_t soffset;
442 uint64_t eoffset;
443 uint32_t flags;
444 bool valid;
445 unsigned ref_count;
446
447 /* protected by vm mutex */
448 struct list_head vm_list;
449
450 /* constant after initialization */
451 struct radeon_vm *vm;
452 struct radeon_bo *bo;
453 };
454
455 struct radeon_bo {
456 /* Protected by gem.mutex */
457 struct list_head list;
458 /* Protected by tbo.reserved */
459 u32 initial_domain;
460 u32 placements[3];
461 struct ttm_placement placement;
462 struct ttm_buffer_object tbo;
463 struct ttm_bo_kmap_obj kmap;
464 unsigned pin_count;
465 void *kptr;
466 u32 tiling_flags;
467 u32 pitch;
468 int surface_reg;
469 /* list of all virtual address to which this bo
470 * is associated to
471 */
472 struct list_head va;
473 /* Constant after initialization */
474 struct radeon_device *rdev;
475 struct drm_gem_object gem_base;
476
477 struct ttm_bo_kmap_obj dma_buf_vmap;
478 pid_t pid;
479 };
480 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
481
482 int radeon_gem_debugfs_init(struct radeon_device *rdev);
483
484 /* sub-allocation manager, it has to be protected by another lock.
485 * By conception this is an helper for other part of the driver
486 * like the indirect buffer or semaphore, which both have their
487 * locking.
488 *
489 * Principe is simple, we keep a list of sub allocation in offset
490 * order (first entry has offset == 0, last entry has the highest
491 * offset).
492 *
493 * When allocating new object we first check if there is room at
494 * the end total_size - (last_object_offset + last_object_size) >=
495 * alloc_size. If so we allocate new object there.
496 *
497 * When there is not enough room at the end, we start waiting for
498 * each sub object until we reach object_offset+object_size >=
499 * alloc_size, this object then become the sub object we return.
500 *
501 * Alignment can't be bigger than page size.
502 *
503 * Hole are not considered for allocation to keep things simple.
504 * Assumption is that there won't be hole (all object on same
505 * alignment).
506 */
507 struct radeon_sa_manager {
508 wait_queue_head_t wq;
509 struct radeon_bo *bo;
510 struct list_head *hole;
511 struct list_head flist[RADEON_NUM_RINGS];
512 struct list_head olist;
513 unsigned size;
514 uint64_t gpu_addr;
515 void *cpu_ptr;
516 uint32_t domain;
517 uint32_t align;
518 };
519
520 struct radeon_sa_bo;
521
522 /* sub-allocation buffer */
523 struct radeon_sa_bo {
524 struct list_head olist;
525 struct list_head flist;
526 struct radeon_sa_manager *manager;
527 unsigned soffset;
528 unsigned eoffset;
529 struct radeon_fence *fence;
530 };
531
532 /*
533 * GEM objects.
534 */
535 struct radeon_gem {
536 struct mutex mutex;
537 struct list_head objects;
538 };
539
540 int radeon_gem_init(struct radeon_device *rdev);
541 void radeon_gem_fini(struct radeon_device *rdev);
542 int radeon_gem_object_create(struct radeon_device *rdev, int size,
543 int alignment, int initial_domain,
544 bool discardable, bool kernel,
545 struct drm_gem_object **obj);
546
547 int radeon_mode_dumb_create(struct drm_file *file_priv,
548 struct drm_device *dev,
549 struct drm_mode_create_dumb *args);
550 int radeon_mode_dumb_mmap(struct drm_file *filp,
551 struct drm_device *dev,
552 uint32_t handle, uint64_t *offset_p);
553
554 /*
555 * Semaphores.
556 */
557 struct radeon_semaphore {
558 struct radeon_sa_bo *sa_bo;
559 signed waiters;
560 uint64_t gpu_addr;
561 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
562 };
563
564 int radeon_semaphore_create(struct radeon_device *rdev,
565 struct radeon_semaphore **semaphore);
566 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
567 struct radeon_semaphore *semaphore);
568 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
569 struct radeon_semaphore *semaphore);
570 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
571 struct radeon_fence *fence);
572 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
573 struct radeon_semaphore *semaphore,
574 int waiting_ring);
575 void radeon_semaphore_free(struct radeon_device *rdev,
576 struct radeon_semaphore **semaphore,
577 struct radeon_fence *fence);
578
579 /*
580 * GART structures, functions & helpers
581 */
582 struct radeon_mc;
583
584 #define RADEON_GPU_PAGE_SIZE 4096
585 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
586 #define RADEON_GPU_PAGE_SHIFT 12
587 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
588
589 struct radeon_gart {
590 dma_addr_t table_addr;
591 struct radeon_bo *robj;
592 void *ptr;
593 unsigned num_gpu_pages;
594 unsigned num_cpu_pages;
595 unsigned table_size;
596 struct page **pages;
597 dma_addr_t *pages_addr;
598 bool ready;
599 };
600
601 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
602 void radeon_gart_table_ram_free(struct radeon_device *rdev);
603 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
604 void radeon_gart_table_vram_free(struct radeon_device *rdev);
605 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
606 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
607 int radeon_gart_init(struct radeon_device *rdev);
608 void radeon_gart_fini(struct radeon_device *rdev);
609 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
610 int pages);
611 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
612 int pages, struct page **pagelist,
613 dma_addr_t *dma_addr);
614 void radeon_gart_restore(struct radeon_device *rdev);
615
616
617 /*
618 * GPU MC structures, functions & helpers
619 */
620 struct radeon_mc {
621 resource_size_t aper_size;
622 resource_size_t aper_base;
623 resource_size_t agp_base;
624 /* for some chips with <= 32MB we need to lie
625 * about vram size near mc fb location */
626 u64 mc_vram_size;
627 u64 visible_vram_size;
628 u64 gtt_size;
629 u64 gtt_start;
630 u64 gtt_end;
631 u64 vram_start;
632 u64 vram_end;
633 unsigned vram_width;
634 u64 real_vram_size;
635 int vram_mtrr;
636 bool vram_is_ddr;
637 bool igp_sideport_enabled;
638 u64 gtt_base_align;
639 u64 mc_mask;
640 };
641
642 bool radeon_combios_sideport_present(struct radeon_device *rdev);
643 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
644
645 /*
646 * GPU scratch registers structures, functions & helpers
647 */
648 struct radeon_scratch {
649 unsigned num_reg;
650 uint32_t reg_base;
651 bool free[32];
652 uint32_t reg[32];
653 };
654
655 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
656 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
657
658 /*
659 * GPU doorbell structures, functions & helpers
660 */
661 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
662
663 struct radeon_doorbell {
664 /* doorbell mmio */
665 resource_size_t base;
666 resource_size_t size;
667 u32 __iomem *ptr;
668 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
669 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
670 };
671
672 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
673 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
674
675 /*
676 * IRQS.
677 */
678
679 struct radeon_unpin_work {
680 struct work_struct work;
681 struct radeon_device *rdev;
682 int crtc_id;
683 struct radeon_fence *fence;
684 struct drm_pending_vblank_event *event;
685 struct radeon_bo *old_rbo;
686 u64 new_crtc_base;
687 };
688
689 struct r500_irq_stat_regs {
690 u32 disp_int;
691 u32 hdmi0_status;
692 };
693
694 struct r600_irq_stat_regs {
695 u32 disp_int;
696 u32 disp_int_cont;
697 u32 disp_int_cont2;
698 u32 d1grph_int;
699 u32 d2grph_int;
700 u32 hdmi0_status;
701 u32 hdmi1_status;
702 };
703
704 struct evergreen_irq_stat_regs {
705 u32 disp_int;
706 u32 disp_int_cont;
707 u32 disp_int_cont2;
708 u32 disp_int_cont3;
709 u32 disp_int_cont4;
710 u32 disp_int_cont5;
711 u32 d1grph_int;
712 u32 d2grph_int;
713 u32 d3grph_int;
714 u32 d4grph_int;
715 u32 d5grph_int;
716 u32 d6grph_int;
717 u32 afmt_status1;
718 u32 afmt_status2;
719 u32 afmt_status3;
720 u32 afmt_status4;
721 u32 afmt_status5;
722 u32 afmt_status6;
723 };
724
725 struct cik_irq_stat_regs {
726 u32 disp_int;
727 u32 disp_int_cont;
728 u32 disp_int_cont2;
729 u32 disp_int_cont3;
730 u32 disp_int_cont4;
731 u32 disp_int_cont5;
732 u32 disp_int_cont6;
733 };
734
735 union radeon_irq_stat_regs {
736 struct r500_irq_stat_regs r500;
737 struct r600_irq_stat_regs r600;
738 struct evergreen_irq_stat_regs evergreen;
739 struct cik_irq_stat_regs cik;
740 };
741
742 #define RADEON_MAX_HPD_PINS 7
743 #define RADEON_MAX_CRTCS 6
744 #define RADEON_MAX_AFMT_BLOCKS 7
745
746 struct radeon_irq {
747 bool installed;
748 spinlock_t lock;
749 atomic_t ring_int[RADEON_NUM_RINGS];
750 bool crtc_vblank_int[RADEON_MAX_CRTCS];
751 atomic_t pflip[RADEON_MAX_CRTCS];
752 wait_queue_head_t vblank_queue;
753 bool hpd[RADEON_MAX_HPD_PINS];
754 bool afmt[RADEON_MAX_AFMT_BLOCKS];
755 union radeon_irq_stat_regs stat_regs;
756 bool dpm_thermal;
757 };
758
759 int radeon_irq_kms_init(struct radeon_device *rdev);
760 void radeon_irq_kms_fini(struct radeon_device *rdev);
761 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
762 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
763 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
764 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
765 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
766 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
767 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
768 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
769
770 /*
771 * CP & rings.
772 */
773
774 struct radeon_ib {
775 struct radeon_sa_bo *sa_bo;
776 uint32_t length_dw;
777 uint64_t gpu_addr;
778 uint32_t *ptr;
779 int ring;
780 struct radeon_fence *fence;
781 struct radeon_vm *vm;
782 bool is_const_ib;
783 struct radeon_semaphore *semaphore;
784 };
785
786 struct radeon_ring {
787 struct radeon_bo *ring_obj;
788 volatile uint32_t *ring;
789 unsigned rptr_offs;
790 unsigned rptr_save_reg;
791 u64 next_rptr_gpu_addr;
792 volatile u32 *next_rptr_cpu_addr;
793 unsigned wptr;
794 unsigned wptr_old;
795 unsigned ring_size;
796 unsigned ring_free_dw;
797 int count_dw;
798 atomic_t last_rptr;
799 atomic64_t last_activity;
800 uint64_t gpu_addr;
801 uint32_t align_mask;
802 uint32_t ptr_mask;
803 bool ready;
804 u32 nop;
805 u32 idx;
806 u64 last_semaphore_signal_addr;
807 u64 last_semaphore_wait_addr;
808 /* for CIK queues */
809 u32 me;
810 u32 pipe;
811 u32 queue;
812 struct radeon_bo *mqd_obj;
813 u32 doorbell_index;
814 unsigned wptr_offs;
815 };
816
817 struct radeon_mec {
818 struct radeon_bo *hpd_eop_obj;
819 u64 hpd_eop_gpu_addr;
820 u32 num_pipe;
821 u32 num_mec;
822 u32 num_queue;
823 };
824
825 /*
826 * VM
827 */
828
829 /* maximum number of VMIDs */
830 #define RADEON_NUM_VM 16
831
832 /* defines number of bits in page table versus page directory,
833 * a page is 4KB so we have 12 bits offset, 9 bits in the page
834 * table and the remaining 19 bits are in the page directory */
835 #define RADEON_VM_BLOCK_SIZE 9
836
837 /* number of entries in page table */
838 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
839
840 /* PTBs (Page Table Blocks) need to be aligned to 32K */
841 #define RADEON_VM_PTB_ALIGN_SIZE 32768
842 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
843 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
844
845 #define R600_PTE_VALID (1 << 0)
846 #define R600_PTE_SYSTEM (1 << 1)
847 #define R600_PTE_SNOOPED (1 << 2)
848 #define R600_PTE_READABLE (1 << 5)
849 #define R600_PTE_WRITEABLE (1 << 6)
850
851 /* PTE (Page Table Entry) fragment field for different page sizes */
852 #define R600_PTE_FRAG_4KB (0 << 7)
853 #define R600_PTE_FRAG_64KB (4 << 7)
854 #define R600_PTE_FRAG_256KB (6 << 7)
855
856 struct radeon_vm_pt {
857 struct radeon_bo *bo;
858 uint64_t addr;
859 };
860
861 struct radeon_vm {
862 struct list_head va;
863 unsigned id;
864
865 /* contains the page directory */
866 struct radeon_bo *page_directory;
867 uint64_t pd_gpu_addr;
868 unsigned max_pde_used;
869
870 /* array of page tables, one for each page directory entry */
871 struct radeon_vm_pt *page_tables;
872
873 struct mutex mutex;
874 /* last fence for cs using this vm */
875 struct radeon_fence *fence;
876 /* last flush or NULL if we still need to flush */
877 struct radeon_fence *last_flush;
878 /* last use of vmid */
879 struct radeon_fence *last_id_use;
880 };
881
882 struct radeon_vm_manager {
883 struct radeon_fence *active[RADEON_NUM_VM];
884 uint32_t max_pfn;
885 /* number of VMIDs */
886 unsigned nvm;
887 /* vram base address for page table entry */
888 u64 vram_base_offset;
889 /* is vm enabled? */
890 bool enabled;
891 };
892
893 /*
894 * file private structure
895 */
896 struct radeon_fpriv {
897 struct radeon_vm vm;
898 };
899
900 /*
901 * R6xx+ IH ring
902 */
903 struct r600_ih {
904 struct radeon_bo *ring_obj;
905 volatile uint32_t *ring;
906 unsigned rptr;
907 unsigned ring_size;
908 uint64_t gpu_addr;
909 uint32_t ptr_mask;
910 atomic_t lock;
911 bool enabled;
912 };
913
914 /*
915 * RLC stuff
916 */
917 #include "clearstate_defs.h"
918
919 struct radeon_rlc {
920 /* for power gating */
921 struct radeon_bo *save_restore_obj;
922 uint64_t save_restore_gpu_addr;
923 volatile uint32_t *sr_ptr;
924 const u32 *reg_list;
925 u32 reg_list_size;
926 /* for clear state */
927 struct radeon_bo *clear_state_obj;
928 uint64_t clear_state_gpu_addr;
929 volatile uint32_t *cs_ptr;
930 const struct cs_section_def *cs_data;
931 u32 clear_state_size;
932 /* for cp tables */
933 struct radeon_bo *cp_table_obj;
934 uint64_t cp_table_gpu_addr;
935 volatile uint32_t *cp_table_ptr;
936 u32 cp_table_size;
937 };
938
939 int radeon_ib_get(struct radeon_device *rdev, int ring,
940 struct radeon_ib *ib, struct radeon_vm *vm,
941 unsigned size);
942 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
943 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
944 struct radeon_ib *const_ib);
945 int radeon_ib_pool_init(struct radeon_device *rdev);
946 void radeon_ib_pool_fini(struct radeon_device *rdev);
947 int radeon_ib_ring_tests(struct radeon_device *rdev);
948 /* Ring access between begin & end cannot sleep */
949 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
950 struct radeon_ring *ring);
951 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
952 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
953 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
954 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
955 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
956 void radeon_ring_undo(struct radeon_ring *ring);
957 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
958 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
959 void radeon_ring_lockup_update(struct radeon_device *rdev,
960 struct radeon_ring *ring);
961 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
962 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
963 uint32_t **data);
964 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
965 unsigned size, uint32_t *data);
966 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
967 unsigned rptr_offs, u32 nop);
968 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
969
970
971 /* r600 async dma */
972 void r600_dma_stop(struct radeon_device *rdev);
973 int r600_dma_resume(struct radeon_device *rdev);
974 void r600_dma_fini(struct radeon_device *rdev);
975
976 void cayman_dma_stop(struct radeon_device *rdev);
977 int cayman_dma_resume(struct radeon_device *rdev);
978 void cayman_dma_fini(struct radeon_device *rdev);
979
980 /*
981 * CS.
982 */
983 struct radeon_cs_reloc {
984 struct drm_gem_object *gobj;
985 struct radeon_bo *robj;
986 struct ttm_validate_buffer tv;
987 uint64_t gpu_offset;
988 unsigned domain;
989 unsigned alt_domain;
990 uint32_t tiling_flags;
991 uint32_t handle;
992 };
993
994 struct radeon_cs_chunk {
995 uint32_t chunk_id;
996 uint32_t length_dw;
997 uint32_t *kdata;
998 void __user *user_ptr;
999 };
1000
1001 struct radeon_cs_parser {
1002 struct device *dev;
1003 struct radeon_device *rdev;
1004 struct drm_file *filp;
1005 /* chunks */
1006 unsigned nchunks;
1007 struct radeon_cs_chunk *chunks;
1008 uint64_t *chunks_array;
1009 /* IB */
1010 unsigned idx;
1011 /* relocations */
1012 unsigned nrelocs;
1013 struct radeon_cs_reloc *relocs;
1014 struct radeon_cs_reloc **relocs_ptr;
1015 struct radeon_cs_reloc *vm_bos;
1016 struct list_head validated;
1017 unsigned dma_reloc_idx;
1018 /* indices of various chunks */
1019 int chunk_ib_idx;
1020 int chunk_relocs_idx;
1021 int chunk_flags_idx;
1022 int chunk_const_ib_idx;
1023 struct radeon_ib ib;
1024 struct radeon_ib const_ib;
1025 void *track;
1026 unsigned family;
1027 int parser_error;
1028 u32 cs_flags;
1029 u32 ring;
1030 s32 priority;
1031 struct ww_acquire_ctx ticket;
1032 };
1033
1034 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1035 {
1036 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1037
1038 if (ibc->kdata)
1039 return ibc->kdata[idx];
1040 return p->ib.ptr[idx];
1041 }
1042
1043
1044 struct radeon_cs_packet {
1045 unsigned idx;
1046 unsigned type;
1047 unsigned reg;
1048 unsigned opcode;
1049 int count;
1050 unsigned one_reg_wr;
1051 };
1052
1053 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1054 struct radeon_cs_packet *pkt,
1055 unsigned idx, unsigned reg);
1056 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1057 struct radeon_cs_packet *pkt);
1058
1059
1060 /*
1061 * AGP
1062 */
1063 int radeon_agp_init(struct radeon_device *rdev);
1064 void radeon_agp_resume(struct radeon_device *rdev);
1065 void radeon_agp_suspend(struct radeon_device *rdev);
1066 void radeon_agp_fini(struct radeon_device *rdev);
1067
1068
1069 /*
1070 * Writeback
1071 */
1072 struct radeon_wb {
1073 struct radeon_bo *wb_obj;
1074 volatile uint32_t *wb;
1075 uint64_t gpu_addr;
1076 bool enabled;
1077 bool use_event;
1078 };
1079
1080 #define RADEON_WB_SCRATCH_OFFSET 0
1081 #define RADEON_WB_RING0_NEXT_RPTR 256
1082 #define RADEON_WB_CP_RPTR_OFFSET 1024
1083 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1084 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1085 #define R600_WB_DMA_RPTR_OFFSET 1792
1086 #define R600_WB_IH_WPTR_OFFSET 2048
1087 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1088 #define R600_WB_EVENT_OFFSET 3072
1089 #define CIK_WB_CP1_WPTR_OFFSET 3328
1090 #define CIK_WB_CP2_WPTR_OFFSET 3584
1091
1092 /**
1093 * struct radeon_pm - power management datas
1094 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1095 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1096 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1097 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1098 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1099 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1100 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1101 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1102 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1103 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1104 * @needed_bandwidth: current bandwidth needs
1105 *
1106 * It keeps track of various data needed to take powermanagement decision.
1107 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1108 * Equation between gpu/memory clock and available bandwidth is hw dependent
1109 * (type of memory, bus size, efficiency, ...)
1110 */
1111
1112 enum radeon_pm_method {
1113 PM_METHOD_PROFILE,
1114 PM_METHOD_DYNPM,
1115 PM_METHOD_DPM,
1116 };
1117
1118 enum radeon_dynpm_state {
1119 DYNPM_STATE_DISABLED,
1120 DYNPM_STATE_MINIMUM,
1121 DYNPM_STATE_PAUSED,
1122 DYNPM_STATE_ACTIVE,
1123 DYNPM_STATE_SUSPENDED,
1124 };
1125 enum radeon_dynpm_action {
1126 DYNPM_ACTION_NONE,
1127 DYNPM_ACTION_MINIMUM,
1128 DYNPM_ACTION_DOWNCLOCK,
1129 DYNPM_ACTION_UPCLOCK,
1130 DYNPM_ACTION_DEFAULT
1131 };
1132
1133 enum radeon_voltage_type {
1134 VOLTAGE_NONE = 0,
1135 VOLTAGE_GPIO,
1136 VOLTAGE_VDDC,
1137 VOLTAGE_SW
1138 };
1139
1140 enum radeon_pm_state_type {
1141 /* not used for dpm */
1142 POWER_STATE_TYPE_DEFAULT,
1143 POWER_STATE_TYPE_POWERSAVE,
1144 /* user selectable states */
1145 POWER_STATE_TYPE_BATTERY,
1146 POWER_STATE_TYPE_BALANCED,
1147 POWER_STATE_TYPE_PERFORMANCE,
1148 /* internal states */
1149 POWER_STATE_TYPE_INTERNAL_UVD,
1150 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1151 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1152 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1153 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1154 POWER_STATE_TYPE_INTERNAL_BOOT,
1155 POWER_STATE_TYPE_INTERNAL_THERMAL,
1156 POWER_STATE_TYPE_INTERNAL_ACPI,
1157 POWER_STATE_TYPE_INTERNAL_ULV,
1158 POWER_STATE_TYPE_INTERNAL_3DPERF,
1159 };
1160
1161 enum radeon_pm_profile_type {
1162 PM_PROFILE_DEFAULT,
1163 PM_PROFILE_AUTO,
1164 PM_PROFILE_LOW,
1165 PM_PROFILE_MID,
1166 PM_PROFILE_HIGH,
1167 };
1168
1169 #define PM_PROFILE_DEFAULT_IDX 0
1170 #define PM_PROFILE_LOW_SH_IDX 1
1171 #define PM_PROFILE_MID_SH_IDX 2
1172 #define PM_PROFILE_HIGH_SH_IDX 3
1173 #define PM_PROFILE_LOW_MH_IDX 4
1174 #define PM_PROFILE_MID_MH_IDX 5
1175 #define PM_PROFILE_HIGH_MH_IDX 6
1176 #define PM_PROFILE_MAX 7
1177
1178 struct radeon_pm_profile {
1179 int dpms_off_ps_idx;
1180 int dpms_on_ps_idx;
1181 int dpms_off_cm_idx;
1182 int dpms_on_cm_idx;
1183 };
1184
1185 enum radeon_int_thermal_type {
1186 THERMAL_TYPE_NONE,
1187 THERMAL_TYPE_EXTERNAL,
1188 THERMAL_TYPE_EXTERNAL_GPIO,
1189 THERMAL_TYPE_RV6XX,
1190 THERMAL_TYPE_RV770,
1191 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1192 THERMAL_TYPE_EVERGREEN,
1193 THERMAL_TYPE_SUMO,
1194 THERMAL_TYPE_NI,
1195 THERMAL_TYPE_SI,
1196 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1197 THERMAL_TYPE_CI,
1198 THERMAL_TYPE_KV,
1199 };
1200
1201 struct radeon_voltage {
1202 enum radeon_voltage_type type;
1203 /* gpio voltage */
1204 struct radeon_gpio_rec gpio;
1205 u32 delay; /* delay in usec from voltage drop to sclk change */
1206 bool active_high; /* voltage drop is active when bit is high */
1207 /* VDDC voltage */
1208 u8 vddc_id; /* index into vddc voltage table */
1209 u8 vddci_id; /* index into vddci voltage table */
1210 bool vddci_enabled;
1211 /* r6xx+ sw */
1212 u16 voltage;
1213 /* evergreen+ vddci */
1214 u16 vddci;
1215 };
1216
1217 /* clock mode flags */
1218 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1219
1220 struct radeon_pm_clock_info {
1221 /* memory clock */
1222 u32 mclk;
1223 /* engine clock */
1224 u32 sclk;
1225 /* voltage info */
1226 struct radeon_voltage voltage;
1227 /* standardized clock flags */
1228 u32 flags;
1229 };
1230
1231 /* state flags */
1232 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1233
1234 struct radeon_power_state {
1235 enum radeon_pm_state_type type;
1236 struct radeon_pm_clock_info *clock_info;
1237 /* number of valid clock modes in this power state */
1238 int num_clock_modes;
1239 struct radeon_pm_clock_info *default_clock_mode;
1240 /* standardized state flags */
1241 u32 flags;
1242 u32 misc; /* vbios specific flags */
1243 u32 misc2; /* vbios specific flags */
1244 int pcie_lanes; /* pcie lanes */
1245 };
1246
1247 /*
1248 * Some modes are overclocked by very low value, accept them
1249 */
1250 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1251
1252 enum radeon_dpm_auto_throttle_src {
1253 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1254 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1255 };
1256
1257 enum radeon_dpm_event_src {
1258 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1259 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1260 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1261 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1262 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1263 };
1264
1265 #define RADEON_MAX_VCE_LEVELS 6
1266
1267 enum radeon_vce_level {
1268 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1269 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1270 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1271 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1272 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1273 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1274 };
1275
1276 struct radeon_ps {
1277 u32 caps; /* vbios flags */
1278 u32 class; /* vbios flags */
1279 u32 class2; /* vbios flags */
1280 /* UVD clocks */
1281 u32 vclk;
1282 u32 dclk;
1283 /* VCE clocks */
1284 u32 evclk;
1285 u32 ecclk;
1286 bool vce_active;
1287 enum radeon_vce_level vce_level;
1288 /* asic priv */
1289 void *ps_priv;
1290 };
1291
1292 struct radeon_dpm_thermal {
1293 /* thermal interrupt work */
1294 struct work_struct work;
1295 /* low temperature threshold */
1296 int min_temp;
1297 /* high temperature threshold */
1298 int max_temp;
1299 /* was interrupt low to high or high to low */
1300 bool high_to_low;
1301 };
1302
1303 enum radeon_clk_action
1304 {
1305 RADEON_SCLK_UP = 1,
1306 RADEON_SCLK_DOWN
1307 };
1308
1309 struct radeon_blacklist_clocks
1310 {
1311 u32 sclk;
1312 u32 mclk;
1313 enum radeon_clk_action action;
1314 };
1315
1316 struct radeon_clock_and_voltage_limits {
1317 u32 sclk;
1318 u32 mclk;
1319 u16 vddc;
1320 u16 vddci;
1321 };
1322
1323 struct radeon_clock_array {
1324 u32 count;
1325 u32 *values;
1326 };
1327
1328 struct radeon_clock_voltage_dependency_entry {
1329 u32 clk;
1330 u16 v;
1331 };
1332
1333 struct radeon_clock_voltage_dependency_table {
1334 u32 count;
1335 struct radeon_clock_voltage_dependency_entry *entries;
1336 };
1337
1338 union radeon_cac_leakage_entry {
1339 struct {
1340 u16 vddc;
1341 u32 leakage;
1342 };
1343 struct {
1344 u16 vddc1;
1345 u16 vddc2;
1346 u16 vddc3;
1347 };
1348 };
1349
1350 struct radeon_cac_leakage_table {
1351 u32 count;
1352 union radeon_cac_leakage_entry *entries;
1353 };
1354
1355 struct radeon_phase_shedding_limits_entry {
1356 u16 voltage;
1357 u32 sclk;
1358 u32 mclk;
1359 };
1360
1361 struct radeon_phase_shedding_limits_table {
1362 u32 count;
1363 struct radeon_phase_shedding_limits_entry *entries;
1364 };
1365
1366 struct radeon_uvd_clock_voltage_dependency_entry {
1367 u32 vclk;
1368 u32 dclk;
1369 u16 v;
1370 };
1371
1372 struct radeon_uvd_clock_voltage_dependency_table {
1373 u8 count;
1374 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1375 };
1376
1377 struct radeon_vce_clock_voltage_dependency_entry {
1378 u32 ecclk;
1379 u32 evclk;
1380 u16 v;
1381 };
1382
1383 struct radeon_vce_clock_voltage_dependency_table {
1384 u8 count;
1385 struct radeon_vce_clock_voltage_dependency_entry *entries;
1386 };
1387
1388 struct radeon_ppm_table {
1389 u8 ppm_design;
1390 u16 cpu_core_number;
1391 u32 platform_tdp;
1392 u32 small_ac_platform_tdp;
1393 u32 platform_tdc;
1394 u32 small_ac_platform_tdc;
1395 u32 apu_tdp;
1396 u32 dgpu_tdp;
1397 u32 dgpu_ulv_power;
1398 u32 tj_max;
1399 };
1400
1401 struct radeon_cac_tdp_table {
1402 u16 tdp;
1403 u16 configurable_tdp;
1404 u16 tdc;
1405 u16 battery_power_limit;
1406 u16 small_power_limit;
1407 u16 low_cac_leakage;
1408 u16 high_cac_leakage;
1409 u16 maximum_power_delivery_limit;
1410 };
1411
1412 struct radeon_dpm_dynamic_state {
1413 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1414 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1415 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1416 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1417 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1418 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1419 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1420 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1421 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1422 struct radeon_clock_array valid_sclk_values;
1423 struct radeon_clock_array valid_mclk_values;
1424 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1425 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1426 u32 mclk_sclk_ratio;
1427 u32 sclk_mclk_delta;
1428 u16 vddc_vddci_delta;
1429 u16 min_vddc_for_pcie_gen2;
1430 struct radeon_cac_leakage_table cac_leakage_table;
1431 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1432 struct radeon_ppm_table *ppm_table;
1433 struct radeon_cac_tdp_table *cac_tdp_table;
1434 };
1435
1436 struct radeon_dpm_fan {
1437 u16 t_min;
1438 u16 t_med;
1439 u16 t_high;
1440 u16 pwm_min;
1441 u16 pwm_med;
1442 u16 pwm_high;
1443 u8 t_hyst;
1444 u32 cycle_delay;
1445 u16 t_max;
1446 bool ucode_fan_control;
1447 };
1448
1449 enum radeon_pcie_gen {
1450 RADEON_PCIE_GEN1 = 0,
1451 RADEON_PCIE_GEN2 = 1,
1452 RADEON_PCIE_GEN3 = 2,
1453 RADEON_PCIE_GEN_INVALID = 0xffff
1454 };
1455
1456 enum radeon_dpm_forced_level {
1457 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1458 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1459 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1460 };
1461
1462 struct radeon_vce_state {
1463 /* vce clocks */
1464 u32 evclk;
1465 u32 ecclk;
1466 /* gpu clocks */
1467 u32 sclk;
1468 u32 mclk;
1469 u8 clk_idx;
1470 u8 pstate;
1471 };
1472
1473 struct radeon_dpm {
1474 struct radeon_ps *ps;
1475 /* number of valid power states */
1476 int num_ps;
1477 /* current power state that is active */
1478 struct radeon_ps *current_ps;
1479 /* requested power state */
1480 struct radeon_ps *requested_ps;
1481 /* boot up power state */
1482 struct radeon_ps *boot_ps;
1483 /* default uvd power state */
1484 struct radeon_ps *uvd_ps;
1485 /* vce requirements */
1486 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1487 enum radeon_vce_level vce_level;
1488 enum radeon_pm_state_type state;
1489 enum radeon_pm_state_type user_state;
1490 u32 platform_caps;
1491 u32 voltage_response_time;
1492 u32 backbias_response_time;
1493 void *priv;
1494 u32 new_active_crtcs;
1495 int new_active_crtc_count;
1496 u32 current_active_crtcs;
1497 int current_active_crtc_count;
1498 struct radeon_dpm_dynamic_state dyn_state;
1499 struct radeon_dpm_fan fan;
1500 u32 tdp_limit;
1501 u32 near_tdp_limit;
1502 u32 near_tdp_limit_adjusted;
1503 u32 sq_ramping_threshold;
1504 u32 cac_leakage;
1505 u16 tdp_od_limit;
1506 u32 tdp_adjustment;
1507 u16 load_line_slope;
1508 bool power_control;
1509 bool ac_power;
1510 /* special states active */
1511 bool thermal_active;
1512 bool uvd_active;
1513 bool vce_active;
1514 /* thermal handling */
1515 struct radeon_dpm_thermal thermal;
1516 /* forced levels */
1517 enum radeon_dpm_forced_level forced_level;
1518 /* track UVD streams */
1519 unsigned sd;
1520 unsigned hd;
1521 };
1522
1523 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1524 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1525
1526 struct radeon_pm {
1527 struct mutex mutex;
1528 /* write locked while reprogramming mclk */
1529 struct rw_semaphore mclk_lock;
1530 u32 active_crtcs;
1531 int active_crtc_count;
1532 int req_vblank;
1533 bool vblank_sync;
1534 fixed20_12 max_bandwidth;
1535 fixed20_12 igp_sideport_mclk;
1536 fixed20_12 igp_system_mclk;
1537 fixed20_12 igp_ht_link_clk;
1538 fixed20_12 igp_ht_link_width;
1539 fixed20_12 k8_bandwidth;
1540 fixed20_12 sideport_bandwidth;
1541 fixed20_12 ht_bandwidth;
1542 fixed20_12 core_bandwidth;
1543 fixed20_12 sclk;
1544 fixed20_12 mclk;
1545 fixed20_12 needed_bandwidth;
1546 struct radeon_power_state *power_state;
1547 /* number of valid power states */
1548 int num_power_states;
1549 int current_power_state_index;
1550 int current_clock_mode_index;
1551 int requested_power_state_index;
1552 int requested_clock_mode_index;
1553 int default_power_state_index;
1554 u32 current_sclk;
1555 u32 current_mclk;
1556 u16 current_vddc;
1557 u16 current_vddci;
1558 u32 default_sclk;
1559 u32 default_mclk;
1560 u16 default_vddc;
1561 u16 default_vddci;
1562 struct radeon_i2c_chan *i2c_bus;
1563 /* selected pm method */
1564 enum radeon_pm_method pm_method;
1565 /* dynpm power management */
1566 struct delayed_work dynpm_idle_work;
1567 enum radeon_dynpm_state dynpm_state;
1568 enum radeon_dynpm_action dynpm_planned_action;
1569 unsigned long dynpm_action_timeout;
1570 bool dynpm_can_upclock;
1571 bool dynpm_can_downclock;
1572 /* profile-based power management */
1573 enum radeon_pm_profile_type profile;
1574 int profile_index;
1575 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1576 /* internal thermal controller on rv6xx+ */
1577 enum radeon_int_thermal_type int_thermal_type;
1578 struct device *int_hwmon_dev;
1579 /* dpm */
1580 bool dpm_enabled;
1581 struct radeon_dpm dpm;
1582 };
1583
1584 int radeon_pm_get_type_index(struct radeon_device *rdev,
1585 enum radeon_pm_state_type ps_type,
1586 int instance);
1587 /*
1588 * UVD
1589 */
1590 #define RADEON_MAX_UVD_HANDLES 10
1591 #define RADEON_UVD_STACK_SIZE (1024*1024)
1592 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1593
1594 struct radeon_uvd {
1595 struct radeon_bo *vcpu_bo;
1596 void *cpu_addr;
1597 uint64_t gpu_addr;
1598 void *saved_bo;
1599 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1600 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1601 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1602 struct delayed_work idle_work;
1603 };
1604
1605 int radeon_uvd_init(struct radeon_device *rdev);
1606 void radeon_uvd_fini(struct radeon_device *rdev);
1607 int radeon_uvd_suspend(struct radeon_device *rdev);
1608 int radeon_uvd_resume(struct radeon_device *rdev);
1609 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1610 uint32_t handle, struct radeon_fence **fence);
1611 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1612 uint32_t handle, struct radeon_fence **fence);
1613 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1614 void radeon_uvd_free_handles(struct radeon_device *rdev,
1615 struct drm_file *filp);
1616 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1617 void radeon_uvd_note_usage(struct radeon_device *rdev);
1618 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1619 unsigned vclk, unsigned dclk,
1620 unsigned vco_min, unsigned vco_max,
1621 unsigned fb_factor, unsigned fb_mask,
1622 unsigned pd_min, unsigned pd_max,
1623 unsigned pd_even,
1624 unsigned *optimal_fb_div,
1625 unsigned *optimal_vclk_div,
1626 unsigned *optimal_dclk_div);
1627 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1628 unsigned cg_upll_func_cntl);
1629
1630 /*
1631 * VCE
1632 */
1633 #define RADEON_MAX_VCE_HANDLES 16
1634 #define RADEON_VCE_STACK_SIZE (1024*1024)
1635 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1636
1637 struct radeon_vce {
1638 struct radeon_bo *vcpu_bo;
1639 uint64_t gpu_addr;
1640 unsigned fw_version;
1641 unsigned fb_version;
1642 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1643 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1644 struct delayed_work idle_work;
1645 };
1646
1647 int radeon_vce_init(struct radeon_device *rdev);
1648 void radeon_vce_fini(struct radeon_device *rdev);
1649 int radeon_vce_suspend(struct radeon_device *rdev);
1650 int radeon_vce_resume(struct radeon_device *rdev);
1651 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1652 uint32_t handle, struct radeon_fence **fence);
1653 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1654 uint32_t handle, struct radeon_fence **fence);
1655 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1656 void radeon_vce_note_usage(struct radeon_device *rdev);
1657 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi);
1658 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1659 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1660 struct radeon_ring *ring,
1661 struct radeon_semaphore *semaphore,
1662 bool emit_wait);
1663 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1664 void radeon_vce_fence_emit(struct radeon_device *rdev,
1665 struct radeon_fence *fence);
1666 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1667 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1668
1669 struct r600_audio_pin {
1670 int channels;
1671 int rate;
1672 int bits_per_sample;
1673 u8 status_bits;
1674 u8 category_code;
1675 u32 offset;
1676 bool connected;
1677 u32 id;
1678 };
1679
1680 struct r600_audio {
1681 bool enabled;
1682 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1683 int num_pins;
1684 };
1685
1686 /*
1687 * Benchmarking
1688 */
1689 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1690
1691
1692 /*
1693 * Testing
1694 */
1695 void radeon_test_moves(struct radeon_device *rdev);
1696 void radeon_test_ring_sync(struct radeon_device *rdev,
1697 struct radeon_ring *cpA,
1698 struct radeon_ring *cpB);
1699 void radeon_test_syncing(struct radeon_device *rdev);
1700
1701
1702 /*
1703 * Debugfs
1704 */
1705 struct radeon_debugfs {
1706 struct drm_info_list *files;
1707 unsigned num_files;
1708 };
1709
1710 int radeon_debugfs_add_files(struct radeon_device *rdev,
1711 struct drm_info_list *files,
1712 unsigned nfiles);
1713 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1714
1715 /*
1716 * ASIC ring specific functions.
1717 */
1718 struct radeon_asic_ring {
1719 /* ring read/write ptr handling */
1720 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1721 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1722 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1723
1724 /* validating and patching of IBs */
1725 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1726 int (*cs_parse)(struct radeon_cs_parser *p);
1727
1728 /* command emmit functions */
1729 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1730 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1731 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1732 struct radeon_semaphore *semaphore, bool emit_wait);
1733 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1734
1735 /* testing functions */
1736 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1737 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1738 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1739
1740 /* deprecated */
1741 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1742 };
1743
1744 /*
1745 * ASIC specific functions.
1746 */
1747 struct radeon_asic {
1748 int (*init)(struct radeon_device *rdev);
1749 void (*fini)(struct radeon_device *rdev);
1750 int (*resume)(struct radeon_device *rdev);
1751 int (*suspend)(struct radeon_device *rdev);
1752 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1753 int (*asic_reset)(struct radeon_device *rdev);
1754 /* ioctl hw specific callback. Some hw might want to perform special
1755 * operation on specific ioctl. For instance on wait idle some hw
1756 * might want to perform and HDP flush through MMIO as it seems that
1757 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1758 * through ring.
1759 */
1760 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1761 /* check if 3D engine is idle */
1762 bool (*gui_idle)(struct radeon_device *rdev);
1763 /* wait for mc_idle */
1764 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1765 /* get the reference clock */
1766 u32 (*get_xclk)(struct radeon_device *rdev);
1767 /* get the gpu clock counter */
1768 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1769 /* gart */
1770 struct {
1771 void (*tlb_flush)(struct radeon_device *rdev);
1772 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1773 } gart;
1774 struct {
1775 int (*init)(struct radeon_device *rdev);
1776 void (*fini)(struct radeon_device *rdev);
1777 void (*set_page)(struct radeon_device *rdev,
1778 struct radeon_ib *ib,
1779 uint64_t pe,
1780 uint64_t addr, unsigned count,
1781 uint32_t incr, uint32_t flags);
1782 } vm;
1783 /* ring specific callbacks */
1784 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1785 /* irqs */
1786 struct {
1787 int (*set)(struct radeon_device *rdev);
1788 int (*process)(struct radeon_device *rdev);
1789 } irq;
1790 /* displays */
1791 struct {
1792 /* display watermarks */
1793 void (*bandwidth_update)(struct radeon_device *rdev);
1794 /* get frame count */
1795 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1796 /* wait for vblank */
1797 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1798 /* set backlight level */
1799 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1800 /* get backlight level */
1801 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1802 /* audio callbacks */
1803 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1804 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1805 } display;
1806 /* copy functions for bo handling */
1807 struct {
1808 int (*blit)(struct radeon_device *rdev,
1809 uint64_t src_offset,
1810 uint64_t dst_offset,
1811 unsigned num_gpu_pages,
1812 struct radeon_fence **fence);
1813 u32 blit_ring_index;
1814 int (*dma)(struct radeon_device *rdev,
1815 uint64_t src_offset,
1816 uint64_t dst_offset,
1817 unsigned num_gpu_pages,
1818 struct radeon_fence **fence);
1819 u32 dma_ring_index;
1820 /* method used for bo copy */
1821 int (*copy)(struct radeon_device *rdev,
1822 uint64_t src_offset,
1823 uint64_t dst_offset,
1824 unsigned num_gpu_pages,
1825 struct radeon_fence **fence);
1826 /* ring used for bo copies */
1827 u32 copy_ring_index;
1828 } copy;
1829 /* surfaces */
1830 struct {
1831 int (*set_reg)(struct radeon_device *rdev, int reg,
1832 uint32_t tiling_flags, uint32_t pitch,
1833 uint32_t offset, uint32_t obj_size);
1834 void (*clear_reg)(struct radeon_device *rdev, int reg);
1835 } surface;
1836 /* hotplug detect */
1837 struct {
1838 void (*init)(struct radeon_device *rdev);
1839 void (*fini)(struct radeon_device *rdev);
1840 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1841 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1842 } hpd;
1843 /* static power management */
1844 struct {
1845 void (*misc)(struct radeon_device *rdev);
1846 void (*prepare)(struct radeon_device *rdev);
1847 void (*finish)(struct radeon_device *rdev);
1848 void (*init_profile)(struct radeon_device *rdev);
1849 void (*get_dynpm_state)(struct radeon_device *rdev);
1850 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1851 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1852 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1853 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1854 int (*get_pcie_lanes)(struct radeon_device *rdev);
1855 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1856 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1857 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1858 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1859 int (*get_temperature)(struct radeon_device *rdev);
1860 } pm;
1861 /* dynamic power management */
1862 struct {
1863 int (*init)(struct radeon_device *rdev);
1864 void (*setup_asic)(struct radeon_device *rdev);
1865 int (*enable)(struct radeon_device *rdev);
1866 int (*late_enable)(struct radeon_device *rdev);
1867 void (*disable)(struct radeon_device *rdev);
1868 int (*pre_set_power_state)(struct radeon_device *rdev);
1869 int (*set_power_state)(struct radeon_device *rdev);
1870 void (*post_set_power_state)(struct radeon_device *rdev);
1871 void (*display_configuration_changed)(struct radeon_device *rdev);
1872 void (*fini)(struct radeon_device *rdev);
1873 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1874 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1875 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1876 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1877 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1878 bool (*vblank_too_short)(struct radeon_device *rdev);
1879 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1880 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1881 } dpm;
1882 /* pageflipping */
1883 struct {
1884 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1885 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1886 } pflip;
1887 };
1888
1889 /*
1890 * Asic structures
1891 */
1892 struct r100_asic {
1893 const unsigned *reg_safe_bm;
1894 unsigned reg_safe_bm_size;
1895 u32 hdp_cntl;
1896 };
1897
1898 struct r300_asic {
1899 const unsigned *reg_safe_bm;
1900 unsigned reg_safe_bm_size;
1901 u32 resync_scratch;
1902 u32 hdp_cntl;
1903 };
1904
1905 struct r600_asic {
1906 unsigned max_pipes;
1907 unsigned max_tile_pipes;
1908 unsigned max_simds;
1909 unsigned max_backends;
1910 unsigned max_gprs;
1911 unsigned max_threads;
1912 unsigned max_stack_entries;
1913 unsigned max_hw_contexts;
1914 unsigned max_gs_threads;
1915 unsigned sx_max_export_size;
1916 unsigned sx_max_export_pos_size;
1917 unsigned sx_max_export_smx_size;
1918 unsigned sq_num_cf_insts;
1919 unsigned tiling_nbanks;
1920 unsigned tiling_npipes;
1921 unsigned tiling_group_size;
1922 unsigned tile_config;
1923 unsigned backend_map;
1924 };
1925
1926 struct rv770_asic {
1927 unsigned max_pipes;
1928 unsigned max_tile_pipes;
1929 unsigned max_simds;
1930 unsigned max_backends;
1931 unsigned max_gprs;
1932 unsigned max_threads;
1933 unsigned max_stack_entries;
1934 unsigned max_hw_contexts;
1935 unsigned max_gs_threads;
1936 unsigned sx_max_export_size;
1937 unsigned sx_max_export_pos_size;
1938 unsigned sx_max_export_smx_size;
1939 unsigned sq_num_cf_insts;
1940 unsigned sx_num_of_sets;
1941 unsigned sc_prim_fifo_size;
1942 unsigned sc_hiz_tile_fifo_size;
1943 unsigned sc_earlyz_tile_fifo_fize;
1944 unsigned tiling_nbanks;
1945 unsigned tiling_npipes;
1946 unsigned tiling_group_size;
1947 unsigned tile_config;
1948 unsigned backend_map;
1949 };
1950
1951 struct evergreen_asic {
1952 unsigned num_ses;
1953 unsigned max_pipes;
1954 unsigned max_tile_pipes;
1955 unsigned max_simds;
1956 unsigned max_backends;
1957 unsigned max_gprs;
1958 unsigned max_threads;
1959 unsigned max_stack_entries;
1960 unsigned max_hw_contexts;
1961 unsigned max_gs_threads;
1962 unsigned sx_max_export_size;
1963 unsigned sx_max_export_pos_size;
1964 unsigned sx_max_export_smx_size;
1965 unsigned sq_num_cf_insts;
1966 unsigned sx_num_of_sets;
1967 unsigned sc_prim_fifo_size;
1968 unsigned sc_hiz_tile_fifo_size;
1969 unsigned sc_earlyz_tile_fifo_size;
1970 unsigned tiling_nbanks;
1971 unsigned tiling_npipes;
1972 unsigned tiling_group_size;
1973 unsigned tile_config;
1974 unsigned backend_map;
1975 };
1976
1977 struct cayman_asic {
1978 unsigned max_shader_engines;
1979 unsigned max_pipes_per_simd;
1980 unsigned max_tile_pipes;
1981 unsigned max_simds_per_se;
1982 unsigned max_backends_per_se;
1983 unsigned max_texture_channel_caches;
1984 unsigned max_gprs;
1985 unsigned max_threads;
1986 unsigned max_gs_threads;
1987 unsigned max_stack_entries;
1988 unsigned sx_num_of_sets;
1989 unsigned sx_max_export_size;
1990 unsigned sx_max_export_pos_size;
1991 unsigned sx_max_export_smx_size;
1992 unsigned max_hw_contexts;
1993 unsigned sq_num_cf_insts;
1994 unsigned sc_prim_fifo_size;
1995 unsigned sc_hiz_tile_fifo_size;
1996 unsigned sc_earlyz_tile_fifo_size;
1997
1998 unsigned num_shader_engines;
1999 unsigned num_shader_pipes_per_simd;
2000 unsigned num_tile_pipes;
2001 unsigned num_simds_per_se;
2002 unsigned num_backends_per_se;
2003 unsigned backend_disable_mask_per_asic;
2004 unsigned backend_map;
2005 unsigned num_texture_channel_caches;
2006 unsigned mem_max_burst_length_bytes;
2007 unsigned mem_row_size_in_kb;
2008 unsigned shader_engine_tile_size;
2009 unsigned num_gpus;
2010 unsigned multi_gpu_tile_size;
2011
2012 unsigned tile_config;
2013 };
2014
2015 struct si_asic {
2016 unsigned max_shader_engines;
2017 unsigned max_tile_pipes;
2018 unsigned max_cu_per_sh;
2019 unsigned max_sh_per_se;
2020 unsigned max_backends_per_se;
2021 unsigned max_texture_channel_caches;
2022 unsigned max_gprs;
2023 unsigned max_gs_threads;
2024 unsigned max_hw_contexts;
2025 unsigned sc_prim_fifo_size_frontend;
2026 unsigned sc_prim_fifo_size_backend;
2027 unsigned sc_hiz_tile_fifo_size;
2028 unsigned sc_earlyz_tile_fifo_size;
2029
2030 unsigned num_tile_pipes;
2031 unsigned backend_enable_mask;
2032 unsigned backend_disable_mask_per_asic;
2033 unsigned backend_map;
2034 unsigned num_texture_channel_caches;
2035 unsigned mem_max_burst_length_bytes;
2036 unsigned mem_row_size_in_kb;
2037 unsigned shader_engine_tile_size;
2038 unsigned num_gpus;
2039 unsigned multi_gpu_tile_size;
2040
2041 unsigned tile_config;
2042 uint32_t tile_mode_array[32];
2043 };
2044
2045 struct cik_asic {
2046 unsigned max_shader_engines;
2047 unsigned max_tile_pipes;
2048 unsigned max_cu_per_sh;
2049 unsigned max_sh_per_se;
2050 unsigned max_backends_per_se;
2051 unsigned max_texture_channel_caches;
2052 unsigned max_gprs;
2053 unsigned max_gs_threads;
2054 unsigned max_hw_contexts;
2055 unsigned sc_prim_fifo_size_frontend;
2056 unsigned sc_prim_fifo_size_backend;
2057 unsigned sc_hiz_tile_fifo_size;
2058 unsigned sc_earlyz_tile_fifo_size;
2059
2060 unsigned num_tile_pipes;
2061 unsigned backend_enable_mask;
2062 unsigned backend_disable_mask_per_asic;
2063 unsigned backend_map;
2064 unsigned num_texture_channel_caches;
2065 unsigned mem_max_burst_length_bytes;
2066 unsigned mem_row_size_in_kb;
2067 unsigned shader_engine_tile_size;
2068 unsigned num_gpus;
2069 unsigned multi_gpu_tile_size;
2070
2071 unsigned tile_config;
2072 uint32_t tile_mode_array[32];
2073 uint32_t macrotile_mode_array[16];
2074 };
2075
2076 union radeon_asic_config {
2077 struct r300_asic r300;
2078 struct r100_asic r100;
2079 struct r600_asic r600;
2080 struct rv770_asic rv770;
2081 struct evergreen_asic evergreen;
2082 struct cayman_asic cayman;
2083 struct si_asic si;
2084 struct cik_asic cik;
2085 };
2086
2087 /*
2088 * asic initizalization from radeon_asic.c
2089 */
2090 void radeon_agp_disable(struct radeon_device *rdev);
2091 int radeon_asic_init(struct radeon_device *rdev);
2092
2093
2094 /*
2095 * IOCTL.
2096 */
2097 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2098 struct drm_file *filp);
2099 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2100 struct drm_file *filp);
2101 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2102 struct drm_file *file_priv);
2103 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2104 struct drm_file *file_priv);
2105 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2106 struct drm_file *file_priv);
2107 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2108 struct drm_file *file_priv);
2109 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2110 struct drm_file *filp);
2111 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2112 struct drm_file *filp);
2113 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2114 struct drm_file *filp);
2115 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2116 struct drm_file *filp);
2117 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2118 struct drm_file *filp);
2119 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2120 struct drm_file *filp);
2121 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2122 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2123 struct drm_file *filp);
2124 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2125 struct drm_file *filp);
2126
2127 /* VRAM scratch page for HDP bug, default vram page */
2128 struct r600_vram_scratch {
2129 struct radeon_bo *robj;
2130 volatile uint32_t *ptr;
2131 u64 gpu_addr;
2132 };
2133
2134 /*
2135 * ACPI
2136 */
2137 struct radeon_atif_notification_cfg {
2138 bool enabled;
2139 int command_code;
2140 };
2141
2142 struct radeon_atif_notifications {
2143 bool display_switch;
2144 bool expansion_mode_change;
2145 bool thermal_state;
2146 bool forced_power_state;
2147 bool system_power_state;
2148 bool display_conf_change;
2149 bool px_gfx_switch;
2150 bool brightness_change;
2151 bool dgpu_display_event;
2152 };
2153
2154 struct radeon_atif_functions {
2155 bool system_params;
2156 bool sbios_requests;
2157 bool select_active_disp;
2158 bool lid_state;
2159 bool get_tv_standard;
2160 bool set_tv_standard;
2161 bool get_panel_expansion_mode;
2162 bool set_panel_expansion_mode;
2163 bool temperature_change;
2164 bool graphics_device_types;
2165 };
2166
2167 struct radeon_atif {
2168 struct radeon_atif_notifications notifications;
2169 struct radeon_atif_functions functions;
2170 struct radeon_atif_notification_cfg notification_cfg;
2171 struct radeon_encoder *encoder_for_bl;
2172 };
2173
2174 struct radeon_atcs_functions {
2175 bool get_ext_state;
2176 bool pcie_perf_req;
2177 bool pcie_dev_rdy;
2178 bool pcie_bus_width;
2179 };
2180
2181 struct radeon_atcs {
2182 struct radeon_atcs_functions functions;
2183 };
2184
2185 /*
2186 * Core structure, functions and helpers.
2187 */
2188 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2189 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2190
2191 struct radeon_device {
2192 struct device *dev;
2193 struct drm_device *ddev;
2194 struct pci_dev *pdev;
2195 struct rw_semaphore exclusive_lock;
2196 /* ASIC */
2197 union radeon_asic_config config;
2198 enum radeon_family family;
2199 unsigned long flags;
2200 int usec_timeout;
2201 enum radeon_pll_errata pll_errata;
2202 int num_gb_pipes;
2203 int num_z_pipes;
2204 int disp_priority;
2205 /* BIOS */
2206 uint8_t *bios;
2207 bool is_atom_bios;
2208 uint16_t bios_header_start;
2209 struct radeon_bo *stollen_vga_memory;
2210 /* Register mmio */
2211 resource_size_t rmmio_base;
2212 resource_size_t rmmio_size;
2213 /* protects concurrent MM_INDEX/DATA based register access */
2214 spinlock_t mmio_idx_lock;
2215 /* protects concurrent SMC based register access */
2216 spinlock_t smc_idx_lock;
2217 /* protects concurrent PLL register access */
2218 spinlock_t pll_idx_lock;
2219 /* protects concurrent MC register access */
2220 spinlock_t mc_idx_lock;
2221 /* protects concurrent PCIE register access */
2222 spinlock_t pcie_idx_lock;
2223 /* protects concurrent PCIE_PORT register access */
2224 spinlock_t pciep_idx_lock;
2225 /* protects concurrent PIF register access */
2226 spinlock_t pif_idx_lock;
2227 /* protects concurrent CG register access */
2228 spinlock_t cg_idx_lock;
2229 /* protects concurrent UVD register access */
2230 spinlock_t uvd_idx_lock;
2231 /* protects concurrent RCU register access */
2232 spinlock_t rcu_idx_lock;
2233 /* protects concurrent DIDT register access */
2234 spinlock_t didt_idx_lock;
2235 /* protects concurrent ENDPOINT (audio) register access */
2236 spinlock_t end_idx_lock;
2237 void __iomem *rmmio;
2238 radeon_rreg_t mc_rreg;
2239 radeon_wreg_t mc_wreg;
2240 radeon_rreg_t pll_rreg;
2241 radeon_wreg_t pll_wreg;
2242 uint32_t pcie_reg_mask;
2243 radeon_rreg_t pciep_rreg;
2244 radeon_wreg_t pciep_wreg;
2245 /* io port */
2246 void __iomem *rio_mem;
2247 resource_size_t rio_mem_size;
2248 struct radeon_clock clock;
2249 struct radeon_mc mc;
2250 struct radeon_gart gart;
2251 struct radeon_mode_info mode_info;
2252 struct radeon_scratch scratch;
2253 struct radeon_doorbell doorbell;
2254 struct radeon_mman mman;
2255 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2256 wait_queue_head_t fence_queue;
2257 struct mutex ring_lock;
2258 struct radeon_ring ring[RADEON_NUM_RINGS];
2259 bool ib_pool_ready;
2260 struct radeon_sa_manager ring_tmp_bo;
2261 struct radeon_irq irq;
2262 struct radeon_asic *asic;
2263 struct radeon_gem gem;
2264 struct radeon_pm pm;
2265 struct radeon_uvd uvd;
2266 struct radeon_vce vce;
2267 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2268 struct radeon_wb wb;
2269 struct radeon_dummy_page dummy_page;
2270 bool shutdown;
2271 bool suspend;
2272 bool need_dma32;
2273 bool accel_working;
2274 bool fastfb_working; /* IGP feature*/
2275 bool needs_reset;
2276 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2277 const struct firmware *me_fw; /* all family ME firmware */
2278 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2279 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2280 const struct firmware *mc_fw; /* NI MC firmware */
2281 const struct firmware *ce_fw; /* SI CE firmware */
2282 const struct firmware *mec_fw; /* CIK MEC firmware */
2283 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2284 const struct firmware *smc_fw; /* SMC firmware */
2285 const struct firmware *uvd_fw; /* UVD firmware */
2286 const struct firmware *vce_fw; /* VCE firmware */
2287 struct r600_vram_scratch vram_scratch;
2288 int msi_enabled; /* msi enabled */
2289 struct r600_ih ih; /* r6/700 interrupt ring */
2290 struct radeon_rlc rlc;
2291 struct radeon_mec mec;
2292 struct work_struct hotplug_work;
2293 struct work_struct audio_work;
2294 struct work_struct reset_work;
2295 int num_crtc; /* number of crtcs */
2296 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2297 bool has_uvd;
2298 struct r600_audio audio; /* audio stuff */
2299 struct notifier_block acpi_nb;
2300 /* only one userspace can use Hyperz features or CMASK at a time */
2301 struct drm_file *hyperz_filp;
2302 struct drm_file *cmask_filp;
2303 /* i2c buses */
2304 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2305 /* debugfs */
2306 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2307 unsigned debugfs_count;
2308 /* virtual memory */
2309 struct radeon_vm_manager vm_manager;
2310 struct mutex gpu_clock_mutex;
2311 /* memory stats */
2312 atomic64_t vram_usage;
2313 atomic64_t gtt_usage;
2314 atomic64_t num_bytes_moved;
2315 /* ACPI interface */
2316 struct radeon_atif atif;
2317 struct radeon_atcs atcs;
2318 /* srbm instance registers */
2319 struct mutex srbm_mutex;
2320 /* clock, powergating flags */
2321 u32 cg_flags;
2322 u32 pg_flags;
2323
2324 struct dev_pm_domain vga_pm_domain;
2325 bool have_disp_power_ref;
2326 };
2327
2328 bool radeon_is_px(struct drm_device *dev);
2329 int radeon_device_init(struct radeon_device *rdev,
2330 struct drm_device *ddev,
2331 struct pci_dev *pdev,
2332 uint32_t flags);
2333 void radeon_device_fini(struct radeon_device *rdev);
2334 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2335
2336 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2337 bool always_indirect);
2338 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2339 bool always_indirect);
2340 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2341 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2342
2343 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2344 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2345
2346 /*
2347 * Cast helper
2348 */
2349 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2350
2351 /*
2352 * Registers read & write functions.
2353 */
2354 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2355 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2356 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2357 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2358 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2359 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2360 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2361 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2362 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2363 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2364 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2365 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2366 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2367 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2368 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2369 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2370 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2371 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2372 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2373 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2374 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2375 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2376 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2377 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2378 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2379 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2380 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2381 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2382 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2383 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2384 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2385 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2386 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2387 #define WREG32_P(reg, val, mask) \
2388 do { \
2389 uint32_t tmp_ = RREG32(reg); \
2390 tmp_ &= (mask); \
2391 tmp_ |= ((val) & ~(mask)); \
2392 WREG32(reg, tmp_); \
2393 } while (0)
2394 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2395 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2396 #define WREG32_PLL_P(reg, val, mask) \
2397 do { \
2398 uint32_t tmp_ = RREG32_PLL(reg); \
2399 tmp_ &= (mask); \
2400 tmp_ |= ((val) & ~(mask)); \
2401 WREG32_PLL(reg, tmp_); \
2402 } while (0)
2403 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2404 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2405 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2406
2407 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2408 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2409
2410 /*
2411 * Indirect registers accessor
2412 */
2413 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2414 {
2415 unsigned long flags;
2416 uint32_t r;
2417
2418 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2419 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2420 r = RREG32(RADEON_PCIE_DATA);
2421 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2422 return r;
2423 }
2424
2425 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2426 {
2427 unsigned long flags;
2428
2429 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2430 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2431 WREG32(RADEON_PCIE_DATA, (v));
2432 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2433 }
2434
2435 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2436 {
2437 unsigned long flags;
2438 u32 r;
2439
2440 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2441 WREG32(TN_SMC_IND_INDEX_0, (reg));
2442 r = RREG32(TN_SMC_IND_DATA_0);
2443 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2444 return r;
2445 }
2446
2447 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2448 {
2449 unsigned long flags;
2450
2451 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2452 WREG32(TN_SMC_IND_INDEX_0, (reg));
2453 WREG32(TN_SMC_IND_DATA_0, (v));
2454 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2455 }
2456
2457 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2458 {
2459 unsigned long flags;
2460 u32 r;
2461
2462 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2463 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2464 r = RREG32(R600_RCU_DATA);
2465 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2466 return r;
2467 }
2468
2469 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2470 {
2471 unsigned long flags;
2472
2473 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2474 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2475 WREG32(R600_RCU_DATA, (v));
2476 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2477 }
2478
2479 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2480 {
2481 unsigned long flags;
2482 u32 r;
2483
2484 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2485 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2486 r = RREG32(EVERGREEN_CG_IND_DATA);
2487 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2488 return r;
2489 }
2490
2491 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2492 {
2493 unsigned long flags;
2494
2495 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2496 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2497 WREG32(EVERGREEN_CG_IND_DATA, (v));
2498 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2499 }
2500
2501 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2502 {
2503 unsigned long flags;
2504 u32 r;
2505
2506 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2507 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2508 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2509 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2510 return r;
2511 }
2512
2513 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2514 {
2515 unsigned long flags;
2516
2517 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2518 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2519 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2520 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2521 }
2522
2523 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2524 {
2525 unsigned long flags;
2526 u32 r;
2527
2528 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2529 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2530 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2531 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2532 return r;
2533 }
2534
2535 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2536 {
2537 unsigned long flags;
2538
2539 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2540 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2541 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2542 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2543 }
2544
2545 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2546 {
2547 unsigned long flags;
2548 u32 r;
2549
2550 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2551 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2552 r = RREG32(R600_UVD_CTX_DATA);
2553 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2554 return r;
2555 }
2556
2557 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2558 {
2559 unsigned long flags;
2560
2561 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2562 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2563 WREG32(R600_UVD_CTX_DATA, (v));
2564 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2565 }
2566
2567
2568 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2569 {
2570 unsigned long flags;
2571 u32 r;
2572
2573 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2574 WREG32(CIK_DIDT_IND_INDEX, (reg));
2575 r = RREG32(CIK_DIDT_IND_DATA);
2576 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2577 return r;
2578 }
2579
2580 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2581 {
2582 unsigned long flags;
2583
2584 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2585 WREG32(CIK_DIDT_IND_INDEX, (reg));
2586 WREG32(CIK_DIDT_IND_DATA, (v));
2587 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2588 }
2589
2590 void r100_pll_errata_after_index(struct radeon_device *rdev);
2591
2592
2593 /*
2594 * ASICs helpers.
2595 */
2596 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2597 (rdev->pdev->device == 0x5969))
2598 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2599 (rdev->family == CHIP_RV200) || \
2600 (rdev->family == CHIP_RS100) || \
2601 (rdev->family == CHIP_RS200) || \
2602 (rdev->family == CHIP_RV250) || \
2603 (rdev->family == CHIP_RV280) || \
2604 (rdev->family == CHIP_RS300))
2605 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2606 (rdev->family == CHIP_RV350) || \
2607 (rdev->family == CHIP_R350) || \
2608 (rdev->family == CHIP_RV380) || \
2609 (rdev->family == CHIP_R420) || \
2610 (rdev->family == CHIP_R423) || \
2611 (rdev->family == CHIP_RV410) || \
2612 (rdev->family == CHIP_RS400) || \
2613 (rdev->family == CHIP_RS480))
2614 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2615 (rdev->ddev->pdev->device == 0x9443) || \
2616 (rdev->ddev->pdev->device == 0x944B) || \
2617 (rdev->ddev->pdev->device == 0x9506) || \
2618 (rdev->ddev->pdev->device == 0x9509) || \
2619 (rdev->ddev->pdev->device == 0x950F) || \
2620 (rdev->ddev->pdev->device == 0x689C) || \
2621 (rdev->ddev->pdev->device == 0x689D))
2622 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2623 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2624 (rdev->family == CHIP_RS690) || \
2625 (rdev->family == CHIP_RS740) || \
2626 (rdev->family >= CHIP_R600))
2627 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2628 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2629 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2630 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2631 (rdev->flags & RADEON_IS_IGP))
2632 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2633 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2634 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2635 (rdev->flags & RADEON_IS_IGP))
2636 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2637 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2638 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2639 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2640 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2641 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI))
2642
2643 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2644 (rdev->ddev->pdev->device == 0x6850) || \
2645 (rdev->ddev->pdev->device == 0x6858) || \
2646 (rdev->ddev->pdev->device == 0x6859) || \
2647 (rdev->ddev->pdev->device == 0x6840) || \
2648 (rdev->ddev->pdev->device == 0x6841) || \
2649 (rdev->ddev->pdev->device == 0x6842) || \
2650 (rdev->ddev->pdev->device == 0x6843))
2651
2652 /*
2653 * BIOS helpers.
2654 */
2655 #define RBIOS8(i) (rdev->bios[i])
2656 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2657 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2658
2659 int radeon_combios_init(struct radeon_device *rdev);
2660 void radeon_combios_fini(struct radeon_device *rdev);
2661 int radeon_atombios_init(struct radeon_device *rdev);
2662 void radeon_atombios_fini(struct radeon_device *rdev);
2663
2664
2665 /*
2666 * RING helpers.
2667 */
2668 #if DRM_DEBUG_CODE == 0
2669 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2670 {
2671 ring->ring[ring->wptr++] = v;
2672 ring->wptr &= ring->ptr_mask;
2673 ring->count_dw--;
2674 ring->ring_free_dw--;
2675 }
2676 #else
2677 /* With debugging this is just too big to inline */
2678 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2679 #endif
2680
2681 /*
2682 * ASICs macro.
2683 */
2684 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2685 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2686 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2687 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2688 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2689 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2690 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2691 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2692 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2693 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2694 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2695 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2696 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2697 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2698 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2699 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2700 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2701 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2702 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2703 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2704 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2705 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2706 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2707 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2708 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2709 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2710 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2711 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2712 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2713 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2714 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2715 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2716 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2717 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2718 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2719 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2720 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2721 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2722 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2723 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2724 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2725 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2726 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2727 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2728 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2729 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2730 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2731 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2732 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2733 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2734 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2735 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2736 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2737 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2738 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2739 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2740 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2741 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2742 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2743 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2744 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2745 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2746 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2747 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2748 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2749 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2750 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2751 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2752 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2753 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2754 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2755 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2756 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2757 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2758 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2759 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2760 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2761 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2762 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2763 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2764 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2765 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2766 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2767 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2768
2769 /* Common functions */
2770 /* AGP */
2771 extern int radeon_gpu_reset(struct radeon_device *rdev);
2772 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2773 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2774 extern void radeon_agp_disable(struct radeon_device *rdev);
2775 extern int radeon_modeset_init(struct radeon_device *rdev);
2776 extern void radeon_modeset_fini(struct radeon_device *rdev);
2777 extern bool radeon_card_posted(struct radeon_device *rdev);
2778 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2779 extern void radeon_update_display_priority(struct radeon_device *rdev);
2780 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2781 extern void radeon_scratch_init(struct radeon_device *rdev);
2782 extern void radeon_wb_fini(struct radeon_device *rdev);
2783 extern int radeon_wb_init(struct radeon_device *rdev);
2784 extern void radeon_wb_disable(struct radeon_device *rdev);
2785 extern void radeon_surface_init(struct radeon_device *rdev);
2786 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2787 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2788 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2789 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2790 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2791 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2792 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2793 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2794 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2795 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2796 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2797 const u32 *registers,
2798 const u32 array_size);
2799
2800 /*
2801 * vm
2802 */
2803 int radeon_vm_manager_init(struct radeon_device *rdev);
2804 void radeon_vm_manager_fini(struct radeon_device *rdev);
2805 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2806 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2807 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2808 struct radeon_vm *vm,
2809 struct list_head *head);
2810 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2811 struct radeon_vm *vm, int ring);
2812 void radeon_vm_flush(struct radeon_device *rdev,
2813 struct radeon_vm *vm,
2814 int ring);
2815 void radeon_vm_fence(struct radeon_device *rdev,
2816 struct radeon_vm *vm,
2817 struct radeon_fence *fence);
2818 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2819 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2820 struct radeon_vm *vm);
2821 int radeon_vm_bo_update(struct radeon_device *rdev,
2822 struct radeon_vm *vm,
2823 struct radeon_bo *bo,
2824 struct ttm_mem_reg *mem);
2825 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2826 struct radeon_bo *bo);
2827 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2828 struct radeon_bo *bo);
2829 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2830 struct radeon_vm *vm,
2831 struct radeon_bo *bo);
2832 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2833 struct radeon_bo_va *bo_va,
2834 uint64_t offset,
2835 uint32_t flags);
2836 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2837 struct radeon_bo_va *bo_va);
2838
2839 /* audio */
2840 void r600_audio_update_hdmi(struct work_struct *work);
2841 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2842 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2843 void r600_audio_enable(struct radeon_device *rdev,
2844 struct r600_audio_pin *pin,
2845 bool enable);
2846 void dce6_audio_enable(struct radeon_device *rdev,
2847 struct r600_audio_pin *pin,
2848 bool enable);
2849
2850 /*
2851 * R600 vram scratch functions
2852 */
2853 int r600_vram_scratch_init(struct radeon_device *rdev);
2854 void r600_vram_scratch_fini(struct radeon_device *rdev);
2855
2856 /*
2857 * r600 cs checking helper
2858 */
2859 unsigned r600_mip_minify(unsigned size, unsigned level);
2860 bool r600_fmt_is_valid_color(u32 format);
2861 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2862 int r600_fmt_get_blocksize(u32 format);
2863 int r600_fmt_get_nblocksx(u32 format, u32 w);
2864 int r600_fmt_get_nblocksy(u32 format, u32 h);
2865
2866 /*
2867 * r600 functions used by radeon_encoder.c
2868 */
2869 struct radeon_hdmi_acr {
2870 u32 clock;
2871
2872 int n_32khz;
2873 int cts_32khz;
2874
2875 int n_44_1khz;
2876 int cts_44_1khz;
2877
2878 int n_48khz;
2879 int cts_48khz;
2880
2881 };
2882
2883 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2884
2885 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2886 u32 tiling_pipe_num,
2887 u32 max_rb_num,
2888 u32 total_max_rb_num,
2889 u32 enabled_rb_mask);
2890
2891 /*
2892 * evergreen functions used by radeon_encoder.c
2893 */
2894
2895 extern int ni_init_microcode(struct radeon_device *rdev);
2896 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2897
2898 /* radeon_acpi.c */
2899 #if defined(CONFIG_ACPI)
2900 extern int radeon_acpi_init(struct radeon_device *rdev);
2901 extern void radeon_acpi_fini(struct radeon_device *rdev);
2902 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2903 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2904 u8 perf_req, bool advertise);
2905 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2906 #else
2907 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2908 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2909 #endif
2910
2911 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2912 struct radeon_cs_packet *pkt,
2913 unsigned idx);
2914 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2915 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2916 struct radeon_cs_packet *pkt);
2917 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2918 struct radeon_cs_reloc **cs_reloc,
2919 int nomm);
2920 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2921 uint32_t *vline_start_end,
2922 uint32_t *vline_status);
2923
2924 #include "radeon_object.h"
2925
2926 #endif
Linux kernel - Deliverables
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