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drm/radeon: Allow write-combined CPU mappings of BOs in GTT (v2)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
102 extern int radeon_hard_reset;
103 extern int radeon_vm_size;
104 extern int radeon_vm_block_size;
105 extern int radeon_deep_color;
106
107 /*
108 * Copy from radeon_drv.h so we don't have to include both and have conflicting
109 * symbol;
110 */
111 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
112 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
113 /* RADEON_IB_POOL_SIZE must be a power of 2 */
114 #define RADEON_IB_POOL_SIZE 16
115 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
116 #define RADEONFB_CONN_LIMIT 4
117 #define RADEON_BIOS_NUM_SCRATCH 8
118
119 /* fence seq are set to this number when signaled */
120 #define RADEON_FENCE_SIGNALED_SEQ 0LL
121
122 /* internal ring indices */
123 /* r1xx+ has gfx CP ring */
124 #define RADEON_RING_TYPE_GFX_INDEX 0
125
126 /* cayman has 2 compute CP rings */
127 #define CAYMAN_RING_TYPE_CP1_INDEX 1
128 #define CAYMAN_RING_TYPE_CP2_INDEX 2
129
130 /* R600+ has an async dma ring */
131 #define R600_RING_TYPE_DMA_INDEX 3
132 /* cayman add a second async dma ring */
133 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
134
135 /* R600+ */
136 #define R600_RING_TYPE_UVD_INDEX 5
137
138 /* TN+ */
139 #define TN_RING_TYPE_VCE1_INDEX 6
140 #define TN_RING_TYPE_VCE2_INDEX 7
141
142 /* max number of rings */
143 #define RADEON_NUM_RINGS 8
144
145 /* number of hw syncs before falling back on blocking */
146 #define RADEON_NUM_SYNCS 4
147
148 /* number of hw syncs before falling back on blocking */
149 #define RADEON_NUM_SYNCS 4
150
151 /* hardcode those limit for now */
152 #define RADEON_VA_IB_OFFSET (1 << 20)
153 #define RADEON_VA_RESERVED_SIZE (8 << 20)
154 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
155
156 /* hard reset data */
157 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
158
159 /* reset flags */
160 #define RADEON_RESET_GFX (1 << 0)
161 #define RADEON_RESET_COMPUTE (1 << 1)
162 #define RADEON_RESET_DMA (1 << 2)
163 #define RADEON_RESET_CP (1 << 3)
164 #define RADEON_RESET_GRBM (1 << 4)
165 #define RADEON_RESET_DMA1 (1 << 5)
166 #define RADEON_RESET_RLC (1 << 6)
167 #define RADEON_RESET_SEM (1 << 7)
168 #define RADEON_RESET_IH (1 << 8)
169 #define RADEON_RESET_VMC (1 << 9)
170 #define RADEON_RESET_MC (1 << 10)
171 #define RADEON_RESET_DISPLAY (1 << 11)
172
173 /* CG block flags */
174 #define RADEON_CG_BLOCK_GFX (1 << 0)
175 #define RADEON_CG_BLOCK_MC (1 << 1)
176 #define RADEON_CG_BLOCK_SDMA (1 << 2)
177 #define RADEON_CG_BLOCK_UVD (1 << 3)
178 #define RADEON_CG_BLOCK_VCE (1 << 4)
179 #define RADEON_CG_BLOCK_HDP (1 << 5)
180 #define RADEON_CG_BLOCK_BIF (1 << 6)
181
182 /* CG flags */
183 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
184 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
185 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
186 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
187 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
188 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
189 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
190 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
191 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
192 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
193 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
194 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
195 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
196 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
197 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
198 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
199 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
200
201 /* PG flags */
202 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
203 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
204 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
205 #define RADEON_PG_SUPPORT_UVD (1 << 3)
206 #define RADEON_PG_SUPPORT_VCE (1 << 4)
207 #define RADEON_PG_SUPPORT_CP (1 << 5)
208 #define RADEON_PG_SUPPORT_GDS (1 << 6)
209 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
210 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
211 #define RADEON_PG_SUPPORT_ACP (1 << 9)
212 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
213
214 /* max cursor sizes (in pixels) */
215 #define CURSOR_WIDTH 64
216 #define CURSOR_HEIGHT 64
217
218 #define CIK_CURSOR_WIDTH 128
219 #define CIK_CURSOR_HEIGHT 128
220
221 /*
222 * Errata workarounds.
223 */
224 enum radeon_pll_errata {
225 CHIP_ERRATA_R300_CG = 0x00000001,
226 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
227 CHIP_ERRATA_PLL_DELAY = 0x00000004
228 };
229
230
231 struct radeon_device;
232
233
234 /*
235 * BIOS.
236 */
237 bool radeon_get_bios(struct radeon_device *rdev);
238
239 /*
240 * Dummy page
241 */
242 struct radeon_dummy_page {
243 struct page *page;
244 dma_addr_t addr;
245 };
246 int radeon_dummy_page_init(struct radeon_device *rdev);
247 void radeon_dummy_page_fini(struct radeon_device *rdev);
248
249
250 /*
251 * Clocks
252 */
253 struct radeon_clock {
254 struct radeon_pll p1pll;
255 struct radeon_pll p2pll;
256 struct radeon_pll dcpll;
257 struct radeon_pll spll;
258 struct radeon_pll mpll;
259 /* 10 Khz units */
260 uint32_t default_mclk;
261 uint32_t default_sclk;
262 uint32_t default_dispclk;
263 uint32_t current_dispclk;
264 uint32_t dp_extclk;
265 uint32_t max_pixel_clock;
266 };
267
268 /*
269 * Power management
270 */
271 int radeon_pm_init(struct radeon_device *rdev);
272 int radeon_pm_late_init(struct radeon_device *rdev);
273 void radeon_pm_fini(struct radeon_device *rdev);
274 void radeon_pm_compute_clocks(struct radeon_device *rdev);
275 void radeon_pm_suspend(struct radeon_device *rdev);
276 void radeon_pm_resume(struct radeon_device *rdev);
277 void radeon_combios_get_power_modes(struct radeon_device *rdev);
278 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
279 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
280 u8 clock_type,
281 u32 clock,
282 bool strobe_mode,
283 struct atom_clock_dividers *dividers);
284 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
285 u32 clock,
286 bool strobe_mode,
287 struct atom_mpll_param *mpll_param);
288 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
289 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
290 u16 voltage_level, u8 voltage_type,
291 u32 *gpio_value, u32 *gpio_mask);
292 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
293 u32 eng_clock, u32 mem_clock);
294 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
295 u8 voltage_type, u16 *voltage_step);
296 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
297 u16 voltage_id, u16 *voltage);
298 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
299 u16 *voltage,
300 u16 leakage_idx);
301 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
302 u16 *leakage_id);
303 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
304 u16 *vddc, u16 *vddci,
305 u16 virtual_voltage_id,
306 u16 vbios_voltage_id);
307 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
308 u8 voltage_type,
309 u16 nominal_voltage,
310 u16 *true_voltage);
311 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
312 u8 voltage_type, u16 *min_voltage);
313 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
314 u8 voltage_type, u16 *max_voltage);
315 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode,
317 struct atom_voltage_table *voltage_table);
318 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
319 u8 voltage_type, u8 voltage_mode);
320 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
321 u8 voltage_type,
322 u8 *svd_gpio_id, u8 *svc_gpio_id);
323 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
324 u32 mem_clock);
325 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
326 u32 mem_clock);
327 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
328 u8 module_index,
329 struct atom_mc_reg_table *reg_table);
330 int radeon_atom_get_memory_info(struct radeon_device *rdev,
331 u8 module_index, struct atom_memory_info *mem_info);
332 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
333 bool gddr5, u8 module_index,
334 struct atom_memory_clock_range_table *mclk_range_table);
335 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
336 u16 voltage_id, u16 *voltage);
337 void rs690_pm_info(struct radeon_device *rdev);
338 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
339 unsigned *bankh, unsigned *mtaspect,
340 unsigned *tile_split);
341
342 /*
343 * Fences.
344 */
345 struct radeon_fence_driver {
346 uint32_t scratch_reg;
347 uint64_t gpu_addr;
348 volatile uint32_t *cpu_addr;
349 /* sync_seq is protected by ring emission lock */
350 uint64_t sync_seq[RADEON_NUM_RINGS];
351 atomic64_t last_seq;
352 bool initialized;
353 };
354
355 struct radeon_fence {
356 struct radeon_device *rdev;
357 struct kref kref;
358 /* protected by radeon_fence.lock */
359 uint64_t seq;
360 /* RB, DMA, etc. */
361 unsigned ring;
362 };
363
364 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
365 int radeon_fence_driver_init(struct radeon_device *rdev);
366 void radeon_fence_driver_fini(struct radeon_device *rdev);
367 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
368 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
369 void radeon_fence_process(struct radeon_device *rdev, int ring);
370 bool radeon_fence_signaled(struct radeon_fence *fence);
371 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
372 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
373 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
374 int radeon_fence_wait_any(struct radeon_device *rdev,
375 struct radeon_fence **fences,
376 bool intr);
377 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
378 void radeon_fence_unref(struct radeon_fence **fence);
379 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
380 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
381 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
382 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
383 struct radeon_fence *b)
384 {
385 if (!a) {
386 return b;
387 }
388
389 if (!b) {
390 return a;
391 }
392
393 BUG_ON(a->ring != b->ring);
394
395 if (a->seq > b->seq) {
396 return a;
397 } else {
398 return b;
399 }
400 }
401
402 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
403 struct radeon_fence *b)
404 {
405 if (!a) {
406 return false;
407 }
408
409 if (!b) {
410 return true;
411 }
412
413 BUG_ON(a->ring != b->ring);
414
415 return a->seq < b->seq;
416 }
417
418 /*
419 * Tiling registers
420 */
421 struct radeon_surface_reg {
422 struct radeon_bo *bo;
423 };
424
425 #define RADEON_GEM_MAX_SURFACES 8
426
427 /*
428 * TTM.
429 */
430 struct radeon_mman {
431 struct ttm_bo_global_ref bo_global_ref;
432 struct drm_global_reference mem_global_ref;
433 struct ttm_bo_device bdev;
434 bool mem_global_referenced;
435 bool initialized;
436
437 #if defined(CONFIG_DEBUG_FS)
438 struct dentry *vram;
439 struct dentry *gtt;
440 #endif
441 };
442
443 /* bo virtual address in a specific vm */
444 struct radeon_bo_va {
445 /* protected by bo being reserved */
446 struct list_head bo_list;
447 uint64_t soffset;
448 uint64_t eoffset;
449 uint32_t flags;
450 bool valid;
451 unsigned ref_count;
452
453 /* protected by vm mutex */
454 struct list_head vm_list;
455 struct list_head vm_status;
456
457 /* constant after initialization */
458 struct radeon_vm *vm;
459 struct radeon_bo *bo;
460 };
461
462 struct radeon_bo {
463 /* Protected by gem.mutex */
464 struct list_head list;
465 /* Protected by tbo.reserved */
466 u32 initial_domain;
467 u32 placements[3];
468 struct ttm_placement placement;
469 struct ttm_buffer_object tbo;
470 struct ttm_bo_kmap_obj kmap;
471 u32 flags;
472 unsigned pin_count;
473 void *kptr;
474 u32 tiling_flags;
475 u32 pitch;
476 int surface_reg;
477 /* list of all virtual address to which this bo
478 * is associated to
479 */
480 struct list_head va;
481 /* Constant after initialization */
482 struct radeon_device *rdev;
483 struct drm_gem_object gem_base;
484
485 struct ttm_bo_kmap_obj dma_buf_vmap;
486 pid_t pid;
487 };
488 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
489
490 int radeon_gem_debugfs_init(struct radeon_device *rdev);
491
492 /* sub-allocation manager, it has to be protected by another lock.
493 * By conception this is an helper for other part of the driver
494 * like the indirect buffer or semaphore, which both have their
495 * locking.
496 *
497 * Principe is simple, we keep a list of sub allocation in offset
498 * order (first entry has offset == 0, last entry has the highest
499 * offset).
500 *
501 * When allocating new object we first check if there is room at
502 * the end total_size - (last_object_offset + last_object_size) >=
503 * alloc_size. If so we allocate new object there.
504 *
505 * When there is not enough room at the end, we start waiting for
506 * each sub object until we reach object_offset+object_size >=
507 * alloc_size, this object then become the sub object we return.
508 *
509 * Alignment can't be bigger than page size.
510 *
511 * Hole are not considered for allocation to keep things simple.
512 * Assumption is that there won't be hole (all object on same
513 * alignment).
514 */
515 struct radeon_sa_manager {
516 wait_queue_head_t wq;
517 struct radeon_bo *bo;
518 struct list_head *hole;
519 struct list_head flist[RADEON_NUM_RINGS];
520 struct list_head olist;
521 unsigned size;
522 uint64_t gpu_addr;
523 void *cpu_ptr;
524 uint32_t domain;
525 uint32_t align;
526 };
527
528 struct radeon_sa_bo;
529
530 /* sub-allocation buffer */
531 struct radeon_sa_bo {
532 struct list_head olist;
533 struct list_head flist;
534 struct radeon_sa_manager *manager;
535 unsigned soffset;
536 unsigned eoffset;
537 struct radeon_fence *fence;
538 };
539
540 /*
541 * GEM objects.
542 */
543 struct radeon_gem {
544 struct mutex mutex;
545 struct list_head objects;
546 };
547
548 int radeon_gem_init(struct radeon_device *rdev);
549 void radeon_gem_fini(struct radeon_device *rdev);
550 int radeon_gem_object_create(struct radeon_device *rdev, int size,
551 int alignment, int initial_domain,
552 u32 flags, bool discardable, bool kernel,
553 struct drm_gem_object **obj);
554
555 int radeon_mode_dumb_create(struct drm_file *file_priv,
556 struct drm_device *dev,
557 struct drm_mode_create_dumb *args);
558 int radeon_mode_dumb_mmap(struct drm_file *filp,
559 struct drm_device *dev,
560 uint32_t handle, uint64_t *offset_p);
561
562 /*
563 * Semaphores.
564 */
565 struct radeon_semaphore {
566 struct radeon_sa_bo *sa_bo;
567 signed waiters;
568 uint64_t gpu_addr;
569 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
570 };
571
572 int radeon_semaphore_create(struct radeon_device *rdev,
573 struct radeon_semaphore **semaphore);
574 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
575 struct radeon_semaphore *semaphore);
576 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
577 struct radeon_semaphore *semaphore);
578 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
579 struct radeon_fence *fence);
580 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
581 struct radeon_semaphore *semaphore,
582 int waiting_ring);
583 void radeon_semaphore_free(struct radeon_device *rdev,
584 struct radeon_semaphore **semaphore,
585 struct radeon_fence *fence);
586
587 /*
588 * GART structures, functions & helpers
589 */
590 struct radeon_mc;
591
592 #define RADEON_GPU_PAGE_SIZE 4096
593 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
594 #define RADEON_GPU_PAGE_SHIFT 12
595 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
596
597 #define RADEON_GART_PAGE_DUMMY 0
598 #define RADEON_GART_PAGE_VALID (1 << 0)
599 #define RADEON_GART_PAGE_READ (1 << 1)
600 #define RADEON_GART_PAGE_WRITE (1 << 2)
601 #define RADEON_GART_PAGE_SNOOP (1 << 3)
602
603 struct radeon_gart {
604 dma_addr_t table_addr;
605 struct radeon_bo *robj;
606 void *ptr;
607 unsigned num_gpu_pages;
608 unsigned num_cpu_pages;
609 unsigned table_size;
610 struct page **pages;
611 dma_addr_t *pages_addr;
612 bool ready;
613 };
614
615 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
616 void radeon_gart_table_ram_free(struct radeon_device *rdev);
617 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
618 void radeon_gart_table_vram_free(struct radeon_device *rdev);
619 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
620 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
621 int radeon_gart_init(struct radeon_device *rdev);
622 void radeon_gart_fini(struct radeon_device *rdev);
623 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
624 int pages);
625 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
626 int pages, struct page **pagelist,
627 dma_addr_t *dma_addr, uint32_t flags);
628
629
630 /*
631 * GPU MC structures, functions & helpers
632 */
633 struct radeon_mc {
634 resource_size_t aper_size;
635 resource_size_t aper_base;
636 resource_size_t agp_base;
637 /* for some chips with <= 32MB we need to lie
638 * about vram size near mc fb location */
639 u64 mc_vram_size;
640 u64 visible_vram_size;
641 u64 gtt_size;
642 u64 gtt_start;
643 u64 gtt_end;
644 u64 vram_start;
645 u64 vram_end;
646 unsigned vram_width;
647 u64 real_vram_size;
648 int vram_mtrr;
649 bool vram_is_ddr;
650 bool igp_sideport_enabled;
651 u64 gtt_base_align;
652 u64 mc_mask;
653 };
654
655 bool radeon_combios_sideport_present(struct radeon_device *rdev);
656 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
657
658 /*
659 * GPU scratch registers structures, functions & helpers
660 */
661 struct radeon_scratch {
662 unsigned num_reg;
663 uint32_t reg_base;
664 bool free[32];
665 uint32_t reg[32];
666 };
667
668 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
669 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
670
671 /*
672 * GPU doorbell structures, functions & helpers
673 */
674 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
675
676 struct radeon_doorbell {
677 /* doorbell mmio */
678 resource_size_t base;
679 resource_size_t size;
680 u32 __iomem *ptr;
681 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
682 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
683 };
684
685 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
686 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
687
688 /*
689 * IRQS.
690 */
691
692 struct radeon_flip_work {
693 struct work_struct flip_work;
694 struct work_struct unpin_work;
695 struct radeon_device *rdev;
696 int crtc_id;
697 uint64_t base;
698 struct drm_pending_vblank_event *event;
699 struct radeon_bo *old_rbo;
700 struct radeon_fence *fence;
701 };
702
703 struct r500_irq_stat_regs {
704 u32 disp_int;
705 u32 hdmi0_status;
706 };
707
708 struct r600_irq_stat_regs {
709 u32 disp_int;
710 u32 disp_int_cont;
711 u32 disp_int_cont2;
712 u32 d1grph_int;
713 u32 d2grph_int;
714 u32 hdmi0_status;
715 u32 hdmi1_status;
716 };
717
718 struct evergreen_irq_stat_regs {
719 u32 disp_int;
720 u32 disp_int_cont;
721 u32 disp_int_cont2;
722 u32 disp_int_cont3;
723 u32 disp_int_cont4;
724 u32 disp_int_cont5;
725 u32 d1grph_int;
726 u32 d2grph_int;
727 u32 d3grph_int;
728 u32 d4grph_int;
729 u32 d5grph_int;
730 u32 d6grph_int;
731 u32 afmt_status1;
732 u32 afmt_status2;
733 u32 afmt_status3;
734 u32 afmt_status4;
735 u32 afmt_status5;
736 u32 afmt_status6;
737 };
738
739 struct cik_irq_stat_regs {
740 u32 disp_int;
741 u32 disp_int_cont;
742 u32 disp_int_cont2;
743 u32 disp_int_cont3;
744 u32 disp_int_cont4;
745 u32 disp_int_cont5;
746 u32 disp_int_cont6;
747 u32 d1grph_int;
748 u32 d2grph_int;
749 u32 d3grph_int;
750 u32 d4grph_int;
751 u32 d5grph_int;
752 u32 d6grph_int;
753 };
754
755 union radeon_irq_stat_regs {
756 struct r500_irq_stat_regs r500;
757 struct r600_irq_stat_regs r600;
758 struct evergreen_irq_stat_regs evergreen;
759 struct cik_irq_stat_regs cik;
760 };
761
762 struct radeon_irq {
763 bool installed;
764 spinlock_t lock;
765 atomic_t ring_int[RADEON_NUM_RINGS];
766 bool crtc_vblank_int[RADEON_MAX_CRTCS];
767 atomic_t pflip[RADEON_MAX_CRTCS];
768 wait_queue_head_t vblank_queue;
769 bool hpd[RADEON_MAX_HPD_PINS];
770 bool afmt[RADEON_MAX_AFMT_BLOCKS];
771 union radeon_irq_stat_regs stat_regs;
772 bool dpm_thermal;
773 };
774
775 int radeon_irq_kms_init(struct radeon_device *rdev);
776 void radeon_irq_kms_fini(struct radeon_device *rdev);
777 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
778 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
779 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
780 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
781 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
782 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
783 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
784 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
785
786 /*
787 * CP & rings.
788 */
789
790 struct radeon_ib {
791 struct radeon_sa_bo *sa_bo;
792 uint32_t length_dw;
793 uint64_t gpu_addr;
794 uint32_t *ptr;
795 int ring;
796 struct radeon_fence *fence;
797 struct radeon_vm *vm;
798 bool is_const_ib;
799 struct radeon_semaphore *semaphore;
800 };
801
802 struct radeon_ring {
803 struct radeon_bo *ring_obj;
804 volatile uint32_t *ring;
805 unsigned rptr_offs;
806 unsigned rptr_save_reg;
807 u64 next_rptr_gpu_addr;
808 volatile u32 *next_rptr_cpu_addr;
809 unsigned wptr;
810 unsigned wptr_old;
811 unsigned ring_size;
812 unsigned ring_free_dw;
813 int count_dw;
814 atomic_t last_rptr;
815 atomic64_t last_activity;
816 uint64_t gpu_addr;
817 uint32_t align_mask;
818 uint32_t ptr_mask;
819 bool ready;
820 u32 nop;
821 u32 idx;
822 u64 last_semaphore_signal_addr;
823 u64 last_semaphore_wait_addr;
824 /* for CIK queues */
825 u32 me;
826 u32 pipe;
827 u32 queue;
828 struct radeon_bo *mqd_obj;
829 u32 doorbell_index;
830 unsigned wptr_offs;
831 };
832
833 struct radeon_mec {
834 struct radeon_bo *hpd_eop_obj;
835 u64 hpd_eop_gpu_addr;
836 u32 num_pipe;
837 u32 num_mec;
838 u32 num_queue;
839 };
840
841 /*
842 * VM
843 */
844
845 /* maximum number of VMIDs */
846 #define RADEON_NUM_VM 16
847
848 /* number of entries in page table */
849 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
850
851 /* PTBs (Page Table Blocks) need to be aligned to 32K */
852 #define RADEON_VM_PTB_ALIGN_SIZE 32768
853 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
854 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
855
856 #define R600_PTE_VALID (1 << 0)
857 #define R600_PTE_SYSTEM (1 << 1)
858 #define R600_PTE_SNOOPED (1 << 2)
859 #define R600_PTE_READABLE (1 << 5)
860 #define R600_PTE_WRITEABLE (1 << 6)
861
862 /* PTE (Page Table Entry) fragment field for different page sizes */
863 #define R600_PTE_FRAG_4KB (0 << 7)
864 #define R600_PTE_FRAG_64KB (4 << 7)
865 #define R600_PTE_FRAG_256KB (6 << 7)
866
867 /* flags used for GART page table entries on R600+ */
868 #define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
869 | R600_PTE_READABLE | R600_PTE_WRITEABLE)
870
871 struct radeon_vm_pt {
872 struct radeon_bo *bo;
873 uint64_t addr;
874 };
875
876 struct radeon_vm {
877 struct list_head va;
878 unsigned id;
879
880 /* BOs freed, but not yet updated in the PT */
881 struct list_head freed;
882
883 /* contains the page directory */
884 struct radeon_bo *page_directory;
885 uint64_t pd_gpu_addr;
886 unsigned max_pde_used;
887
888 /* array of page tables, one for each page directory entry */
889 struct radeon_vm_pt *page_tables;
890
891 struct radeon_bo_va *ib_bo_va;
892
893 struct mutex mutex;
894 /* last fence for cs using this vm */
895 struct radeon_fence *fence;
896 /* last flush or NULL if we still need to flush */
897 struct radeon_fence *last_flush;
898 /* last use of vmid */
899 struct radeon_fence *last_id_use;
900 };
901
902 struct radeon_vm_manager {
903 struct radeon_fence *active[RADEON_NUM_VM];
904 uint32_t max_pfn;
905 /* number of VMIDs */
906 unsigned nvm;
907 /* vram base address for page table entry */
908 u64 vram_base_offset;
909 /* is vm enabled? */
910 bool enabled;
911 };
912
913 /*
914 * file private structure
915 */
916 struct radeon_fpriv {
917 struct radeon_vm vm;
918 };
919
920 /*
921 * R6xx+ IH ring
922 */
923 struct r600_ih {
924 struct radeon_bo *ring_obj;
925 volatile uint32_t *ring;
926 unsigned rptr;
927 unsigned ring_size;
928 uint64_t gpu_addr;
929 uint32_t ptr_mask;
930 atomic_t lock;
931 bool enabled;
932 };
933
934 /*
935 * RLC stuff
936 */
937 #include "clearstate_defs.h"
938
939 struct radeon_rlc {
940 /* for power gating */
941 struct radeon_bo *save_restore_obj;
942 uint64_t save_restore_gpu_addr;
943 volatile uint32_t *sr_ptr;
944 const u32 *reg_list;
945 u32 reg_list_size;
946 /* for clear state */
947 struct radeon_bo *clear_state_obj;
948 uint64_t clear_state_gpu_addr;
949 volatile uint32_t *cs_ptr;
950 const struct cs_section_def *cs_data;
951 u32 clear_state_size;
952 /* for cp tables */
953 struct radeon_bo *cp_table_obj;
954 uint64_t cp_table_gpu_addr;
955 volatile uint32_t *cp_table_ptr;
956 u32 cp_table_size;
957 };
958
959 int radeon_ib_get(struct radeon_device *rdev, int ring,
960 struct radeon_ib *ib, struct radeon_vm *vm,
961 unsigned size);
962 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
963 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
964 struct radeon_ib *const_ib);
965 int radeon_ib_pool_init(struct radeon_device *rdev);
966 void radeon_ib_pool_fini(struct radeon_device *rdev);
967 int radeon_ib_ring_tests(struct radeon_device *rdev);
968 /* Ring access between begin & end cannot sleep */
969 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
970 struct radeon_ring *ring);
971 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
972 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
973 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
974 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
975 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
976 void radeon_ring_undo(struct radeon_ring *ring);
977 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
978 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
979 void radeon_ring_lockup_update(struct radeon_device *rdev,
980 struct radeon_ring *ring);
981 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
982 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
983 uint32_t **data);
984 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
985 unsigned size, uint32_t *data);
986 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
987 unsigned rptr_offs, u32 nop);
988 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
989
990
991 /* r600 async dma */
992 void r600_dma_stop(struct radeon_device *rdev);
993 int r600_dma_resume(struct radeon_device *rdev);
994 void r600_dma_fini(struct radeon_device *rdev);
995
996 void cayman_dma_stop(struct radeon_device *rdev);
997 int cayman_dma_resume(struct radeon_device *rdev);
998 void cayman_dma_fini(struct radeon_device *rdev);
999
1000 /*
1001 * CS.
1002 */
1003 struct radeon_cs_reloc {
1004 struct drm_gem_object *gobj;
1005 struct radeon_bo *robj;
1006 struct ttm_validate_buffer tv;
1007 uint64_t gpu_offset;
1008 unsigned prefered_domains;
1009 unsigned allowed_domains;
1010 uint32_t tiling_flags;
1011 uint32_t handle;
1012 };
1013
1014 struct radeon_cs_chunk {
1015 uint32_t chunk_id;
1016 uint32_t length_dw;
1017 uint32_t *kdata;
1018 void __user *user_ptr;
1019 };
1020
1021 struct radeon_cs_parser {
1022 struct device *dev;
1023 struct radeon_device *rdev;
1024 struct drm_file *filp;
1025 /* chunks */
1026 unsigned nchunks;
1027 struct radeon_cs_chunk *chunks;
1028 uint64_t *chunks_array;
1029 /* IB */
1030 unsigned idx;
1031 /* relocations */
1032 unsigned nrelocs;
1033 struct radeon_cs_reloc *relocs;
1034 struct radeon_cs_reloc **relocs_ptr;
1035 struct radeon_cs_reloc *vm_bos;
1036 struct list_head validated;
1037 unsigned dma_reloc_idx;
1038 /* indices of various chunks */
1039 int chunk_ib_idx;
1040 int chunk_relocs_idx;
1041 int chunk_flags_idx;
1042 int chunk_const_ib_idx;
1043 struct radeon_ib ib;
1044 struct radeon_ib const_ib;
1045 void *track;
1046 unsigned family;
1047 int parser_error;
1048 u32 cs_flags;
1049 u32 ring;
1050 s32 priority;
1051 struct ww_acquire_ctx ticket;
1052 };
1053
1054 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1055 {
1056 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1057
1058 if (ibc->kdata)
1059 return ibc->kdata[idx];
1060 return p->ib.ptr[idx];
1061 }
1062
1063
1064 struct radeon_cs_packet {
1065 unsigned idx;
1066 unsigned type;
1067 unsigned reg;
1068 unsigned opcode;
1069 int count;
1070 unsigned one_reg_wr;
1071 };
1072
1073 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1074 struct radeon_cs_packet *pkt,
1075 unsigned idx, unsigned reg);
1076 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1077 struct radeon_cs_packet *pkt);
1078
1079
1080 /*
1081 * AGP
1082 */
1083 int radeon_agp_init(struct radeon_device *rdev);
1084 void radeon_agp_resume(struct radeon_device *rdev);
1085 void radeon_agp_suspend(struct radeon_device *rdev);
1086 void radeon_agp_fini(struct radeon_device *rdev);
1087
1088
1089 /*
1090 * Writeback
1091 */
1092 struct radeon_wb {
1093 struct radeon_bo *wb_obj;
1094 volatile uint32_t *wb;
1095 uint64_t gpu_addr;
1096 bool enabled;
1097 bool use_event;
1098 };
1099
1100 #define RADEON_WB_SCRATCH_OFFSET 0
1101 #define RADEON_WB_RING0_NEXT_RPTR 256
1102 #define RADEON_WB_CP_RPTR_OFFSET 1024
1103 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1104 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1105 #define R600_WB_DMA_RPTR_OFFSET 1792
1106 #define R600_WB_IH_WPTR_OFFSET 2048
1107 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1108 #define R600_WB_EVENT_OFFSET 3072
1109 #define CIK_WB_CP1_WPTR_OFFSET 3328
1110 #define CIK_WB_CP2_WPTR_OFFSET 3584
1111
1112 /**
1113 * struct radeon_pm - power management datas
1114 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1115 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1116 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1117 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1118 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1119 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1120 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1121 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1122 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1123 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1124 * @needed_bandwidth: current bandwidth needs
1125 *
1126 * It keeps track of various data needed to take powermanagement decision.
1127 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1128 * Equation between gpu/memory clock and available bandwidth is hw dependent
1129 * (type of memory, bus size, efficiency, ...)
1130 */
1131
1132 enum radeon_pm_method {
1133 PM_METHOD_PROFILE,
1134 PM_METHOD_DYNPM,
1135 PM_METHOD_DPM,
1136 };
1137
1138 enum radeon_dynpm_state {
1139 DYNPM_STATE_DISABLED,
1140 DYNPM_STATE_MINIMUM,
1141 DYNPM_STATE_PAUSED,
1142 DYNPM_STATE_ACTIVE,
1143 DYNPM_STATE_SUSPENDED,
1144 };
1145 enum radeon_dynpm_action {
1146 DYNPM_ACTION_NONE,
1147 DYNPM_ACTION_MINIMUM,
1148 DYNPM_ACTION_DOWNCLOCK,
1149 DYNPM_ACTION_UPCLOCK,
1150 DYNPM_ACTION_DEFAULT
1151 };
1152
1153 enum radeon_voltage_type {
1154 VOLTAGE_NONE = 0,
1155 VOLTAGE_GPIO,
1156 VOLTAGE_VDDC,
1157 VOLTAGE_SW
1158 };
1159
1160 enum radeon_pm_state_type {
1161 /* not used for dpm */
1162 POWER_STATE_TYPE_DEFAULT,
1163 POWER_STATE_TYPE_POWERSAVE,
1164 /* user selectable states */
1165 POWER_STATE_TYPE_BATTERY,
1166 POWER_STATE_TYPE_BALANCED,
1167 POWER_STATE_TYPE_PERFORMANCE,
1168 /* internal states */
1169 POWER_STATE_TYPE_INTERNAL_UVD,
1170 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1171 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1172 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1173 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1174 POWER_STATE_TYPE_INTERNAL_BOOT,
1175 POWER_STATE_TYPE_INTERNAL_THERMAL,
1176 POWER_STATE_TYPE_INTERNAL_ACPI,
1177 POWER_STATE_TYPE_INTERNAL_ULV,
1178 POWER_STATE_TYPE_INTERNAL_3DPERF,
1179 };
1180
1181 enum radeon_pm_profile_type {
1182 PM_PROFILE_DEFAULT,
1183 PM_PROFILE_AUTO,
1184 PM_PROFILE_LOW,
1185 PM_PROFILE_MID,
1186 PM_PROFILE_HIGH,
1187 };
1188
1189 #define PM_PROFILE_DEFAULT_IDX 0
1190 #define PM_PROFILE_LOW_SH_IDX 1
1191 #define PM_PROFILE_MID_SH_IDX 2
1192 #define PM_PROFILE_HIGH_SH_IDX 3
1193 #define PM_PROFILE_LOW_MH_IDX 4
1194 #define PM_PROFILE_MID_MH_IDX 5
1195 #define PM_PROFILE_HIGH_MH_IDX 6
1196 #define PM_PROFILE_MAX 7
1197
1198 struct radeon_pm_profile {
1199 int dpms_off_ps_idx;
1200 int dpms_on_ps_idx;
1201 int dpms_off_cm_idx;
1202 int dpms_on_cm_idx;
1203 };
1204
1205 enum radeon_int_thermal_type {
1206 THERMAL_TYPE_NONE,
1207 THERMAL_TYPE_EXTERNAL,
1208 THERMAL_TYPE_EXTERNAL_GPIO,
1209 THERMAL_TYPE_RV6XX,
1210 THERMAL_TYPE_RV770,
1211 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1212 THERMAL_TYPE_EVERGREEN,
1213 THERMAL_TYPE_SUMO,
1214 THERMAL_TYPE_NI,
1215 THERMAL_TYPE_SI,
1216 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1217 THERMAL_TYPE_CI,
1218 THERMAL_TYPE_KV,
1219 };
1220
1221 struct radeon_voltage {
1222 enum radeon_voltage_type type;
1223 /* gpio voltage */
1224 struct radeon_gpio_rec gpio;
1225 u32 delay; /* delay in usec from voltage drop to sclk change */
1226 bool active_high; /* voltage drop is active when bit is high */
1227 /* VDDC voltage */
1228 u8 vddc_id; /* index into vddc voltage table */
1229 u8 vddci_id; /* index into vddci voltage table */
1230 bool vddci_enabled;
1231 /* r6xx+ sw */
1232 u16 voltage;
1233 /* evergreen+ vddci */
1234 u16 vddci;
1235 };
1236
1237 /* clock mode flags */
1238 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1239
1240 struct radeon_pm_clock_info {
1241 /* memory clock */
1242 u32 mclk;
1243 /* engine clock */
1244 u32 sclk;
1245 /* voltage info */
1246 struct radeon_voltage voltage;
1247 /* standardized clock flags */
1248 u32 flags;
1249 };
1250
1251 /* state flags */
1252 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1253
1254 struct radeon_power_state {
1255 enum radeon_pm_state_type type;
1256 struct radeon_pm_clock_info *clock_info;
1257 /* number of valid clock modes in this power state */
1258 int num_clock_modes;
1259 struct radeon_pm_clock_info *default_clock_mode;
1260 /* standardized state flags */
1261 u32 flags;
1262 u32 misc; /* vbios specific flags */
1263 u32 misc2; /* vbios specific flags */
1264 int pcie_lanes; /* pcie lanes */
1265 };
1266
1267 /*
1268 * Some modes are overclocked by very low value, accept them
1269 */
1270 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1271
1272 enum radeon_dpm_auto_throttle_src {
1273 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1274 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1275 };
1276
1277 enum radeon_dpm_event_src {
1278 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1279 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1280 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1281 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1282 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1283 };
1284
1285 #define RADEON_MAX_VCE_LEVELS 6
1286
1287 enum radeon_vce_level {
1288 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1289 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1290 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1291 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1292 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1293 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1294 };
1295
1296 struct radeon_ps {
1297 u32 caps; /* vbios flags */
1298 u32 class; /* vbios flags */
1299 u32 class2; /* vbios flags */
1300 /* UVD clocks */
1301 u32 vclk;
1302 u32 dclk;
1303 /* VCE clocks */
1304 u32 evclk;
1305 u32 ecclk;
1306 bool vce_active;
1307 enum radeon_vce_level vce_level;
1308 /* asic priv */
1309 void *ps_priv;
1310 };
1311
1312 struct radeon_dpm_thermal {
1313 /* thermal interrupt work */
1314 struct work_struct work;
1315 /* low temperature threshold */
1316 int min_temp;
1317 /* high temperature threshold */
1318 int max_temp;
1319 /* was interrupt low to high or high to low */
1320 bool high_to_low;
1321 };
1322
1323 enum radeon_clk_action
1324 {
1325 RADEON_SCLK_UP = 1,
1326 RADEON_SCLK_DOWN
1327 };
1328
1329 struct radeon_blacklist_clocks
1330 {
1331 u32 sclk;
1332 u32 mclk;
1333 enum radeon_clk_action action;
1334 };
1335
1336 struct radeon_clock_and_voltage_limits {
1337 u32 sclk;
1338 u32 mclk;
1339 u16 vddc;
1340 u16 vddci;
1341 };
1342
1343 struct radeon_clock_array {
1344 u32 count;
1345 u32 *values;
1346 };
1347
1348 struct radeon_clock_voltage_dependency_entry {
1349 u32 clk;
1350 u16 v;
1351 };
1352
1353 struct radeon_clock_voltage_dependency_table {
1354 u32 count;
1355 struct radeon_clock_voltage_dependency_entry *entries;
1356 };
1357
1358 union radeon_cac_leakage_entry {
1359 struct {
1360 u16 vddc;
1361 u32 leakage;
1362 };
1363 struct {
1364 u16 vddc1;
1365 u16 vddc2;
1366 u16 vddc3;
1367 };
1368 };
1369
1370 struct radeon_cac_leakage_table {
1371 u32 count;
1372 union radeon_cac_leakage_entry *entries;
1373 };
1374
1375 struct radeon_phase_shedding_limits_entry {
1376 u16 voltage;
1377 u32 sclk;
1378 u32 mclk;
1379 };
1380
1381 struct radeon_phase_shedding_limits_table {
1382 u32 count;
1383 struct radeon_phase_shedding_limits_entry *entries;
1384 };
1385
1386 struct radeon_uvd_clock_voltage_dependency_entry {
1387 u32 vclk;
1388 u32 dclk;
1389 u16 v;
1390 };
1391
1392 struct radeon_uvd_clock_voltage_dependency_table {
1393 u8 count;
1394 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1395 };
1396
1397 struct radeon_vce_clock_voltage_dependency_entry {
1398 u32 ecclk;
1399 u32 evclk;
1400 u16 v;
1401 };
1402
1403 struct radeon_vce_clock_voltage_dependency_table {
1404 u8 count;
1405 struct radeon_vce_clock_voltage_dependency_entry *entries;
1406 };
1407
1408 struct radeon_ppm_table {
1409 u8 ppm_design;
1410 u16 cpu_core_number;
1411 u32 platform_tdp;
1412 u32 small_ac_platform_tdp;
1413 u32 platform_tdc;
1414 u32 small_ac_platform_tdc;
1415 u32 apu_tdp;
1416 u32 dgpu_tdp;
1417 u32 dgpu_ulv_power;
1418 u32 tj_max;
1419 };
1420
1421 struct radeon_cac_tdp_table {
1422 u16 tdp;
1423 u16 configurable_tdp;
1424 u16 tdc;
1425 u16 battery_power_limit;
1426 u16 small_power_limit;
1427 u16 low_cac_leakage;
1428 u16 high_cac_leakage;
1429 u16 maximum_power_delivery_limit;
1430 };
1431
1432 struct radeon_dpm_dynamic_state {
1433 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1434 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1435 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1436 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1437 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1438 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1439 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1440 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1441 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1442 struct radeon_clock_array valid_sclk_values;
1443 struct radeon_clock_array valid_mclk_values;
1444 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1445 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1446 u32 mclk_sclk_ratio;
1447 u32 sclk_mclk_delta;
1448 u16 vddc_vddci_delta;
1449 u16 min_vddc_for_pcie_gen2;
1450 struct radeon_cac_leakage_table cac_leakage_table;
1451 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1452 struct radeon_ppm_table *ppm_table;
1453 struct radeon_cac_tdp_table *cac_tdp_table;
1454 };
1455
1456 struct radeon_dpm_fan {
1457 u16 t_min;
1458 u16 t_med;
1459 u16 t_high;
1460 u16 pwm_min;
1461 u16 pwm_med;
1462 u16 pwm_high;
1463 u8 t_hyst;
1464 u32 cycle_delay;
1465 u16 t_max;
1466 bool ucode_fan_control;
1467 };
1468
1469 enum radeon_pcie_gen {
1470 RADEON_PCIE_GEN1 = 0,
1471 RADEON_PCIE_GEN2 = 1,
1472 RADEON_PCIE_GEN3 = 2,
1473 RADEON_PCIE_GEN_INVALID = 0xffff
1474 };
1475
1476 enum radeon_dpm_forced_level {
1477 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1478 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1479 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1480 };
1481
1482 struct radeon_vce_state {
1483 /* vce clocks */
1484 u32 evclk;
1485 u32 ecclk;
1486 /* gpu clocks */
1487 u32 sclk;
1488 u32 mclk;
1489 u8 clk_idx;
1490 u8 pstate;
1491 };
1492
1493 struct radeon_dpm {
1494 struct radeon_ps *ps;
1495 /* number of valid power states */
1496 int num_ps;
1497 /* current power state that is active */
1498 struct radeon_ps *current_ps;
1499 /* requested power state */
1500 struct radeon_ps *requested_ps;
1501 /* boot up power state */
1502 struct radeon_ps *boot_ps;
1503 /* default uvd power state */
1504 struct radeon_ps *uvd_ps;
1505 /* vce requirements */
1506 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1507 enum radeon_vce_level vce_level;
1508 enum radeon_pm_state_type state;
1509 enum radeon_pm_state_type user_state;
1510 u32 platform_caps;
1511 u32 voltage_response_time;
1512 u32 backbias_response_time;
1513 void *priv;
1514 u32 new_active_crtcs;
1515 int new_active_crtc_count;
1516 u32 current_active_crtcs;
1517 int current_active_crtc_count;
1518 struct radeon_dpm_dynamic_state dyn_state;
1519 struct radeon_dpm_fan fan;
1520 u32 tdp_limit;
1521 u32 near_tdp_limit;
1522 u32 near_tdp_limit_adjusted;
1523 u32 sq_ramping_threshold;
1524 u32 cac_leakage;
1525 u16 tdp_od_limit;
1526 u32 tdp_adjustment;
1527 u16 load_line_slope;
1528 bool power_control;
1529 bool ac_power;
1530 /* special states active */
1531 bool thermal_active;
1532 bool uvd_active;
1533 bool vce_active;
1534 /* thermal handling */
1535 struct radeon_dpm_thermal thermal;
1536 /* forced levels */
1537 enum radeon_dpm_forced_level forced_level;
1538 /* track UVD streams */
1539 unsigned sd;
1540 unsigned hd;
1541 };
1542
1543 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1544 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1545
1546 struct radeon_pm {
1547 struct mutex mutex;
1548 /* write locked while reprogramming mclk */
1549 struct rw_semaphore mclk_lock;
1550 u32 active_crtcs;
1551 int active_crtc_count;
1552 int req_vblank;
1553 bool vblank_sync;
1554 fixed20_12 max_bandwidth;
1555 fixed20_12 igp_sideport_mclk;
1556 fixed20_12 igp_system_mclk;
1557 fixed20_12 igp_ht_link_clk;
1558 fixed20_12 igp_ht_link_width;
1559 fixed20_12 k8_bandwidth;
1560 fixed20_12 sideport_bandwidth;
1561 fixed20_12 ht_bandwidth;
1562 fixed20_12 core_bandwidth;
1563 fixed20_12 sclk;
1564 fixed20_12 mclk;
1565 fixed20_12 needed_bandwidth;
1566 struct radeon_power_state *power_state;
1567 /* number of valid power states */
1568 int num_power_states;
1569 int current_power_state_index;
1570 int current_clock_mode_index;
1571 int requested_power_state_index;
1572 int requested_clock_mode_index;
1573 int default_power_state_index;
1574 u32 current_sclk;
1575 u32 current_mclk;
1576 u16 current_vddc;
1577 u16 current_vddci;
1578 u32 default_sclk;
1579 u32 default_mclk;
1580 u16 default_vddc;
1581 u16 default_vddci;
1582 struct radeon_i2c_chan *i2c_bus;
1583 /* selected pm method */
1584 enum radeon_pm_method pm_method;
1585 /* dynpm power management */
1586 struct delayed_work dynpm_idle_work;
1587 enum radeon_dynpm_state dynpm_state;
1588 enum radeon_dynpm_action dynpm_planned_action;
1589 unsigned long dynpm_action_timeout;
1590 bool dynpm_can_upclock;
1591 bool dynpm_can_downclock;
1592 /* profile-based power management */
1593 enum radeon_pm_profile_type profile;
1594 int profile_index;
1595 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1596 /* internal thermal controller on rv6xx+ */
1597 enum radeon_int_thermal_type int_thermal_type;
1598 struct device *int_hwmon_dev;
1599 /* dpm */
1600 bool dpm_enabled;
1601 struct radeon_dpm dpm;
1602 };
1603
1604 int radeon_pm_get_type_index(struct radeon_device *rdev,
1605 enum radeon_pm_state_type ps_type,
1606 int instance);
1607 /*
1608 * UVD
1609 */
1610 #define RADEON_MAX_UVD_HANDLES 10
1611 #define RADEON_UVD_STACK_SIZE (1024*1024)
1612 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1613
1614 struct radeon_uvd {
1615 struct radeon_bo *vcpu_bo;
1616 void *cpu_addr;
1617 uint64_t gpu_addr;
1618 void *saved_bo;
1619 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1620 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1621 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1622 struct delayed_work idle_work;
1623 };
1624
1625 int radeon_uvd_init(struct radeon_device *rdev);
1626 void radeon_uvd_fini(struct radeon_device *rdev);
1627 int radeon_uvd_suspend(struct radeon_device *rdev);
1628 int radeon_uvd_resume(struct radeon_device *rdev);
1629 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1630 uint32_t handle, struct radeon_fence **fence);
1631 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1632 uint32_t handle, struct radeon_fence **fence);
1633 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1634 void radeon_uvd_free_handles(struct radeon_device *rdev,
1635 struct drm_file *filp);
1636 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1637 void radeon_uvd_note_usage(struct radeon_device *rdev);
1638 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1639 unsigned vclk, unsigned dclk,
1640 unsigned vco_min, unsigned vco_max,
1641 unsigned fb_factor, unsigned fb_mask,
1642 unsigned pd_min, unsigned pd_max,
1643 unsigned pd_even,
1644 unsigned *optimal_fb_div,
1645 unsigned *optimal_vclk_div,
1646 unsigned *optimal_dclk_div);
1647 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1648 unsigned cg_upll_func_cntl);
1649
1650 /*
1651 * VCE
1652 */
1653 #define RADEON_MAX_VCE_HANDLES 16
1654 #define RADEON_VCE_STACK_SIZE (1024*1024)
1655 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1656
1657 struct radeon_vce {
1658 struct radeon_bo *vcpu_bo;
1659 uint64_t gpu_addr;
1660 unsigned fw_version;
1661 unsigned fb_version;
1662 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1663 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1664 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1665 struct delayed_work idle_work;
1666 };
1667
1668 int radeon_vce_init(struct radeon_device *rdev);
1669 void radeon_vce_fini(struct radeon_device *rdev);
1670 int radeon_vce_suspend(struct radeon_device *rdev);
1671 int radeon_vce_resume(struct radeon_device *rdev);
1672 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1673 uint32_t handle, struct radeon_fence **fence);
1674 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1675 uint32_t handle, struct radeon_fence **fence);
1676 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1677 void radeon_vce_note_usage(struct radeon_device *rdev);
1678 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1679 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1680 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1681 struct radeon_ring *ring,
1682 struct radeon_semaphore *semaphore,
1683 bool emit_wait);
1684 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1685 void radeon_vce_fence_emit(struct radeon_device *rdev,
1686 struct radeon_fence *fence);
1687 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1688 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1689
1690 struct r600_audio_pin {
1691 int channels;
1692 int rate;
1693 int bits_per_sample;
1694 u8 status_bits;
1695 u8 category_code;
1696 u32 offset;
1697 bool connected;
1698 u32 id;
1699 };
1700
1701 struct r600_audio {
1702 bool enabled;
1703 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1704 int num_pins;
1705 };
1706
1707 /*
1708 * Benchmarking
1709 */
1710 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1711
1712
1713 /*
1714 * Testing
1715 */
1716 void radeon_test_moves(struct radeon_device *rdev);
1717 void radeon_test_ring_sync(struct radeon_device *rdev,
1718 struct radeon_ring *cpA,
1719 struct radeon_ring *cpB);
1720 void radeon_test_syncing(struct radeon_device *rdev);
1721
1722
1723 /*
1724 * Debugfs
1725 */
1726 struct radeon_debugfs {
1727 struct drm_info_list *files;
1728 unsigned num_files;
1729 };
1730
1731 int radeon_debugfs_add_files(struct radeon_device *rdev,
1732 struct drm_info_list *files,
1733 unsigned nfiles);
1734 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1735
1736 /*
1737 * ASIC ring specific functions.
1738 */
1739 struct radeon_asic_ring {
1740 /* ring read/write ptr handling */
1741 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1742 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1743 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1744
1745 /* validating and patching of IBs */
1746 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1747 int (*cs_parse)(struct radeon_cs_parser *p);
1748
1749 /* command emmit functions */
1750 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1751 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1752 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1753 struct radeon_semaphore *semaphore, bool emit_wait);
1754 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1755
1756 /* testing functions */
1757 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1758 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1759 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1760
1761 /* deprecated */
1762 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1763 };
1764
1765 /*
1766 * ASIC specific functions.
1767 */
1768 struct radeon_asic {
1769 int (*init)(struct radeon_device *rdev);
1770 void (*fini)(struct radeon_device *rdev);
1771 int (*resume)(struct radeon_device *rdev);
1772 int (*suspend)(struct radeon_device *rdev);
1773 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1774 int (*asic_reset)(struct radeon_device *rdev);
1775 /* ioctl hw specific callback. Some hw might want to perform special
1776 * operation on specific ioctl. For instance on wait idle some hw
1777 * might want to perform and HDP flush through MMIO as it seems that
1778 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1779 * through ring.
1780 */
1781 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1782 /* check if 3D engine is idle */
1783 bool (*gui_idle)(struct radeon_device *rdev);
1784 /* wait for mc_idle */
1785 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1786 /* get the reference clock */
1787 u32 (*get_xclk)(struct radeon_device *rdev);
1788 /* get the gpu clock counter */
1789 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1790 /* gart */
1791 struct {
1792 void (*tlb_flush)(struct radeon_device *rdev);
1793 void (*set_page)(struct radeon_device *rdev, unsigned i,
1794 uint64_t addr, uint32_t flags);
1795 } gart;
1796 struct {
1797 int (*init)(struct radeon_device *rdev);
1798 void (*fini)(struct radeon_device *rdev);
1799 void (*set_page)(struct radeon_device *rdev,
1800 struct radeon_ib *ib,
1801 uint64_t pe,
1802 uint64_t addr, unsigned count,
1803 uint32_t incr, uint32_t flags);
1804 } vm;
1805 /* ring specific callbacks */
1806 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1807 /* irqs */
1808 struct {
1809 int (*set)(struct radeon_device *rdev);
1810 int (*process)(struct radeon_device *rdev);
1811 } irq;
1812 /* displays */
1813 struct {
1814 /* display watermarks */
1815 void (*bandwidth_update)(struct radeon_device *rdev);
1816 /* get frame count */
1817 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1818 /* wait for vblank */
1819 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1820 /* set backlight level */
1821 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1822 /* get backlight level */
1823 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1824 /* audio callbacks */
1825 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1826 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1827 } display;
1828 /* copy functions for bo handling */
1829 struct {
1830 int (*blit)(struct radeon_device *rdev,
1831 uint64_t src_offset,
1832 uint64_t dst_offset,
1833 unsigned num_gpu_pages,
1834 struct radeon_fence **fence);
1835 u32 blit_ring_index;
1836 int (*dma)(struct radeon_device *rdev,
1837 uint64_t src_offset,
1838 uint64_t dst_offset,
1839 unsigned num_gpu_pages,
1840 struct radeon_fence **fence);
1841 u32 dma_ring_index;
1842 /* method used for bo copy */
1843 int (*copy)(struct radeon_device *rdev,
1844 uint64_t src_offset,
1845 uint64_t dst_offset,
1846 unsigned num_gpu_pages,
1847 struct radeon_fence **fence);
1848 /* ring used for bo copies */
1849 u32 copy_ring_index;
1850 } copy;
1851 /* surfaces */
1852 struct {
1853 int (*set_reg)(struct radeon_device *rdev, int reg,
1854 uint32_t tiling_flags, uint32_t pitch,
1855 uint32_t offset, uint32_t obj_size);
1856 void (*clear_reg)(struct radeon_device *rdev, int reg);
1857 } surface;
1858 /* hotplug detect */
1859 struct {
1860 void (*init)(struct radeon_device *rdev);
1861 void (*fini)(struct radeon_device *rdev);
1862 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1863 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1864 } hpd;
1865 /* static power management */
1866 struct {
1867 void (*misc)(struct radeon_device *rdev);
1868 void (*prepare)(struct radeon_device *rdev);
1869 void (*finish)(struct radeon_device *rdev);
1870 void (*init_profile)(struct radeon_device *rdev);
1871 void (*get_dynpm_state)(struct radeon_device *rdev);
1872 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1873 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1874 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1875 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1876 int (*get_pcie_lanes)(struct radeon_device *rdev);
1877 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1878 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1879 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1880 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1881 int (*get_temperature)(struct radeon_device *rdev);
1882 } pm;
1883 /* dynamic power management */
1884 struct {
1885 int (*init)(struct radeon_device *rdev);
1886 void (*setup_asic)(struct radeon_device *rdev);
1887 int (*enable)(struct radeon_device *rdev);
1888 int (*late_enable)(struct radeon_device *rdev);
1889 void (*disable)(struct radeon_device *rdev);
1890 int (*pre_set_power_state)(struct radeon_device *rdev);
1891 int (*set_power_state)(struct radeon_device *rdev);
1892 void (*post_set_power_state)(struct radeon_device *rdev);
1893 void (*display_configuration_changed)(struct radeon_device *rdev);
1894 void (*fini)(struct radeon_device *rdev);
1895 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1896 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1897 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1898 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1899 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1900 bool (*vblank_too_short)(struct radeon_device *rdev);
1901 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1902 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1903 } dpm;
1904 /* pageflipping */
1905 struct {
1906 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1907 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1908 } pflip;
1909 };
1910
1911 /*
1912 * Asic structures
1913 */
1914 struct r100_asic {
1915 const unsigned *reg_safe_bm;
1916 unsigned reg_safe_bm_size;
1917 u32 hdp_cntl;
1918 };
1919
1920 struct r300_asic {
1921 const unsigned *reg_safe_bm;
1922 unsigned reg_safe_bm_size;
1923 u32 resync_scratch;
1924 u32 hdp_cntl;
1925 };
1926
1927 struct r600_asic {
1928 unsigned max_pipes;
1929 unsigned max_tile_pipes;
1930 unsigned max_simds;
1931 unsigned max_backends;
1932 unsigned max_gprs;
1933 unsigned max_threads;
1934 unsigned max_stack_entries;
1935 unsigned max_hw_contexts;
1936 unsigned max_gs_threads;
1937 unsigned sx_max_export_size;
1938 unsigned sx_max_export_pos_size;
1939 unsigned sx_max_export_smx_size;
1940 unsigned sq_num_cf_insts;
1941 unsigned tiling_nbanks;
1942 unsigned tiling_npipes;
1943 unsigned tiling_group_size;
1944 unsigned tile_config;
1945 unsigned backend_map;
1946 unsigned active_simds;
1947 };
1948
1949 struct rv770_asic {
1950 unsigned max_pipes;
1951 unsigned max_tile_pipes;
1952 unsigned max_simds;
1953 unsigned max_backends;
1954 unsigned max_gprs;
1955 unsigned max_threads;
1956 unsigned max_stack_entries;
1957 unsigned max_hw_contexts;
1958 unsigned max_gs_threads;
1959 unsigned sx_max_export_size;
1960 unsigned sx_max_export_pos_size;
1961 unsigned sx_max_export_smx_size;
1962 unsigned sq_num_cf_insts;
1963 unsigned sx_num_of_sets;
1964 unsigned sc_prim_fifo_size;
1965 unsigned sc_hiz_tile_fifo_size;
1966 unsigned sc_earlyz_tile_fifo_fize;
1967 unsigned tiling_nbanks;
1968 unsigned tiling_npipes;
1969 unsigned tiling_group_size;
1970 unsigned tile_config;
1971 unsigned backend_map;
1972 unsigned active_simds;
1973 };
1974
1975 struct evergreen_asic {
1976 unsigned num_ses;
1977 unsigned max_pipes;
1978 unsigned max_tile_pipes;
1979 unsigned max_simds;
1980 unsigned max_backends;
1981 unsigned max_gprs;
1982 unsigned max_threads;
1983 unsigned max_stack_entries;
1984 unsigned max_hw_contexts;
1985 unsigned max_gs_threads;
1986 unsigned sx_max_export_size;
1987 unsigned sx_max_export_pos_size;
1988 unsigned sx_max_export_smx_size;
1989 unsigned sq_num_cf_insts;
1990 unsigned sx_num_of_sets;
1991 unsigned sc_prim_fifo_size;
1992 unsigned sc_hiz_tile_fifo_size;
1993 unsigned sc_earlyz_tile_fifo_size;
1994 unsigned tiling_nbanks;
1995 unsigned tiling_npipes;
1996 unsigned tiling_group_size;
1997 unsigned tile_config;
1998 unsigned backend_map;
1999 unsigned active_simds;
2000 };
2001
2002 struct cayman_asic {
2003 unsigned max_shader_engines;
2004 unsigned max_pipes_per_simd;
2005 unsigned max_tile_pipes;
2006 unsigned max_simds_per_se;
2007 unsigned max_backends_per_se;
2008 unsigned max_texture_channel_caches;
2009 unsigned max_gprs;
2010 unsigned max_threads;
2011 unsigned max_gs_threads;
2012 unsigned max_stack_entries;
2013 unsigned sx_num_of_sets;
2014 unsigned sx_max_export_size;
2015 unsigned sx_max_export_pos_size;
2016 unsigned sx_max_export_smx_size;
2017 unsigned max_hw_contexts;
2018 unsigned sq_num_cf_insts;
2019 unsigned sc_prim_fifo_size;
2020 unsigned sc_hiz_tile_fifo_size;
2021 unsigned sc_earlyz_tile_fifo_size;
2022
2023 unsigned num_shader_engines;
2024 unsigned num_shader_pipes_per_simd;
2025 unsigned num_tile_pipes;
2026 unsigned num_simds_per_se;
2027 unsigned num_backends_per_se;
2028 unsigned backend_disable_mask_per_asic;
2029 unsigned backend_map;
2030 unsigned num_texture_channel_caches;
2031 unsigned mem_max_burst_length_bytes;
2032 unsigned mem_row_size_in_kb;
2033 unsigned shader_engine_tile_size;
2034 unsigned num_gpus;
2035 unsigned multi_gpu_tile_size;
2036
2037 unsigned tile_config;
2038 unsigned active_simds;
2039 };
2040
2041 struct si_asic {
2042 unsigned max_shader_engines;
2043 unsigned max_tile_pipes;
2044 unsigned max_cu_per_sh;
2045 unsigned max_sh_per_se;
2046 unsigned max_backends_per_se;
2047 unsigned max_texture_channel_caches;
2048 unsigned max_gprs;
2049 unsigned max_gs_threads;
2050 unsigned max_hw_contexts;
2051 unsigned sc_prim_fifo_size_frontend;
2052 unsigned sc_prim_fifo_size_backend;
2053 unsigned sc_hiz_tile_fifo_size;
2054 unsigned sc_earlyz_tile_fifo_size;
2055
2056 unsigned num_tile_pipes;
2057 unsigned backend_enable_mask;
2058 unsigned backend_disable_mask_per_asic;
2059 unsigned backend_map;
2060 unsigned num_texture_channel_caches;
2061 unsigned mem_max_burst_length_bytes;
2062 unsigned mem_row_size_in_kb;
2063 unsigned shader_engine_tile_size;
2064 unsigned num_gpus;
2065 unsigned multi_gpu_tile_size;
2066
2067 unsigned tile_config;
2068 uint32_t tile_mode_array[32];
2069 uint32_t active_cus;
2070 };
2071
2072 struct cik_asic {
2073 unsigned max_shader_engines;
2074 unsigned max_tile_pipes;
2075 unsigned max_cu_per_sh;
2076 unsigned max_sh_per_se;
2077 unsigned max_backends_per_se;
2078 unsigned max_texture_channel_caches;
2079 unsigned max_gprs;
2080 unsigned max_gs_threads;
2081 unsigned max_hw_contexts;
2082 unsigned sc_prim_fifo_size_frontend;
2083 unsigned sc_prim_fifo_size_backend;
2084 unsigned sc_hiz_tile_fifo_size;
2085 unsigned sc_earlyz_tile_fifo_size;
2086
2087 unsigned num_tile_pipes;
2088 unsigned backend_enable_mask;
2089 unsigned backend_disable_mask_per_asic;
2090 unsigned backend_map;
2091 unsigned num_texture_channel_caches;
2092 unsigned mem_max_burst_length_bytes;
2093 unsigned mem_row_size_in_kb;
2094 unsigned shader_engine_tile_size;
2095 unsigned num_gpus;
2096 unsigned multi_gpu_tile_size;
2097
2098 unsigned tile_config;
2099 uint32_t tile_mode_array[32];
2100 uint32_t macrotile_mode_array[16];
2101 uint32_t active_cus;
2102 };
2103
2104 union radeon_asic_config {
2105 struct r300_asic r300;
2106 struct r100_asic r100;
2107 struct r600_asic r600;
2108 struct rv770_asic rv770;
2109 struct evergreen_asic evergreen;
2110 struct cayman_asic cayman;
2111 struct si_asic si;
2112 struct cik_asic cik;
2113 };
2114
2115 /*
2116 * asic initizalization from radeon_asic.c
2117 */
2118 void radeon_agp_disable(struct radeon_device *rdev);
2119 int radeon_asic_init(struct radeon_device *rdev);
2120
2121
2122 /*
2123 * IOCTL.
2124 */
2125 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2126 struct drm_file *filp);
2127 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2128 struct drm_file *filp);
2129 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2130 struct drm_file *file_priv);
2131 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2132 struct drm_file *file_priv);
2133 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2134 struct drm_file *file_priv);
2135 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2136 struct drm_file *file_priv);
2137 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2138 struct drm_file *filp);
2139 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2140 struct drm_file *filp);
2141 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2142 struct drm_file *filp);
2143 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2144 struct drm_file *filp);
2145 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2146 struct drm_file *filp);
2147 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2148 struct drm_file *filp);
2149 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2150 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2151 struct drm_file *filp);
2152 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2153 struct drm_file *filp);
2154
2155 /* VRAM scratch page for HDP bug, default vram page */
2156 struct r600_vram_scratch {
2157 struct radeon_bo *robj;
2158 volatile uint32_t *ptr;
2159 u64 gpu_addr;
2160 };
2161
2162 /*
2163 * ACPI
2164 */
2165 struct radeon_atif_notification_cfg {
2166 bool enabled;
2167 int command_code;
2168 };
2169
2170 struct radeon_atif_notifications {
2171 bool display_switch;
2172 bool expansion_mode_change;
2173 bool thermal_state;
2174 bool forced_power_state;
2175 bool system_power_state;
2176 bool display_conf_change;
2177 bool px_gfx_switch;
2178 bool brightness_change;
2179 bool dgpu_display_event;
2180 };
2181
2182 struct radeon_atif_functions {
2183 bool system_params;
2184 bool sbios_requests;
2185 bool select_active_disp;
2186 bool lid_state;
2187 bool get_tv_standard;
2188 bool set_tv_standard;
2189 bool get_panel_expansion_mode;
2190 bool set_panel_expansion_mode;
2191 bool temperature_change;
2192 bool graphics_device_types;
2193 };
2194
2195 struct radeon_atif {
2196 struct radeon_atif_notifications notifications;
2197 struct radeon_atif_functions functions;
2198 struct radeon_atif_notification_cfg notification_cfg;
2199 struct radeon_encoder *encoder_for_bl;
2200 };
2201
2202 struct radeon_atcs_functions {
2203 bool get_ext_state;
2204 bool pcie_perf_req;
2205 bool pcie_dev_rdy;
2206 bool pcie_bus_width;
2207 };
2208
2209 struct radeon_atcs {
2210 struct radeon_atcs_functions functions;
2211 };
2212
2213 /*
2214 * Core structure, functions and helpers.
2215 */
2216 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2217 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2218
2219 struct radeon_device {
2220 struct device *dev;
2221 struct drm_device *ddev;
2222 struct pci_dev *pdev;
2223 struct rw_semaphore exclusive_lock;
2224 /* ASIC */
2225 union radeon_asic_config config;
2226 enum radeon_family family;
2227 unsigned long flags;
2228 int usec_timeout;
2229 enum radeon_pll_errata pll_errata;
2230 int num_gb_pipes;
2231 int num_z_pipes;
2232 int disp_priority;
2233 /* BIOS */
2234 uint8_t *bios;
2235 bool is_atom_bios;
2236 uint16_t bios_header_start;
2237 struct radeon_bo *stollen_vga_memory;
2238 /* Register mmio */
2239 resource_size_t rmmio_base;
2240 resource_size_t rmmio_size;
2241 /* protects concurrent MM_INDEX/DATA based register access */
2242 spinlock_t mmio_idx_lock;
2243 /* protects concurrent SMC based register access */
2244 spinlock_t smc_idx_lock;
2245 /* protects concurrent PLL register access */
2246 spinlock_t pll_idx_lock;
2247 /* protects concurrent MC register access */
2248 spinlock_t mc_idx_lock;
2249 /* protects concurrent PCIE register access */
2250 spinlock_t pcie_idx_lock;
2251 /* protects concurrent PCIE_PORT register access */
2252 spinlock_t pciep_idx_lock;
2253 /* protects concurrent PIF register access */
2254 spinlock_t pif_idx_lock;
2255 /* protects concurrent CG register access */
2256 spinlock_t cg_idx_lock;
2257 /* protects concurrent UVD register access */
2258 spinlock_t uvd_idx_lock;
2259 /* protects concurrent RCU register access */
2260 spinlock_t rcu_idx_lock;
2261 /* protects concurrent DIDT register access */
2262 spinlock_t didt_idx_lock;
2263 /* protects concurrent ENDPOINT (audio) register access */
2264 spinlock_t end_idx_lock;
2265 void __iomem *rmmio;
2266 radeon_rreg_t mc_rreg;
2267 radeon_wreg_t mc_wreg;
2268 radeon_rreg_t pll_rreg;
2269 radeon_wreg_t pll_wreg;
2270 uint32_t pcie_reg_mask;
2271 radeon_rreg_t pciep_rreg;
2272 radeon_wreg_t pciep_wreg;
2273 /* io port */
2274 void __iomem *rio_mem;
2275 resource_size_t rio_mem_size;
2276 struct radeon_clock clock;
2277 struct radeon_mc mc;
2278 struct radeon_gart gart;
2279 struct radeon_mode_info mode_info;
2280 struct radeon_scratch scratch;
2281 struct radeon_doorbell doorbell;
2282 struct radeon_mman mman;
2283 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2284 wait_queue_head_t fence_queue;
2285 struct mutex ring_lock;
2286 struct radeon_ring ring[RADEON_NUM_RINGS];
2287 bool ib_pool_ready;
2288 struct radeon_sa_manager ring_tmp_bo;
2289 struct radeon_irq irq;
2290 struct radeon_asic *asic;
2291 struct radeon_gem gem;
2292 struct radeon_pm pm;
2293 struct radeon_uvd uvd;
2294 struct radeon_vce vce;
2295 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2296 struct radeon_wb wb;
2297 struct radeon_dummy_page dummy_page;
2298 bool shutdown;
2299 bool suspend;
2300 bool need_dma32;
2301 bool accel_working;
2302 bool fastfb_working; /* IGP feature*/
2303 bool needs_reset;
2304 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2305 const struct firmware *me_fw; /* all family ME firmware */
2306 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2307 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2308 const struct firmware *mc_fw; /* NI MC firmware */
2309 const struct firmware *ce_fw; /* SI CE firmware */
2310 const struct firmware *mec_fw; /* CIK MEC firmware */
2311 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2312 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2313 const struct firmware *smc_fw; /* SMC firmware */
2314 const struct firmware *uvd_fw; /* UVD firmware */
2315 const struct firmware *vce_fw; /* VCE firmware */
2316 bool new_fw;
2317 struct r600_vram_scratch vram_scratch;
2318 int msi_enabled; /* msi enabled */
2319 struct r600_ih ih; /* r6/700 interrupt ring */
2320 struct radeon_rlc rlc;
2321 struct radeon_mec mec;
2322 struct work_struct hotplug_work;
2323 struct work_struct audio_work;
2324 struct work_struct reset_work;
2325 int num_crtc; /* number of crtcs */
2326 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2327 bool has_uvd;
2328 struct r600_audio audio; /* audio stuff */
2329 struct notifier_block acpi_nb;
2330 /* only one userspace can use Hyperz features or CMASK at a time */
2331 struct drm_file *hyperz_filp;
2332 struct drm_file *cmask_filp;
2333 /* i2c buses */
2334 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2335 /* debugfs */
2336 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2337 unsigned debugfs_count;
2338 /* virtual memory */
2339 struct radeon_vm_manager vm_manager;
2340 struct mutex gpu_clock_mutex;
2341 /* memory stats */
2342 atomic64_t vram_usage;
2343 atomic64_t gtt_usage;
2344 atomic64_t num_bytes_moved;
2345 /* ACPI interface */
2346 struct radeon_atif atif;
2347 struct radeon_atcs atcs;
2348 /* srbm instance registers */
2349 struct mutex srbm_mutex;
2350 /* clock, powergating flags */
2351 u32 cg_flags;
2352 u32 pg_flags;
2353
2354 struct dev_pm_domain vga_pm_domain;
2355 bool have_disp_power_ref;
2356 };
2357
2358 bool radeon_is_px(struct drm_device *dev);
2359 int radeon_device_init(struct radeon_device *rdev,
2360 struct drm_device *ddev,
2361 struct pci_dev *pdev,
2362 uint32_t flags);
2363 void radeon_device_fini(struct radeon_device *rdev);
2364 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2365
2366 #define RADEON_MIN_MMIO_SIZE 0x10000
2367
2368 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2369 bool always_indirect)
2370 {
2371 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2372 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2373 return readl(((void __iomem *)rdev->rmmio) + reg);
2374 else {
2375 unsigned long flags;
2376 uint32_t ret;
2377
2378 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2379 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2380 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2381 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2382
2383 return ret;
2384 }
2385 }
2386
2387 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2388 bool always_indirect)
2389 {
2390 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2391 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2392 else {
2393 unsigned long flags;
2394
2395 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2396 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2397 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2398 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2399 }
2400 }
2401
2402 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2403 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2404
2405 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2406 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2407
2408 /*
2409 * Cast helper
2410 */
2411 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2412
2413 /*
2414 * Registers read & write functions.
2415 */
2416 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2417 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2418 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2419 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2420 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2421 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2422 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2423 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2424 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2425 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2426 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2427 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2428 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2429 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2430 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2431 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2432 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2433 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2434 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2435 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2436 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2437 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2438 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2439 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2440 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2441 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2442 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2443 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2444 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2445 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2446 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2447 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2448 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2449 #define WREG32_P(reg, val, mask) \
2450 do { \
2451 uint32_t tmp_ = RREG32(reg); \
2452 tmp_ &= (mask); \
2453 tmp_ |= ((val) & ~(mask)); \
2454 WREG32(reg, tmp_); \
2455 } while (0)
2456 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2457 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2458 #define WREG32_PLL_P(reg, val, mask) \
2459 do { \
2460 uint32_t tmp_ = RREG32_PLL(reg); \
2461 tmp_ &= (mask); \
2462 tmp_ |= ((val) & ~(mask)); \
2463 WREG32_PLL(reg, tmp_); \
2464 } while (0)
2465 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2466 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2467 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2468
2469 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2470 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2471
2472 /*
2473 * Indirect registers accessor
2474 */
2475 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2476 {
2477 unsigned long flags;
2478 uint32_t r;
2479
2480 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2481 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2482 r = RREG32(RADEON_PCIE_DATA);
2483 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2484 return r;
2485 }
2486
2487 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2488 {
2489 unsigned long flags;
2490
2491 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2492 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2493 WREG32(RADEON_PCIE_DATA, (v));
2494 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2495 }
2496
2497 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2498 {
2499 unsigned long flags;
2500 u32 r;
2501
2502 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2503 WREG32(TN_SMC_IND_INDEX_0, (reg));
2504 r = RREG32(TN_SMC_IND_DATA_0);
2505 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2506 return r;
2507 }
2508
2509 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2510 {
2511 unsigned long flags;
2512
2513 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2514 WREG32(TN_SMC_IND_INDEX_0, (reg));
2515 WREG32(TN_SMC_IND_DATA_0, (v));
2516 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2517 }
2518
2519 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2520 {
2521 unsigned long flags;
2522 u32 r;
2523
2524 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2525 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2526 r = RREG32(R600_RCU_DATA);
2527 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2528 return r;
2529 }
2530
2531 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2532 {
2533 unsigned long flags;
2534
2535 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2536 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2537 WREG32(R600_RCU_DATA, (v));
2538 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2539 }
2540
2541 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2542 {
2543 unsigned long flags;
2544 u32 r;
2545
2546 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2547 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2548 r = RREG32(EVERGREEN_CG_IND_DATA);
2549 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2550 return r;
2551 }
2552
2553 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2554 {
2555 unsigned long flags;
2556
2557 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2558 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2559 WREG32(EVERGREEN_CG_IND_DATA, (v));
2560 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2561 }
2562
2563 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2564 {
2565 unsigned long flags;
2566 u32 r;
2567
2568 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2569 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2570 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2571 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2572 return r;
2573 }
2574
2575 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2576 {
2577 unsigned long flags;
2578
2579 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2580 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2581 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2582 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2583 }
2584
2585 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2586 {
2587 unsigned long flags;
2588 u32 r;
2589
2590 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2591 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2592 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2593 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2594 return r;
2595 }
2596
2597 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2598 {
2599 unsigned long flags;
2600
2601 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2602 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2603 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2604 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2605 }
2606
2607 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2608 {
2609 unsigned long flags;
2610 u32 r;
2611
2612 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2613 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2614 r = RREG32(R600_UVD_CTX_DATA);
2615 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2616 return r;
2617 }
2618
2619 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2620 {
2621 unsigned long flags;
2622
2623 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2624 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2625 WREG32(R600_UVD_CTX_DATA, (v));
2626 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2627 }
2628
2629
2630 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2631 {
2632 unsigned long flags;
2633 u32 r;
2634
2635 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2636 WREG32(CIK_DIDT_IND_INDEX, (reg));
2637 r = RREG32(CIK_DIDT_IND_DATA);
2638 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2639 return r;
2640 }
2641
2642 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2643 {
2644 unsigned long flags;
2645
2646 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2647 WREG32(CIK_DIDT_IND_INDEX, (reg));
2648 WREG32(CIK_DIDT_IND_DATA, (v));
2649 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2650 }
2651
2652 void r100_pll_errata_after_index(struct radeon_device *rdev);
2653
2654
2655 /*
2656 * ASICs helpers.
2657 */
2658 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2659 (rdev->pdev->device == 0x5969))
2660 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2661 (rdev->family == CHIP_RV200) || \
2662 (rdev->family == CHIP_RS100) || \
2663 (rdev->family == CHIP_RS200) || \
2664 (rdev->family == CHIP_RV250) || \
2665 (rdev->family == CHIP_RV280) || \
2666 (rdev->family == CHIP_RS300))
2667 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2668 (rdev->family == CHIP_RV350) || \
2669 (rdev->family == CHIP_R350) || \
2670 (rdev->family == CHIP_RV380) || \
2671 (rdev->family == CHIP_R420) || \
2672 (rdev->family == CHIP_R423) || \
2673 (rdev->family == CHIP_RV410) || \
2674 (rdev->family == CHIP_RS400) || \
2675 (rdev->family == CHIP_RS480))
2676 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2677 (rdev->ddev->pdev->device == 0x9443) || \
2678 (rdev->ddev->pdev->device == 0x944B) || \
2679 (rdev->ddev->pdev->device == 0x9506) || \
2680 (rdev->ddev->pdev->device == 0x9509) || \
2681 (rdev->ddev->pdev->device == 0x950F) || \
2682 (rdev->ddev->pdev->device == 0x689C) || \
2683 (rdev->ddev->pdev->device == 0x689D))
2684 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2685 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2686 (rdev->family == CHIP_RS690) || \
2687 (rdev->family == CHIP_RS740) || \
2688 (rdev->family >= CHIP_R600))
2689 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2690 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2691 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2692 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2693 (rdev->flags & RADEON_IS_IGP))
2694 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2695 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2696 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2697 (rdev->flags & RADEON_IS_IGP))
2698 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2699 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2700 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2701 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2702 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2703 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2704 (rdev->family == CHIP_MULLINS))
2705
2706 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2707 (rdev->ddev->pdev->device == 0x6850) || \
2708 (rdev->ddev->pdev->device == 0x6858) || \
2709 (rdev->ddev->pdev->device == 0x6859) || \
2710 (rdev->ddev->pdev->device == 0x6840) || \
2711 (rdev->ddev->pdev->device == 0x6841) || \
2712 (rdev->ddev->pdev->device == 0x6842) || \
2713 (rdev->ddev->pdev->device == 0x6843))
2714
2715 /*
2716 * BIOS helpers.
2717 */
2718 #define RBIOS8(i) (rdev->bios[i])
2719 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2720 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2721
2722 int radeon_combios_init(struct radeon_device *rdev);
2723 void radeon_combios_fini(struct radeon_device *rdev);
2724 int radeon_atombios_init(struct radeon_device *rdev);
2725 void radeon_atombios_fini(struct radeon_device *rdev);
2726
2727
2728 /*
2729 * RING helpers.
2730 */
2731 #if DRM_DEBUG_CODE == 0
2732 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2733 {
2734 ring->ring[ring->wptr++] = v;
2735 ring->wptr &= ring->ptr_mask;
2736 ring->count_dw--;
2737 ring->ring_free_dw--;
2738 }
2739 #else
2740 /* With debugging this is just too big to inline */
2741 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2742 #endif
2743
2744 /*
2745 * ASICs macro.
2746 */
2747 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2748 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2749 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2750 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2751 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2752 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2753 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2754 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2755 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2756 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2757 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2758 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2759 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2760 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2761 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2762 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2763 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2764 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2765 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2766 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2767 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2768 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2769 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2770 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2771 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2772 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2773 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2774 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2775 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2776 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2777 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2778 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2779 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2780 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2781 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2782 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2783 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2784 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2785 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2786 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2787 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2788 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2789 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2790 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2791 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2792 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2793 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2794 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2795 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2796 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2797 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2798 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2799 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2800 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2801 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2802 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2803 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2804 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2805 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2806 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2807 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2808 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2809 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2810 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2811 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2812 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2813 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2814 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2815 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2816 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2817 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2818 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2819 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2820 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2821 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2822 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2823 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2824 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2825 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2826 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2827 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2828 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2829 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2830 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2831
2832 /* Common functions */
2833 /* AGP */
2834 extern int radeon_gpu_reset(struct radeon_device *rdev);
2835 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2836 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2837 extern void radeon_agp_disable(struct radeon_device *rdev);
2838 extern int radeon_modeset_init(struct radeon_device *rdev);
2839 extern void radeon_modeset_fini(struct radeon_device *rdev);
2840 extern bool radeon_card_posted(struct radeon_device *rdev);
2841 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2842 extern void radeon_update_display_priority(struct radeon_device *rdev);
2843 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2844 extern void radeon_scratch_init(struct radeon_device *rdev);
2845 extern void radeon_wb_fini(struct radeon_device *rdev);
2846 extern int radeon_wb_init(struct radeon_device *rdev);
2847 extern void radeon_wb_disable(struct radeon_device *rdev);
2848 extern void radeon_surface_init(struct radeon_device *rdev);
2849 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2850 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2851 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2852 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2853 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2854 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2855 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2856 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2857 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2858 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2859 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2860 const u32 *registers,
2861 const u32 array_size);
2862
2863 /*
2864 * vm
2865 */
2866 int radeon_vm_manager_init(struct radeon_device *rdev);
2867 void radeon_vm_manager_fini(struct radeon_device *rdev);
2868 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2869 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2870 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2871 struct radeon_vm *vm,
2872 struct list_head *head);
2873 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2874 struct radeon_vm *vm, int ring);
2875 void radeon_vm_flush(struct radeon_device *rdev,
2876 struct radeon_vm *vm,
2877 int ring);
2878 void radeon_vm_fence(struct radeon_device *rdev,
2879 struct radeon_vm *vm,
2880 struct radeon_fence *fence);
2881 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2882 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2883 struct radeon_vm *vm);
2884 int radeon_vm_clear_freed(struct radeon_device *rdev,
2885 struct radeon_vm *vm);
2886 int radeon_vm_bo_update(struct radeon_device *rdev,
2887 struct radeon_bo_va *bo_va,
2888 struct ttm_mem_reg *mem);
2889 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2890 struct radeon_bo *bo);
2891 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2892 struct radeon_bo *bo);
2893 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2894 struct radeon_vm *vm,
2895 struct radeon_bo *bo);
2896 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2897 struct radeon_bo_va *bo_va,
2898 uint64_t offset,
2899 uint32_t flags);
2900 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2901 struct radeon_bo_va *bo_va);
2902
2903 /* audio */
2904 void r600_audio_update_hdmi(struct work_struct *work);
2905 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2906 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2907 void r600_audio_enable(struct radeon_device *rdev,
2908 struct r600_audio_pin *pin,
2909 bool enable);
2910 void dce6_audio_enable(struct radeon_device *rdev,
2911 struct r600_audio_pin *pin,
2912 bool enable);
2913
2914 /*
2915 * R600 vram scratch functions
2916 */
2917 int r600_vram_scratch_init(struct radeon_device *rdev);
2918 void r600_vram_scratch_fini(struct radeon_device *rdev);
2919
2920 /*
2921 * r600 cs checking helper
2922 */
2923 unsigned r600_mip_minify(unsigned size, unsigned level);
2924 bool r600_fmt_is_valid_color(u32 format);
2925 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2926 int r600_fmt_get_blocksize(u32 format);
2927 int r600_fmt_get_nblocksx(u32 format, u32 w);
2928 int r600_fmt_get_nblocksy(u32 format, u32 h);
2929
2930 /*
2931 * r600 functions used by radeon_encoder.c
2932 */
2933 struct radeon_hdmi_acr {
2934 u32 clock;
2935
2936 int n_32khz;
2937 int cts_32khz;
2938
2939 int n_44_1khz;
2940 int cts_44_1khz;
2941
2942 int n_48khz;
2943 int cts_48khz;
2944
2945 };
2946
2947 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2948
2949 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2950 u32 tiling_pipe_num,
2951 u32 max_rb_num,
2952 u32 total_max_rb_num,
2953 u32 enabled_rb_mask);
2954
2955 /*
2956 * evergreen functions used by radeon_encoder.c
2957 */
2958
2959 extern int ni_init_microcode(struct radeon_device *rdev);
2960 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2961
2962 /* radeon_acpi.c */
2963 #if defined(CONFIG_ACPI)
2964 extern int radeon_acpi_init(struct radeon_device *rdev);
2965 extern void radeon_acpi_fini(struct radeon_device *rdev);
2966 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2967 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2968 u8 perf_req, bool advertise);
2969 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2970 #else
2971 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2972 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2973 #endif
2974
2975 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2976 struct radeon_cs_packet *pkt,
2977 unsigned idx);
2978 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2979 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2980 struct radeon_cs_packet *pkt);
2981 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2982 struct radeon_cs_reloc **cs_reloc,
2983 int nomm);
2984 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2985 uint32_t *vline_start_end,
2986 uint32_t *vline_status);
2987
2988 #include "radeon_object.h"
2989
2990 #endif
Linux kernel - Deliverables
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