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[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97
98 /*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
109
110 /* max number of rings */
111 #define RADEON_NUM_RINGS 3
112
113 /* internal ring indices */
114 /* r1xx+ has gfx CP ring */
115 #define RADEON_RING_TYPE_GFX_INDEX 0
116
117 /* cayman has 2 compute CP rings */
118 #define CAYMAN_RING_TYPE_CP1_INDEX 1
119 #define CAYMAN_RING_TYPE_CP2_INDEX 2
120
121 /* hardcode those limit for now */
122 #define RADEON_VA_RESERVED_SIZE (8 << 20)
123 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
124
125 /*
126 * Errata workarounds.
127 */
128 enum radeon_pll_errata {
129 CHIP_ERRATA_R300_CG = 0x00000001,
130 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
131 CHIP_ERRATA_PLL_DELAY = 0x00000004
132 };
133
134
135 struct radeon_device;
136
137
138 /*
139 * BIOS.
140 */
141 #define ATRM_BIOS_PAGE 4096
142
143 #if defined(CONFIG_VGA_SWITCHEROO)
144 bool radeon_atrm_supported(struct pci_dev *pdev);
145 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
146 #else
147 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
148 {
149 return false;
150 }
151
152 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
153 return -EINVAL;
154 }
155 #endif
156 bool radeon_get_bios(struct radeon_device *rdev);
157
158
159 /*
160 * Dummy page
161 */
162 struct radeon_dummy_page {
163 struct page *page;
164 dma_addr_t addr;
165 };
166 int radeon_dummy_page_init(struct radeon_device *rdev);
167 void radeon_dummy_page_fini(struct radeon_device *rdev);
168
169
170 /*
171 * Clocks
172 */
173 struct radeon_clock {
174 struct radeon_pll p1pll;
175 struct radeon_pll p2pll;
176 struct radeon_pll dcpll;
177 struct radeon_pll spll;
178 struct radeon_pll mpll;
179 /* 10 Khz units */
180 uint32_t default_mclk;
181 uint32_t default_sclk;
182 uint32_t default_dispclk;
183 uint32_t dp_extclk;
184 uint32_t max_pixel_clock;
185 };
186
187 /*
188 * Power management
189 */
190 int radeon_pm_init(struct radeon_device *rdev);
191 void radeon_pm_fini(struct radeon_device *rdev);
192 void radeon_pm_compute_clocks(struct radeon_device *rdev);
193 void radeon_pm_suspend(struct radeon_device *rdev);
194 void radeon_pm_resume(struct radeon_device *rdev);
195 void radeon_combios_get_power_modes(struct radeon_device *rdev);
196 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
197 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
198 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
199 void rs690_pm_info(struct radeon_device *rdev);
200 extern int rv6xx_get_temp(struct radeon_device *rdev);
201 extern int rv770_get_temp(struct radeon_device *rdev);
202 extern int evergreen_get_temp(struct radeon_device *rdev);
203 extern int sumo_get_temp(struct radeon_device *rdev);
204
205 /*
206 * Fences.
207 */
208 struct radeon_fence_driver {
209 uint32_t scratch_reg;
210 uint64_t gpu_addr;
211 volatile uint32_t *cpu_addr;
212 atomic_t seq;
213 uint32_t last_seq;
214 unsigned long last_jiffies;
215 unsigned long last_timeout;
216 wait_queue_head_t queue;
217 struct list_head created;
218 struct list_head emitted;
219 struct list_head signaled;
220 bool initialized;
221 };
222
223 struct radeon_fence {
224 struct radeon_device *rdev;
225 struct kref kref;
226 struct list_head list;
227 /* protected by radeon_fence.lock */
228 uint32_t seq;
229 bool emitted;
230 bool signaled;
231 /* RB, DMA, etc. */
232 int ring;
233 struct radeon_semaphore *semaphore;
234 };
235
236 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
237 int radeon_fence_driver_init(struct radeon_device *rdev);
238 void radeon_fence_driver_fini(struct radeon_device *rdev);
239 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
240 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
241 void radeon_fence_process(struct radeon_device *rdev, int ring);
242 bool radeon_fence_signaled(struct radeon_fence *fence);
243 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
244 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
245 int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
246 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
247 void radeon_fence_unref(struct radeon_fence **fence);
248 int radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
249
250 /*
251 * Tiling registers
252 */
253 struct radeon_surface_reg {
254 struct radeon_bo *bo;
255 };
256
257 #define RADEON_GEM_MAX_SURFACES 8
258
259 /*
260 * TTM.
261 */
262 struct radeon_mman {
263 struct ttm_bo_global_ref bo_global_ref;
264 struct drm_global_reference mem_global_ref;
265 struct ttm_bo_device bdev;
266 bool mem_global_referenced;
267 bool initialized;
268 };
269
270 /* bo virtual address in a specific vm */
271 struct radeon_bo_va {
272 /* bo list is protected by bo being reserved */
273 struct list_head bo_list;
274 /* vm list is protected by vm mutex */
275 struct list_head vm_list;
276 /* constant after initialization */
277 struct radeon_vm *vm;
278 struct radeon_bo *bo;
279 uint64_t soffset;
280 uint64_t eoffset;
281 uint32_t flags;
282 bool valid;
283 };
284
285 struct radeon_bo {
286 /* Protected by gem.mutex */
287 struct list_head list;
288 /* Protected by tbo.reserved */
289 u32 placements[3];
290 struct ttm_placement placement;
291 struct ttm_buffer_object tbo;
292 struct ttm_bo_kmap_obj kmap;
293 unsigned pin_count;
294 void *kptr;
295 u32 tiling_flags;
296 u32 pitch;
297 int surface_reg;
298 /* list of all virtual address to which this bo
299 * is associated to
300 */
301 struct list_head va;
302 /* Constant after initialization */
303 struct radeon_device *rdev;
304 struct drm_gem_object gem_base;
305 };
306 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
307
308 struct radeon_bo_list {
309 struct ttm_validate_buffer tv;
310 struct radeon_bo *bo;
311 uint64_t gpu_offset;
312 unsigned rdomain;
313 unsigned wdomain;
314 u32 tiling_flags;
315 };
316
317 /* sub-allocation manager, it has to be protected by another lock.
318 * By conception this is an helper for other part of the driver
319 * like the indirect buffer or semaphore, which both have their
320 * locking.
321 *
322 * Principe is simple, we keep a list of sub allocation in offset
323 * order (first entry has offset == 0, last entry has the highest
324 * offset).
325 *
326 * When allocating new object we first check if there is room at
327 * the end total_size - (last_object_offset + last_object_size) >=
328 * alloc_size. If so we allocate new object there.
329 *
330 * When there is not enough room at the end, we start waiting for
331 * each sub object until we reach object_offset+object_size >=
332 * alloc_size, this object then become the sub object we return.
333 *
334 * Alignment can't be bigger than page size.
335 *
336 * Hole are not considered for allocation to keep things simple.
337 * Assumption is that there won't be hole (all object on same
338 * alignment).
339 */
340 struct radeon_sa_manager {
341 struct radeon_bo *bo;
342 struct list_head sa_bo;
343 unsigned size;
344 uint64_t gpu_addr;
345 void *cpu_ptr;
346 uint32_t domain;
347 };
348
349 struct radeon_sa_bo;
350
351 /* sub-allocation buffer */
352 struct radeon_sa_bo {
353 struct list_head list;
354 struct radeon_sa_manager *manager;
355 unsigned offset;
356 unsigned size;
357 };
358
359 /*
360 * GEM objects.
361 */
362 struct radeon_gem {
363 struct mutex mutex;
364 struct list_head objects;
365 };
366
367 int radeon_gem_init(struct radeon_device *rdev);
368 void radeon_gem_fini(struct radeon_device *rdev);
369 int radeon_gem_object_create(struct radeon_device *rdev, int size,
370 int alignment, int initial_domain,
371 bool discardable, bool kernel,
372 struct drm_gem_object **obj);
373 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
374 uint64_t *gpu_addr);
375 void radeon_gem_object_unpin(struct drm_gem_object *obj);
376
377 int radeon_mode_dumb_create(struct drm_file *file_priv,
378 struct drm_device *dev,
379 struct drm_mode_create_dumb *args);
380 int radeon_mode_dumb_mmap(struct drm_file *filp,
381 struct drm_device *dev,
382 uint32_t handle, uint64_t *offset_p);
383 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
384 struct drm_device *dev,
385 uint32_t handle);
386
387 /*
388 * Semaphores.
389 */
390 struct radeon_ring;
391
392 #define RADEON_SEMAPHORE_BO_SIZE 256
393
394 struct radeon_semaphore_driver {
395 rwlock_t lock;
396 struct list_head bo;
397 };
398
399 struct radeon_semaphore_bo;
400
401 /* everything here is constant */
402 struct radeon_semaphore {
403 struct list_head list;
404 uint64_t gpu_addr;
405 uint32_t *cpu_ptr;
406 struct radeon_semaphore_bo *bo;
407 };
408
409 struct radeon_semaphore_bo {
410 struct list_head list;
411 struct radeon_ib *ib;
412 struct list_head free;
413 struct radeon_semaphore semaphores[RADEON_SEMAPHORE_BO_SIZE/8];
414 unsigned nused;
415 };
416
417 void radeon_semaphore_driver_fini(struct radeon_device *rdev);
418 int radeon_semaphore_create(struct radeon_device *rdev,
419 struct radeon_semaphore **semaphore);
420 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
421 struct radeon_semaphore *semaphore);
422 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
423 struct radeon_semaphore *semaphore);
424 void radeon_semaphore_free(struct radeon_device *rdev,
425 struct radeon_semaphore *semaphore);
426
427 /*
428 * GART structures, functions & helpers
429 */
430 struct radeon_mc;
431
432 #define RADEON_GPU_PAGE_SIZE 4096
433 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
434 #define RADEON_GPU_PAGE_SHIFT 12
435 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
436
437 struct radeon_gart {
438 dma_addr_t table_addr;
439 struct radeon_bo *robj;
440 void *ptr;
441 unsigned num_gpu_pages;
442 unsigned num_cpu_pages;
443 unsigned table_size;
444 struct page **pages;
445 dma_addr_t *pages_addr;
446 bool ready;
447 };
448
449 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
450 void radeon_gart_table_ram_free(struct radeon_device *rdev);
451 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
452 void radeon_gart_table_vram_free(struct radeon_device *rdev);
453 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
454 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
455 int radeon_gart_init(struct radeon_device *rdev);
456 void radeon_gart_fini(struct radeon_device *rdev);
457 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
458 int pages);
459 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
460 int pages, struct page **pagelist,
461 dma_addr_t *dma_addr);
462 void radeon_gart_restore(struct radeon_device *rdev);
463
464
465 /*
466 * GPU MC structures, functions & helpers
467 */
468 struct radeon_mc {
469 resource_size_t aper_size;
470 resource_size_t aper_base;
471 resource_size_t agp_base;
472 /* for some chips with <= 32MB we need to lie
473 * about vram size near mc fb location */
474 u64 mc_vram_size;
475 u64 visible_vram_size;
476 u64 gtt_size;
477 u64 gtt_start;
478 u64 gtt_end;
479 u64 vram_start;
480 u64 vram_end;
481 unsigned vram_width;
482 u64 real_vram_size;
483 int vram_mtrr;
484 bool vram_is_ddr;
485 bool igp_sideport_enabled;
486 u64 gtt_base_align;
487 };
488
489 bool radeon_combios_sideport_present(struct radeon_device *rdev);
490 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
491
492 /*
493 * GPU scratch registers structures, functions & helpers
494 */
495 struct radeon_scratch {
496 unsigned num_reg;
497 uint32_t reg_base;
498 bool free[32];
499 uint32_t reg[32];
500 };
501
502 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
503 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
504
505
506 /*
507 * IRQS.
508 */
509
510 struct radeon_unpin_work {
511 struct work_struct work;
512 struct radeon_device *rdev;
513 int crtc_id;
514 struct radeon_fence *fence;
515 struct drm_pending_vblank_event *event;
516 struct radeon_bo *old_rbo;
517 u64 new_crtc_base;
518 };
519
520 struct r500_irq_stat_regs {
521 u32 disp_int;
522 };
523
524 struct r600_irq_stat_regs {
525 u32 disp_int;
526 u32 disp_int_cont;
527 u32 disp_int_cont2;
528 u32 d1grph_int;
529 u32 d2grph_int;
530 };
531
532 struct evergreen_irq_stat_regs {
533 u32 disp_int;
534 u32 disp_int_cont;
535 u32 disp_int_cont2;
536 u32 disp_int_cont3;
537 u32 disp_int_cont4;
538 u32 disp_int_cont5;
539 u32 d1grph_int;
540 u32 d2grph_int;
541 u32 d3grph_int;
542 u32 d4grph_int;
543 u32 d5grph_int;
544 u32 d6grph_int;
545 };
546
547 union radeon_irq_stat_regs {
548 struct r500_irq_stat_regs r500;
549 struct r600_irq_stat_regs r600;
550 struct evergreen_irq_stat_regs evergreen;
551 };
552
553 #define RADEON_MAX_HPD_PINS 6
554 #define RADEON_MAX_CRTCS 6
555 #define RADEON_MAX_HDMI_BLOCKS 2
556
557 struct radeon_irq {
558 bool installed;
559 bool sw_int[RADEON_NUM_RINGS];
560 bool crtc_vblank_int[RADEON_MAX_CRTCS];
561 bool pflip[RADEON_MAX_CRTCS];
562 wait_queue_head_t vblank_queue;
563 bool hpd[RADEON_MAX_HPD_PINS];
564 bool gui_idle;
565 bool gui_idle_acked;
566 wait_queue_head_t idle_queue;
567 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
568 spinlock_t sw_lock;
569 int sw_refcount[RADEON_NUM_RINGS];
570 union radeon_irq_stat_regs stat_regs;
571 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
572 int pflip_refcount[RADEON_MAX_CRTCS];
573 };
574
575 int radeon_irq_kms_init(struct radeon_device *rdev);
576 void radeon_irq_kms_fini(struct radeon_device *rdev);
577 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
578 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
579 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
580 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
581
582 /*
583 * CP & rings.
584 */
585
586 struct radeon_ib {
587 struct radeon_sa_bo sa_bo;
588 unsigned idx;
589 uint32_t length_dw;
590 uint64_t gpu_addr;
591 uint32_t *ptr;
592 struct radeon_fence *fence;
593 unsigned vm_id;
594 };
595
596 /*
597 * locking -
598 * mutex protects scheduled_ibs, ready, alloc_bm
599 */
600 struct radeon_ib_pool {
601 struct mutex mutex;
602 struct radeon_sa_manager sa_manager;
603 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
604 bool ready;
605 unsigned head_id;
606 };
607
608 struct radeon_ring {
609 struct radeon_bo *ring_obj;
610 volatile uint32_t *ring;
611 unsigned rptr;
612 unsigned rptr_offs;
613 unsigned rptr_reg;
614 unsigned wptr;
615 unsigned wptr_old;
616 unsigned wptr_reg;
617 unsigned ring_size;
618 unsigned ring_free_dw;
619 int count_dw;
620 uint64_t gpu_addr;
621 uint32_t align_mask;
622 uint32_t ptr_mask;
623 struct mutex mutex;
624 bool ready;
625 u32 ptr_reg_shift;
626 u32 ptr_reg_mask;
627 u32 nop;
628 };
629
630 /*
631 * VM
632 */
633 struct radeon_vm {
634 struct list_head list;
635 struct list_head va;
636 int id;
637 unsigned last_pfn;
638 u64 pt_gpu_addr;
639 u64 *pt;
640 struct radeon_sa_bo sa_bo;
641 struct mutex mutex;
642 /* last fence for cs using this vm */
643 struct radeon_fence *fence;
644 };
645
646 struct radeon_vm_funcs {
647 int (*init)(struct radeon_device *rdev);
648 void (*fini)(struct radeon_device *rdev);
649 /* cs mutex must be lock for schedule_ib */
650 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
651 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
652 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
653 uint32_t (*page_flags)(struct radeon_device *rdev,
654 struct radeon_vm *vm,
655 uint32_t flags);
656 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
657 unsigned pfn, uint64_t addr, uint32_t flags);
658 };
659
660 struct radeon_vm_manager {
661 struct list_head lru_vm;
662 uint32_t use_bitmap;
663 struct radeon_sa_manager sa_manager;
664 uint32_t max_pfn;
665 /* fields constant after init */
666 const struct radeon_vm_funcs *funcs;
667 /* number of VMIDs */
668 unsigned nvm;
669 /* vram base address for page table entry */
670 u64 vram_base_offset;
671 };
672
673 /*
674 * file private structure
675 */
676 struct radeon_fpriv {
677 struct radeon_vm vm;
678 };
679
680 /*
681 * R6xx+ IH ring
682 */
683 struct r600_ih {
684 struct radeon_bo *ring_obj;
685 volatile uint32_t *ring;
686 unsigned rptr;
687 unsigned rptr_offs;
688 unsigned wptr;
689 unsigned wptr_old;
690 unsigned ring_size;
691 uint64_t gpu_addr;
692 uint32_t ptr_mask;
693 spinlock_t lock;
694 bool enabled;
695 };
696
697 struct r600_blit_cp_primitives {
698 void (*set_render_target)(struct radeon_device *rdev, int format,
699 int w, int h, u64 gpu_addr);
700 void (*cp_set_surface_sync)(struct radeon_device *rdev,
701 u32 sync_type, u32 size,
702 u64 mc_addr);
703 void (*set_shaders)(struct radeon_device *rdev);
704 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
705 void (*set_tex_resource)(struct radeon_device *rdev,
706 int format, int w, int h, int pitch,
707 u64 gpu_addr, u32 size);
708 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
709 int x2, int y2);
710 void (*draw_auto)(struct radeon_device *rdev);
711 void (*set_default_state)(struct radeon_device *rdev);
712 };
713
714 struct r600_blit {
715 struct mutex mutex;
716 struct radeon_bo *shader_obj;
717 struct r600_blit_cp_primitives primitives;
718 int max_dim;
719 int ring_size_common;
720 int ring_size_per_loop;
721 u64 shader_gpu_addr;
722 u32 vs_offset, ps_offset;
723 u32 state_offset;
724 u32 state_len;
725 u32 vb_used, vb_total;
726 struct radeon_ib *vb_ib;
727 };
728
729 void r600_blit_suspend(struct radeon_device *rdev);
730
731 int radeon_ib_get(struct radeon_device *rdev, int ring,
732 struct radeon_ib **ib, unsigned size);
733 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
734 bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib);
735 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
736 int radeon_ib_pool_init(struct radeon_device *rdev);
737 void radeon_ib_pool_fini(struct radeon_device *rdev);
738 int radeon_ib_pool_start(struct radeon_device *rdev);
739 int radeon_ib_pool_suspend(struct radeon_device *rdev);
740 int radeon_ib_test(struct radeon_device *rdev);
741 /* Ring access between begin & end cannot sleep */
742 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
743 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
744 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
745 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
746 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
747 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
748 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
749 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
750 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
751 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
752 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
753 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
754
755
756 /*
757 * CS.
758 */
759 struct radeon_cs_reloc {
760 struct drm_gem_object *gobj;
761 struct radeon_bo *robj;
762 struct radeon_bo_list lobj;
763 uint32_t handle;
764 uint32_t flags;
765 };
766
767 struct radeon_cs_chunk {
768 uint32_t chunk_id;
769 uint32_t length_dw;
770 int kpage_idx[2];
771 uint32_t *kpage[2];
772 uint32_t *kdata;
773 void __user *user_ptr;
774 int last_copied_page;
775 int last_page_index;
776 };
777
778 struct radeon_cs_parser {
779 struct device *dev;
780 struct radeon_device *rdev;
781 struct drm_file *filp;
782 /* chunks */
783 unsigned nchunks;
784 struct radeon_cs_chunk *chunks;
785 uint64_t *chunks_array;
786 /* IB */
787 unsigned idx;
788 /* relocations */
789 unsigned nrelocs;
790 struct radeon_cs_reloc *relocs;
791 struct radeon_cs_reloc **relocs_ptr;
792 struct list_head validated;
793 bool sync_to_ring[RADEON_NUM_RINGS];
794 /* indices of various chunks */
795 int chunk_ib_idx;
796 int chunk_relocs_idx;
797 int chunk_flags_idx;
798 struct radeon_ib *ib;
799 void *track;
800 unsigned family;
801 int parser_error;
802 u32 cs_flags;
803 u32 ring;
804 s32 priority;
805 };
806
807 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
808 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
809 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
810
811 struct radeon_cs_packet {
812 unsigned idx;
813 unsigned type;
814 unsigned reg;
815 unsigned opcode;
816 int count;
817 unsigned one_reg_wr;
818 };
819
820 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
821 struct radeon_cs_packet *pkt,
822 unsigned idx, unsigned reg);
823 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
824 struct radeon_cs_packet *pkt);
825
826
827 /*
828 * AGP
829 */
830 int radeon_agp_init(struct radeon_device *rdev);
831 void radeon_agp_resume(struct radeon_device *rdev);
832 void radeon_agp_suspend(struct radeon_device *rdev);
833 void radeon_agp_fini(struct radeon_device *rdev);
834
835
836 /*
837 * Writeback
838 */
839 struct radeon_wb {
840 struct radeon_bo *wb_obj;
841 volatile uint32_t *wb;
842 uint64_t gpu_addr;
843 bool enabled;
844 bool use_event;
845 };
846
847 #define RADEON_WB_SCRATCH_OFFSET 0
848 #define RADEON_WB_CP_RPTR_OFFSET 1024
849 #define RADEON_WB_CP1_RPTR_OFFSET 1280
850 #define RADEON_WB_CP2_RPTR_OFFSET 1536
851 #define R600_WB_IH_WPTR_OFFSET 2048
852 #define R600_WB_EVENT_OFFSET 3072
853
854 /**
855 * struct radeon_pm - power management datas
856 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
857 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
858 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
859 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
860 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
861 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
862 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
863 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
864 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
865 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
866 * @needed_bandwidth: current bandwidth needs
867 *
868 * It keeps track of various data needed to take powermanagement decision.
869 * Bandwidth need is used to determine minimun clock of the GPU and memory.
870 * Equation between gpu/memory clock and available bandwidth is hw dependent
871 * (type of memory, bus size, efficiency, ...)
872 */
873
874 enum radeon_pm_method {
875 PM_METHOD_PROFILE,
876 PM_METHOD_DYNPM,
877 };
878
879 enum radeon_dynpm_state {
880 DYNPM_STATE_DISABLED,
881 DYNPM_STATE_MINIMUM,
882 DYNPM_STATE_PAUSED,
883 DYNPM_STATE_ACTIVE,
884 DYNPM_STATE_SUSPENDED,
885 };
886 enum radeon_dynpm_action {
887 DYNPM_ACTION_NONE,
888 DYNPM_ACTION_MINIMUM,
889 DYNPM_ACTION_DOWNCLOCK,
890 DYNPM_ACTION_UPCLOCK,
891 DYNPM_ACTION_DEFAULT
892 };
893
894 enum radeon_voltage_type {
895 VOLTAGE_NONE = 0,
896 VOLTAGE_GPIO,
897 VOLTAGE_VDDC,
898 VOLTAGE_SW
899 };
900
901 enum radeon_pm_state_type {
902 POWER_STATE_TYPE_DEFAULT,
903 POWER_STATE_TYPE_POWERSAVE,
904 POWER_STATE_TYPE_BATTERY,
905 POWER_STATE_TYPE_BALANCED,
906 POWER_STATE_TYPE_PERFORMANCE,
907 };
908
909 enum radeon_pm_profile_type {
910 PM_PROFILE_DEFAULT,
911 PM_PROFILE_AUTO,
912 PM_PROFILE_LOW,
913 PM_PROFILE_MID,
914 PM_PROFILE_HIGH,
915 };
916
917 #define PM_PROFILE_DEFAULT_IDX 0
918 #define PM_PROFILE_LOW_SH_IDX 1
919 #define PM_PROFILE_MID_SH_IDX 2
920 #define PM_PROFILE_HIGH_SH_IDX 3
921 #define PM_PROFILE_LOW_MH_IDX 4
922 #define PM_PROFILE_MID_MH_IDX 5
923 #define PM_PROFILE_HIGH_MH_IDX 6
924 #define PM_PROFILE_MAX 7
925
926 struct radeon_pm_profile {
927 int dpms_off_ps_idx;
928 int dpms_on_ps_idx;
929 int dpms_off_cm_idx;
930 int dpms_on_cm_idx;
931 };
932
933 enum radeon_int_thermal_type {
934 THERMAL_TYPE_NONE,
935 THERMAL_TYPE_RV6XX,
936 THERMAL_TYPE_RV770,
937 THERMAL_TYPE_EVERGREEN,
938 THERMAL_TYPE_SUMO,
939 THERMAL_TYPE_NI,
940 };
941
942 struct radeon_voltage {
943 enum radeon_voltage_type type;
944 /* gpio voltage */
945 struct radeon_gpio_rec gpio;
946 u32 delay; /* delay in usec from voltage drop to sclk change */
947 bool active_high; /* voltage drop is active when bit is high */
948 /* VDDC voltage */
949 u8 vddc_id; /* index into vddc voltage table */
950 u8 vddci_id; /* index into vddci voltage table */
951 bool vddci_enabled;
952 /* r6xx+ sw */
953 u16 voltage;
954 /* evergreen+ vddci */
955 u16 vddci;
956 };
957
958 /* clock mode flags */
959 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
960
961 struct radeon_pm_clock_info {
962 /* memory clock */
963 u32 mclk;
964 /* engine clock */
965 u32 sclk;
966 /* voltage info */
967 struct radeon_voltage voltage;
968 /* standardized clock flags */
969 u32 flags;
970 };
971
972 /* state flags */
973 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
974
975 struct radeon_power_state {
976 enum radeon_pm_state_type type;
977 struct radeon_pm_clock_info *clock_info;
978 /* number of valid clock modes in this power state */
979 int num_clock_modes;
980 struct radeon_pm_clock_info *default_clock_mode;
981 /* standardized state flags */
982 u32 flags;
983 u32 misc; /* vbios specific flags */
984 u32 misc2; /* vbios specific flags */
985 int pcie_lanes; /* pcie lanes */
986 };
987
988 /*
989 * Some modes are overclocked by very low value, accept them
990 */
991 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
992
993 struct radeon_pm {
994 struct mutex mutex;
995 u32 active_crtcs;
996 int active_crtc_count;
997 int req_vblank;
998 bool vblank_sync;
999 bool gui_idle;
1000 fixed20_12 max_bandwidth;
1001 fixed20_12 igp_sideport_mclk;
1002 fixed20_12 igp_system_mclk;
1003 fixed20_12 igp_ht_link_clk;
1004 fixed20_12 igp_ht_link_width;
1005 fixed20_12 k8_bandwidth;
1006 fixed20_12 sideport_bandwidth;
1007 fixed20_12 ht_bandwidth;
1008 fixed20_12 core_bandwidth;
1009 fixed20_12 sclk;
1010 fixed20_12 mclk;
1011 fixed20_12 needed_bandwidth;
1012 struct radeon_power_state *power_state;
1013 /* number of valid power states */
1014 int num_power_states;
1015 int current_power_state_index;
1016 int current_clock_mode_index;
1017 int requested_power_state_index;
1018 int requested_clock_mode_index;
1019 int default_power_state_index;
1020 u32 current_sclk;
1021 u32 current_mclk;
1022 u16 current_vddc;
1023 u16 current_vddci;
1024 u32 default_sclk;
1025 u32 default_mclk;
1026 u16 default_vddc;
1027 u16 default_vddci;
1028 struct radeon_i2c_chan *i2c_bus;
1029 /* selected pm method */
1030 enum radeon_pm_method pm_method;
1031 /* dynpm power management */
1032 struct delayed_work dynpm_idle_work;
1033 enum radeon_dynpm_state dynpm_state;
1034 enum radeon_dynpm_action dynpm_planned_action;
1035 unsigned long dynpm_action_timeout;
1036 bool dynpm_can_upclock;
1037 bool dynpm_can_downclock;
1038 /* profile-based power management */
1039 enum radeon_pm_profile_type profile;
1040 int profile_index;
1041 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1042 /* internal thermal controller on rv6xx+ */
1043 enum radeon_int_thermal_type int_thermal_type;
1044 struct device *int_hwmon_dev;
1045 };
1046
1047 int radeon_pm_get_type_index(struct radeon_device *rdev,
1048 enum radeon_pm_state_type ps_type,
1049 int instance);
1050
1051 /*
1052 * Benchmarking
1053 */
1054 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1055
1056
1057 /*
1058 * Testing
1059 */
1060 void radeon_test_moves(struct radeon_device *rdev);
1061 void radeon_test_ring_sync(struct radeon_device *rdev,
1062 struct radeon_ring *cpA,
1063 struct radeon_ring *cpB);
1064 void radeon_test_syncing(struct radeon_device *rdev);
1065
1066
1067 /*
1068 * Debugfs
1069 */
1070 struct radeon_debugfs {
1071 struct drm_info_list *files;
1072 unsigned num_files;
1073 };
1074
1075 int radeon_debugfs_add_files(struct radeon_device *rdev,
1076 struct drm_info_list *files,
1077 unsigned nfiles);
1078 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1079
1080
1081 /*
1082 * ASIC specific functions.
1083 */
1084 struct radeon_asic {
1085 int (*init)(struct radeon_device *rdev);
1086 void (*fini)(struct radeon_device *rdev);
1087 int (*resume)(struct radeon_device *rdev);
1088 int (*suspend)(struct radeon_device *rdev);
1089 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1090 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1091 int (*asic_reset)(struct radeon_device *rdev);
1092 void (*gart_tlb_flush)(struct radeon_device *rdev);
1093 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1094 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
1095 void (*cp_fini)(struct radeon_device *rdev);
1096 void (*cp_disable)(struct radeon_device *rdev);
1097 void (*ring_start)(struct radeon_device *rdev);
1098
1099 struct {
1100 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1101 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1102 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1103 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1104 struct radeon_semaphore *semaphore, bool emit_wait);
1105 } ring[RADEON_NUM_RINGS];
1106
1107 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1108 int (*irq_set)(struct radeon_device *rdev);
1109 int (*irq_process)(struct radeon_device *rdev);
1110 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1111 int (*cs_parse)(struct radeon_cs_parser *p);
1112 int (*copy_blit)(struct radeon_device *rdev,
1113 uint64_t src_offset,
1114 uint64_t dst_offset,
1115 unsigned num_gpu_pages,
1116 struct radeon_fence *fence);
1117 int (*copy_dma)(struct radeon_device *rdev,
1118 uint64_t src_offset,
1119 uint64_t dst_offset,
1120 unsigned num_gpu_pages,
1121 struct radeon_fence *fence);
1122 int (*copy)(struct radeon_device *rdev,
1123 uint64_t src_offset,
1124 uint64_t dst_offset,
1125 unsigned num_gpu_pages,
1126 struct radeon_fence *fence);
1127 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1128 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1129 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1130 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1131 int (*get_pcie_lanes)(struct radeon_device *rdev);
1132 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1133 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1134 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
1135 uint32_t tiling_flags, uint32_t pitch,
1136 uint32_t offset, uint32_t obj_size);
1137 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
1138 void (*bandwidth_update)(struct radeon_device *rdev);
1139 void (*hpd_init)(struct radeon_device *rdev);
1140 void (*hpd_fini)(struct radeon_device *rdev);
1141 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1142 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1143 /* ioctl hw specific callback. Some hw might want to perform special
1144 * operation on specific ioctl. For instance on wait idle some hw
1145 * might want to perform and HDP flush through MMIO as it seems that
1146 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1147 * through ring.
1148 */
1149 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1150 bool (*gui_idle)(struct radeon_device *rdev);
1151 /* power management */
1152 void (*pm_misc)(struct radeon_device *rdev);
1153 void (*pm_prepare)(struct radeon_device *rdev);
1154 void (*pm_finish)(struct radeon_device *rdev);
1155 void (*pm_init_profile)(struct radeon_device *rdev);
1156 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
1157 /* pageflipping */
1158 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1159 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1160 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1161 };
1162
1163 /*
1164 * Asic structures
1165 */
1166 struct r100_gpu_lockup {
1167 unsigned long last_jiffies;
1168 u32 last_cp_rptr;
1169 };
1170
1171 struct r100_asic {
1172 const unsigned *reg_safe_bm;
1173 unsigned reg_safe_bm_size;
1174 u32 hdp_cntl;
1175 struct r100_gpu_lockup lockup;
1176 };
1177
1178 struct r300_asic {
1179 const unsigned *reg_safe_bm;
1180 unsigned reg_safe_bm_size;
1181 u32 resync_scratch;
1182 u32 hdp_cntl;
1183 struct r100_gpu_lockup lockup;
1184 };
1185
1186 struct r600_asic {
1187 unsigned max_pipes;
1188 unsigned max_tile_pipes;
1189 unsigned max_simds;
1190 unsigned max_backends;
1191 unsigned max_gprs;
1192 unsigned max_threads;
1193 unsigned max_stack_entries;
1194 unsigned max_hw_contexts;
1195 unsigned max_gs_threads;
1196 unsigned sx_max_export_size;
1197 unsigned sx_max_export_pos_size;
1198 unsigned sx_max_export_smx_size;
1199 unsigned sq_num_cf_insts;
1200 unsigned tiling_nbanks;
1201 unsigned tiling_npipes;
1202 unsigned tiling_group_size;
1203 unsigned tile_config;
1204 unsigned backend_map;
1205 struct r100_gpu_lockup lockup;
1206 };
1207
1208 struct rv770_asic {
1209 unsigned max_pipes;
1210 unsigned max_tile_pipes;
1211 unsigned max_simds;
1212 unsigned max_backends;
1213 unsigned max_gprs;
1214 unsigned max_threads;
1215 unsigned max_stack_entries;
1216 unsigned max_hw_contexts;
1217 unsigned max_gs_threads;
1218 unsigned sx_max_export_size;
1219 unsigned sx_max_export_pos_size;
1220 unsigned sx_max_export_smx_size;
1221 unsigned sq_num_cf_insts;
1222 unsigned sx_num_of_sets;
1223 unsigned sc_prim_fifo_size;
1224 unsigned sc_hiz_tile_fifo_size;
1225 unsigned sc_earlyz_tile_fifo_fize;
1226 unsigned tiling_nbanks;
1227 unsigned tiling_npipes;
1228 unsigned tiling_group_size;
1229 unsigned tile_config;
1230 unsigned backend_map;
1231 struct r100_gpu_lockup lockup;
1232 };
1233
1234 struct evergreen_asic {
1235 unsigned num_ses;
1236 unsigned max_pipes;
1237 unsigned max_tile_pipes;
1238 unsigned max_simds;
1239 unsigned max_backends;
1240 unsigned max_gprs;
1241 unsigned max_threads;
1242 unsigned max_stack_entries;
1243 unsigned max_hw_contexts;
1244 unsigned max_gs_threads;
1245 unsigned sx_max_export_size;
1246 unsigned sx_max_export_pos_size;
1247 unsigned sx_max_export_smx_size;
1248 unsigned sq_num_cf_insts;
1249 unsigned sx_num_of_sets;
1250 unsigned sc_prim_fifo_size;
1251 unsigned sc_hiz_tile_fifo_size;
1252 unsigned sc_earlyz_tile_fifo_size;
1253 unsigned tiling_nbanks;
1254 unsigned tiling_npipes;
1255 unsigned tiling_group_size;
1256 unsigned tile_config;
1257 unsigned backend_map;
1258 struct r100_gpu_lockup lockup;
1259 };
1260
1261 struct cayman_asic {
1262 unsigned max_shader_engines;
1263 unsigned max_pipes_per_simd;
1264 unsigned max_tile_pipes;
1265 unsigned max_simds_per_se;
1266 unsigned max_backends_per_se;
1267 unsigned max_texture_channel_caches;
1268 unsigned max_gprs;
1269 unsigned max_threads;
1270 unsigned max_gs_threads;
1271 unsigned max_stack_entries;
1272 unsigned sx_num_of_sets;
1273 unsigned sx_max_export_size;
1274 unsigned sx_max_export_pos_size;
1275 unsigned sx_max_export_smx_size;
1276 unsigned max_hw_contexts;
1277 unsigned sq_num_cf_insts;
1278 unsigned sc_prim_fifo_size;
1279 unsigned sc_hiz_tile_fifo_size;
1280 unsigned sc_earlyz_tile_fifo_size;
1281
1282 unsigned num_shader_engines;
1283 unsigned num_shader_pipes_per_simd;
1284 unsigned num_tile_pipes;
1285 unsigned num_simds_per_se;
1286 unsigned num_backends_per_se;
1287 unsigned backend_disable_mask_per_asic;
1288 unsigned backend_map;
1289 unsigned num_texture_channel_caches;
1290 unsigned mem_max_burst_length_bytes;
1291 unsigned mem_row_size_in_kb;
1292 unsigned shader_engine_tile_size;
1293 unsigned num_gpus;
1294 unsigned multi_gpu_tile_size;
1295
1296 unsigned tile_config;
1297 struct r100_gpu_lockup lockup;
1298 };
1299
1300 union radeon_asic_config {
1301 struct r300_asic r300;
1302 struct r100_asic r100;
1303 struct r600_asic r600;
1304 struct rv770_asic rv770;
1305 struct evergreen_asic evergreen;
1306 struct cayman_asic cayman;
1307 };
1308
1309 /*
1310 * asic initizalization from radeon_asic.c
1311 */
1312 void radeon_agp_disable(struct radeon_device *rdev);
1313 int radeon_asic_init(struct radeon_device *rdev);
1314
1315
1316 /*
1317 * IOCTL.
1318 */
1319 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1320 struct drm_file *filp);
1321 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1322 struct drm_file *filp);
1323 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1324 struct drm_file *file_priv);
1325 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1326 struct drm_file *file_priv);
1327 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1328 struct drm_file *file_priv);
1329 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1330 struct drm_file *file_priv);
1331 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1332 struct drm_file *filp);
1333 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1334 struct drm_file *filp);
1335 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1336 struct drm_file *filp);
1337 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1338 struct drm_file *filp);
1339 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1340 struct drm_file *filp);
1341 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1342 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1343 struct drm_file *filp);
1344 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1345 struct drm_file *filp);
1346
1347 /* VRAM scratch page for HDP bug, default vram page */
1348 struct r600_vram_scratch {
1349 struct radeon_bo *robj;
1350 volatile uint32_t *ptr;
1351 u64 gpu_addr;
1352 };
1353
1354
1355 /*
1356 * Mutex which allows recursive locking from the same process.
1357 */
1358 struct radeon_mutex {
1359 struct mutex mutex;
1360 struct task_struct *owner;
1361 int level;
1362 };
1363
1364 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
1365 {
1366 mutex_init(&mutex->mutex);
1367 mutex->owner = NULL;
1368 mutex->level = 0;
1369 }
1370
1371 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
1372 {
1373 if (mutex_trylock(&mutex->mutex)) {
1374 /* The mutex was unlocked before, so it's ours now */
1375 mutex->owner = current;
1376 } else if (mutex->owner != current) {
1377 /* Another process locked the mutex, take it */
1378 mutex_lock(&mutex->mutex);
1379 mutex->owner = current;
1380 }
1381 /* Otherwise the mutex was already locked by this process */
1382
1383 mutex->level++;
1384 }
1385
1386 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
1387 {
1388 if (--mutex->level > 0)
1389 return;
1390
1391 mutex->owner = NULL;
1392 mutex_unlock(&mutex->mutex);
1393 }
1394
1395
1396 /*
1397 * Core structure, functions and helpers.
1398 */
1399 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1400 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1401
1402 struct radeon_device {
1403 struct device *dev;
1404 struct drm_device *ddev;
1405 struct pci_dev *pdev;
1406 /* ASIC */
1407 union radeon_asic_config config;
1408 enum radeon_family family;
1409 unsigned long flags;
1410 int usec_timeout;
1411 enum radeon_pll_errata pll_errata;
1412 int num_gb_pipes;
1413 int num_z_pipes;
1414 int disp_priority;
1415 /* BIOS */
1416 uint8_t *bios;
1417 bool is_atom_bios;
1418 uint16_t bios_header_start;
1419 struct radeon_bo *stollen_vga_memory;
1420 /* Register mmio */
1421 resource_size_t rmmio_base;
1422 resource_size_t rmmio_size;
1423 void __iomem *rmmio;
1424 radeon_rreg_t mc_rreg;
1425 radeon_wreg_t mc_wreg;
1426 radeon_rreg_t pll_rreg;
1427 radeon_wreg_t pll_wreg;
1428 uint32_t pcie_reg_mask;
1429 radeon_rreg_t pciep_rreg;
1430 radeon_wreg_t pciep_wreg;
1431 /* io port */
1432 void __iomem *rio_mem;
1433 resource_size_t rio_mem_size;
1434 struct radeon_clock clock;
1435 struct radeon_mc mc;
1436 struct radeon_gart gart;
1437 struct radeon_mode_info mode_info;
1438 struct radeon_scratch scratch;
1439 struct radeon_mman mman;
1440 rwlock_t fence_lock;
1441 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1442 struct radeon_semaphore_driver semaphore_drv;
1443 struct radeon_ring ring[RADEON_NUM_RINGS];
1444 struct radeon_ib_pool ib_pool;
1445 struct radeon_irq irq;
1446 struct radeon_asic *asic;
1447 struct radeon_gem gem;
1448 struct radeon_pm pm;
1449 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1450 struct radeon_mutex cs_mutex;
1451 struct radeon_wb wb;
1452 struct radeon_dummy_page dummy_page;
1453 bool gpu_lockup;
1454 bool shutdown;
1455 bool suspend;
1456 bool need_dma32;
1457 bool accel_working;
1458 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1459 const struct firmware *me_fw; /* all family ME firmware */
1460 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1461 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1462 const struct firmware *mc_fw; /* NI MC firmware */
1463 struct r600_blit r600_blit;
1464 struct r600_vram_scratch vram_scratch;
1465 int msi_enabled; /* msi enabled */
1466 struct r600_ih ih; /* r6/700 interrupt ring */
1467 struct work_struct hotplug_work;
1468 int num_crtc; /* number of crtcs */
1469 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1470 struct mutex vram_mutex;
1471
1472 /* audio stuff */
1473 bool audio_enabled;
1474 struct timer_list audio_timer;
1475 int audio_channels;
1476 int audio_rate;
1477 int audio_bits_per_sample;
1478 uint8_t audio_status_bits;
1479 uint8_t audio_category_code;
1480
1481 struct notifier_block acpi_nb;
1482 /* only one userspace can use Hyperz features or CMASK at a time */
1483 struct drm_file *hyperz_filp;
1484 struct drm_file *cmask_filp;
1485 /* i2c buses */
1486 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1487 /* debugfs */
1488 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1489 unsigned debugfs_count;
1490 /* virtual memory */
1491 struct radeon_vm_manager vm_manager;
1492 /* ring used for bo copies */
1493 u32 copy_ring;
1494 };
1495
1496 int radeon_device_init(struct radeon_device *rdev,
1497 struct drm_device *ddev,
1498 struct pci_dev *pdev,
1499 uint32_t flags);
1500 void radeon_device_fini(struct radeon_device *rdev);
1501 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1502
1503 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1504 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1505 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1506 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1507
1508 /*
1509 * Cast helper
1510 */
1511 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1512
1513 /*
1514 * Registers read & write functions.
1515 */
1516 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1517 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1518 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1519 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1520 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1521 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1522 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1523 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1524 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1525 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1526 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1527 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1528 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1529 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1530 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1531 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1532 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1533 #define WREG32_P(reg, val, mask) \
1534 do { \
1535 uint32_t tmp_ = RREG32(reg); \
1536 tmp_ &= (mask); \
1537 tmp_ |= ((val) & ~(mask)); \
1538 WREG32(reg, tmp_); \
1539 } while (0)
1540 #define WREG32_PLL_P(reg, val, mask) \
1541 do { \
1542 uint32_t tmp_ = RREG32_PLL(reg); \
1543 tmp_ &= (mask); \
1544 tmp_ |= ((val) & ~(mask)); \
1545 WREG32_PLL(reg, tmp_); \
1546 } while (0)
1547 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1548 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1549 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1550
1551 /*
1552 * Indirect registers accessor
1553 */
1554 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1555 {
1556 uint32_t r;
1557
1558 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1559 r = RREG32(RADEON_PCIE_DATA);
1560 return r;
1561 }
1562
1563 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1564 {
1565 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1566 WREG32(RADEON_PCIE_DATA, (v));
1567 }
1568
1569 void r100_pll_errata_after_index(struct radeon_device *rdev);
1570
1571
1572 /*
1573 * ASICs helpers.
1574 */
1575 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1576 (rdev->pdev->device == 0x5969))
1577 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1578 (rdev->family == CHIP_RV200) || \
1579 (rdev->family == CHIP_RS100) || \
1580 (rdev->family == CHIP_RS200) || \
1581 (rdev->family == CHIP_RV250) || \
1582 (rdev->family == CHIP_RV280) || \
1583 (rdev->family == CHIP_RS300))
1584 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1585 (rdev->family == CHIP_RV350) || \
1586 (rdev->family == CHIP_R350) || \
1587 (rdev->family == CHIP_RV380) || \
1588 (rdev->family == CHIP_R420) || \
1589 (rdev->family == CHIP_R423) || \
1590 (rdev->family == CHIP_RV410) || \
1591 (rdev->family == CHIP_RS400) || \
1592 (rdev->family == CHIP_RS480))
1593 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1594 (rdev->ddev->pdev->device == 0x9443) || \
1595 (rdev->ddev->pdev->device == 0x944B) || \
1596 (rdev->ddev->pdev->device == 0x9506) || \
1597 (rdev->ddev->pdev->device == 0x9509) || \
1598 (rdev->ddev->pdev->device == 0x950F) || \
1599 (rdev->ddev->pdev->device == 0x689C) || \
1600 (rdev->ddev->pdev->device == 0x689D))
1601 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1602 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1603 (rdev->family == CHIP_RS690) || \
1604 (rdev->family == CHIP_RS740) || \
1605 (rdev->family >= CHIP_R600))
1606 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1607 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1608 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1609 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1610 (rdev->flags & RADEON_IS_IGP))
1611 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1612
1613 /*
1614 * BIOS helpers.
1615 */
1616 #define RBIOS8(i) (rdev->bios[i])
1617 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1618 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1619
1620 int radeon_combios_init(struct radeon_device *rdev);
1621 void radeon_combios_fini(struct radeon_device *rdev);
1622 int radeon_atombios_init(struct radeon_device *rdev);
1623 void radeon_atombios_fini(struct radeon_device *rdev);
1624
1625
1626 /*
1627 * RING helpers.
1628 */
1629 #if DRM_DEBUG_CODE == 0
1630 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1631 {
1632 ring->ring[ring->wptr++] = v;
1633 ring->wptr &= ring->ptr_mask;
1634 ring->count_dw--;
1635 ring->ring_free_dw--;
1636 }
1637 #else
1638 /* With debugging this is just too big to inline */
1639 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1640 #endif
1641
1642 /*
1643 * ASICs macro.
1644 */
1645 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1646 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1647 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1648 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1649 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1650 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1651 #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
1652 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1653 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1654 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1655 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1656 #define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
1657 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1658 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1659 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1660 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1661 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1662 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1663 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1664 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1665 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1666 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1667 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1668 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1669 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1670 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1671 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1672 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1673 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1674 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1675 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1676 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1677 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1678 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1679 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1680 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1681 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1682 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1683 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1684 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1685 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1686 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1687 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1688 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1689 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1690
1691 /* Common functions */
1692 /* AGP */
1693 extern int radeon_gpu_reset(struct radeon_device *rdev);
1694 extern void radeon_agp_disable(struct radeon_device *rdev);
1695 extern int radeon_modeset_init(struct radeon_device *rdev);
1696 extern void radeon_modeset_fini(struct radeon_device *rdev);
1697 extern bool radeon_card_posted(struct radeon_device *rdev);
1698 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1699 extern void radeon_update_display_priority(struct radeon_device *rdev);
1700 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1701 extern void radeon_scratch_init(struct radeon_device *rdev);
1702 extern void radeon_wb_fini(struct radeon_device *rdev);
1703 extern int radeon_wb_init(struct radeon_device *rdev);
1704 extern void radeon_wb_disable(struct radeon_device *rdev);
1705 extern void radeon_surface_init(struct radeon_device *rdev);
1706 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1707 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1708 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1709 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1710 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1711 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1712 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1713 extern int radeon_resume_kms(struct drm_device *dev);
1714 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1715 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1716
1717 /*
1718 * vm
1719 */
1720 int radeon_vm_manager_init(struct radeon_device *rdev);
1721 void radeon_vm_manager_fini(struct radeon_device *rdev);
1722 int radeon_vm_manager_start(struct radeon_device *rdev);
1723 int radeon_vm_manager_suspend(struct radeon_device *rdev);
1724 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1725 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1726 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1727 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1728 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1729 struct radeon_vm *vm,
1730 struct radeon_bo *bo,
1731 struct ttm_mem_reg *mem);
1732 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1733 struct radeon_bo *bo);
1734 int radeon_vm_bo_add(struct radeon_device *rdev,
1735 struct radeon_vm *vm,
1736 struct radeon_bo *bo,
1737 uint64_t offset,
1738 uint32_t flags);
1739 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1740 struct radeon_vm *vm,
1741 struct radeon_bo *bo);
1742
1743
1744 /*
1745 * R600 vram scratch functions
1746 */
1747 int r600_vram_scratch_init(struct radeon_device *rdev);
1748 void r600_vram_scratch_fini(struct radeon_device *rdev);
1749
1750 /*
1751 * r600 functions used by radeon_encoder.c
1752 */
1753 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1754 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1755 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1756
1757 extern int ni_init_microcode(struct radeon_device *rdev);
1758 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1759
1760 /* radeon_acpi.c */
1761 #if defined(CONFIG_ACPI)
1762 extern int radeon_acpi_init(struct radeon_device *rdev);
1763 #else
1764 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1765 #endif
1766
1767 #include "radeon_object.h"
1768
1769 #endif
Linux kernel - Deliverables
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