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[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/fence.h>
70
71 #include <ttm/ttm_bo_api.h>
72 #include <ttm/ttm_bo_driver.h>
73 #include <ttm/ttm_placement.h>
74 #include <ttm/ttm_module.h>
75 #include <ttm/ttm_execbuf_util.h>
76
77 #include <drm/drm_gem.h>
78
79 #include "radeon_family.h"
80 #include "radeon_mode.h"
81 #include "radeon_reg.h"
82
83 /*
84 * Modules parameters.
85 */
86 extern int radeon_no_wb;
87 extern int radeon_modeset;
88 extern int radeon_dynclks;
89 extern int radeon_r4xx_atom;
90 extern int radeon_agpmode;
91 extern int radeon_vram_limit;
92 extern int radeon_gart_size;
93 extern int radeon_benchmarking;
94 extern int radeon_testing;
95 extern int radeon_connector_table;
96 extern int radeon_tv;
97 extern int radeon_audio;
98 extern int radeon_disp_priority;
99 extern int radeon_hw_i2c;
100 extern int radeon_pcie_gen2;
101 extern int radeon_msi;
102 extern int radeon_lockup_timeout;
103 extern int radeon_fastfb;
104 extern int radeon_dpm;
105 extern int radeon_aspm;
106 extern int radeon_runtime_pm;
107 extern int radeon_hard_reset;
108 extern int radeon_vm_size;
109 extern int radeon_vm_block_size;
110 extern int radeon_deep_color;
111 extern int radeon_use_pflipirq;
112 extern int radeon_bapm;
113 extern int radeon_backlight;
114 extern int radeon_auxch;
115 extern int radeon_mst;
116
117 /*
118 * Copy from radeon_drv.h so we don't have to include both and have conflicting
119 * symbol;
120 */
121 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
122 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
123 /* RADEON_IB_POOL_SIZE must be a power of 2 */
124 #define RADEON_IB_POOL_SIZE 16
125 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
126 #define RADEONFB_CONN_LIMIT 4
127 #define RADEON_BIOS_NUM_SCRATCH 8
128
129 /* internal ring indices */
130 /* r1xx+ has gfx CP ring */
131 #define RADEON_RING_TYPE_GFX_INDEX 0
132
133 /* cayman has 2 compute CP rings */
134 #define CAYMAN_RING_TYPE_CP1_INDEX 1
135 #define CAYMAN_RING_TYPE_CP2_INDEX 2
136
137 /* R600+ has an async dma ring */
138 #define R600_RING_TYPE_DMA_INDEX 3
139 /* cayman add a second async dma ring */
140 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
141
142 /* R600+ */
143 #define R600_RING_TYPE_UVD_INDEX 5
144
145 /* TN+ */
146 #define TN_RING_TYPE_VCE1_INDEX 6
147 #define TN_RING_TYPE_VCE2_INDEX 7
148
149 /* max number of rings */
150 #define RADEON_NUM_RINGS 8
151
152 /* number of hw syncs before falling back on blocking */
153 #define RADEON_NUM_SYNCS 4
154
155 /* hardcode those limit for now */
156 #define RADEON_VA_IB_OFFSET (1 << 20)
157 #define RADEON_VA_RESERVED_SIZE (8 << 20)
158 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
159
160 /* hard reset data */
161 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
162
163 /* reset flags */
164 #define RADEON_RESET_GFX (1 << 0)
165 #define RADEON_RESET_COMPUTE (1 << 1)
166 #define RADEON_RESET_DMA (1 << 2)
167 #define RADEON_RESET_CP (1 << 3)
168 #define RADEON_RESET_GRBM (1 << 4)
169 #define RADEON_RESET_DMA1 (1 << 5)
170 #define RADEON_RESET_RLC (1 << 6)
171 #define RADEON_RESET_SEM (1 << 7)
172 #define RADEON_RESET_IH (1 << 8)
173 #define RADEON_RESET_VMC (1 << 9)
174 #define RADEON_RESET_MC (1 << 10)
175 #define RADEON_RESET_DISPLAY (1 << 11)
176
177 /* CG block flags */
178 #define RADEON_CG_BLOCK_GFX (1 << 0)
179 #define RADEON_CG_BLOCK_MC (1 << 1)
180 #define RADEON_CG_BLOCK_SDMA (1 << 2)
181 #define RADEON_CG_BLOCK_UVD (1 << 3)
182 #define RADEON_CG_BLOCK_VCE (1 << 4)
183 #define RADEON_CG_BLOCK_HDP (1 << 5)
184 #define RADEON_CG_BLOCK_BIF (1 << 6)
185
186 /* CG flags */
187 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
188 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
189 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
190 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
191 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
192 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
193 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
194 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
195 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
196 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
197 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
198 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
199 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
200 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
201 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
202 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
203 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
204
205 /* PG flags */
206 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
207 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
208 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
209 #define RADEON_PG_SUPPORT_UVD (1 << 3)
210 #define RADEON_PG_SUPPORT_VCE (1 << 4)
211 #define RADEON_PG_SUPPORT_CP (1 << 5)
212 #define RADEON_PG_SUPPORT_GDS (1 << 6)
213 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
214 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
215 #define RADEON_PG_SUPPORT_ACP (1 << 9)
216 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
217
218 /* max cursor sizes (in pixels) */
219 #define CURSOR_WIDTH 64
220 #define CURSOR_HEIGHT 64
221
222 #define CIK_CURSOR_WIDTH 128
223 #define CIK_CURSOR_HEIGHT 128
224
225 /*
226 * Errata workarounds.
227 */
228 enum radeon_pll_errata {
229 CHIP_ERRATA_R300_CG = 0x00000001,
230 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
231 CHIP_ERRATA_PLL_DELAY = 0x00000004
232 };
233
234
235 struct radeon_device;
236
237
238 /*
239 * BIOS.
240 */
241 bool radeon_get_bios(struct radeon_device *rdev);
242
243 /*
244 * Dummy page
245 */
246 struct radeon_dummy_page {
247 uint64_t entry;
248 struct page *page;
249 dma_addr_t addr;
250 };
251 int radeon_dummy_page_init(struct radeon_device *rdev);
252 void radeon_dummy_page_fini(struct radeon_device *rdev);
253
254
255 /*
256 * Clocks
257 */
258 struct radeon_clock {
259 struct radeon_pll p1pll;
260 struct radeon_pll p2pll;
261 struct radeon_pll dcpll;
262 struct radeon_pll spll;
263 struct radeon_pll mpll;
264 /* 10 Khz units */
265 uint32_t default_mclk;
266 uint32_t default_sclk;
267 uint32_t default_dispclk;
268 uint32_t current_dispclk;
269 uint32_t dp_extclk;
270 uint32_t max_pixel_clock;
271 };
272
273 /*
274 * Power management
275 */
276 int radeon_pm_init(struct radeon_device *rdev);
277 int radeon_pm_late_init(struct radeon_device *rdev);
278 void radeon_pm_fini(struct radeon_device *rdev);
279 void radeon_pm_compute_clocks(struct radeon_device *rdev);
280 void radeon_pm_suspend(struct radeon_device *rdev);
281 void radeon_pm_resume(struct radeon_device *rdev);
282 void radeon_combios_get_power_modes(struct radeon_device *rdev);
283 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
284 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
285 u8 clock_type,
286 u32 clock,
287 bool strobe_mode,
288 struct atom_clock_dividers *dividers);
289 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
290 u32 clock,
291 bool strobe_mode,
292 struct atom_mpll_param *mpll_param);
293 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
294 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
295 u16 voltage_level, u8 voltage_type,
296 u32 *gpio_value, u32 *gpio_mask);
297 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
298 u32 eng_clock, u32 mem_clock);
299 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
300 u8 voltage_type, u16 *voltage_step);
301 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
302 u16 voltage_id, u16 *voltage);
303 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
304 u16 *voltage,
305 u16 leakage_idx);
306 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
307 u16 *leakage_id);
308 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
309 u16 *vddc, u16 *vddci,
310 u16 virtual_voltage_id,
311 u16 vbios_voltage_id);
312 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
313 u16 virtual_voltage_id,
314 u16 *voltage);
315 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
316 u8 voltage_type,
317 u16 nominal_voltage,
318 u16 *true_voltage);
319 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
320 u8 voltage_type, u16 *min_voltage);
321 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
322 u8 voltage_type, u16 *max_voltage);
323 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
324 u8 voltage_type, u8 voltage_mode,
325 struct atom_voltage_table *voltage_table);
326 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
327 u8 voltage_type, u8 voltage_mode);
328 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
329 u8 voltage_type,
330 u8 *svd_gpio_id, u8 *svc_gpio_id);
331 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
332 u32 mem_clock);
333 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
334 u32 mem_clock);
335 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
336 u8 module_index,
337 struct atom_mc_reg_table *reg_table);
338 int radeon_atom_get_memory_info(struct radeon_device *rdev,
339 u8 module_index, struct atom_memory_info *mem_info);
340 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
341 bool gddr5, u8 module_index,
342 struct atom_memory_clock_range_table *mclk_range_table);
343 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
344 u16 voltage_id, u16 *voltage);
345 void rs690_pm_info(struct radeon_device *rdev);
346 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
347 unsigned *bankh, unsigned *mtaspect,
348 unsigned *tile_split);
349
350 /*
351 * Fences.
352 */
353 struct radeon_fence_driver {
354 struct radeon_device *rdev;
355 uint32_t scratch_reg;
356 uint64_t gpu_addr;
357 volatile uint32_t *cpu_addr;
358 /* sync_seq is protected by ring emission lock */
359 uint64_t sync_seq[RADEON_NUM_RINGS];
360 atomic64_t last_seq;
361 bool initialized, delayed_irq;
362 struct delayed_work lockup_work;
363 };
364
365 struct radeon_fence {
366 struct fence base;
367
368 struct radeon_device *rdev;
369 uint64_t seq;
370 /* RB, DMA, etc. */
371 unsigned ring;
372 bool is_vm_update;
373
374 wait_queue_t fence_wake;
375 };
376
377 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
378 int radeon_fence_driver_init(struct radeon_device *rdev);
379 void radeon_fence_driver_fini(struct radeon_device *rdev);
380 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
381 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
382 void radeon_fence_process(struct radeon_device *rdev, int ring);
383 bool radeon_fence_signaled(struct radeon_fence *fence);
384 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
385 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
386 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
387 int radeon_fence_wait_any(struct radeon_device *rdev,
388 struct radeon_fence **fences,
389 bool intr);
390 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
391 void radeon_fence_unref(struct radeon_fence **fence);
392 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
393 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
394 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
395 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
396 struct radeon_fence *b)
397 {
398 if (!a) {
399 return b;
400 }
401
402 if (!b) {
403 return a;
404 }
405
406 BUG_ON(a->ring != b->ring);
407
408 if (a->seq > b->seq) {
409 return a;
410 } else {
411 return b;
412 }
413 }
414
415 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
416 struct radeon_fence *b)
417 {
418 if (!a) {
419 return false;
420 }
421
422 if (!b) {
423 return true;
424 }
425
426 BUG_ON(a->ring != b->ring);
427
428 return a->seq < b->seq;
429 }
430
431 /*
432 * Tiling registers
433 */
434 struct radeon_surface_reg {
435 struct radeon_bo *bo;
436 };
437
438 #define RADEON_GEM_MAX_SURFACES 8
439
440 /*
441 * TTM.
442 */
443 struct radeon_mman {
444 struct ttm_bo_global_ref bo_global_ref;
445 struct drm_global_reference mem_global_ref;
446 struct ttm_bo_device bdev;
447 bool mem_global_referenced;
448 bool initialized;
449
450 #if defined(CONFIG_DEBUG_FS)
451 struct dentry *vram;
452 struct dentry *gtt;
453 #endif
454 };
455
456 struct radeon_bo_list {
457 struct radeon_bo *robj;
458 struct ttm_validate_buffer tv;
459 uint64_t gpu_offset;
460 unsigned prefered_domains;
461 unsigned allowed_domains;
462 uint32_t tiling_flags;
463 };
464
465 /* bo virtual address in a specific vm */
466 struct radeon_bo_va {
467 /* protected by bo being reserved */
468 struct list_head bo_list;
469 uint32_t flags;
470 uint64_t addr;
471 struct radeon_fence *last_pt_update;
472 unsigned ref_count;
473
474 /* protected by vm mutex */
475 struct interval_tree_node it;
476 struct list_head vm_status;
477
478 /* constant after initialization */
479 struct radeon_vm *vm;
480 struct radeon_bo *bo;
481 };
482
483 struct radeon_bo {
484 /* Protected by gem.mutex */
485 struct list_head list;
486 /* Protected by tbo.reserved */
487 u32 initial_domain;
488 struct ttm_place placements[4];
489 struct ttm_placement placement;
490 struct ttm_buffer_object tbo;
491 struct ttm_bo_kmap_obj kmap;
492 u32 flags;
493 unsigned pin_count;
494 void *kptr;
495 u32 tiling_flags;
496 u32 pitch;
497 int surface_reg;
498 /* list of all virtual address to which this bo
499 * is associated to
500 */
501 struct list_head va;
502 /* Constant after initialization */
503 struct radeon_device *rdev;
504 struct drm_gem_object gem_base;
505
506 struct ttm_bo_kmap_obj dma_buf_vmap;
507 pid_t pid;
508
509 struct radeon_mn *mn;
510 struct list_head mn_list;
511 };
512 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
513
514 int radeon_gem_debugfs_init(struct radeon_device *rdev);
515
516 /* sub-allocation manager, it has to be protected by another lock.
517 * By conception this is an helper for other part of the driver
518 * like the indirect buffer or semaphore, which both have their
519 * locking.
520 *
521 * Principe is simple, we keep a list of sub allocation in offset
522 * order (first entry has offset == 0, last entry has the highest
523 * offset).
524 *
525 * When allocating new object we first check if there is room at
526 * the end total_size - (last_object_offset + last_object_size) >=
527 * alloc_size. If so we allocate new object there.
528 *
529 * When there is not enough room at the end, we start waiting for
530 * each sub object until we reach object_offset+object_size >=
531 * alloc_size, this object then become the sub object we return.
532 *
533 * Alignment can't be bigger than page size.
534 *
535 * Hole are not considered for allocation to keep things simple.
536 * Assumption is that there won't be hole (all object on same
537 * alignment).
538 */
539 struct radeon_sa_manager {
540 wait_queue_head_t wq;
541 struct radeon_bo *bo;
542 struct list_head *hole;
543 struct list_head flist[RADEON_NUM_RINGS];
544 struct list_head olist;
545 unsigned size;
546 uint64_t gpu_addr;
547 void *cpu_ptr;
548 uint32_t domain;
549 uint32_t align;
550 };
551
552 struct radeon_sa_bo;
553
554 /* sub-allocation buffer */
555 struct radeon_sa_bo {
556 struct list_head olist;
557 struct list_head flist;
558 struct radeon_sa_manager *manager;
559 unsigned soffset;
560 unsigned eoffset;
561 struct radeon_fence *fence;
562 };
563
564 /*
565 * GEM objects.
566 */
567 struct radeon_gem {
568 struct mutex mutex;
569 struct list_head objects;
570 };
571
572 int radeon_gem_init(struct radeon_device *rdev);
573 void radeon_gem_fini(struct radeon_device *rdev);
574 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
575 int alignment, int initial_domain,
576 u32 flags, bool kernel,
577 struct drm_gem_object **obj);
578
579 int radeon_mode_dumb_create(struct drm_file *file_priv,
580 struct drm_device *dev,
581 struct drm_mode_create_dumb *args);
582 int radeon_mode_dumb_mmap(struct drm_file *filp,
583 struct drm_device *dev,
584 uint32_t handle, uint64_t *offset_p);
585
586 /*
587 * Semaphores.
588 */
589 struct radeon_semaphore {
590 struct radeon_sa_bo *sa_bo;
591 signed waiters;
592 uint64_t gpu_addr;
593 };
594
595 int radeon_semaphore_create(struct radeon_device *rdev,
596 struct radeon_semaphore **semaphore);
597 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
598 struct radeon_semaphore *semaphore);
599 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
600 struct radeon_semaphore *semaphore);
601 void radeon_semaphore_free(struct radeon_device *rdev,
602 struct radeon_semaphore **semaphore,
603 struct radeon_fence *fence);
604
605 /*
606 * Synchronization
607 */
608 struct radeon_sync {
609 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
610 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
611 struct radeon_fence *last_vm_update;
612 };
613
614 void radeon_sync_create(struct radeon_sync *sync);
615 void radeon_sync_fence(struct radeon_sync *sync,
616 struct radeon_fence *fence);
617 int radeon_sync_resv(struct radeon_device *rdev,
618 struct radeon_sync *sync,
619 struct reservation_object *resv,
620 bool shared);
621 int radeon_sync_rings(struct radeon_device *rdev,
622 struct radeon_sync *sync,
623 int waiting_ring);
624 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
625 struct radeon_fence *fence);
626
627 /*
628 * GART structures, functions & helpers
629 */
630 struct radeon_mc;
631
632 #define RADEON_GPU_PAGE_SIZE 4096
633 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
634 #define RADEON_GPU_PAGE_SHIFT 12
635 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
636
637 #define RADEON_GART_PAGE_DUMMY 0
638 #define RADEON_GART_PAGE_VALID (1 << 0)
639 #define RADEON_GART_PAGE_READ (1 << 1)
640 #define RADEON_GART_PAGE_WRITE (1 << 2)
641 #define RADEON_GART_PAGE_SNOOP (1 << 3)
642
643 struct radeon_gart {
644 dma_addr_t table_addr;
645 struct radeon_bo *robj;
646 void *ptr;
647 unsigned num_gpu_pages;
648 unsigned num_cpu_pages;
649 unsigned table_size;
650 struct page **pages;
651 uint64_t *pages_entry;
652 bool ready;
653 };
654
655 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
656 void radeon_gart_table_ram_free(struct radeon_device *rdev);
657 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
658 void radeon_gart_table_vram_free(struct radeon_device *rdev);
659 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
660 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
661 int radeon_gart_init(struct radeon_device *rdev);
662 void radeon_gart_fini(struct radeon_device *rdev);
663 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
664 int pages);
665 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
666 int pages, struct page **pagelist,
667 dma_addr_t *dma_addr, uint32_t flags);
668
669
670 /*
671 * GPU MC structures, functions & helpers
672 */
673 struct radeon_mc {
674 resource_size_t aper_size;
675 resource_size_t aper_base;
676 resource_size_t agp_base;
677 /* for some chips with <= 32MB we need to lie
678 * about vram size near mc fb location */
679 u64 mc_vram_size;
680 u64 visible_vram_size;
681 u64 gtt_size;
682 u64 gtt_start;
683 u64 gtt_end;
684 u64 vram_start;
685 u64 vram_end;
686 unsigned vram_width;
687 u64 real_vram_size;
688 int vram_mtrr;
689 bool vram_is_ddr;
690 bool igp_sideport_enabled;
691 u64 gtt_base_align;
692 u64 mc_mask;
693 };
694
695 bool radeon_combios_sideport_present(struct radeon_device *rdev);
696 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
697
698 /*
699 * GPU scratch registers structures, functions & helpers
700 */
701 struct radeon_scratch {
702 unsigned num_reg;
703 uint32_t reg_base;
704 bool free[32];
705 uint32_t reg[32];
706 };
707
708 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
709 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
710
711 /*
712 * GPU doorbell structures, functions & helpers
713 */
714 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
715
716 struct radeon_doorbell {
717 /* doorbell mmio */
718 resource_size_t base;
719 resource_size_t size;
720 u32 __iomem *ptr;
721 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
722 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
723 };
724
725 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
726 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
727 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
728 phys_addr_t *aperture_base,
729 size_t *aperture_size,
730 size_t *start_offset);
731
732 /*
733 * IRQS.
734 */
735
736 struct radeon_flip_work {
737 struct work_struct flip_work;
738 struct work_struct unpin_work;
739 struct radeon_device *rdev;
740 int crtc_id;
741 uint64_t base;
742 struct drm_pending_vblank_event *event;
743 struct radeon_bo *old_rbo;
744 struct fence *fence;
745 };
746
747 struct r500_irq_stat_regs {
748 u32 disp_int;
749 u32 hdmi0_status;
750 };
751
752 struct r600_irq_stat_regs {
753 u32 disp_int;
754 u32 disp_int_cont;
755 u32 disp_int_cont2;
756 u32 d1grph_int;
757 u32 d2grph_int;
758 u32 hdmi0_status;
759 u32 hdmi1_status;
760 };
761
762 struct evergreen_irq_stat_regs {
763 u32 disp_int;
764 u32 disp_int_cont;
765 u32 disp_int_cont2;
766 u32 disp_int_cont3;
767 u32 disp_int_cont4;
768 u32 disp_int_cont5;
769 u32 d1grph_int;
770 u32 d2grph_int;
771 u32 d3grph_int;
772 u32 d4grph_int;
773 u32 d5grph_int;
774 u32 d6grph_int;
775 u32 afmt_status1;
776 u32 afmt_status2;
777 u32 afmt_status3;
778 u32 afmt_status4;
779 u32 afmt_status5;
780 u32 afmt_status6;
781 };
782
783 struct cik_irq_stat_regs {
784 u32 disp_int;
785 u32 disp_int_cont;
786 u32 disp_int_cont2;
787 u32 disp_int_cont3;
788 u32 disp_int_cont4;
789 u32 disp_int_cont5;
790 u32 disp_int_cont6;
791 u32 d1grph_int;
792 u32 d2grph_int;
793 u32 d3grph_int;
794 u32 d4grph_int;
795 u32 d5grph_int;
796 u32 d6grph_int;
797 };
798
799 union radeon_irq_stat_regs {
800 struct r500_irq_stat_regs r500;
801 struct r600_irq_stat_regs r600;
802 struct evergreen_irq_stat_regs evergreen;
803 struct cik_irq_stat_regs cik;
804 };
805
806 struct radeon_irq {
807 bool installed;
808 spinlock_t lock;
809 atomic_t ring_int[RADEON_NUM_RINGS];
810 bool crtc_vblank_int[RADEON_MAX_CRTCS];
811 atomic_t pflip[RADEON_MAX_CRTCS];
812 wait_queue_head_t vblank_queue;
813 bool hpd[RADEON_MAX_HPD_PINS];
814 bool afmt[RADEON_MAX_AFMT_BLOCKS];
815 union radeon_irq_stat_regs stat_regs;
816 bool dpm_thermal;
817 };
818
819 int radeon_irq_kms_init(struct radeon_device *rdev);
820 void radeon_irq_kms_fini(struct radeon_device *rdev);
821 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
822 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
823 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
824 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
825 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
826 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
827 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
828 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
829 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
830
831 /*
832 * CP & rings.
833 */
834
835 struct radeon_ib {
836 struct radeon_sa_bo *sa_bo;
837 uint32_t length_dw;
838 uint64_t gpu_addr;
839 uint32_t *ptr;
840 int ring;
841 struct radeon_fence *fence;
842 struct radeon_vm *vm;
843 bool is_const_ib;
844 struct radeon_sync sync;
845 };
846
847 struct radeon_ring {
848 struct radeon_bo *ring_obj;
849 volatile uint32_t *ring;
850 unsigned rptr_offs;
851 unsigned rptr_save_reg;
852 u64 next_rptr_gpu_addr;
853 volatile u32 *next_rptr_cpu_addr;
854 unsigned wptr;
855 unsigned wptr_old;
856 unsigned ring_size;
857 unsigned ring_free_dw;
858 int count_dw;
859 atomic_t last_rptr;
860 atomic64_t last_activity;
861 uint64_t gpu_addr;
862 uint32_t align_mask;
863 uint32_t ptr_mask;
864 bool ready;
865 u32 nop;
866 u32 idx;
867 u64 last_semaphore_signal_addr;
868 u64 last_semaphore_wait_addr;
869 /* for CIK queues */
870 u32 me;
871 u32 pipe;
872 u32 queue;
873 struct radeon_bo *mqd_obj;
874 u32 doorbell_index;
875 unsigned wptr_offs;
876 };
877
878 struct radeon_mec {
879 struct radeon_bo *hpd_eop_obj;
880 u64 hpd_eop_gpu_addr;
881 u32 num_pipe;
882 u32 num_mec;
883 u32 num_queue;
884 };
885
886 /*
887 * VM
888 */
889
890 /* maximum number of VMIDs */
891 #define RADEON_NUM_VM 16
892
893 /* number of entries in page table */
894 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
895
896 /* PTBs (Page Table Blocks) need to be aligned to 32K */
897 #define RADEON_VM_PTB_ALIGN_SIZE 32768
898 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
899 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
900
901 #define R600_PTE_VALID (1 << 0)
902 #define R600_PTE_SYSTEM (1 << 1)
903 #define R600_PTE_SNOOPED (1 << 2)
904 #define R600_PTE_READABLE (1 << 5)
905 #define R600_PTE_WRITEABLE (1 << 6)
906
907 /* PTE (Page Table Entry) fragment field for different page sizes */
908 #define R600_PTE_FRAG_4KB (0 << 7)
909 #define R600_PTE_FRAG_64KB (4 << 7)
910 #define R600_PTE_FRAG_256KB (6 << 7)
911
912 /* flags needed to be set so we can copy directly from the GART table */
913 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
914 R600_PTE_SYSTEM | R600_PTE_VALID )
915
916 struct radeon_vm_pt {
917 struct radeon_bo *bo;
918 uint64_t addr;
919 };
920
921 struct radeon_vm_id {
922 unsigned id;
923 uint64_t pd_gpu_addr;
924 /* last flushed PD/PT update */
925 struct radeon_fence *flushed_updates;
926 /* last use of vmid */
927 struct radeon_fence *last_id_use;
928 };
929
930 struct radeon_vm {
931 struct mutex mutex;
932
933 struct rb_root va;
934
935 /* protecting invalidated and freed */
936 spinlock_t status_lock;
937
938 /* BOs moved, but not yet updated in the PT */
939 struct list_head invalidated;
940
941 /* BOs freed, but not yet updated in the PT */
942 struct list_head freed;
943
944 /* contains the page directory */
945 struct radeon_bo *page_directory;
946 unsigned max_pde_used;
947
948 /* array of page tables, one for each page directory entry */
949 struct radeon_vm_pt *page_tables;
950
951 struct radeon_bo_va *ib_bo_va;
952
953 /* for id and flush management per ring */
954 struct radeon_vm_id ids[RADEON_NUM_RINGS];
955 };
956
957 struct radeon_vm_manager {
958 struct radeon_fence *active[RADEON_NUM_VM];
959 uint32_t max_pfn;
960 /* number of VMIDs */
961 unsigned nvm;
962 /* vram base address for page table entry */
963 u64 vram_base_offset;
964 /* is vm enabled? */
965 bool enabled;
966 /* for hw to save the PD addr on suspend/resume */
967 uint32_t saved_table_addr[RADEON_NUM_VM];
968 };
969
970 /*
971 * file private structure
972 */
973 struct radeon_fpriv {
974 struct radeon_vm vm;
975 };
976
977 /*
978 * R6xx+ IH ring
979 */
980 struct r600_ih {
981 struct radeon_bo *ring_obj;
982 volatile uint32_t *ring;
983 unsigned rptr;
984 unsigned ring_size;
985 uint64_t gpu_addr;
986 uint32_t ptr_mask;
987 atomic_t lock;
988 bool enabled;
989 };
990
991 /*
992 * RLC stuff
993 */
994 #include "clearstate_defs.h"
995
996 struct radeon_rlc {
997 /* for power gating */
998 struct radeon_bo *save_restore_obj;
999 uint64_t save_restore_gpu_addr;
1000 volatile uint32_t *sr_ptr;
1001 const u32 *reg_list;
1002 u32 reg_list_size;
1003 /* for clear state */
1004 struct radeon_bo *clear_state_obj;
1005 uint64_t clear_state_gpu_addr;
1006 volatile uint32_t *cs_ptr;
1007 const struct cs_section_def *cs_data;
1008 u32 clear_state_size;
1009 /* for cp tables */
1010 struct radeon_bo *cp_table_obj;
1011 uint64_t cp_table_gpu_addr;
1012 volatile uint32_t *cp_table_ptr;
1013 u32 cp_table_size;
1014 };
1015
1016 int radeon_ib_get(struct radeon_device *rdev, int ring,
1017 struct radeon_ib *ib, struct radeon_vm *vm,
1018 unsigned size);
1019 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1020 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1021 struct radeon_ib *const_ib, bool hdp_flush);
1022 int radeon_ib_pool_init(struct radeon_device *rdev);
1023 void radeon_ib_pool_fini(struct radeon_device *rdev);
1024 int radeon_ib_ring_tests(struct radeon_device *rdev);
1025 /* Ring access between begin & end cannot sleep */
1026 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1027 struct radeon_ring *ring);
1028 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1029 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1030 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1031 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1032 bool hdp_flush);
1033 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1034 bool hdp_flush);
1035 void radeon_ring_undo(struct radeon_ring *ring);
1036 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1037 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1038 void radeon_ring_lockup_update(struct radeon_device *rdev,
1039 struct radeon_ring *ring);
1040 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1041 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1042 uint32_t **data);
1043 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1044 unsigned size, uint32_t *data);
1045 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1046 unsigned rptr_offs, u32 nop);
1047 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1048
1049
1050 /* r600 async dma */
1051 void r600_dma_stop(struct radeon_device *rdev);
1052 int r600_dma_resume(struct radeon_device *rdev);
1053 void r600_dma_fini(struct radeon_device *rdev);
1054
1055 void cayman_dma_stop(struct radeon_device *rdev);
1056 int cayman_dma_resume(struct radeon_device *rdev);
1057 void cayman_dma_fini(struct radeon_device *rdev);
1058
1059 /*
1060 * CS.
1061 */
1062 struct radeon_cs_chunk {
1063 uint32_t length_dw;
1064 uint32_t *kdata;
1065 void __user *user_ptr;
1066 };
1067
1068 struct radeon_cs_parser {
1069 struct device *dev;
1070 struct radeon_device *rdev;
1071 struct drm_file *filp;
1072 /* chunks */
1073 unsigned nchunks;
1074 struct radeon_cs_chunk *chunks;
1075 uint64_t *chunks_array;
1076 /* IB */
1077 unsigned idx;
1078 /* relocations */
1079 unsigned nrelocs;
1080 struct radeon_bo_list *relocs;
1081 struct radeon_bo_list *vm_bos;
1082 struct list_head validated;
1083 unsigned dma_reloc_idx;
1084 /* indices of various chunks */
1085 struct radeon_cs_chunk *chunk_ib;
1086 struct radeon_cs_chunk *chunk_relocs;
1087 struct radeon_cs_chunk *chunk_flags;
1088 struct radeon_cs_chunk *chunk_const_ib;
1089 struct radeon_ib ib;
1090 struct radeon_ib const_ib;
1091 void *track;
1092 unsigned family;
1093 int parser_error;
1094 u32 cs_flags;
1095 u32 ring;
1096 s32 priority;
1097 struct ww_acquire_ctx ticket;
1098 };
1099
1100 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1101 {
1102 struct radeon_cs_chunk *ibc = p->chunk_ib;
1103
1104 if (ibc->kdata)
1105 return ibc->kdata[idx];
1106 return p->ib.ptr[idx];
1107 }
1108
1109
1110 struct radeon_cs_packet {
1111 unsigned idx;
1112 unsigned type;
1113 unsigned reg;
1114 unsigned opcode;
1115 int count;
1116 unsigned one_reg_wr;
1117 };
1118
1119 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1120 struct radeon_cs_packet *pkt,
1121 unsigned idx, unsigned reg);
1122 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1123 struct radeon_cs_packet *pkt);
1124
1125
1126 /*
1127 * AGP
1128 */
1129 int radeon_agp_init(struct radeon_device *rdev);
1130 void radeon_agp_resume(struct radeon_device *rdev);
1131 void radeon_agp_suspend(struct radeon_device *rdev);
1132 void radeon_agp_fini(struct radeon_device *rdev);
1133
1134
1135 /*
1136 * Writeback
1137 */
1138 struct radeon_wb {
1139 struct radeon_bo *wb_obj;
1140 volatile uint32_t *wb;
1141 uint64_t gpu_addr;
1142 bool enabled;
1143 bool use_event;
1144 };
1145
1146 #define RADEON_WB_SCRATCH_OFFSET 0
1147 #define RADEON_WB_RING0_NEXT_RPTR 256
1148 #define RADEON_WB_CP_RPTR_OFFSET 1024
1149 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1150 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1151 #define R600_WB_DMA_RPTR_OFFSET 1792
1152 #define R600_WB_IH_WPTR_OFFSET 2048
1153 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1154 #define R600_WB_EVENT_OFFSET 3072
1155 #define CIK_WB_CP1_WPTR_OFFSET 3328
1156 #define CIK_WB_CP2_WPTR_OFFSET 3584
1157 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1158 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1159
1160 /**
1161 * struct radeon_pm - power management datas
1162 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1163 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1164 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1165 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1166 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1167 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1168 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1169 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1170 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1171 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1172 * @needed_bandwidth: current bandwidth needs
1173 *
1174 * It keeps track of various data needed to take powermanagement decision.
1175 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1176 * Equation between gpu/memory clock and available bandwidth is hw dependent
1177 * (type of memory, bus size, efficiency, ...)
1178 */
1179
1180 enum radeon_pm_method {
1181 PM_METHOD_PROFILE,
1182 PM_METHOD_DYNPM,
1183 PM_METHOD_DPM,
1184 };
1185
1186 enum radeon_dynpm_state {
1187 DYNPM_STATE_DISABLED,
1188 DYNPM_STATE_MINIMUM,
1189 DYNPM_STATE_PAUSED,
1190 DYNPM_STATE_ACTIVE,
1191 DYNPM_STATE_SUSPENDED,
1192 };
1193 enum radeon_dynpm_action {
1194 DYNPM_ACTION_NONE,
1195 DYNPM_ACTION_MINIMUM,
1196 DYNPM_ACTION_DOWNCLOCK,
1197 DYNPM_ACTION_UPCLOCK,
1198 DYNPM_ACTION_DEFAULT
1199 };
1200
1201 enum radeon_voltage_type {
1202 VOLTAGE_NONE = 0,
1203 VOLTAGE_GPIO,
1204 VOLTAGE_VDDC,
1205 VOLTAGE_SW
1206 };
1207
1208 enum radeon_pm_state_type {
1209 /* not used for dpm */
1210 POWER_STATE_TYPE_DEFAULT,
1211 POWER_STATE_TYPE_POWERSAVE,
1212 /* user selectable states */
1213 POWER_STATE_TYPE_BATTERY,
1214 POWER_STATE_TYPE_BALANCED,
1215 POWER_STATE_TYPE_PERFORMANCE,
1216 /* internal states */
1217 POWER_STATE_TYPE_INTERNAL_UVD,
1218 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1219 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1220 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1221 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1222 POWER_STATE_TYPE_INTERNAL_BOOT,
1223 POWER_STATE_TYPE_INTERNAL_THERMAL,
1224 POWER_STATE_TYPE_INTERNAL_ACPI,
1225 POWER_STATE_TYPE_INTERNAL_ULV,
1226 POWER_STATE_TYPE_INTERNAL_3DPERF,
1227 };
1228
1229 enum radeon_pm_profile_type {
1230 PM_PROFILE_DEFAULT,
1231 PM_PROFILE_AUTO,
1232 PM_PROFILE_LOW,
1233 PM_PROFILE_MID,
1234 PM_PROFILE_HIGH,
1235 };
1236
1237 #define PM_PROFILE_DEFAULT_IDX 0
1238 #define PM_PROFILE_LOW_SH_IDX 1
1239 #define PM_PROFILE_MID_SH_IDX 2
1240 #define PM_PROFILE_HIGH_SH_IDX 3
1241 #define PM_PROFILE_LOW_MH_IDX 4
1242 #define PM_PROFILE_MID_MH_IDX 5
1243 #define PM_PROFILE_HIGH_MH_IDX 6
1244 #define PM_PROFILE_MAX 7
1245
1246 struct radeon_pm_profile {
1247 int dpms_off_ps_idx;
1248 int dpms_on_ps_idx;
1249 int dpms_off_cm_idx;
1250 int dpms_on_cm_idx;
1251 };
1252
1253 enum radeon_int_thermal_type {
1254 THERMAL_TYPE_NONE,
1255 THERMAL_TYPE_EXTERNAL,
1256 THERMAL_TYPE_EXTERNAL_GPIO,
1257 THERMAL_TYPE_RV6XX,
1258 THERMAL_TYPE_RV770,
1259 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1260 THERMAL_TYPE_EVERGREEN,
1261 THERMAL_TYPE_SUMO,
1262 THERMAL_TYPE_NI,
1263 THERMAL_TYPE_SI,
1264 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1265 THERMAL_TYPE_CI,
1266 THERMAL_TYPE_KV,
1267 };
1268
1269 struct radeon_voltage {
1270 enum radeon_voltage_type type;
1271 /* gpio voltage */
1272 struct radeon_gpio_rec gpio;
1273 u32 delay; /* delay in usec from voltage drop to sclk change */
1274 bool active_high; /* voltage drop is active when bit is high */
1275 /* VDDC voltage */
1276 u8 vddc_id; /* index into vddc voltage table */
1277 u8 vddci_id; /* index into vddci voltage table */
1278 bool vddci_enabled;
1279 /* r6xx+ sw */
1280 u16 voltage;
1281 /* evergreen+ vddci */
1282 u16 vddci;
1283 };
1284
1285 /* clock mode flags */
1286 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1287
1288 struct radeon_pm_clock_info {
1289 /* memory clock */
1290 u32 mclk;
1291 /* engine clock */
1292 u32 sclk;
1293 /* voltage info */
1294 struct radeon_voltage voltage;
1295 /* standardized clock flags */
1296 u32 flags;
1297 };
1298
1299 /* state flags */
1300 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1301
1302 struct radeon_power_state {
1303 enum radeon_pm_state_type type;
1304 struct radeon_pm_clock_info *clock_info;
1305 /* number of valid clock modes in this power state */
1306 int num_clock_modes;
1307 struct radeon_pm_clock_info *default_clock_mode;
1308 /* standardized state flags */
1309 u32 flags;
1310 u32 misc; /* vbios specific flags */
1311 u32 misc2; /* vbios specific flags */
1312 int pcie_lanes; /* pcie lanes */
1313 };
1314
1315 /*
1316 * Some modes are overclocked by very low value, accept them
1317 */
1318 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1319
1320 enum radeon_dpm_auto_throttle_src {
1321 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1322 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1323 };
1324
1325 enum radeon_dpm_event_src {
1326 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1327 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1328 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1329 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1330 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1331 };
1332
1333 #define RADEON_MAX_VCE_LEVELS 6
1334
1335 enum radeon_vce_level {
1336 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1337 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1338 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1339 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1340 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1341 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1342 };
1343
1344 struct radeon_ps {
1345 u32 caps; /* vbios flags */
1346 u32 class; /* vbios flags */
1347 u32 class2; /* vbios flags */
1348 /* UVD clocks */
1349 u32 vclk;
1350 u32 dclk;
1351 /* VCE clocks */
1352 u32 evclk;
1353 u32 ecclk;
1354 bool vce_active;
1355 enum radeon_vce_level vce_level;
1356 /* asic priv */
1357 void *ps_priv;
1358 };
1359
1360 struct radeon_dpm_thermal {
1361 /* thermal interrupt work */
1362 struct work_struct work;
1363 /* low temperature threshold */
1364 int min_temp;
1365 /* high temperature threshold */
1366 int max_temp;
1367 /* was interrupt low to high or high to low */
1368 bool high_to_low;
1369 };
1370
1371 enum radeon_clk_action
1372 {
1373 RADEON_SCLK_UP = 1,
1374 RADEON_SCLK_DOWN
1375 };
1376
1377 struct radeon_blacklist_clocks
1378 {
1379 u32 sclk;
1380 u32 mclk;
1381 enum radeon_clk_action action;
1382 };
1383
1384 struct radeon_clock_and_voltage_limits {
1385 u32 sclk;
1386 u32 mclk;
1387 u16 vddc;
1388 u16 vddci;
1389 };
1390
1391 struct radeon_clock_array {
1392 u32 count;
1393 u32 *values;
1394 };
1395
1396 struct radeon_clock_voltage_dependency_entry {
1397 u32 clk;
1398 u16 v;
1399 };
1400
1401 struct radeon_clock_voltage_dependency_table {
1402 u32 count;
1403 struct radeon_clock_voltage_dependency_entry *entries;
1404 };
1405
1406 union radeon_cac_leakage_entry {
1407 struct {
1408 u16 vddc;
1409 u32 leakage;
1410 };
1411 struct {
1412 u16 vddc1;
1413 u16 vddc2;
1414 u16 vddc3;
1415 };
1416 };
1417
1418 struct radeon_cac_leakage_table {
1419 u32 count;
1420 union radeon_cac_leakage_entry *entries;
1421 };
1422
1423 struct radeon_phase_shedding_limits_entry {
1424 u16 voltage;
1425 u32 sclk;
1426 u32 mclk;
1427 };
1428
1429 struct radeon_phase_shedding_limits_table {
1430 u32 count;
1431 struct radeon_phase_shedding_limits_entry *entries;
1432 };
1433
1434 struct radeon_uvd_clock_voltage_dependency_entry {
1435 u32 vclk;
1436 u32 dclk;
1437 u16 v;
1438 };
1439
1440 struct radeon_uvd_clock_voltage_dependency_table {
1441 u8 count;
1442 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1443 };
1444
1445 struct radeon_vce_clock_voltage_dependency_entry {
1446 u32 ecclk;
1447 u32 evclk;
1448 u16 v;
1449 };
1450
1451 struct radeon_vce_clock_voltage_dependency_table {
1452 u8 count;
1453 struct radeon_vce_clock_voltage_dependency_entry *entries;
1454 };
1455
1456 struct radeon_ppm_table {
1457 u8 ppm_design;
1458 u16 cpu_core_number;
1459 u32 platform_tdp;
1460 u32 small_ac_platform_tdp;
1461 u32 platform_tdc;
1462 u32 small_ac_platform_tdc;
1463 u32 apu_tdp;
1464 u32 dgpu_tdp;
1465 u32 dgpu_ulv_power;
1466 u32 tj_max;
1467 };
1468
1469 struct radeon_cac_tdp_table {
1470 u16 tdp;
1471 u16 configurable_tdp;
1472 u16 tdc;
1473 u16 battery_power_limit;
1474 u16 small_power_limit;
1475 u16 low_cac_leakage;
1476 u16 high_cac_leakage;
1477 u16 maximum_power_delivery_limit;
1478 };
1479
1480 struct radeon_dpm_dynamic_state {
1481 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1482 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1483 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1484 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1485 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1486 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1487 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1488 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1489 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1490 struct radeon_clock_array valid_sclk_values;
1491 struct radeon_clock_array valid_mclk_values;
1492 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1493 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1494 u32 mclk_sclk_ratio;
1495 u32 sclk_mclk_delta;
1496 u16 vddc_vddci_delta;
1497 u16 min_vddc_for_pcie_gen2;
1498 struct radeon_cac_leakage_table cac_leakage_table;
1499 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1500 struct radeon_ppm_table *ppm_table;
1501 struct radeon_cac_tdp_table *cac_tdp_table;
1502 };
1503
1504 struct radeon_dpm_fan {
1505 u16 t_min;
1506 u16 t_med;
1507 u16 t_high;
1508 u16 pwm_min;
1509 u16 pwm_med;
1510 u16 pwm_high;
1511 u8 t_hyst;
1512 u32 cycle_delay;
1513 u16 t_max;
1514 u8 control_mode;
1515 u16 default_max_fan_pwm;
1516 u16 default_fan_output_sensitivity;
1517 u16 fan_output_sensitivity;
1518 bool ucode_fan_control;
1519 };
1520
1521 enum radeon_pcie_gen {
1522 RADEON_PCIE_GEN1 = 0,
1523 RADEON_PCIE_GEN2 = 1,
1524 RADEON_PCIE_GEN3 = 2,
1525 RADEON_PCIE_GEN_INVALID = 0xffff
1526 };
1527
1528 enum radeon_dpm_forced_level {
1529 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1530 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1531 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1532 };
1533
1534 struct radeon_vce_state {
1535 /* vce clocks */
1536 u32 evclk;
1537 u32 ecclk;
1538 /* gpu clocks */
1539 u32 sclk;
1540 u32 mclk;
1541 u8 clk_idx;
1542 u8 pstate;
1543 };
1544
1545 struct radeon_dpm {
1546 struct radeon_ps *ps;
1547 /* number of valid power states */
1548 int num_ps;
1549 /* current power state that is active */
1550 struct radeon_ps *current_ps;
1551 /* requested power state */
1552 struct radeon_ps *requested_ps;
1553 /* boot up power state */
1554 struct radeon_ps *boot_ps;
1555 /* default uvd power state */
1556 struct radeon_ps *uvd_ps;
1557 /* vce requirements */
1558 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1559 enum radeon_vce_level vce_level;
1560 enum radeon_pm_state_type state;
1561 enum radeon_pm_state_type user_state;
1562 u32 platform_caps;
1563 u32 voltage_response_time;
1564 u32 backbias_response_time;
1565 void *priv;
1566 u32 new_active_crtcs;
1567 int new_active_crtc_count;
1568 u32 current_active_crtcs;
1569 int current_active_crtc_count;
1570 bool single_display;
1571 struct radeon_dpm_dynamic_state dyn_state;
1572 struct radeon_dpm_fan fan;
1573 u32 tdp_limit;
1574 u32 near_tdp_limit;
1575 u32 near_tdp_limit_adjusted;
1576 u32 sq_ramping_threshold;
1577 u32 cac_leakage;
1578 u16 tdp_od_limit;
1579 u32 tdp_adjustment;
1580 u16 load_line_slope;
1581 bool power_control;
1582 bool ac_power;
1583 /* special states active */
1584 bool thermal_active;
1585 bool uvd_active;
1586 bool vce_active;
1587 /* thermal handling */
1588 struct radeon_dpm_thermal thermal;
1589 /* forced levels */
1590 enum radeon_dpm_forced_level forced_level;
1591 /* track UVD streams */
1592 unsigned sd;
1593 unsigned hd;
1594 };
1595
1596 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1597 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1598
1599 struct radeon_pm {
1600 struct mutex mutex;
1601 /* write locked while reprogramming mclk */
1602 struct rw_semaphore mclk_lock;
1603 u32 active_crtcs;
1604 int active_crtc_count;
1605 int req_vblank;
1606 bool vblank_sync;
1607 fixed20_12 max_bandwidth;
1608 fixed20_12 igp_sideport_mclk;
1609 fixed20_12 igp_system_mclk;
1610 fixed20_12 igp_ht_link_clk;
1611 fixed20_12 igp_ht_link_width;
1612 fixed20_12 k8_bandwidth;
1613 fixed20_12 sideport_bandwidth;
1614 fixed20_12 ht_bandwidth;
1615 fixed20_12 core_bandwidth;
1616 fixed20_12 sclk;
1617 fixed20_12 mclk;
1618 fixed20_12 needed_bandwidth;
1619 struct radeon_power_state *power_state;
1620 /* number of valid power states */
1621 int num_power_states;
1622 int current_power_state_index;
1623 int current_clock_mode_index;
1624 int requested_power_state_index;
1625 int requested_clock_mode_index;
1626 int default_power_state_index;
1627 u32 current_sclk;
1628 u32 current_mclk;
1629 u16 current_vddc;
1630 u16 current_vddci;
1631 u32 default_sclk;
1632 u32 default_mclk;
1633 u16 default_vddc;
1634 u16 default_vddci;
1635 struct radeon_i2c_chan *i2c_bus;
1636 /* selected pm method */
1637 enum radeon_pm_method pm_method;
1638 /* dynpm power management */
1639 struct delayed_work dynpm_idle_work;
1640 enum radeon_dynpm_state dynpm_state;
1641 enum radeon_dynpm_action dynpm_planned_action;
1642 unsigned long dynpm_action_timeout;
1643 bool dynpm_can_upclock;
1644 bool dynpm_can_downclock;
1645 /* profile-based power management */
1646 enum radeon_pm_profile_type profile;
1647 int profile_index;
1648 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1649 /* internal thermal controller on rv6xx+ */
1650 enum radeon_int_thermal_type int_thermal_type;
1651 struct device *int_hwmon_dev;
1652 /* fan control parameters */
1653 bool no_fan;
1654 u8 fan_pulses_per_revolution;
1655 u8 fan_min_rpm;
1656 u8 fan_max_rpm;
1657 /* dpm */
1658 bool dpm_enabled;
1659 struct radeon_dpm dpm;
1660 };
1661
1662 int radeon_pm_get_type_index(struct radeon_device *rdev,
1663 enum radeon_pm_state_type ps_type,
1664 int instance);
1665 /*
1666 * UVD
1667 */
1668 #define RADEON_MAX_UVD_HANDLES 10
1669 #define RADEON_UVD_STACK_SIZE (1024*1024)
1670 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1671
1672 struct radeon_uvd {
1673 struct radeon_bo *vcpu_bo;
1674 void *cpu_addr;
1675 uint64_t gpu_addr;
1676 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1677 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1678 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1679 struct delayed_work idle_work;
1680 };
1681
1682 int radeon_uvd_init(struct radeon_device *rdev);
1683 void radeon_uvd_fini(struct radeon_device *rdev);
1684 int radeon_uvd_suspend(struct radeon_device *rdev);
1685 int radeon_uvd_resume(struct radeon_device *rdev);
1686 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1687 uint32_t handle, struct radeon_fence **fence);
1688 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1689 uint32_t handle, struct radeon_fence **fence);
1690 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1691 uint32_t allowed_domains);
1692 void radeon_uvd_free_handles(struct radeon_device *rdev,
1693 struct drm_file *filp);
1694 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1695 void radeon_uvd_note_usage(struct radeon_device *rdev);
1696 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1697 unsigned vclk, unsigned dclk,
1698 unsigned vco_min, unsigned vco_max,
1699 unsigned fb_factor, unsigned fb_mask,
1700 unsigned pd_min, unsigned pd_max,
1701 unsigned pd_even,
1702 unsigned *optimal_fb_div,
1703 unsigned *optimal_vclk_div,
1704 unsigned *optimal_dclk_div);
1705 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1706 unsigned cg_upll_func_cntl);
1707
1708 /*
1709 * VCE
1710 */
1711 #define RADEON_MAX_VCE_HANDLES 16
1712
1713 struct radeon_vce {
1714 struct radeon_bo *vcpu_bo;
1715 uint64_t gpu_addr;
1716 unsigned fw_version;
1717 unsigned fb_version;
1718 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1719 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1720 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1721 struct delayed_work idle_work;
1722 uint32_t keyselect;
1723 };
1724
1725 int radeon_vce_init(struct radeon_device *rdev);
1726 void radeon_vce_fini(struct radeon_device *rdev);
1727 int radeon_vce_suspend(struct radeon_device *rdev);
1728 int radeon_vce_resume(struct radeon_device *rdev);
1729 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1730 uint32_t handle, struct radeon_fence **fence);
1731 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1732 uint32_t handle, struct radeon_fence **fence);
1733 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1734 void radeon_vce_note_usage(struct radeon_device *rdev);
1735 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1736 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1737 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1738 struct radeon_ring *ring,
1739 struct radeon_semaphore *semaphore,
1740 bool emit_wait);
1741 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1742 void radeon_vce_fence_emit(struct radeon_device *rdev,
1743 struct radeon_fence *fence);
1744 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1745 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1746
1747 struct r600_audio_pin {
1748 int channels;
1749 int rate;
1750 int bits_per_sample;
1751 u8 status_bits;
1752 u8 category_code;
1753 u32 offset;
1754 bool connected;
1755 u32 id;
1756 };
1757
1758 struct r600_audio {
1759 bool enabled;
1760 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1761 int num_pins;
1762 struct radeon_audio_funcs *hdmi_funcs;
1763 struct radeon_audio_funcs *dp_funcs;
1764 struct radeon_audio_basic_funcs *funcs;
1765 };
1766
1767 /*
1768 * Benchmarking
1769 */
1770 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1771
1772
1773 /*
1774 * Testing
1775 */
1776 void radeon_test_moves(struct radeon_device *rdev);
1777 void radeon_test_ring_sync(struct radeon_device *rdev,
1778 struct radeon_ring *cpA,
1779 struct radeon_ring *cpB);
1780 void radeon_test_syncing(struct radeon_device *rdev);
1781
1782 /*
1783 * MMU Notifier
1784 */
1785 #if defined(CONFIG_MMU_NOTIFIER)
1786 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1787 void radeon_mn_unregister(struct radeon_bo *bo);
1788 #else
1789 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1790 {
1791 return -ENODEV;
1792 }
1793 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1794 #endif
1795
1796 /*
1797 * Debugfs
1798 */
1799 struct radeon_debugfs {
1800 struct drm_info_list *files;
1801 unsigned num_files;
1802 };
1803
1804 int radeon_debugfs_add_files(struct radeon_device *rdev,
1805 struct drm_info_list *files,
1806 unsigned nfiles);
1807 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1808
1809 /*
1810 * ASIC ring specific functions.
1811 */
1812 struct radeon_asic_ring {
1813 /* ring read/write ptr handling */
1814 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1815 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1816 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1817
1818 /* validating and patching of IBs */
1819 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1820 int (*cs_parse)(struct radeon_cs_parser *p);
1821
1822 /* command emmit functions */
1823 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1824 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1825 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1826 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1827 struct radeon_semaphore *semaphore, bool emit_wait);
1828 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1829 unsigned vm_id, uint64_t pd_addr);
1830
1831 /* testing functions */
1832 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1833 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1834 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1835
1836 /* deprecated */
1837 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1838 };
1839
1840 /*
1841 * ASIC specific functions.
1842 */
1843 struct radeon_asic {
1844 int (*init)(struct radeon_device *rdev);
1845 void (*fini)(struct radeon_device *rdev);
1846 int (*resume)(struct radeon_device *rdev);
1847 int (*suspend)(struct radeon_device *rdev);
1848 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1849 int (*asic_reset)(struct radeon_device *rdev);
1850 /* Flush the HDP cache via MMIO */
1851 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1852 /* check if 3D engine is idle */
1853 bool (*gui_idle)(struct radeon_device *rdev);
1854 /* wait for mc_idle */
1855 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1856 /* get the reference clock */
1857 u32 (*get_xclk)(struct radeon_device *rdev);
1858 /* get the gpu clock counter */
1859 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1860 /* get register for info ioctl */
1861 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1862 /* gart */
1863 struct {
1864 void (*tlb_flush)(struct radeon_device *rdev);
1865 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1866 void (*set_page)(struct radeon_device *rdev, unsigned i,
1867 uint64_t entry);
1868 } gart;
1869 struct {
1870 int (*init)(struct radeon_device *rdev);
1871 void (*fini)(struct radeon_device *rdev);
1872 void (*copy_pages)(struct radeon_device *rdev,
1873 struct radeon_ib *ib,
1874 uint64_t pe, uint64_t src,
1875 unsigned count);
1876 void (*write_pages)(struct radeon_device *rdev,
1877 struct radeon_ib *ib,
1878 uint64_t pe,
1879 uint64_t addr, unsigned count,
1880 uint32_t incr, uint32_t flags);
1881 void (*set_pages)(struct radeon_device *rdev,
1882 struct radeon_ib *ib,
1883 uint64_t pe,
1884 uint64_t addr, unsigned count,
1885 uint32_t incr, uint32_t flags);
1886 void (*pad_ib)(struct radeon_ib *ib);
1887 } vm;
1888 /* ring specific callbacks */
1889 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1890 /* irqs */
1891 struct {
1892 int (*set)(struct radeon_device *rdev);
1893 int (*process)(struct radeon_device *rdev);
1894 } irq;
1895 /* displays */
1896 struct {
1897 /* display watermarks */
1898 void (*bandwidth_update)(struct radeon_device *rdev);
1899 /* get frame count */
1900 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1901 /* wait for vblank */
1902 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1903 /* set backlight level */
1904 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1905 /* get backlight level */
1906 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1907 /* audio callbacks */
1908 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1909 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1910 } display;
1911 /* copy functions for bo handling */
1912 struct {
1913 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1914 uint64_t src_offset,
1915 uint64_t dst_offset,
1916 unsigned num_gpu_pages,
1917 struct reservation_object *resv);
1918 u32 blit_ring_index;
1919 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1920 uint64_t src_offset,
1921 uint64_t dst_offset,
1922 unsigned num_gpu_pages,
1923 struct reservation_object *resv);
1924 u32 dma_ring_index;
1925 /* method used for bo copy */
1926 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1927 uint64_t src_offset,
1928 uint64_t dst_offset,
1929 unsigned num_gpu_pages,
1930 struct reservation_object *resv);
1931 /* ring used for bo copies */
1932 u32 copy_ring_index;
1933 } copy;
1934 /* surfaces */
1935 struct {
1936 int (*set_reg)(struct radeon_device *rdev, int reg,
1937 uint32_t tiling_flags, uint32_t pitch,
1938 uint32_t offset, uint32_t obj_size);
1939 void (*clear_reg)(struct radeon_device *rdev, int reg);
1940 } surface;
1941 /* hotplug detect */
1942 struct {
1943 void (*init)(struct radeon_device *rdev);
1944 void (*fini)(struct radeon_device *rdev);
1945 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1946 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1947 } hpd;
1948 /* static power management */
1949 struct {
1950 void (*misc)(struct radeon_device *rdev);
1951 void (*prepare)(struct radeon_device *rdev);
1952 void (*finish)(struct radeon_device *rdev);
1953 void (*init_profile)(struct radeon_device *rdev);
1954 void (*get_dynpm_state)(struct radeon_device *rdev);
1955 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1956 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1957 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1958 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1959 int (*get_pcie_lanes)(struct radeon_device *rdev);
1960 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1961 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1962 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1963 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1964 int (*get_temperature)(struct radeon_device *rdev);
1965 } pm;
1966 /* dynamic power management */
1967 struct {
1968 int (*init)(struct radeon_device *rdev);
1969 void (*setup_asic)(struct radeon_device *rdev);
1970 int (*enable)(struct radeon_device *rdev);
1971 int (*late_enable)(struct radeon_device *rdev);
1972 void (*disable)(struct radeon_device *rdev);
1973 int (*pre_set_power_state)(struct radeon_device *rdev);
1974 int (*set_power_state)(struct radeon_device *rdev);
1975 void (*post_set_power_state)(struct radeon_device *rdev);
1976 void (*display_configuration_changed)(struct radeon_device *rdev);
1977 void (*fini)(struct radeon_device *rdev);
1978 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1979 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1980 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1981 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1982 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1983 bool (*vblank_too_short)(struct radeon_device *rdev);
1984 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1985 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1986 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1987 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1988 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1989 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1990 u32 (*get_current_sclk)(struct radeon_device *rdev);
1991 u32 (*get_current_mclk)(struct radeon_device *rdev);
1992 } dpm;
1993 /* pageflipping */
1994 struct {
1995 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1996 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1997 } pflip;
1998 };
1999
2000 /*
2001 * Asic structures
2002 */
2003 struct r100_asic {
2004 const unsigned *reg_safe_bm;
2005 unsigned reg_safe_bm_size;
2006 u32 hdp_cntl;
2007 };
2008
2009 struct r300_asic {
2010 const unsigned *reg_safe_bm;
2011 unsigned reg_safe_bm_size;
2012 u32 resync_scratch;
2013 u32 hdp_cntl;
2014 };
2015
2016 struct r600_asic {
2017 unsigned max_pipes;
2018 unsigned max_tile_pipes;
2019 unsigned max_simds;
2020 unsigned max_backends;
2021 unsigned max_gprs;
2022 unsigned max_threads;
2023 unsigned max_stack_entries;
2024 unsigned max_hw_contexts;
2025 unsigned max_gs_threads;
2026 unsigned sx_max_export_size;
2027 unsigned sx_max_export_pos_size;
2028 unsigned sx_max_export_smx_size;
2029 unsigned sq_num_cf_insts;
2030 unsigned tiling_nbanks;
2031 unsigned tiling_npipes;
2032 unsigned tiling_group_size;
2033 unsigned tile_config;
2034 unsigned backend_map;
2035 unsigned active_simds;
2036 };
2037
2038 struct rv770_asic {
2039 unsigned max_pipes;
2040 unsigned max_tile_pipes;
2041 unsigned max_simds;
2042 unsigned max_backends;
2043 unsigned max_gprs;
2044 unsigned max_threads;
2045 unsigned max_stack_entries;
2046 unsigned max_hw_contexts;
2047 unsigned max_gs_threads;
2048 unsigned sx_max_export_size;
2049 unsigned sx_max_export_pos_size;
2050 unsigned sx_max_export_smx_size;
2051 unsigned sq_num_cf_insts;
2052 unsigned sx_num_of_sets;
2053 unsigned sc_prim_fifo_size;
2054 unsigned sc_hiz_tile_fifo_size;
2055 unsigned sc_earlyz_tile_fifo_fize;
2056 unsigned tiling_nbanks;
2057 unsigned tiling_npipes;
2058 unsigned tiling_group_size;
2059 unsigned tile_config;
2060 unsigned backend_map;
2061 unsigned active_simds;
2062 };
2063
2064 struct evergreen_asic {
2065 unsigned num_ses;
2066 unsigned max_pipes;
2067 unsigned max_tile_pipes;
2068 unsigned max_simds;
2069 unsigned max_backends;
2070 unsigned max_gprs;
2071 unsigned max_threads;
2072 unsigned max_stack_entries;
2073 unsigned max_hw_contexts;
2074 unsigned max_gs_threads;
2075 unsigned sx_max_export_size;
2076 unsigned sx_max_export_pos_size;
2077 unsigned sx_max_export_smx_size;
2078 unsigned sq_num_cf_insts;
2079 unsigned sx_num_of_sets;
2080 unsigned sc_prim_fifo_size;
2081 unsigned sc_hiz_tile_fifo_size;
2082 unsigned sc_earlyz_tile_fifo_size;
2083 unsigned tiling_nbanks;
2084 unsigned tiling_npipes;
2085 unsigned tiling_group_size;
2086 unsigned tile_config;
2087 unsigned backend_map;
2088 unsigned active_simds;
2089 };
2090
2091 struct cayman_asic {
2092 unsigned max_shader_engines;
2093 unsigned max_pipes_per_simd;
2094 unsigned max_tile_pipes;
2095 unsigned max_simds_per_se;
2096 unsigned max_backends_per_se;
2097 unsigned max_texture_channel_caches;
2098 unsigned max_gprs;
2099 unsigned max_threads;
2100 unsigned max_gs_threads;
2101 unsigned max_stack_entries;
2102 unsigned sx_num_of_sets;
2103 unsigned sx_max_export_size;
2104 unsigned sx_max_export_pos_size;
2105 unsigned sx_max_export_smx_size;
2106 unsigned max_hw_contexts;
2107 unsigned sq_num_cf_insts;
2108 unsigned sc_prim_fifo_size;
2109 unsigned sc_hiz_tile_fifo_size;
2110 unsigned sc_earlyz_tile_fifo_size;
2111
2112 unsigned num_shader_engines;
2113 unsigned num_shader_pipes_per_simd;
2114 unsigned num_tile_pipes;
2115 unsigned num_simds_per_se;
2116 unsigned num_backends_per_se;
2117 unsigned backend_disable_mask_per_asic;
2118 unsigned backend_map;
2119 unsigned num_texture_channel_caches;
2120 unsigned mem_max_burst_length_bytes;
2121 unsigned mem_row_size_in_kb;
2122 unsigned shader_engine_tile_size;
2123 unsigned num_gpus;
2124 unsigned multi_gpu_tile_size;
2125
2126 unsigned tile_config;
2127 unsigned active_simds;
2128 };
2129
2130 struct si_asic {
2131 unsigned max_shader_engines;
2132 unsigned max_tile_pipes;
2133 unsigned max_cu_per_sh;
2134 unsigned max_sh_per_se;
2135 unsigned max_backends_per_se;
2136 unsigned max_texture_channel_caches;
2137 unsigned max_gprs;
2138 unsigned max_gs_threads;
2139 unsigned max_hw_contexts;
2140 unsigned sc_prim_fifo_size_frontend;
2141 unsigned sc_prim_fifo_size_backend;
2142 unsigned sc_hiz_tile_fifo_size;
2143 unsigned sc_earlyz_tile_fifo_size;
2144
2145 unsigned num_tile_pipes;
2146 unsigned backend_enable_mask;
2147 unsigned backend_disable_mask_per_asic;
2148 unsigned backend_map;
2149 unsigned num_texture_channel_caches;
2150 unsigned mem_max_burst_length_bytes;
2151 unsigned mem_row_size_in_kb;
2152 unsigned shader_engine_tile_size;
2153 unsigned num_gpus;
2154 unsigned multi_gpu_tile_size;
2155
2156 unsigned tile_config;
2157 uint32_t tile_mode_array[32];
2158 uint32_t active_cus;
2159 };
2160
2161 struct cik_asic {
2162 unsigned max_shader_engines;
2163 unsigned max_tile_pipes;
2164 unsigned max_cu_per_sh;
2165 unsigned max_sh_per_se;
2166 unsigned max_backends_per_se;
2167 unsigned max_texture_channel_caches;
2168 unsigned max_gprs;
2169 unsigned max_gs_threads;
2170 unsigned max_hw_contexts;
2171 unsigned sc_prim_fifo_size_frontend;
2172 unsigned sc_prim_fifo_size_backend;
2173 unsigned sc_hiz_tile_fifo_size;
2174 unsigned sc_earlyz_tile_fifo_size;
2175
2176 unsigned num_tile_pipes;
2177 unsigned backend_enable_mask;
2178 unsigned backend_disable_mask_per_asic;
2179 unsigned backend_map;
2180 unsigned num_texture_channel_caches;
2181 unsigned mem_max_burst_length_bytes;
2182 unsigned mem_row_size_in_kb;
2183 unsigned shader_engine_tile_size;
2184 unsigned num_gpus;
2185 unsigned multi_gpu_tile_size;
2186
2187 unsigned tile_config;
2188 uint32_t tile_mode_array[32];
2189 uint32_t macrotile_mode_array[16];
2190 uint32_t active_cus;
2191 };
2192
2193 union radeon_asic_config {
2194 struct r300_asic r300;
2195 struct r100_asic r100;
2196 struct r600_asic r600;
2197 struct rv770_asic rv770;
2198 struct evergreen_asic evergreen;
2199 struct cayman_asic cayman;
2200 struct si_asic si;
2201 struct cik_asic cik;
2202 };
2203
2204 /*
2205 * asic initizalization from radeon_asic.c
2206 */
2207 void radeon_agp_disable(struct radeon_device *rdev);
2208 int radeon_asic_init(struct radeon_device *rdev);
2209
2210
2211 /*
2212 * IOCTL.
2213 */
2214 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2215 struct drm_file *filp);
2216 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2217 struct drm_file *filp);
2218 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2219 struct drm_file *filp);
2220 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *file_priv);
2222 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *file_priv);
2224 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *file_priv);
2226 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *file_priv);
2228 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *filp);
2230 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *filp);
2232 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *filp);
2234 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *filp);
2236 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *filp);
2238 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *filp);
2240 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2241 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2242 struct drm_file *filp);
2243 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2244 struct drm_file *filp);
2245
2246 /* VRAM scratch page for HDP bug, default vram page */
2247 struct r600_vram_scratch {
2248 struct radeon_bo *robj;
2249 volatile uint32_t *ptr;
2250 u64 gpu_addr;
2251 };
2252
2253 /*
2254 * ACPI
2255 */
2256 struct radeon_atif_notification_cfg {
2257 bool enabled;
2258 int command_code;
2259 };
2260
2261 struct radeon_atif_notifications {
2262 bool display_switch;
2263 bool expansion_mode_change;
2264 bool thermal_state;
2265 bool forced_power_state;
2266 bool system_power_state;
2267 bool display_conf_change;
2268 bool px_gfx_switch;
2269 bool brightness_change;
2270 bool dgpu_display_event;
2271 };
2272
2273 struct radeon_atif_functions {
2274 bool system_params;
2275 bool sbios_requests;
2276 bool select_active_disp;
2277 bool lid_state;
2278 bool get_tv_standard;
2279 bool set_tv_standard;
2280 bool get_panel_expansion_mode;
2281 bool set_panel_expansion_mode;
2282 bool temperature_change;
2283 bool graphics_device_types;
2284 };
2285
2286 struct radeon_atif {
2287 struct radeon_atif_notifications notifications;
2288 struct radeon_atif_functions functions;
2289 struct radeon_atif_notification_cfg notification_cfg;
2290 struct radeon_encoder *encoder_for_bl;
2291 };
2292
2293 struct radeon_atcs_functions {
2294 bool get_ext_state;
2295 bool pcie_perf_req;
2296 bool pcie_dev_rdy;
2297 bool pcie_bus_width;
2298 };
2299
2300 struct radeon_atcs {
2301 struct radeon_atcs_functions functions;
2302 };
2303
2304 /*
2305 * Core structure, functions and helpers.
2306 */
2307 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2308 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2309
2310 struct radeon_device {
2311 struct device *dev;
2312 struct drm_device *ddev;
2313 struct pci_dev *pdev;
2314 struct rw_semaphore exclusive_lock;
2315 /* ASIC */
2316 union radeon_asic_config config;
2317 enum radeon_family family;
2318 unsigned long flags;
2319 int usec_timeout;
2320 enum radeon_pll_errata pll_errata;
2321 int num_gb_pipes;
2322 int num_z_pipes;
2323 int disp_priority;
2324 /* BIOS */
2325 uint8_t *bios;
2326 bool is_atom_bios;
2327 uint16_t bios_header_start;
2328 struct radeon_bo *stollen_vga_memory;
2329 /* Register mmio */
2330 resource_size_t rmmio_base;
2331 resource_size_t rmmio_size;
2332 /* protects concurrent MM_INDEX/DATA based register access */
2333 spinlock_t mmio_idx_lock;
2334 /* protects concurrent SMC based register access */
2335 spinlock_t smc_idx_lock;
2336 /* protects concurrent PLL register access */
2337 spinlock_t pll_idx_lock;
2338 /* protects concurrent MC register access */
2339 spinlock_t mc_idx_lock;
2340 /* protects concurrent PCIE register access */
2341 spinlock_t pcie_idx_lock;
2342 /* protects concurrent PCIE_PORT register access */
2343 spinlock_t pciep_idx_lock;
2344 /* protects concurrent PIF register access */
2345 spinlock_t pif_idx_lock;
2346 /* protects concurrent CG register access */
2347 spinlock_t cg_idx_lock;
2348 /* protects concurrent UVD register access */
2349 spinlock_t uvd_idx_lock;
2350 /* protects concurrent RCU register access */
2351 spinlock_t rcu_idx_lock;
2352 /* protects concurrent DIDT register access */
2353 spinlock_t didt_idx_lock;
2354 /* protects concurrent ENDPOINT (audio) register access */
2355 spinlock_t end_idx_lock;
2356 void __iomem *rmmio;
2357 radeon_rreg_t mc_rreg;
2358 radeon_wreg_t mc_wreg;
2359 radeon_rreg_t pll_rreg;
2360 radeon_wreg_t pll_wreg;
2361 uint32_t pcie_reg_mask;
2362 radeon_rreg_t pciep_rreg;
2363 radeon_wreg_t pciep_wreg;
2364 /* io port */
2365 void __iomem *rio_mem;
2366 resource_size_t rio_mem_size;
2367 struct radeon_clock clock;
2368 struct radeon_mc mc;
2369 struct radeon_gart gart;
2370 struct radeon_mode_info mode_info;
2371 struct radeon_scratch scratch;
2372 struct radeon_doorbell doorbell;
2373 struct radeon_mman mman;
2374 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2375 wait_queue_head_t fence_queue;
2376 unsigned fence_context;
2377 struct mutex ring_lock;
2378 struct radeon_ring ring[RADEON_NUM_RINGS];
2379 bool ib_pool_ready;
2380 struct radeon_sa_manager ring_tmp_bo;
2381 struct radeon_irq irq;
2382 struct radeon_asic *asic;
2383 struct radeon_gem gem;
2384 struct radeon_pm pm;
2385 struct radeon_uvd uvd;
2386 struct radeon_vce vce;
2387 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2388 struct radeon_wb wb;
2389 struct radeon_dummy_page dummy_page;
2390 bool shutdown;
2391 bool suspend;
2392 bool need_dma32;
2393 bool accel_working;
2394 bool fastfb_working; /* IGP feature*/
2395 bool needs_reset, in_reset;
2396 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2397 const struct firmware *me_fw; /* all family ME firmware */
2398 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2399 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2400 const struct firmware *mc_fw; /* NI MC firmware */
2401 const struct firmware *ce_fw; /* SI CE firmware */
2402 const struct firmware *mec_fw; /* CIK MEC firmware */
2403 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2404 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2405 const struct firmware *smc_fw; /* SMC firmware */
2406 const struct firmware *uvd_fw; /* UVD firmware */
2407 const struct firmware *vce_fw; /* VCE firmware */
2408 bool new_fw;
2409 struct r600_vram_scratch vram_scratch;
2410 int msi_enabled; /* msi enabled */
2411 struct r600_ih ih; /* r6/700 interrupt ring */
2412 struct radeon_rlc rlc;
2413 struct radeon_mec mec;
2414 struct work_struct hotplug_work;
2415 struct work_struct dp_work;
2416 struct work_struct audio_work;
2417 int num_crtc; /* number of crtcs */
2418 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2419 bool has_uvd;
2420 struct r600_audio audio; /* audio stuff */
2421 struct notifier_block acpi_nb;
2422 /* only one userspace can use Hyperz features or CMASK at a time */
2423 struct drm_file *hyperz_filp;
2424 struct drm_file *cmask_filp;
2425 /* i2c buses */
2426 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2427 /* debugfs */
2428 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2429 unsigned debugfs_count;
2430 /* virtual memory */
2431 struct radeon_vm_manager vm_manager;
2432 struct mutex gpu_clock_mutex;
2433 /* memory stats */
2434 atomic64_t vram_usage;
2435 atomic64_t gtt_usage;
2436 atomic64_t num_bytes_moved;
2437 atomic_t gpu_reset_counter;
2438 /* ACPI interface */
2439 struct radeon_atif atif;
2440 struct radeon_atcs atcs;
2441 /* srbm instance registers */
2442 struct mutex srbm_mutex;
2443 /* GRBM index mutex. Protects concurrents access to GRBM index */
2444 struct mutex grbm_idx_mutex;
2445 /* clock, powergating flags */
2446 u32 cg_flags;
2447 u32 pg_flags;
2448
2449 struct dev_pm_domain vga_pm_domain;
2450 bool have_disp_power_ref;
2451 u32 px_quirk_flags;
2452
2453 /* tracking pinned memory */
2454 u64 vram_pin_size;
2455 u64 gart_pin_size;
2456
2457 /* amdkfd interface */
2458 struct kfd_dev *kfd;
2459 struct radeon_sa_manager kfd_bo;
2460
2461 struct mutex mn_lock;
2462 DECLARE_HASHTABLE(mn_hash, 7);
2463 };
2464
2465 bool radeon_is_px(struct drm_device *dev);
2466 int radeon_device_init(struct radeon_device *rdev,
2467 struct drm_device *ddev,
2468 struct pci_dev *pdev,
2469 uint32_t flags);
2470 void radeon_device_fini(struct radeon_device *rdev);
2471 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2472
2473 #define RADEON_MIN_MMIO_SIZE 0x10000
2474
2475 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2476 bool always_indirect)
2477 {
2478 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2479 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2480 return readl(((void __iomem *)rdev->rmmio) + reg);
2481 else {
2482 unsigned long flags;
2483 uint32_t ret;
2484
2485 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2486 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2487 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2488 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2489
2490 return ret;
2491 }
2492 }
2493
2494 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2495 bool always_indirect)
2496 {
2497 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2498 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2499 else {
2500 unsigned long flags;
2501
2502 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2503 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2504 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2505 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2506 }
2507 }
2508
2509 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2510 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2511
2512 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2513 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2514
2515 /*
2516 * Cast helper
2517 */
2518 extern const struct fence_ops radeon_fence_ops;
2519
2520 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2521 {
2522 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2523
2524 if (__f->base.ops == &radeon_fence_ops)
2525 return __f;
2526
2527 return NULL;
2528 }
2529
2530 /*
2531 * Registers read & write functions.
2532 */
2533 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2534 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2535 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2536 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2537 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2538 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2539 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2540 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2541 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2542 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2543 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2544 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2545 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2546 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2547 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2548 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2549 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2550 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2551 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2552 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2553 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2554 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2555 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2556 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2557 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2558 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2559 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2560 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2561 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2562 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2563 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2564 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2565 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2566 #define WREG32_P(reg, val, mask) \
2567 do { \
2568 uint32_t tmp_ = RREG32(reg); \
2569 tmp_ &= (mask); \
2570 tmp_ |= ((val) & ~(mask)); \
2571 WREG32(reg, tmp_); \
2572 } while (0)
2573 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2574 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2575 #define WREG32_PLL_P(reg, val, mask) \
2576 do { \
2577 uint32_t tmp_ = RREG32_PLL(reg); \
2578 tmp_ &= (mask); \
2579 tmp_ |= ((val) & ~(mask)); \
2580 WREG32_PLL(reg, tmp_); \
2581 } while (0)
2582 #define WREG32_SMC_P(reg, val, mask) \
2583 do { \
2584 uint32_t tmp_ = RREG32_SMC(reg); \
2585 tmp_ &= (mask); \
2586 tmp_ |= ((val) & ~(mask)); \
2587 WREG32_SMC(reg, tmp_); \
2588 } while (0)
2589 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2590 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2591 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2592
2593 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2594 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2595
2596 /*
2597 * Indirect registers accessor
2598 */
2599 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2600 {
2601 unsigned long flags;
2602 uint32_t r;
2603
2604 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2605 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2606 r = RREG32(RADEON_PCIE_DATA);
2607 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2608 return r;
2609 }
2610
2611 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2612 {
2613 unsigned long flags;
2614
2615 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2616 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2617 WREG32(RADEON_PCIE_DATA, (v));
2618 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2619 }
2620
2621 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2622 {
2623 unsigned long flags;
2624 u32 r;
2625
2626 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2627 WREG32(TN_SMC_IND_INDEX_0, (reg));
2628 r = RREG32(TN_SMC_IND_DATA_0);
2629 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2630 return r;
2631 }
2632
2633 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2634 {
2635 unsigned long flags;
2636
2637 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2638 WREG32(TN_SMC_IND_INDEX_0, (reg));
2639 WREG32(TN_SMC_IND_DATA_0, (v));
2640 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2641 }
2642
2643 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2644 {
2645 unsigned long flags;
2646 u32 r;
2647
2648 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2649 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2650 r = RREG32(R600_RCU_DATA);
2651 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2652 return r;
2653 }
2654
2655 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2656 {
2657 unsigned long flags;
2658
2659 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2660 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2661 WREG32(R600_RCU_DATA, (v));
2662 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2663 }
2664
2665 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2666 {
2667 unsigned long flags;
2668 u32 r;
2669
2670 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2671 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2672 r = RREG32(EVERGREEN_CG_IND_DATA);
2673 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2674 return r;
2675 }
2676
2677 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2678 {
2679 unsigned long flags;
2680
2681 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2682 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2683 WREG32(EVERGREEN_CG_IND_DATA, (v));
2684 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2685 }
2686
2687 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2688 {
2689 unsigned long flags;
2690 u32 r;
2691
2692 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2693 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2694 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2695 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2696 return r;
2697 }
2698
2699 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2700 {
2701 unsigned long flags;
2702
2703 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2704 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2705 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2706 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2707 }
2708
2709 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2710 {
2711 unsigned long flags;
2712 u32 r;
2713
2714 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2715 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2716 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2717 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2718 return r;
2719 }
2720
2721 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2722 {
2723 unsigned long flags;
2724
2725 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2726 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2727 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2728 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2729 }
2730
2731 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2732 {
2733 unsigned long flags;
2734 u32 r;
2735
2736 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2737 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2738 r = RREG32(R600_UVD_CTX_DATA);
2739 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2740 return r;
2741 }
2742
2743 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2744 {
2745 unsigned long flags;
2746
2747 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2748 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2749 WREG32(R600_UVD_CTX_DATA, (v));
2750 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2751 }
2752
2753
2754 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2755 {
2756 unsigned long flags;
2757 u32 r;
2758
2759 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2760 WREG32(CIK_DIDT_IND_INDEX, (reg));
2761 r = RREG32(CIK_DIDT_IND_DATA);
2762 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2763 return r;
2764 }
2765
2766 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2767 {
2768 unsigned long flags;
2769
2770 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2771 WREG32(CIK_DIDT_IND_INDEX, (reg));
2772 WREG32(CIK_DIDT_IND_DATA, (v));
2773 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2774 }
2775
2776 void r100_pll_errata_after_index(struct radeon_device *rdev);
2777
2778
2779 /*
2780 * ASICs helpers.
2781 */
2782 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2783 (rdev->pdev->device == 0x5969))
2784 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2785 (rdev->family == CHIP_RV200) || \
2786 (rdev->family == CHIP_RS100) || \
2787 (rdev->family == CHIP_RS200) || \
2788 (rdev->family == CHIP_RV250) || \
2789 (rdev->family == CHIP_RV280) || \
2790 (rdev->family == CHIP_RS300))
2791 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2792 (rdev->family == CHIP_RV350) || \
2793 (rdev->family == CHIP_R350) || \
2794 (rdev->family == CHIP_RV380) || \
2795 (rdev->family == CHIP_R420) || \
2796 (rdev->family == CHIP_R423) || \
2797 (rdev->family == CHIP_RV410) || \
2798 (rdev->family == CHIP_RS400) || \
2799 (rdev->family == CHIP_RS480))
2800 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2801 (rdev->ddev->pdev->device == 0x9443) || \
2802 (rdev->ddev->pdev->device == 0x944B) || \
2803 (rdev->ddev->pdev->device == 0x9506) || \
2804 (rdev->ddev->pdev->device == 0x9509) || \
2805 (rdev->ddev->pdev->device == 0x950F) || \
2806 (rdev->ddev->pdev->device == 0x689C) || \
2807 (rdev->ddev->pdev->device == 0x689D))
2808 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2809 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2810 (rdev->family == CHIP_RS690) || \
2811 (rdev->family == CHIP_RS740) || \
2812 (rdev->family >= CHIP_R600))
2813 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2814 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2815 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2816 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2817 (rdev->flags & RADEON_IS_IGP))
2818 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2819 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2820 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2821 (rdev->flags & RADEON_IS_IGP))
2822 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2823 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2824 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2825 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2826 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2827 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2828 (rdev->family == CHIP_MULLINS))
2829
2830 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2831 (rdev->ddev->pdev->device == 0x6850) || \
2832 (rdev->ddev->pdev->device == 0x6858) || \
2833 (rdev->ddev->pdev->device == 0x6859) || \
2834 (rdev->ddev->pdev->device == 0x6840) || \
2835 (rdev->ddev->pdev->device == 0x6841) || \
2836 (rdev->ddev->pdev->device == 0x6842) || \
2837 (rdev->ddev->pdev->device == 0x6843))
2838
2839 /*
2840 * BIOS helpers.
2841 */
2842 #define RBIOS8(i) (rdev->bios[i])
2843 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2844 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2845
2846 int radeon_combios_init(struct radeon_device *rdev);
2847 void radeon_combios_fini(struct radeon_device *rdev);
2848 int radeon_atombios_init(struct radeon_device *rdev);
2849 void radeon_atombios_fini(struct radeon_device *rdev);
2850
2851
2852 /*
2853 * RING helpers.
2854 */
2855
2856 /**
2857 * radeon_ring_write - write a value to the ring
2858 *
2859 * @ring: radeon_ring structure holding ring information
2860 * @v: dword (dw) value to write
2861 *
2862 * Write a value to the requested ring buffer (all asics).
2863 */
2864 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2865 {
2866 if (ring->count_dw <= 0)
2867 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2868
2869 ring->ring[ring->wptr++] = v;
2870 ring->wptr &= ring->ptr_mask;
2871 ring->count_dw--;
2872 ring->ring_free_dw--;
2873 }
2874
2875 /*
2876 * ASICs macro.
2877 */
2878 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2879 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2880 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2881 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2882 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2883 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2884 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2885 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2886 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2887 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2888 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2889 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2890 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2891 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2892 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2893 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2894 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2895 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2896 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2897 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2898 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2899 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2900 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2901 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2902 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2903 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2904 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2905 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2906 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2907 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2908 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2909 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2910 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2911 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2912 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2913 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2914 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2915 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2916 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2917 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2918 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2919 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2920 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2921 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2922 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2923 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2924 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2925 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2926 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2927 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2928 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2929 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2930 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2931 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2932 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2933 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2934 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2935 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2936 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2937 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2938 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2939 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2940 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2941 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2942 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2943 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2944 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2945 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2946 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2947 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2948 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2949 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2950 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2951 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2952 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2953 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2954 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2955 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2956 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2957 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2958 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2959 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2960 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2961 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2962 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2963 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2964 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2965 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2966 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2967 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2968 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2969
2970 /* Common functions */
2971 /* AGP */
2972 extern int radeon_gpu_reset(struct radeon_device *rdev);
2973 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2974 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2975 extern void radeon_agp_disable(struct radeon_device *rdev);
2976 extern int radeon_modeset_init(struct radeon_device *rdev);
2977 extern void radeon_modeset_fini(struct radeon_device *rdev);
2978 extern bool radeon_card_posted(struct radeon_device *rdev);
2979 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2980 extern void radeon_update_display_priority(struct radeon_device *rdev);
2981 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2982 extern void radeon_scratch_init(struct radeon_device *rdev);
2983 extern void radeon_wb_fini(struct radeon_device *rdev);
2984 extern int radeon_wb_init(struct radeon_device *rdev);
2985 extern void radeon_wb_disable(struct radeon_device *rdev);
2986 extern void radeon_surface_init(struct radeon_device *rdev);
2987 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2988 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2989 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2990 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2991 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2992 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2993 uint32_t flags);
2994 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2995 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2996 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2997 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2998 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2999 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
3000 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
3001 extern void radeon_program_register_sequence(struct radeon_device *rdev,
3002 const u32 *registers,
3003 const u32 array_size);
3004
3005 /*
3006 * vm
3007 */
3008 int radeon_vm_manager_init(struct radeon_device *rdev);
3009 void radeon_vm_manager_fini(struct radeon_device *rdev);
3010 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
3011 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
3012 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
3013 struct radeon_vm *vm,
3014 struct list_head *head);
3015 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
3016 struct radeon_vm *vm, int ring);
3017 void radeon_vm_flush(struct radeon_device *rdev,
3018 struct radeon_vm *vm,
3019 int ring, struct radeon_fence *fence);
3020 void radeon_vm_fence(struct radeon_device *rdev,
3021 struct radeon_vm *vm,
3022 struct radeon_fence *fence);
3023 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
3024 int radeon_vm_update_page_directory(struct radeon_device *rdev,
3025 struct radeon_vm *vm);
3026 int radeon_vm_clear_freed(struct radeon_device *rdev,
3027 struct radeon_vm *vm);
3028 int radeon_vm_clear_invalids(struct radeon_device *rdev,
3029 struct radeon_vm *vm);
3030 int radeon_vm_bo_update(struct radeon_device *rdev,
3031 struct radeon_bo_va *bo_va,
3032 struct ttm_mem_reg *mem);
3033 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
3034 struct radeon_bo *bo);
3035 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
3036 struct radeon_bo *bo);
3037 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
3038 struct radeon_vm *vm,
3039 struct radeon_bo *bo);
3040 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
3041 struct radeon_bo_va *bo_va,
3042 uint64_t offset,
3043 uint32_t flags);
3044 void radeon_vm_bo_rmv(struct radeon_device *rdev,
3045 struct radeon_bo_va *bo_va);
3046
3047 /* audio */
3048 void r600_audio_update_hdmi(struct work_struct *work);
3049 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
3050 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
3051 void r600_audio_enable(struct radeon_device *rdev,
3052 struct r600_audio_pin *pin,
3053 u8 enable_mask);
3054 void dce6_audio_enable(struct radeon_device *rdev,
3055 struct r600_audio_pin *pin,
3056 u8 enable_mask);
3057
3058 /*
3059 * R600 vram scratch functions
3060 */
3061 int r600_vram_scratch_init(struct radeon_device *rdev);
3062 void r600_vram_scratch_fini(struct radeon_device *rdev);
3063
3064 /*
3065 * r600 cs checking helper
3066 */
3067 unsigned r600_mip_minify(unsigned size, unsigned level);
3068 bool r600_fmt_is_valid_color(u32 format);
3069 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3070 int r600_fmt_get_blocksize(u32 format);
3071 int r600_fmt_get_nblocksx(u32 format, u32 w);
3072 int r600_fmt_get_nblocksy(u32 format, u32 h);
3073
3074 /*
3075 * r600 functions used by radeon_encoder.c
3076 */
3077 struct radeon_hdmi_acr {
3078 u32 clock;
3079
3080 int n_32khz;
3081 int cts_32khz;
3082
3083 int n_44_1khz;
3084 int cts_44_1khz;
3085
3086 int n_48khz;
3087 int cts_48khz;
3088
3089 };
3090
3091 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3092
3093 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3094 u32 tiling_pipe_num,
3095 u32 max_rb_num,
3096 u32 total_max_rb_num,
3097 u32 enabled_rb_mask);
3098
3099 /*
3100 * evergreen functions used by radeon_encoder.c
3101 */
3102
3103 extern int ni_init_microcode(struct radeon_device *rdev);
3104 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3105
3106 /* radeon_acpi.c */
3107 #if defined(CONFIG_ACPI)
3108 extern int radeon_acpi_init(struct radeon_device *rdev);
3109 extern void radeon_acpi_fini(struct radeon_device *rdev);
3110 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3111 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3112 u8 perf_req, bool advertise);
3113 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3114 #else
3115 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3116 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3117 #endif
3118
3119 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3120 struct radeon_cs_packet *pkt,
3121 unsigned idx);
3122 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3123 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3124 struct radeon_cs_packet *pkt);
3125 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3126 struct radeon_bo_list **cs_reloc,
3127 int nomm);
3128 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3129 uint32_t *vline_start_end,
3130 uint32_t *vline_status);
3131
3132 #include "radeon_object.h"
3133
3134 #endif
Linux kernel - Deliverables
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