2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #ifndef __RADEON_ASIC_H__
29 #define __RADEON_ASIC_H__
34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device
*rdev
);
35 void radeon_legacy_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device
*rdev
);
37 void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
39 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
);
40 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
41 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
);
42 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
, uint32_t mem_clock
);
43 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
45 void atombios_set_backlight_level(struct radeon_encoder
*radeon_encoder
, u8 level
);
46 u8
atombios_get_backlight_level(struct radeon_encoder
*radeon_encoder
);
47 void radeon_legacy_set_backlight_level(struct radeon_encoder
*radeon_encoder
, u8 level
);
48 u8
radeon_legacy_get_backlight_level(struct radeon_encoder
*radeon_encoder
);
51 * r100,rv100,rs100,rv200,rs200
61 int r100_init(struct radeon_device
*rdev
);
62 void r100_fini(struct radeon_device
*rdev
);
63 int r100_suspend(struct radeon_device
*rdev
);
64 int r100_resume(struct radeon_device
*rdev
);
65 void r100_vga_set_state(struct radeon_device
*rdev
, bool state
);
66 bool r100_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
67 int r100_asic_reset(struct radeon_device
*rdev
);
68 u32
r100_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
69 void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
);
70 void r100_pci_gart_set_page(struct radeon_device
*rdev
, unsigned i
,
71 uint64_t addr
, uint32_t flags
);
72 void r100_ring_start(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
73 int r100_irq_set(struct radeon_device
*rdev
);
74 int r100_irq_process(struct radeon_device
*rdev
);
75 void r100_fence_ring_emit(struct radeon_device
*rdev
,
76 struct radeon_fence
*fence
);
77 bool r100_semaphore_ring_emit(struct radeon_device
*rdev
,
78 struct radeon_ring
*cp
,
79 struct radeon_semaphore
*semaphore
,
81 int r100_cs_parse(struct radeon_cs_parser
*p
);
82 void r100_pll_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
83 uint32_t r100_pll_rreg(struct radeon_device
*rdev
, uint32_t reg
);
84 struct radeon_fence
*r100_copy_blit(struct radeon_device
*rdev
,
87 unsigned num_gpu_pages
,
88 struct reservation_object
*resv
);
89 int r100_set_surface_reg(struct radeon_device
*rdev
, int reg
,
90 uint32_t tiling_flags
, uint32_t pitch
,
91 uint32_t offset
, uint32_t obj_size
);
92 void r100_clear_surface_reg(struct radeon_device
*rdev
, int reg
);
93 void r100_bandwidth_update(struct radeon_device
*rdev
);
94 void r100_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
95 int r100_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
96 void r100_hpd_init(struct radeon_device
*rdev
);
97 void r100_hpd_fini(struct radeon_device
*rdev
);
98 bool r100_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
99 void r100_hpd_set_polarity(struct radeon_device
*rdev
,
100 enum radeon_hpd_id hpd
);
101 int r100_debugfs_rbbm_init(struct radeon_device
*rdev
);
102 int r100_debugfs_cp_init(struct radeon_device
*rdev
);
103 void r100_cp_disable(struct radeon_device
*rdev
);
104 int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
);
105 void r100_cp_fini(struct radeon_device
*rdev
);
106 int r100_pci_gart_init(struct radeon_device
*rdev
);
107 void r100_pci_gart_fini(struct radeon_device
*rdev
);
108 int r100_pci_gart_enable(struct radeon_device
*rdev
);
109 void r100_pci_gart_disable(struct radeon_device
*rdev
);
110 int r100_debugfs_mc_info_init(struct radeon_device
*rdev
);
111 int r100_gui_wait_for_idle(struct radeon_device
*rdev
);
112 int r100_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
113 void r100_irq_disable(struct radeon_device
*rdev
);
114 void r100_mc_stop(struct radeon_device
*rdev
, struct r100_mc_save
*save
);
115 void r100_mc_resume(struct radeon_device
*rdev
, struct r100_mc_save
*save
);
116 void r100_vram_init_sizes(struct radeon_device
*rdev
);
117 int r100_cp_reset(struct radeon_device
*rdev
);
118 void r100_vga_render_disable(struct radeon_device
*rdev
);
119 void r100_restore_sanity(struct radeon_device
*rdev
);
120 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser
*p
,
121 struct radeon_cs_packet
*pkt
,
122 struct radeon_bo
*robj
);
123 int r100_cs_parse_packet0(struct radeon_cs_parser
*p
,
124 struct radeon_cs_packet
*pkt
,
125 const unsigned *auth
, unsigned n
,
126 radeon_packet0_check_t check
);
127 int r100_cs_packet_parse(struct radeon_cs_parser
*p
,
128 struct radeon_cs_packet
*pkt
,
130 void r100_enable_bm(struct radeon_device
*rdev
);
131 void r100_set_common_regs(struct radeon_device
*rdev
);
132 void r100_bm_disable(struct radeon_device
*rdev
);
133 extern bool r100_gui_idle(struct radeon_device
*rdev
);
134 extern void r100_pm_misc(struct radeon_device
*rdev
);
135 extern void r100_pm_prepare(struct radeon_device
*rdev
);
136 extern void r100_pm_finish(struct radeon_device
*rdev
);
137 extern void r100_pm_init_profile(struct radeon_device
*rdev
);
138 extern void r100_pm_get_dynpm_state(struct radeon_device
*rdev
);
139 extern void r100_page_flip(struct radeon_device
*rdev
, int crtc
,
141 extern bool r100_page_flip_pending(struct radeon_device
*rdev
, int crtc
);
142 extern void r100_wait_for_vblank(struct radeon_device
*rdev
, int crtc
);
143 extern int r100_mc_wait_for_idle(struct radeon_device
*rdev
);
145 u32
r100_gfx_get_rptr(struct radeon_device
*rdev
,
146 struct radeon_ring
*ring
);
147 u32
r100_gfx_get_wptr(struct radeon_device
*rdev
,
148 struct radeon_ring
*ring
);
149 void r100_gfx_set_wptr(struct radeon_device
*rdev
,
150 struct radeon_ring
*ring
);
153 * r200,rv250,rs300,rv280
155 struct radeon_fence
*r200_copy_dma(struct radeon_device
*rdev
,
158 unsigned num_gpu_pages
,
159 struct reservation_object
*resv
);
160 void r200_set_safe_registers(struct radeon_device
*rdev
);
163 * r300,r350,rv350,rv380
165 extern int r300_init(struct radeon_device
*rdev
);
166 extern void r300_fini(struct radeon_device
*rdev
);
167 extern int r300_suspend(struct radeon_device
*rdev
);
168 extern int r300_resume(struct radeon_device
*rdev
);
169 extern int r300_asic_reset(struct radeon_device
*rdev
);
170 extern void r300_ring_start(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
171 extern void r300_fence_ring_emit(struct radeon_device
*rdev
,
172 struct radeon_fence
*fence
);
173 extern int r300_cs_parse(struct radeon_cs_parser
*p
);
174 extern void rv370_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
175 extern void rv370_pcie_gart_set_page(struct radeon_device
*rdev
, unsigned i
,
176 uint64_t addr
, uint32_t flags
);
177 extern void rv370_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
);
178 extern int rv370_get_pcie_lanes(struct radeon_device
*rdev
);
179 extern void r300_set_reg_safe(struct radeon_device
*rdev
);
180 extern void r300_mc_program(struct radeon_device
*rdev
);
181 extern void r300_mc_init(struct radeon_device
*rdev
);
182 extern void r300_clock_startup(struct radeon_device
*rdev
);
183 extern int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
184 extern int rv370_pcie_gart_init(struct radeon_device
*rdev
);
185 extern void rv370_pcie_gart_fini(struct radeon_device
*rdev
);
186 extern int rv370_pcie_gart_enable(struct radeon_device
*rdev
);
187 extern void rv370_pcie_gart_disable(struct radeon_device
*rdev
);
188 extern int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
193 extern int r420_init(struct radeon_device
*rdev
);
194 extern void r420_fini(struct radeon_device
*rdev
);
195 extern int r420_suspend(struct radeon_device
*rdev
);
196 extern int r420_resume(struct radeon_device
*rdev
);
197 extern void r420_pm_init_profile(struct radeon_device
*rdev
);
198 extern u32
r420_mc_rreg(struct radeon_device
*rdev
, u32 reg
);
199 extern void r420_mc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
);
200 extern int r420_debugfs_pipes_info_init(struct radeon_device
*rdev
);
201 extern void r420_pipes_init(struct radeon_device
*rdev
);
206 extern int rs400_init(struct radeon_device
*rdev
);
207 extern void rs400_fini(struct radeon_device
*rdev
);
208 extern int rs400_suspend(struct radeon_device
*rdev
);
209 extern int rs400_resume(struct radeon_device
*rdev
);
210 void rs400_gart_tlb_flush(struct radeon_device
*rdev
);
211 void rs400_gart_set_page(struct radeon_device
*rdev
, unsigned i
,
212 uint64_t addr
, uint32_t flags
);
213 uint32_t rs400_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
214 void rs400_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
215 int rs400_gart_init(struct radeon_device
*rdev
);
216 int rs400_gart_enable(struct radeon_device
*rdev
);
217 void rs400_gart_adjust_size(struct radeon_device
*rdev
);
218 void rs400_gart_disable(struct radeon_device
*rdev
);
219 void rs400_gart_fini(struct radeon_device
*rdev
);
220 extern int rs400_mc_wait_for_idle(struct radeon_device
*rdev
);
225 extern int rs600_asic_reset(struct radeon_device
*rdev
);
226 extern int rs600_init(struct radeon_device
*rdev
);
227 extern void rs600_fini(struct radeon_device
*rdev
);
228 extern int rs600_suspend(struct radeon_device
*rdev
);
229 extern int rs600_resume(struct radeon_device
*rdev
);
230 int rs600_irq_set(struct radeon_device
*rdev
);
231 int rs600_irq_process(struct radeon_device
*rdev
);
232 void rs600_irq_disable(struct radeon_device
*rdev
);
233 u32
rs600_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
234 void rs600_gart_tlb_flush(struct radeon_device
*rdev
);
235 void rs600_gart_set_page(struct radeon_device
*rdev
, unsigned i
,
236 uint64_t addr
, uint32_t flags
);
237 uint32_t rs600_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
238 void rs600_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
239 void rs600_bandwidth_update(struct radeon_device
*rdev
);
240 void rs600_hpd_init(struct radeon_device
*rdev
);
241 void rs600_hpd_fini(struct radeon_device
*rdev
);
242 bool rs600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
243 void rs600_hpd_set_polarity(struct radeon_device
*rdev
,
244 enum radeon_hpd_id hpd
);
245 extern void rs600_pm_misc(struct radeon_device
*rdev
);
246 extern void rs600_pm_prepare(struct radeon_device
*rdev
);
247 extern void rs600_pm_finish(struct radeon_device
*rdev
);
248 extern void rs600_page_flip(struct radeon_device
*rdev
, int crtc
,
250 extern bool rs600_page_flip_pending(struct radeon_device
*rdev
, int crtc
);
251 void rs600_set_safe_registers(struct radeon_device
*rdev
);
252 extern void avivo_wait_for_vblank(struct radeon_device
*rdev
, int crtc
);
253 extern int rs600_mc_wait_for_idle(struct radeon_device
*rdev
);
258 int rs690_init(struct radeon_device
*rdev
);
259 void rs690_fini(struct radeon_device
*rdev
);
260 int rs690_resume(struct radeon_device
*rdev
);
261 int rs690_suspend(struct radeon_device
*rdev
);
262 uint32_t rs690_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
263 void rs690_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
264 void rs690_bandwidth_update(struct radeon_device
*rdev
);
265 void rs690_line_buffer_adjust(struct radeon_device
*rdev
,
266 struct drm_display_mode
*mode1
,
267 struct drm_display_mode
*mode2
);
268 extern int rs690_mc_wait_for_idle(struct radeon_device
*rdev
);
273 struct rv515_mc_save
{
274 u32 vga_render_control
;
276 bool crtc_enabled
[2];
279 int rv515_init(struct radeon_device
*rdev
);
280 void rv515_fini(struct radeon_device
*rdev
);
281 uint32_t rv515_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
282 void rv515_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
283 void rv515_ring_start(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
284 void rv515_bandwidth_update(struct radeon_device
*rdev
);
285 int rv515_resume(struct radeon_device
*rdev
);
286 int rv515_suspend(struct radeon_device
*rdev
);
287 void rv515_bandwidth_avivo_update(struct radeon_device
*rdev
);
288 void rv515_vga_render_disable(struct radeon_device
*rdev
);
289 void rv515_set_safe_registers(struct radeon_device
*rdev
);
290 void rv515_mc_stop(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
291 void rv515_mc_resume(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
292 void rv515_clock_startup(struct radeon_device
*rdev
);
293 void rv515_debugfs(struct radeon_device
*rdev
);
294 int rv515_mc_wait_for_idle(struct radeon_device
*rdev
);
297 * r520,rv530,rv560,rv570,r580
299 int r520_init(struct radeon_device
*rdev
);
300 int r520_resume(struct radeon_device
*rdev
);
301 int r520_mc_wait_for_idle(struct radeon_device
*rdev
);
304 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
306 int r600_init(struct radeon_device
*rdev
);
307 void r600_fini(struct radeon_device
*rdev
);
308 int r600_suspend(struct radeon_device
*rdev
);
309 int r600_resume(struct radeon_device
*rdev
);
310 void r600_vga_set_state(struct radeon_device
*rdev
, bool state
);
311 int r600_wb_init(struct radeon_device
*rdev
);
312 void r600_wb_fini(struct radeon_device
*rdev
);
313 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
314 uint32_t r600_pciep_rreg(struct radeon_device
*rdev
, uint32_t reg
);
315 void r600_pciep_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
316 int r600_cs_parse(struct radeon_cs_parser
*p
);
317 int r600_dma_cs_parse(struct radeon_cs_parser
*p
);
318 void r600_fence_ring_emit(struct radeon_device
*rdev
,
319 struct radeon_fence
*fence
);
320 bool r600_semaphore_ring_emit(struct radeon_device
*rdev
,
321 struct radeon_ring
*cp
,
322 struct radeon_semaphore
*semaphore
,
324 void r600_dma_fence_ring_emit(struct radeon_device
*rdev
,
325 struct radeon_fence
*fence
);
326 bool r600_dma_semaphore_ring_emit(struct radeon_device
*rdev
,
327 struct radeon_ring
*ring
,
328 struct radeon_semaphore
*semaphore
,
330 void r600_dma_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
331 bool r600_dma_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
332 bool r600_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
333 int r600_asic_reset(struct radeon_device
*rdev
);
334 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
335 uint32_t tiling_flags
, uint32_t pitch
,
336 uint32_t offset
, uint32_t obj_size
);
337 void r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
);
338 int r600_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
339 int r600_dma_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
340 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
341 int r600_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
342 int r600_dma_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
343 struct radeon_fence
*r600_copy_cpdma(struct radeon_device
*rdev
,
344 uint64_t src_offset
, uint64_t dst_offset
,
345 unsigned num_gpu_pages
,
346 struct reservation_object
*resv
);
347 struct radeon_fence
*r600_copy_dma(struct radeon_device
*rdev
,
348 uint64_t src_offset
, uint64_t dst_offset
,
349 unsigned num_gpu_pages
,
350 struct reservation_object
*resv
);
351 void r600_hpd_init(struct radeon_device
*rdev
);
352 void r600_hpd_fini(struct radeon_device
*rdev
);
353 bool r600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
354 void r600_hpd_set_polarity(struct radeon_device
*rdev
,
355 enum radeon_hpd_id hpd
);
356 extern void r600_mmio_hdp_flush(struct radeon_device
*rdev
);
357 extern bool r600_gui_idle(struct radeon_device
*rdev
);
358 extern void r600_pm_misc(struct radeon_device
*rdev
);
359 extern void r600_pm_init_profile(struct radeon_device
*rdev
);
360 extern void rs780_pm_init_profile(struct radeon_device
*rdev
);
361 extern uint32_t rs780_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
362 extern void rs780_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
363 extern void r600_pm_get_dynpm_state(struct radeon_device
*rdev
);
364 extern void r600_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
);
365 extern int r600_get_pcie_lanes(struct radeon_device
*rdev
);
366 bool r600_card_posted(struct radeon_device
*rdev
);
367 void r600_cp_stop(struct radeon_device
*rdev
);
368 int r600_cp_start(struct radeon_device
*rdev
);
369 void r600_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*cp
, unsigned ring_size
);
370 int r600_cp_resume(struct radeon_device
*rdev
);
371 void r600_cp_fini(struct radeon_device
*rdev
);
372 int r600_count_pipe_bits(uint32_t val
);
373 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
374 int r600_pcie_gart_init(struct radeon_device
*rdev
);
375 void r600_scratch_init(struct radeon_device
*rdev
);
376 int r600_init_microcode(struct radeon_device
*rdev
);
377 u32
r600_gfx_get_rptr(struct radeon_device
*rdev
,
378 struct radeon_ring
*ring
);
379 u32
r600_gfx_get_wptr(struct radeon_device
*rdev
,
380 struct radeon_ring
*ring
);
381 void r600_gfx_set_wptr(struct radeon_device
*rdev
,
382 struct radeon_ring
*ring
);
384 int r600_irq_process(struct radeon_device
*rdev
);
385 int r600_irq_init(struct radeon_device
*rdev
);
386 void r600_irq_fini(struct radeon_device
*rdev
);
387 void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
388 int r600_irq_set(struct radeon_device
*rdev
);
389 void r600_irq_suspend(struct radeon_device
*rdev
);
390 void r600_disable_interrupts(struct radeon_device
*rdev
);
391 void r600_rlc_stop(struct radeon_device
*rdev
);
393 void r600_audio_fini(struct radeon_device
*rdev
);
394 void r600_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
);
395 void r600_hdmi_update_avi_infoframe(struct drm_encoder
*encoder
, void *buffer
,
397 void r600_hdmi_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
);
398 void r600_hdmi_audio_workaround(struct drm_encoder
*encoder
);
399 int r600_hdmi_buffer_status_changed(struct drm_encoder
*encoder
);
400 void r600_hdmi_update_audio_settings(struct drm_encoder
*encoder
);
401 void r600_hdmi_enable(struct drm_encoder
*encoder
, bool enable
);
402 void r600_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
);
403 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
404 u32
r600_get_xclk(struct radeon_device
*rdev
);
405 uint64_t r600_get_gpu_clock_counter(struct radeon_device
*rdev
);
406 int rv6xx_get_temp(struct radeon_device
*rdev
);
407 int r600_set_uvd_clocks(struct radeon_device
*rdev
, u32 vclk
, u32 dclk
);
408 int r600_dpm_pre_set_power_state(struct radeon_device
*rdev
);
409 void r600_dpm_post_set_power_state(struct radeon_device
*rdev
);
410 int r600_dpm_late_enable(struct radeon_device
*rdev
);
412 uint32_t r600_dma_get_rptr(struct radeon_device
*rdev
,
413 struct radeon_ring
*ring
);
414 uint32_t r600_dma_get_wptr(struct radeon_device
*rdev
,
415 struct radeon_ring
*ring
);
416 void r600_dma_set_wptr(struct radeon_device
*rdev
,
417 struct radeon_ring
*ring
);
419 int rv6xx_dpm_init(struct radeon_device
*rdev
);
420 int rv6xx_dpm_enable(struct radeon_device
*rdev
);
421 void rv6xx_dpm_disable(struct radeon_device
*rdev
);
422 int rv6xx_dpm_set_power_state(struct radeon_device
*rdev
);
423 void rv6xx_setup_asic(struct radeon_device
*rdev
);
424 void rv6xx_dpm_display_configuration_changed(struct radeon_device
*rdev
);
425 void rv6xx_dpm_fini(struct radeon_device
*rdev
);
426 u32
rv6xx_dpm_get_sclk(struct radeon_device
*rdev
, bool low
);
427 u32
rv6xx_dpm_get_mclk(struct radeon_device
*rdev
, bool low
);
428 void rv6xx_dpm_print_power_state(struct radeon_device
*rdev
,
429 struct radeon_ps
*ps
);
430 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
432 int rv6xx_dpm_force_performance_level(struct radeon_device
*rdev
,
433 enum radeon_dpm_forced_level level
);
435 int rs780_dpm_init(struct radeon_device
*rdev
);
436 int rs780_dpm_enable(struct radeon_device
*rdev
);
437 void rs780_dpm_disable(struct radeon_device
*rdev
);
438 int rs780_dpm_set_power_state(struct radeon_device
*rdev
);
439 void rs780_dpm_setup_asic(struct radeon_device
*rdev
);
440 void rs780_dpm_display_configuration_changed(struct radeon_device
*rdev
);
441 void rs780_dpm_fini(struct radeon_device
*rdev
);
442 u32
rs780_dpm_get_sclk(struct radeon_device
*rdev
, bool low
);
443 u32
rs780_dpm_get_mclk(struct radeon_device
*rdev
, bool low
);
444 void rs780_dpm_print_power_state(struct radeon_device
*rdev
,
445 struct radeon_ps
*ps
);
446 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
448 int rs780_dpm_force_performance_level(struct radeon_device
*rdev
,
449 enum radeon_dpm_forced_level level
);
452 * rv770,rv730,rv710,rv740
454 int rv770_init(struct radeon_device
*rdev
);
455 void rv770_fini(struct radeon_device
*rdev
);
456 int rv770_suspend(struct radeon_device
*rdev
);
457 int rv770_resume(struct radeon_device
*rdev
);
458 void rv770_pm_misc(struct radeon_device
*rdev
);
459 void rv770_page_flip(struct radeon_device
*rdev
, int crtc
, u64 crtc_base
);
460 bool rv770_page_flip_pending(struct radeon_device
*rdev
, int crtc
);
461 void r700_vram_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
);
462 void r700_cp_stop(struct radeon_device
*rdev
);
463 void r700_cp_fini(struct radeon_device
*rdev
);
464 struct radeon_fence
*rv770_copy_dma(struct radeon_device
*rdev
,
465 uint64_t src_offset
, uint64_t dst_offset
,
466 unsigned num_gpu_pages
,
467 struct reservation_object
*resv
);
468 u32
rv770_get_xclk(struct radeon_device
*rdev
);
469 int rv770_set_uvd_clocks(struct radeon_device
*rdev
, u32 vclk
, u32 dclk
);
470 int rv770_get_temp(struct radeon_device
*rdev
);
472 void dce3_1_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
);
474 int rv770_dpm_init(struct radeon_device
*rdev
);
475 int rv770_dpm_enable(struct radeon_device
*rdev
);
476 int rv770_dpm_late_enable(struct radeon_device
*rdev
);
477 void rv770_dpm_disable(struct radeon_device
*rdev
);
478 int rv770_dpm_set_power_state(struct radeon_device
*rdev
);
479 void rv770_dpm_setup_asic(struct radeon_device
*rdev
);
480 void rv770_dpm_display_configuration_changed(struct radeon_device
*rdev
);
481 void rv770_dpm_fini(struct radeon_device
*rdev
);
482 u32
rv770_dpm_get_sclk(struct radeon_device
*rdev
, bool low
);
483 u32
rv770_dpm_get_mclk(struct radeon_device
*rdev
, bool low
);
484 void rv770_dpm_print_power_state(struct radeon_device
*rdev
,
485 struct radeon_ps
*ps
);
486 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
488 int rv770_dpm_force_performance_level(struct radeon_device
*rdev
,
489 enum radeon_dpm_forced_level level
);
490 bool rv770_dpm_vblank_too_short(struct radeon_device
*rdev
);
495 struct evergreen_mc_save
{
496 u32 vga_render_control
;
498 bool crtc_enabled
[RADEON_MAX_CRTCS
];
501 void evergreen_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
502 int evergreen_init(struct radeon_device
*rdev
);
503 void evergreen_fini(struct radeon_device
*rdev
);
504 int evergreen_suspend(struct radeon_device
*rdev
);
505 int evergreen_resume(struct radeon_device
*rdev
);
506 bool evergreen_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
507 bool evergreen_dma_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
508 int evergreen_asic_reset(struct radeon_device
*rdev
);
509 void evergreen_bandwidth_update(struct radeon_device
*rdev
);
510 void evergreen_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
511 void evergreen_hpd_init(struct radeon_device
*rdev
);
512 void evergreen_hpd_fini(struct radeon_device
*rdev
);
513 bool evergreen_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
514 void evergreen_hpd_set_polarity(struct radeon_device
*rdev
,
515 enum radeon_hpd_id hpd
);
516 u32
evergreen_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
517 int evergreen_irq_set(struct radeon_device
*rdev
);
518 int evergreen_irq_process(struct radeon_device
*rdev
);
519 extern int evergreen_cs_parse(struct radeon_cs_parser
*p
);
520 extern int evergreen_dma_cs_parse(struct radeon_cs_parser
*p
);
521 extern void evergreen_pm_misc(struct radeon_device
*rdev
);
522 extern void evergreen_pm_prepare(struct radeon_device
*rdev
);
523 extern void evergreen_pm_finish(struct radeon_device
*rdev
);
524 extern void sumo_pm_init_profile(struct radeon_device
*rdev
);
525 extern void btc_pm_init_profile(struct radeon_device
*rdev
);
526 int sumo_set_uvd_clocks(struct radeon_device
*rdev
, u32 vclk
, u32 dclk
);
527 int evergreen_set_uvd_clocks(struct radeon_device
*rdev
, u32 vclk
, u32 dclk
);
528 extern void evergreen_page_flip(struct radeon_device
*rdev
, int crtc
,
530 extern bool evergreen_page_flip_pending(struct radeon_device
*rdev
, int crtc
);
531 extern void dce4_wait_for_vblank(struct radeon_device
*rdev
, int crtc
);
532 void evergreen_disable_interrupt_state(struct radeon_device
*rdev
);
533 int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
);
534 void evergreen_dma_fence_ring_emit(struct radeon_device
*rdev
,
535 struct radeon_fence
*fence
);
536 void evergreen_dma_ring_ib_execute(struct radeon_device
*rdev
,
537 struct radeon_ib
*ib
);
538 struct radeon_fence
*evergreen_copy_dma(struct radeon_device
*rdev
,
539 uint64_t src_offset
, uint64_t dst_offset
,
540 unsigned num_gpu_pages
,
541 struct reservation_object
*resv
);
542 void evergreen_hdmi_enable(struct drm_encoder
*encoder
, bool enable
);
543 void evergreen_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
);
544 int evergreen_get_temp(struct radeon_device
*rdev
);
545 int sumo_get_temp(struct radeon_device
*rdev
);
546 int tn_get_temp(struct radeon_device
*rdev
);
547 int cypress_dpm_init(struct radeon_device
*rdev
);
548 void cypress_dpm_setup_asic(struct radeon_device
*rdev
);
549 int cypress_dpm_enable(struct radeon_device
*rdev
);
550 void cypress_dpm_disable(struct radeon_device
*rdev
);
551 int cypress_dpm_set_power_state(struct radeon_device
*rdev
);
552 void cypress_dpm_display_configuration_changed(struct radeon_device
*rdev
);
553 void cypress_dpm_fini(struct radeon_device
*rdev
);
554 bool cypress_dpm_vblank_too_short(struct radeon_device
*rdev
);
555 int btc_dpm_init(struct radeon_device
*rdev
);
556 void btc_dpm_setup_asic(struct radeon_device
*rdev
);
557 int btc_dpm_enable(struct radeon_device
*rdev
);
558 void btc_dpm_disable(struct radeon_device
*rdev
);
559 int btc_dpm_pre_set_power_state(struct radeon_device
*rdev
);
560 int btc_dpm_set_power_state(struct radeon_device
*rdev
);
561 void btc_dpm_post_set_power_state(struct radeon_device
*rdev
);
562 void btc_dpm_fini(struct radeon_device
*rdev
);
563 u32
btc_dpm_get_sclk(struct radeon_device
*rdev
, bool low
);
564 u32
btc_dpm_get_mclk(struct radeon_device
*rdev
, bool low
);
565 bool btc_dpm_vblank_too_short(struct radeon_device
*rdev
);
566 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
568 int sumo_dpm_init(struct radeon_device
*rdev
);
569 int sumo_dpm_enable(struct radeon_device
*rdev
);
570 int sumo_dpm_late_enable(struct radeon_device
*rdev
);
571 void sumo_dpm_disable(struct radeon_device
*rdev
);
572 int sumo_dpm_pre_set_power_state(struct radeon_device
*rdev
);
573 int sumo_dpm_set_power_state(struct radeon_device
*rdev
);
574 void sumo_dpm_post_set_power_state(struct radeon_device
*rdev
);
575 void sumo_dpm_setup_asic(struct radeon_device
*rdev
);
576 void sumo_dpm_display_configuration_changed(struct radeon_device
*rdev
);
577 void sumo_dpm_fini(struct radeon_device
*rdev
);
578 u32
sumo_dpm_get_sclk(struct radeon_device
*rdev
, bool low
);
579 u32
sumo_dpm_get_mclk(struct radeon_device
*rdev
, bool low
);
580 void sumo_dpm_print_power_state(struct radeon_device
*rdev
,
581 struct radeon_ps
*ps
);
582 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
584 int sumo_dpm_force_performance_level(struct radeon_device
*rdev
,
585 enum radeon_dpm_forced_level level
);
590 void cayman_fence_ring_emit(struct radeon_device
*rdev
,
591 struct radeon_fence
*fence
);
592 void cayman_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
593 int cayman_init(struct radeon_device
*rdev
);
594 void cayman_fini(struct radeon_device
*rdev
);
595 int cayman_suspend(struct radeon_device
*rdev
);
596 int cayman_resume(struct radeon_device
*rdev
);
597 int cayman_asic_reset(struct radeon_device
*rdev
);
598 void cayman_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
599 int cayman_vm_init(struct radeon_device
*rdev
);
600 void cayman_vm_fini(struct radeon_device
*rdev
);
601 void cayman_vm_flush(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
602 unsigned vm_id
, uint64_t pd_addr
);
603 uint32_t cayman_vm_page_flags(struct radeon_device
*rdev
, uint32_t flags
);
604 int evergreen_ib_parse(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
605 int evergreen_dma_ib_parse(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
606 void cayman_dma_ring_ib_execute(struct radeon_device
*rdev
,
607 struct radeon_ib
*ib
);
608 bool cayman_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
609 bool cayman_dma_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
611 void cayman_dma_vm_copy_pages(struct radeon_device
*rdev
,
612 struct radeon_ib
*ib
,
613 uint64_t pe
, uint64_t src
,
615 void cayman_dma_vm_write_pages(struct radeon_device
*rdev
,
616 struct radeon_ib
*ib
,
618 uint64_t addr
, unsigned count
,
619 uint32_t incr
, uint32_t flags
);
620 void cayman_dma_vm_set_pages(struct radeon_device
*rdev
,
621 struct radeon_ib
*ib
,
623 uint64_t addr
, unsigned count
,
624 uint32_t incr
, uint32_t flags
);
625 void cayman_dma_vm_pad_ib(struct radeon_ib
*ib
);
627 void cayman_dma_vm_flush(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
628 unsigned vm_id
, uint64_t pd_addr
);
630 u32
cayman_gfx_get_rptr(struct radeon_device
*rdev
,
631 struct radeon_ring
*ring
);
632 u32
cayman_gfx_get_wptr(struct radeon_device
*rdev
,
633 struct radeon_ring
*ring
);
634 void cayman_gfx_set_wptr(struct radeon_device
*rdev
,
635 struct radeon_ring
*ring
);
636 uint32_t cayman_dma_get_rptr(struct radeon_device
*rdev
,
637 struct radeon_ring
*ring
);
638 uint32_t cayman_dma_get_wptr(struct radeon_device
*rdev
,
639 struct radeon_ring
*ring
);
640 void cayman_dma_set_wptr(struct radeon_device
*rdev
,
641 struct radeon_ring
*ring
);
643 int ni_dpm_init(struct radeon_device
*rdev
);
644 void ni_dpm_setup_asic(struct radeon_device
*rdev
);
645 int ni_dpm_enable(struct radeon_device
*rdev
);
646 void ni_dpm_disable(struct radeon_device
*rdev
);
647 int ni_dpm_pre_set_power_state(struct radeon_device
*rdev
);
648 int ni_dpm_set_power_state(struct radeon_device
*rdev
);
649 void ni_dpm_post_set_power_state(struct radeon_device
*rdev
);
650 void ni_dpm_fini(struct radeon_device
*rdev
);
651 u32
ni_dpm_get_sclk(struct radeon_device
*rdev
, bool low
);
652 u32
ni_dpm_get_mclk(struct radeon_device
*rdev
, bool low
);
653 void ni_dpm_print_power_state(struct radeon_device
*rdev
,
654 struct radeon_ps
*ps
);
655 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
657 int ni_dpm_force_performance_level(struct radeon_device
*rdev
,
658 enum radeon_dpm_forced_level level
);
659 bool ni_dpm_vblank_too_short(struct radeon_device
*rdev
);
660 int trinity_dpm_init(struct radeon_device
*rdev
);
661 int trinity_dpm_enable(struct radeon_device
*rdev
);
662 int trinity_dpm_late_enable(struct radeon_device
*rdev
);
663 void trinity_dpm_disable(struct radeon_device
*rdev
);
664 int trinity_dpm_pre_set_power_state(struct radeon_device
*rdev
);
665 int trinity_dpm_set_power_state(struct radeon_device
*rdev
);
666 void trinity_dpm_post_set_power_state(struct radeon_device
*rdev
);
667 void trinity_dpm_setup_asic(struct radeon_device
*rdev
);
668 void trinity_dpm_display_configuration_changed(struct radeon_device
*rdev
);
669 void trinity_dpm_fini(struct radeon_device
*rdev
);
670 u32
trinity_dpm_get_sclk(struct radeon_device
*rdev
, bool low
);
671 u32
trinity_dpm_get_mclk(struct radeon_device
*rdev
, bool low
);
672 void trinity_dpm_print_power_state(struct radeon_device
*rdev
,
673 struct radeon_ps
*ps
);
674 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
676 int trinity_dpm_force_performance_level(struct radeon_device
*rdev
,
677 enum radeon_dpm_forced_level level
);
678 void trinity_dpm_enable_bapm(struct radeon_device
*rdev
, bool enable
);
681 void dce6_bandwidth_update(struct radeon_device
*rdev
);
682 void dce6_audio_fini(struct radeon_device
*rdev
);
687 void si_fence_ring_emit(struct radeon_device
*rdev
,
688 struct radeon_fence
*fence
);
689 void si_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
690 int si_init(struct radeon_device
*rdev
);
691 void si_fini(struct radeon_device
*rdev
);
692 int si_suspend(struct radeon_device
*rdev
);
693 int si_resume(struct radeon_device
*rdev
);
694 bool si_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
695 bool si_dma_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
696 int si_asic_reset(struct radeon_device
*rdev
);
697 void si_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
698 int si_irq_set(struct radeon_device
*rdev
);
699 int si_irq_process(struct radeon_device
*rdev
);
700 int si_vm_init(struct radeon_device
*rdev
);
701 void si_vm_fini(struct radeon_device
*rdev
);
702 void si_vm_flush(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
703 unsigned vm_id
, uint64_t pd_addr
);
704 int si_ib_parse(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
705 struct radeon_fence
*si_copy_dma(struct radeon_device
*rdev
,
706 uint64_t src_offset
, uint64_t dst_offset
,
707 unsigned num_gpu_pages
,
708 struct reservation_object
*resv
);
710 void si_dma_vm_copy_pages(struct radeon_device
*rdev
,
711 struct radeon_ib
*ib
,
712 uint64_t pe
, uint64_t src
,
714 void si_dma_vm_write_pages(struct radeon_device
*rdev
,
715 struct radeon_ib
*ib
,
717 uint64_t addr
, unsigned count
,
718 uint32_t incr
, uint32_t flags
);
719 void si_dma_vm_set_pages(struct radeon_device
*rdev
,
720 struct radeon_ib
*ib
,
722 uint64_t addr
, unsigned count
,
723 uint32_t incr
, uint32_t flags
);
725 void si_dma_vm_flush(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
726 unsigned vm_id
, uint64_t pd_addr
);
727 u32
si_get_xclk(struct radeon_device
*rdev
);
728 uint64_t si_get_gpu_clock_counter(struct radeon_device
*rdev
);
729 int si_set_uvd_clocks(struct radeon_device
*rdev
, u32 vclk
, u32 dclk
);
730 int si_get_temp(struct radeon_device
*rdev
);
731 int si_dpm_init(struct radeon_device
*rdev
);
732 void si_dpm_setup_asic(struct radeon_device
*rdev
);
733 int si_dpm_enable(struct radeon_device
*rdev
);
734 int si_dpm_late_enable(struct radeon_device
*rdev
);
735 void si_dpm_disable(struct radeon_device
*rdev
);
736 int si_dpm_pre_set_power_state(struct radeon_device
*rdev
);
737 int si_dpm_set_power_state(struct radeon_device
*rdev
);
738 void si_dpm_post_set_power_state(struct radeon_device
*rdev
);
739 void si_dpm_fini(struct radeon_device
*rdev
);
740 void si_dpm_display_configuration_changed(struct radeon_device
*rdev
);
741 void si_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
743 int si_dpm_force_performance_level(struct radeon_device
*rdev
,
744 enum radeon_dpm_forced_level level
);
745 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device
*rdev
,
747 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device
*rdev
,
749 u32
si_fan_ctrl_get_mode(struct radeon_device
*rdev
);
750 void si_fan_ctrl_set_mode(struct radeon_device
*rdev
, u32 mode
);
753 void dce8_bandwidth_update(struct radeon_device
*rdev
);
758 uint64_t cik_get_gpu_clock_counter(struct radeon_device
*rdev
);
759 u32
cik_get_xclk(struct radeon_device
*rdev
);
760 uint32_t cik_pciep_rreg(struct radeon_device
*rdev
, uint32_t reg
);
761 void cik_pciep_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
762 int cik_set_uvd_clocks(struct radeon_device
*rdev
, u32 vclk
, u32 dclk
);
763 int cik_set_vce_clocks(struct radeon_device
*rdev
, u32 evclk
, u32 ecclk
);
764 void cik_sdma_fence_ring_emit(struct radeon_device
*rdev
,
765 struct radeon_fence
*fence
);
766 bool cik_sdma_semaphore_ring_emit(struct radeon_device
*rdev
,
767 struct radeon_ring
*ring
,
768 struct radeon_semaphore
*semaphore
,
770 void cik_sdma_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
771 struct radeon_fence
*cik_copy_dma(struct radeon_device
*rdev
,
772 uint64_t src_offset
, uint64_t dst_offset
,
773 unsigned num_gpu_pages
,
774 struct reservation_object
*resv
);
775 struct radeon_fence
*cik_copy_cpdma(struct radeon_device
*rdev
,
776 uint64_t src_offset
, uint64_t dst_offset
,
777 unsigned num_gpu_pages
,
778 struct reservation_object
*resv
);
779 int cik_sdma_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
780 int cik_sdma_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
781 bool cik_sdma_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
782 void cik_fence_gfx_ring_emit(struct radeon_device
*rdev
,
783 struct radeon_fence
*fence
);
784 void cik_fence_compute_ring_emit(struct radeon_device
*rdev
,
785 struct radeon_fence
*fence
);
786 bool cik_semaphore_ring_emit(struct radeon_device
*rdev
,
787 struct radeon_ring
*cp
,
788 struct radeon_semaphore
*semaphore
,
790 void cik_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
791 int cik_init(struct radeon_device
*rdev
);
792 void cik_fini(struct radeon_device
*rdev
);
793 int cik_suspend(struct radeon_device
*rdev
);
794 int cik_resume(struct radeon_device
*rdev
);
795 bool cik_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
796 int cik_asic_reset(struct radeon_device
*rdev
);
797 void cik_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
798 int cik_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
799 int cik_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
800 int cik_irq_set(struct radeon_device
*rdev
);
801 int cik_irq_process(struct radeon_device
*rdev
);
802 int cik_vm_init(struct radeon_device
*rdev
);
803 void cik_vm_fini(struct radeon_device
*rdev
);
804 void cik_vm_flush(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
805 unsigned vm_id
, uint64_t pd_addr
);
807 void cik_sdma_vm_copy_pages(struct radeon_device
*rdev
,
808 struct radeon_ib
*ib
,
809 uint64_t pe
, uint64_t src
,
811 void cik_sdma_vm_write_pages(struct radeon_device
*rdev
,
812 struct radeon_ib
*ib
,
814 uint64_t addr
, unsigned count
,
815 uint32_t incr
, uint32_t flags
);
816 void cik_sdma_vm_set_pages(struct radeon_device
*rdev
,
817 struct radeon_ib
*ib
,
819 uint64_t addr
, unsigned count
,
820 uint32_t incr
, uint32_t flags
);
821 void cik_sdma_vm_pad_ib(struct radeon_ib
*ib
);
823 void cik_dma_vm_flush(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
824 unsigned vm_id
, uint64_t pd_addr
);
825 int cik_ib_parse(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
826 u32
cik_gfx_get_rptr(struct radeon_device
*rdev
,
827 struct radeon_ring
*ring
);
828 u32
cik_gfx_get_wptr(struct radeon_device
*rdev
,
829 struct radeon_ring
*ring
);
830 void cik_gfx_set_wptr(struct radeon_device
*rdev
,
831 struct radeon_ring
*ring
);
832 u32
cik_compute_get_rptr(struct radeon_device
*rdev
,
833 struct radeon_ring
*ring
);
834 u32
cik_compute_get_wptr(struct radeon_device
*rdev
,
835 struct radeon_ring
*ring
);
836 void cik_compute_set_wptr(struct radeon_device
*rdev
,
837 struct radeon_ring
*ring
);
838 u32
cik_sdma_get_rptr(struct radeon_device
*rdev
,
839 struct radeon_ring
*ring
);
840 u32
cik_sdma_get_wptr(struct radeon_device
*rdev
,
841 struct radeon_ring
*ring
);
842 void cik_sdma_set_wptr(struct radeon_device
*rdev
,
843 struct radeon_ring
*ring
);
844 int ci_get_temp(struct radeon_device
*rdev
);
845 int kv_get_temp(struct radeon_device
*rdev
);
847 int ci_dpm_init(struct radeon_device
*rdev
);
848 int ci_dpm_enable(struct radeon_device
*rdev
);
849 int ci_dpm_late_enable(struct radeon_device
*rdev
);
850 void ci_dpm_disable(struct radeon_device
*rdev
);
851 int ci_dpm_pre_set_power_state(struct radeon_device
*rdev
);
852 int ci_dpm_set_power_state(struct radeon_device
*rdev
);
853 void ci_dpm_post_set_power_state(struct radeon_device
*rdev
);
854 void ci_dpm_setup_asic(struct radeon_device
*rdev
);
855 void ci_dpm_display_configuration_changed(struct radeon_device
*rdev
);
856 void ci_dpm_fini(struct radeon_device
*rdev
);
857 u32
ci_dpm_get_sclk(struct radeon_device
*rdev
, bool low
);
858 u32
ci_dpm_get_mclk(struct radeon_device
*rdev
, bool low
);
859 void ci_dpm_print_power_state(struct radeon_device
*rdev
,
860 struct radeon_ps
*ps
);
861 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
863 int ci_dpm_force_performance_level(struct radeon_device
*rdev
,
864 enum radeon_dpm_forced_level level
);
865 bool ci_dpm_vblank_too_short(struct radeon_device
*rdev
);
866 void ci_dpm_powergate_uvd(struct radeon_device
*rdev
, bool gate
);
868 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device
*rdev
,
870 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device
*rdev
,
872 u32
ci_fan_ctrl_get_mode(struct radeon_device
*rdev
);
873 void ci_fan_ctrl_set_mode(struct radeon_device
*rdev
, u32 mode
);
875 int kv_dpm_init(struct radeon_device
*rdev
);
876 int kv_dpm_enable(struct radeon_device
*rdev
);
877 int kv_dpm_late_enable(struct radeon_device
*rdev
);
878 void kv_dpm_disable(struct radeon_device
*rdev
);
879 int kv_dpm_pre_set_power_state(struct radeon_device
*rdev
);
880 int kv_dpm_set_power_state(struct radeon_device
*rdev
);
881 void kv_dpm_post_set_power_state(struct radeon_device
*rdev
);
882 void kv_dpm_setup_asic(struct radeon_device
*rdev
);
883 void kv_dpm_display_configuration_changed(struct radeon_device
*rdev
);
884 void kv_dpm_fini(struct radeon_device
*rdev
);
885 u32
kv_dpm_get_sclk(struct radeon_device
*rdev
, bool low
);
886 u32
kv_dpm_get_mclk(struct radeon_device
*rdev
, bool low
);
887 void kv_dpm_print_power_state(struct radeon_device
*rdev
,
888 struct radeon_ps
*ps
);
889 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
891 int kv_dpm_force_performance_level(struct radeon_device
*rdev
,
892 enum radeon_dpm_forced_level level
);
893 void kv_dpm_powergate_uvd(struct radeon_device
*rdev
, bool gate
);
894 void kv_dpm_enable_bapm(struct radeon_device
*rdev
, bool enable
);
897 uint32_t uvd_v1_0_get_rptr(struct radeon_device
*rdev
,
898 struct radeon_ring
*ring
);
899 uint32_t uvd_v1_0_get_wptr(struct radeon_device
*rdev
,
900 struct radeon_ring
*ring
);
901 void uvd_v1_0_set_wptr(struct radeon_device
*rdev
,
902 struct radeon_ring
*ring
);
903 int uvd_v1_0_resume(struct radeon_device
*rdev
);
905 int uvd_v1_0_init(struct radeon_device
*rdev
);
906 void uvd_v1_0_fini(struct radeon_device
*rdev
);
907 int uvd_v1_0_start(struct radeon_device
*rdev
);
908 void uvd_v1_0_stop(struct radeon_device
*rdev
);
910 int uvd_v1_0_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
911 void uvd_v1_0_fence_emit(struct radeon_device
*rdev
,
912 struct radeon_fence
*fence
);
913 int uvd_v1_0_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
914 bool uvd_v1_0_semaphore_emit(struct radeon_device
*rdev
,
915 struct radeon_ring
*ring
,
916 struct radeon_semaphore
*semaphore
,
918 void uvd_v1_0_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
921 int uvd_v2_2_resume(struct radeon_device
*rdev
);
922 void uvd_v2_2_fence_emit(struct radeon_device
*rdev
,
923 struct radeon_fence
*fence
);
926 bool uvd_v3_1_semaphore_emit(struct radeon_device
*rdev
,
927 struct radeon_ring
*ring
,
928 struct radeon_semaphore
*semaphore
,
932 int uvd_v4_2_resume(struct radeon_device
*rdev
);
935 uint32_t vce_v1_0_get_rptr(struct radeon_device
*rdev
,
936 struct radeon_ring
*ring
);
937 uint32_t vce_v1_0_get_wptr(struct radeon_device
*rdev
,
938 struct radeon_ring
*ring
);
939 void vce_v1_0_set_wptr(struct radeon_device
*rdev
,
940 struct radeon_ring
*ring
);
941 int vce_v1_0_init(struct radeon_device
*rdev
);
942 int vce_v1_0_start(struct radeon_device
*rdev
);
945 int vce_v2_0_resume(struct radeon_device
*rdev
);