1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
39 #include "radeon_microcode.h"
41 #define RADEON_FIFO_DEBUG 0
43 static int radeon_do_cleanup_cp(struct drm_device
* dev
);
44 static void radeon_do_cp_start(drm_radeon_private_t
* dev_priv
);
46 static u32
R500_READ_MCIND(drm_radeon_private_t
*dev_priv
, int addr
)
49 RADEON_WRITE(R520_MC_IND_INDEX
, 0x7f0000 | (addr
& 0xff));
50 ret
= RADEON_READ(R520_MC_IND_DATA
);
51 RADEON_WRITE(R520_MC_IND_INDEX
, 0);
55 static u32
RS480_READ_MCIND(drm_radeon_private_t
*dev_priv
, int addr
)
58 RADEON_WRITE(RS480_NB_MC_INDEX
, addr
& 0xff);
59 ret
= RADEON_READ(RS480_NB_MC_DATA
);
60 RADEON_WRITE(RS480_NB_MC_INDEX
, 0xff);
64 static u32
RS690_READ_MCIND(drm_radeon_private_t
*dev_priv
, int addr
)
67 RADEON_WRITE(RS690_MC_INDEX
, (addr
& RS690_MC_INDEX_MASK
));
68 ret
= RADEON_READ(RS690_MC_DATA
);
69 RADEON_WRITE(RS690_MC_INDEX
, RS690_MC_INDEX_MASK
);
73 static u32
IGP_READ_MCIND(drm_radeon_private_t
*dev_priv
, int addr
)
75 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
76 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
77 return RS690_READ_MCIND(dev_priv
, addr
);
79 return RS480_READ_MCIND(dev_priv
, addr
);
82 u32
radeon_read_fb_location(drm_radeon_private_t
*dev_priv
)
85 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
)
86 return R500_READ_MCIND(dev_priv
, RV515_MC_FB_LOCATION
);
87 else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
88 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
89 return RS690_READ_MCIND(dev_priv
, RS690_MC_FB_LOCATION
);
90 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_RV515
)
91 return R500_READ_MCIND(dev_priv
, R520_MC_FB_LOCATION
);
93 return RADEON_READ(RADEON_MC_FB_LOCATION
);
96 static void radeon_write_fb_location(drm_radeon_private_t
*dev_priv
, u32 fb_loc
)
98 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
)
99 R500_WRITE_MCIND(RV515_MC_FB_LOCATION
, fb_loc
);
100 else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
101 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
102 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION
, fb_loc
);
103 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_RV515
)
104 R500_WRITE_MCIND(R520_MC_FB_LOCATION
, fb_loc
);
106 RADEON_WRITE(RADEON_MC_FB_LOCATION
, fb_loc
);
109 static void radeon_write_agp_location(drm_radeon_private_t
*dev_priv
, u32 agp_loc
)
111 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
)
112 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION
, agp_loc
);
113 else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
114 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
115 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION
, agp_loc
);
116 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_RV515
)
117 R500_WRITE_MCIND(R520_MC_AGP_LOCATION
, agp_loc
);
119 RADEON_WRITE(RADEON_MC_AGP_LOCATION
, agp_loc
);
122 static void radeon_write_agp_base(drm_radeon_private_t
*dev_priv
, u64 agp_base
)
124 u32 agp_base_hi
= upper_32_bits(agp_base
);
125 u32 agp_base_lo
= agp_base
& 0xffffffff;
127 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
) {
128 R500_WRITE_MCIND(RV515_MC_AGP_BASE
, agp_base_lo
);
129 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2
, agp_base_hi
);
130 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
131 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
)) {
132 RS690_WRITE_MCIND(RS690_MC_AGP_BASE
, agp_base_lo
);
133 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2
, agp_base_hi
);
134 } else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_RV515
) {
135 R500_WRITE_MCIND(R520_MC_AGP_BASE
, agp_base_lo
);
136 R500_WRITE_MCIND(R520_MC_AGP_BASE_2
, agp_base_hi
);
137 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS400
) ||
138 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS480
)) {
139 RADEON_WRITE(RADEON_AGP_BASE
, agp_base_lo
);
140 RADEON_WRITE(RS480_AGP_BASE_2
, agp_base_hi
);
142 RADEON_WRITE(RADEON_AGP_BASE
, agp_base_lo
);
143 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R200
)
144 RADEON_WRITE(RADEON_AGP_BASE_2
, agp_base_hi
);
148 static int RADEON_READ_PLL(struct drm_device
* dev
, int addr
)
150 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
152 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX
, addr
& 0x1f);
153 return RADEON_READ(RADEON_CLOCK_CNTL_DATA
);
156 static u32
RADEON_READ_PCIE(drm_radeon_private_t
*dev_priv
, int addr
)
158 RADEON_WRITE8(RADEON_PCIE_INDEX
, addr
& 0xff);
159 return RADEON_READ(RADEON_PCIE_DATA
);
162 #if RADEON_FIFO_DEBUG
163 static void radeon_status(drm_radeon_private_t
* dev_priv
)
165 printk("%s:\n", __func__
);
166 printk("RBBM_STATUS = 0x%08x\n",
167 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS
));
168 printk("CP_RB_RTPR = 0x%08x\n",
169 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR
));
170 printk("CP_RB_WTPR = 0x%08x\n",
171 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR
));
172 printk("AIC_CNTL = 0x%08x\n",
173 (unsigned int)RADEON_READ(RADEON_AIC_CNTL
));
174 printk("AIC_STAT = 0x%08x\n",
175 (unsigned int)RADEON_READ(RADEON_AIC_STAT
));
176 printk("AIC_PT_BASE = 0x%08x\n",
177 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE
));
178 printk("TLB_ADDR = 0x%08x\n",
179 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR
));
180 printk("TLB_DATA = 0x%08x\n",
181 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA
));
185 /* ================================================================
186 * Engine, FIFO control
189 static int radeon_do_pixcache_flush(drm_radeon_private_t
* dev_priv
)
194 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
196 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) <= CHIP_RV280
) {
197 tmp
= RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT
);
198 tmp
|= RADEON_RB3D_DC_FLUSH_ALL
;
199 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT
, tmp
);
201 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
202 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT
)
203 & RADEON_RB3D_DC_BUSY
)) {
209 /* don't flush or purge cache here or lockup */
213 #if RADEON_FIFO_DEBUG
214 DRM_ERROR("failed!\n");
215 radeon_status(dev_priv
);
220 static int radeon_do_wait_for_fifo(drm_radeon_private_t
* dev_priv
, int entries
)
224 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
226 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
227 int slots
= (RADEON_READ(RADEON_RBBM_STATUS
)
228 & RADEON_RBBM_FIFOCNT_MASK
);
229 if (slots
>= entries
)
233 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
234 RADEON_READ(RADEON_RBBM_STATUS
),
235 RADEON_READ(R300_VAP_CNTL_STATUS
));
237 #if RADEON_FIFO_DEBUG
238 DRM_ERROR("failed!\n");
239 radeon_status(dev_priv
);
244 static int radeon_do_wait_for_idle(drm_radeon_private_t
* dev_priv
)
248 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
250 ret
= radeon_do_wait_for_fifo(dev_priv
, 64);
254 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
255 if (!(RADEON_READ(RADEON_RBBM_STATUS
)
256 & RADEON_RBBM_ACTIVE
)) {
257 radeon_do_pixcache_flush(dev_priv
);
262 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
263 RADEON_READ(RADEON_RBBM_STATUS
),
264 RADEON_READ(R300_VAP_CNTL_STATUS
));
266 #if RADEON_FIFO_DEBUG
267 DRM_ERROR("failed!\n");
268 radeon_status(dev_priv
);
273 static void radeon_init_pipes(drm_radeon_private_t
*dev_priv
)
275 uint32_t gb_tile_config
, gb_pipe_sel
= 0;
277 /* RS4xx/RS6xx/R4xx/R5xx */
278 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R420
) {
279 gb_pipe_sel
= RADEON_READ(R400_GB_PIPE_SELECT
);
280 dev_priv
->num_gb_pipes
= ((gb_pipe_sel
>> 12) & 0x3) + 1;
283 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R300
) ||
284 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R350
)) {
285 dev_priv
->num_gb_pipes
= 2;
288 dev_priv
->num_gb_pipes
= 1;
291 DRM_INFO("Num pipes: %d\n", dev_priv
->num_gb_pipes
);
293 gb_tile_config
= (R300_ENABLE_TILING
| R300_TILE_SIZE_16
/*| R300_SUBPIXEL_1_16*/);
295 switch (dev_priv
->num_gb_pipes
) {
296 case 2: gb_tile_config
|= R300_PIPE_COUNT_R300
; break;
297 case 3: gb_tile_config
|= R300_PIPE_COUNT_R420_3P
; break;
298 case 4: gb_tile_config
|= R300_PIPE_COUNT_R420
; break;
300 case 1: gb_tile_config
|= R300_PIPE_COUNT_RV350
; break;
303 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV515
) {
304 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE
, (1 | ((gb_pipe_sel
>> 8) & 0xf) << 4));
305 RADEON_WRITE(R500_SU_REG_DEST
, ((1 << dev_priv
->num_gb_pipes
) - 1));
307 RADEON_WRITE(R300_GB_TILE_CONFIG
, gb_tile_config
);
308 radeon_do_wait_for_idle(dev_priv
);
309 RADEON_WRITE(R300_DST_PIPE_CONFIG
, RADEON_READ(R300_DST_PIPE_CONFIG
) | R300_PIPE_AUTO_CONFIG
);
310 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE
, (RADEON_READ(R300_RB2D_DSTCACHE_MODE
) |
311 R300_DC_AUTOFLUSH_ENABLE
|
312 R300_DC_DC_DISABLE_IGNORE_PE
));
317 /* ================================================================
318 * CP control, initialization
321 /* Load the microcode for the CP */
322 static void radeon_cp_load_microcode(drm_radeon_private_t
* dev_priv
)
327 radeon_do_wait_for_idle(dev_priv
);
329 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR
, 0);
330 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R100
) ||
331 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV100
) ||
332 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV200
) ||
333 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS100
) ||
334 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS200
)) {
335 DRM_INFO("Loading R100 Microcode\n");
336 for (i
= 0; i
< 256; i
++) {
337 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
338 R100_cp_microcode
[i
][1]);
339 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
340 R100_cp_microcode
[i
][0]);
342 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R200
) ||
343 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV250
) ||
344 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV280
) ||
345 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS300
)) {
346 DRM_INFO("Loading R200 Microcode\n");
347 for (i
= 0; i
< 256; i
++) {
348 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
349 R200_cp_microcode
[i
][1]);
350 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
351 R200_cp_microcode
[i
][0]);
353 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R300
) ||
354 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R350
) ||
355 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV350
) ||
356 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV380
) ||
357 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS400
) ||
358 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS480
)) {
359 DRM_INFO("Loading R300 Microcode\n");
360 for (i
= 0; i
< 256; i
++) {
361 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
362 R300_cp_microcode
[i
][1]);
363 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
364 R300_cp_microcode
[i
][0]);
366 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R420
) ||
367 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R423
) ||
368 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV410
)) {
369 DRM_INFO("Loading R400 Microcode\n");
370 for (i
= 0; i
< 256; i
++) {
371 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
372 R420_cp_microcode
[i
][1]);
373 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
374 R420_cp_microcode
[i
][0]);
376 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
377 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
)) {
378 DRM_INFO("Loading RS690/RS740 Microcode\n");
379 for (i
= 0; i
< 256; i
++) {
380 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
381 RS690_cp_microcode
[i
][1]);
382 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
383 RS690_cp_microcode
[i
][0]);
385 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
) ||
386 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R520
) ||
387 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV530
) ||
388 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R580
) ||
389 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV560
) ||
390 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV570
)) {
391 DRM_INFO("Loading R500 Microcode\n");
392 for (i
= 0; i
< 256; i
++) {
393 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
394 R520_cp_microcode
[i
][1]);
395 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
396 R520_cp_microcode
[i
][0]);
401 /* Flush any pending commands to the CP. This should only be used just
402 * prior to a wait for idle, as it informs the engine that the command
405 static void radeon_do_cp_flush(drm_radeon_private_t
* dev_priv
)
411 tmp
= RADEON_READ(RADEON_CP_RB_WPTR
) | (1 << 31);
412 RADEON_WRITE(RADEON_CP_RB_WPTR
, tmp
);
416 /* Wait for the CP to go idle.
418 int radeon_do_cp_idle(drm_radeon_private_t
* dev_priv
)
425 RADEON_PURGE_CACHE();
426 RADEON_PURGE_ZCACHE();
427 RADEON_WAIT_UNTIL_IDLE();
432 return radeon_do_wait_for_idle(dev_priv
);
435 /* Start the Command Processor.
437 static void radeon_do_cp_start(drm_radeon_private_t
* dev_priv
)
442 radeon_do_wait_for_idle(dev_priv
);
444 RADEON_WRITE(RADEON_CP_CSQ_CNTL
, dev_priv
->cp_mode
);
446 dev_priv
->cp_running
= 1;
449 /* isync can only be written through cp on r5xx write it here */
450 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL
, 0));
451 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D
|
452 RADEON_ISYNC_ANY3D_IDLE2D
|
453 RADEON_ISYNC_WAIT_IDLEGUI
|
454 RADEON_ISYNC_CPSCRATCH_IDLEGUI
);
455 RADEON_PURGE_CACHE();
456 RADEON_PURGE_ZCACHE();
457 RADEON_WAIT_UNTIL_IDLE();
461 dev_priv
->track_flush
|= RADEON_FLUSH_EMITED
| RADEON_PURGE_EMITED
;
464 /* Reset the Command Processor. This will not flush any pending
465 * commands, so you must wait for the CP command stream to complete
466 * before calling this routine.
468 static void radeon_do_cp_reset(drm_radeon_private_t
* dev_priv
)
473 cur_read_ptr
= RADEON_READ(RADEON_CP_RB_RPTR
);
474 RADEON_WRITE(RADEON_CP_RB_WPTR
, cur_read_ptr
);
475 SET_RING_HEAD(dev_priv
, cur_read_ptr
);
476 dev_priv
->ring
.tail
= cur_read_ptr
;
479 /* Stop the Command Processor. This will not flush any pending
480 * commands, so you must flush the command stream and wait for the CP
481 * to go idle before calling this routine.
483 static void radeon_do_cp_stop(drm_radeon_private_t
* dev_priv
)
487 RADEON_WRITE(RADEON_CP_CSQ_CNTL
, RADEON_CSQ_PRIDIS_INDDIS
);
489 dev_priv
->cp_running
= 0;
492 /* Reset the engine. This will stop the CP if it is running.
494 static int radeon_do_engine_reset(struct drm_device
* dev
)
496 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
497 u32 clock_cntl_index
= 0, mclk_cntl
= 0, rbbm_soft_reset
;
500 radeon_do_pixcache_flush(dev_priv
);
502 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) <= CHIP_RV410
) {
503 /* may need something similar for newer chips */
504 clock_cntl_index
= RADEON_READ(RADEON_CLOCK_CNTL_INDEX
);
505 mclk_cntl
= RADEON_READ_PLL(dev
, RADEON_MCLK_CNTL
);
507 RADEON_WRITE_PLL(RADEON_MCLK_CNTL
, (mclk_cntl
|
508 RADEON_FORCEON_MCLKA
|
509 RADEON_FORCEON_MCLKB
|
510 RADEON_FORCEON_YCLKA
|
511 RADEON_FORCEON_YCLKB
|
513 RADEON_FORCEON_AIC
));
516 rbbm_soft_reset
= RADEON_READ(RADEON_RBBM_SOFT_RESET
);
518 RADEON_WRITE(RADEON_RBBM_SOFT_RESET
, (rbbm_soft_reset
|
519 RADEON_SOFT_RESET_CP
|
520 RADEON_SOFT_RESET_HI
|
521 RADEON_SOFT_RESET_SE
|
522 RADEON_SOFT_RESET_RE
|
523 RADEON_SOFT_RESET_PP
|
524 RADEON_SOFT_RESET_E2
|
525 RADEON_SOFT_RESET_RB
));
526 RADEON_READ(RADEON_RBBM_SOFT_RESET
);
527 RADEON_WRITE(RADEON_RBBM_SOFT_RESET
, (rbbm_soft_reset
&
528 ~(RADEON_SOFT_RESET_CP
|
529 RADEON_SOFT_RESET_HI
|
530 RADEON_SOFT_RESET_SE
|
531 RADEON_SOFT_RESET_RE
|
532 RADEON_SOFT_RESET_PP
|
533 RADEON_SOFT_RESET_E2
|
534 RADEON_SOFT_RESET_RB
)));
535 RADEON_READ(RADEON_RBBM_SOFT_RESET
);
537 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) <= CHIP_RV410
) {
538 RADEON_WRITE_PLL(RADEON_MCLK_CNTL
, mclk_cntl
);
539 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX
, clock_cntl_index
);
540 RADEON_WRITE(RADEON_RBBM_SOFT_RESET
, rbbm_soft_reset
);
543 /* setup the raster pipes */
544 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R300
)
545 radeon_init_pipes(dev_priv
);
547 /* Reset the CP ring */
548 radeon_do_cp_reset(dev_priv
);
550 /* The CP is no longer running after an engine reset */
551 dev_priv
->cp_running
= 0;
553 /* Reset any pending vertex, indirect buffers */
554 radeon_freelist_reset(dev
);
559 static void radeon_cp_init_ring_buffer(struct drm_device
* dev
,
560 drm_radeon_private_t
* dev_priv
)
562 u32 ring_start
, cur_read_ptr
;
565 /* Initialize the memory controller. With new memory map, the fb location
566 * is not changed, it should have been properly initialized already. Part
567 * of the problem is that the code below is bogus, assuming the GART is
568 * always appended to the fb which is not necessarily the case
570 if (!dev_priv
->new_memmap
)
571 radeon_write_fb_location(dev_priv
,
572 ((dev_priv
->gart_vm_start
- 1) & 0xffff0000)
573 | (dev_priv
->fb_location
>> 16));
576 if (dev_priv
->flags
& RADEON_IS_AGP
) {
577 radeon_write_agp_base(dev_priv
, dev
->agp
->base
);
579 radeon_write_agp_location(dev_priv
,
580 (((dev_priv
->gart_vm_start
- 1 +
581 dev_priv
->gart_size
) & 0xffff0000) |
582 (dev_priv
->gart_vm_start
>> 16)));
584 ring_start
= (dev_priv
->cp_ring
->offset
586 + dev_priv
->gart_vm_start
);
589 ring_start
= (dev_priv
->cp_ring
->offset
590 - (unsigned long)dev
->sg
->virtual
591 + dev_priv
->gart_vm_start
);
593 RADEON_WRITE(RADEON_CP_RB_BASE
, ring_start
);
595 /* Set the write pointer delay */
596 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY
, 0);
598 /* Initialize the ring buffer's read and write pointers */
599 cur_read_ptr
= RADEON_READ(RADEON_CP_RB_RPTR
);
600 RADEON_WRITE(RADEON_CP_RB_WPTR
, cur_read_ptr
);
601 SET_RING_HEAD(dev_priv
, cur_read_ptr
);
602 dev_priv
->ring
.tail
= cur_read_ptr
;
605 if (dev_priv
->flags
& RADEON_IS_AGP
) {
606 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR
,
607 dev_priv
->ring_rptr
->offset
608 - dev
->agp
->base
+ dev_priv
->gart_vm_start
);
612 struct drm_sg_mem
*entry
= dev
->sg
;
613 unsigned long tmp_ofs
, page_ofs
;
615 tmp_ofs
= dev_priv
->ring_rptr
->offset
-
616 (unsigned long)dev
->sg
->virtual;
617 page_ofs
= tmp_ofs
>> PAGE_SHIFT
;
619 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR
, entry
->busaddr
[page_ofs
]);
620 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
621 (unsigned long)entry
->busaddr
[page_ofs
],
622 entry
->handle
+ tmp_ofs
);
625 /* Set ring buffer size */
627 RADEON_WRITE(RADEON_CP_RB_CNTL
,
628 RADEON_BUF_SWAP_32BIT
|
629 (dev_priv
->ring
.fetch_size_l2ow
<< 18) |
630 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
631 dev_priv
->ring
.size_l2qw
);
633 RADEON_WRITE(RADEON_CP_RB_CNTL
,
634 (dev_priv
->ring
.fetch_size_l2ow
<< 18) |
635 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
636 dev_priv
->ring
.size_l2qw
);
640 /* Initialize the scratch register pointer. This will cause
641 * the scratch register values to be written out to memory
642 * whenever they are updated.
644 * We simply put this behind the ring read pointer, this works
645 * with PCI GART as well as (whatever kind of) AGP GART
647 RADEON_WRITE(RADEON_SCRATCH_ADDR
, RADEON_READ(RADEON_CP_RB_RPTR_ADDR
)
648 + RADEON_SCRATCH_REG_OFFSET
);
650 dev_priv
->scratch
= ((__volatile__ u32
*)
651 dev_priv
->ring_rptr
->handle
+
652 (RADEON_SCRATCH_REG_OFFSET
/ sizeof(u32
)));
654 RADEON_WRITE(RADEON_SCRATCH_UMSK
, 0x7);
656 /* Turn on bus mastering */
657 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
658 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
)) {
659 /* rs600/rs690/rs740 */
660 tmp
= RADEON_READ(RADEON_BUS_CNTL
) & ~RS600_BUS_MASTER_DIS
;
661 RADEON_WRITE(RADEON_BUS_CNTL
, tmp
);
662 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) <= CHIP_RV350
) ||
663 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R420
) ||
664 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS400
) ||
665 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS480
)) {
666 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
667 tmp
= RADEON_READ(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
668 RADEON_WRITE(RADEON_BUS_CNTL
, tmp
);
669 } /* PCIE cards appears to not need this */
671 dev_priv
->scratch
[0] = 0;
672 RADEON_WRITE(RADEON_LAST_FRAME_REG
, 0);
674 dev_priv
->scratch
[1] = 0;
675 RADEON_WRITE(RADEON_LAST_DISPATCH_REG
, 0);
677 dev_priv
->scratch
[2] = 0;
678 RADEON_WRITE(RADEON_LAST_CLEAR_REG
, 0);
680 radeon_do_wait_for_idle(dev_priv
);
682 /* Sync everything up */
683 RADEON_WRITE(RADEON_ISYNC_CNTL
,
684 (RADEON_ISYNC_ANY2D_IDLE3D
|
685 RADEON_ISYNC_ANY3D_IDLE2D
|
686 RADEON_ISYNC_WAIT_IDLEGUI
|
687 RADEON_ISYNC_CPSCRATCH_IDLEGUI
));
691 static void radeon_test_writeback(drm_radeon_private_t
* dev_priv
)
695 /* Start with assuming that writeback doesn't work */
696 dev_priv
->writeback_works
= 0;
698 /* Writeback doesn't seem to work everywhere, test it here and possibly
699 * enable it if it appears to work
701 DRM_WRITE32(dev_priv
->ring_rptr
, RADEON_SCRATCHOFF(1), 0);
702 RADEON_WRITE(RADEON_SCRATCH_REG1
, 0xdeadbeef);
704 for (tmp
= 0; tmp
< dev_priv
->usec_timeout
; tmp
++) {
705 if (DRM_READ32(dev_priv
->ring_rptr
, RADEON_SCRATCHOFF(1)) ==
711 if (tmp
< dev_priv
->usec_timeout
) {
712 dev_priv
->writeback_works
= 1;
713 DRM_INFO("writeback test succeeded in %d usecs\n", tmp
);
715 dev_priv
->writeback_works
= 0;
716 DRM_INFO("writeback test failed\n");
718 if (radeon_no_wb
== 1) {
719 dev_priv
->writeback_works
= 0;
720 DRM_INFO("writeback forced off\n");
723 if (!dev_priv
->writeback_works
) {
724 /* Disable writeback to avoid unnecessary bus master transfer */
725 RADEON_WRITE(RADEON_CP_RB_CNTL
, RADEON_READ(RADEON_CP_RB_CNTL
) |
726 RADEON_RB_NO_UPDATE
);
727 RADEON_WRITE(RADEON_SCRATCH_UMSK
, 0);
731 /* Enable or disable IGP GART on the chip */
732 static void radeon_set_igpgart(drm_radeon_private_t
* dev_priv
, int on
)
737 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
738 dev_priv
->gart_vm_start
,
739 (long)dev_priv
->gart_info
.bus_addr
,
740 dev_priv
->gart_size
);
742 temp
= IGP_READ_MCIND(dev_priv
, RS480_MC_MISC_CNTL
);
743 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
744 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
745 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL
, (RS480_GART_INDEX_REG_EN
|
746 RS690_BLOCK_GFX_D3_EN
));
748 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL
, RS480_GART_INDEX_REG_EN
);
750 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE
, (RS480_GART_EN
|
751 RS480_VA_SIZE_32MB
));
753 temp
= IGP_READ_MCIND(dev_priv
, RS480_GART_FEATURE_ID
);
754 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID
, (RS480_HANG_EN
|
759 temp
= dev_priv
->gart_info
.bus_addr
& 0xfffff000;
760 temp
|= (upper_32_bits(dev_priv
->gart_info
.bus_addr
) & 0xff) << 4;
761 IGP_WRITE_MCIND(RS480_GART_BASE
, temp
);
763 temp
= IGP_READ_MCIND(dev_priv
, RS480_AGP_MODE_CNTL
);
764 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL
, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT
) |
765 RS480_REQ_TYPE_SNOOP_DIS
));
767 radeon_write_agp_base(dev_priv
, dev_priv
->gart_vm_start
);
769 dev_priv
->gart_size
= 32*1024*1024;
770 temp
= (((dev_priv
->gart_vm_start
- 1 + dev_priv
->gart_size
) &
771 0xffff0000) | (dev_priv
->gart_vm_start
>> 16));
773 radeon_write_agp_location(dev_priv
, temp
);
775 temp
= IGP_READ_MCIND(dev_priv
, RS480_AGP_ADDRESS_SPACE_SIZE
);
776 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE
, (RS480_GART_EN
|
777 RS480_VA_SIZE_32MB
));
780 temp
= IGP_READ_MCIND(dev_priv
, RS480_GART_CACHE_CNTRL
);
781 if ((temp
& RS480_GART_CACHE_INVALIDATE
) == 0)
786 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL
,
787 RS480_GART_CACHE_INVALIDATE
);
790 temp
= IGP_READ_MCIND(dev_priv
, RS480_GART_CACHE_CNTRL
);
791 if ((temp
& RS480_GART_CACHE_INVALIDATE
) == 0)
796 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL
, 0);
798 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE
, 0);
802 static void radeon_set_pciegart(drm_radeon_private_t
* dev_priv
, int on
)
804 u32 tmp
= RADEON_READ_PCIE(dev_priv
, RADEON_PCIE_TX_GART_CNTL
);
807 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
808 dev_priv
->gart_vm_start
,
809 (long)dev_priv
->gart_info
.bus_addr
,
810 dev_priv
->gart_size
);
811 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO
,
812 dev_priv
->gart_vm_start
);
813 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE
,
814 dev_priv
->gart_info
.bus_addr
);
815 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO
,
816 dev_priv
->gart_vm_start
);
817 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO
,
818 dev_priv
->gart_vm_start
+
819 dev_priv
->gart_size
- 1);
821 radeon_write_agp_location(dev_priv
, 0xffffffc0); /* ?? */
823 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL
,
824 RADEON_PCIE_TX_GART_EN
);
826 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL
,
827 tmp
& ~RADEON_PCIE_TX_GART_EN
);
831 /* Enable or disable PCI GART on the chip */
832 static void radeon_set_pcigart(drm_radeon_private_t
* dev_priv
, int on
)
836 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
837 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
) ||
838 (dev_priv
->flags
& RADEON_IS_IGPGART
)) {
839 radeon_set_igpgart(dev_priv
, on
);
843 if (dev_priv
->flags
& RADEON_IS_PCIE
) {
844 radeon_set_pciegart(dev_priv
, on
);
848 tmp
= RADEON_READ(RADEON_AIC_CNTL
);
851 RADEON_WRITE(RADEON_AIC_CNTL
,
852 tmp
| RADEON_PCIGART_TRANSLATE_EN
);
854 /* set PCI GART page-table base address
856 RADEON_WRITE(RADEON_AIC_PT_BASE
, dev_priv
->gart_info
.bus_addr
);
858 /* set address range for PCI address translate
860 RADEON_WRITE(RADEON_AIC_LO_ADDR
, dev_priv
->gart_vm_start
);
861 RADEON_WRITE(RADEON_AIC_HI_ADDR
, dev_priv
->gart_vm_start
862 + dev_priv
->gart_size
- 1);
864 /* Turn off AGP aperture -- is this required for PCI GART?
866 radeon_write_agp_location(dev_priv
, 0xffffffc0);
867 RADEON_WRITE(RADEON_AGP_COMMAND
, 0); /* clear AGP_COMMAND */
869 RADEON_WRITE(RADEON_AIC_CNTL
,
870 tmp
& ~RADEON_PCIGART_TRANSLATE_EN
);
874 static int radeon_do_init_cp(struct drm_device
*dev
, drm_radeon_init_t
*init
,
875 struct drm_file
*file_priv
)
877 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
878 struct drm_radeon_master_private
*master_priv
= file_priv
->master
->driver_priv
;
882 /* if we require new memory map but we don't have it fail */
883 if ((dev_priv
->flags
& RADEON_NEW_MEMMAP
) && !dev_priv
->new_memmap
) {
884 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
885 radeon_do_cleanup_cp(dev
);
889 if (init
->is_pci
&& (dev_priv
->flags
& RADEON_IS_AGP
)) {
890 DRM_DEBUG("Forcing AGP card to PCI mode\n");
891 dev_priv
->flags
&= ~RADEON_IS_AGP
;
892 } else if (!(dev_priv
->flags
& (RADEON_IS_AGP
| RADEON_IS_PCI
| RADEON_IS_PCIE
))
894 DRM_DEBUG("Restoring AGP flag\n");
895 dev_priv
->flags
|= RADEON_IS_AGP
;
898 if ((!(dev_priv
->flags
& RADEON_IS_AGP
)) && !dev
->sg
) {
899 DRM_ERROR("PCI GART memory not allocated!\n");
900 radeon_do_cleanup_cp(dev
);
904 dev_priv
->usec_timeout
= init
->usec_timeout
;
905 if (dev_priv
->usec_timeout
< 1 ||
906 dev_priv
->usec_timeout
> RADEON_MAX_USEC_TIMEOUT
) {
907 DRM_DEBUG("TIMEOUT problem!\n");
908 radeon_do_cleanup_cp(dev
);
912 /* Enable vblank on CRTC1 for older X servers
914 dev_priv
->vblank_crtc
= DRM_RADEON_VBLANK_CRTC1
;
917 case RADEON_INIT_R200_CP
:
918 dev_priv
->microcode_version
= UCODE_R200
;
920 case RADEON_INIT_R300_CP
:
921 dev_priv
->microcode_version
= UCODE_R300
;
924 dev_priv
->microcode_version
= UCODE_R100
;
927 dev_priv
->do_boxes
= 0;
928 dev_priv
->cp_mode
= init
->cp_mode
;
930 /* We don't support anything other than bus-mastering ring mode,
931 * but the ring can be in either AGP or PCI space for the ring
934 if ((init
->cp_mode
!= RADEON_CSQ_PRIBM_INDDIS
) &&
935 (init
->cp_mode
!= RADEON_CSQ_PRIBM_INDBM
)) {
936 DRM_DEBUG("BAD cp_mode (%x)!\n", init
->cp_mode
);
937 radeon_do_cleanup_cp(dev
);
941 switch (init
->fb_bpp
) {
943 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_RGB565
;
947 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_ARGB8888
;
950 dev_priv
->front_offset
= init
->front_offset
;
951 dev_priv
->front_pitch
= init
->front_pitch
;
952 dev_priv
->back_offset
= init
->back_offset
;
953 dev_priv
->back_pitch
= init
->back_pitch
;
955 switch (init
->depth_bpp
) {
957 dev_priv
->depth_fmt
= RADEON_DEPTH_FORMAT_16BIT_INT_Z
;
961 dev_priv
->depth_fmt
= RADEON_DEPTH_FORMAT_24BIT_INT_Z
;
964 dev_priv
->depth_offset
= init
->depth_offset
;
965 dev_priv
->depth_pitch
= init
->depth_pitch
;
967 /* Hardware state for depth clears. Remove this if/when we no
968 * longer clear the depth buffer with a 3D rectangle. Hard-code
969 * all values to prevent unwanted 3D state from slipping through
970 * and screwing with the clear operation.
972 dev_priv
->depth_clear
.rb3d_cntl
= (RADEON_PLANE_MASK_ENABLE
|
973 (dev_priv
->color_fmt
<< 10) |
974 (dev_priv
->microcode_version
==
975 UCODE_R100
? RADEON_ZBLOCK16
: 0));
977 dev_priv
->depth_clear
.rb3d_zstencilcntl
=
978 (dev_priv
->depth_fmt
|
979 RADEON_Z_TEST_ALWAYS
|
980 RADEON_STENCIL_TEST_ALWAYS
|
981 RADEON_STENCIL_S_FAIL_REPLACE
|
982 RADEON_STENCIL_ZPASS_REPLACE
|
983 RADEON_STENCIL_ZFAIL_REPLACE
| RADEON_Z_WRITE_ENABLE
);
985 dev_priv
->depth_clear
.se_cntl
= (RADEON_FFACE_CULL_CW
|
988 RADEON_FLAT_SHADE_VTX_LAST
|
989 RADEON_DIFFUSE_SHADE_FLAT
|
990 RADEON_ALPHA_SHADE_FLAT
|
991 RADEON_SPECULAR_SHADE_FLAT
|
992 RADEON_FOG_SHADE_FLAT
|
993 RADEON_VTX_PIX_CENTER_OGL
|
994 RADEON_ROUND_MODE_TRUNC
|
995 RADEON_ROUND_PREC_8TH_PIX
);
998 dev_priv
->ring_offset
= init
->ring_offset
;
999 dev_priv
->ring_rptr_offset
= init
->ring_rptr_offset
;
1000 dev_priv
->buffers_offset
= init
->buffers_offset
;
1001 dev_priv
->gart_textures_offset
= init
->gart_textures_offset
;
1003 master_priv
->sarea
= drm_getsarea(dev
);
1004 if (!master_priv
->sarea
) {
1005 DRM_ERROR("could not find sarea!\n");
1006 radeon_do_cleanup_cp(dev
);
1010 dev_priv
->cp_ring
= drm_core_findmap(dev
, init
->ring_offset
);
1011 if (!dev_priv
->cp_ring
) {
1012 DRM_ERROR("could not find cp ring region!\n");
1013 radeon_do_cleanup_cp(dev
);
1016 dev_priv
->ring_rptr
= drm_core_findmap(dev
, init
->ring_rptr_offset
);
1017 if (!dev_priv
->ring_rptr
) {
1018 DRM_ERROR("could not find ring read pointer!\n");
1019 radeon_do_cleanup_cp(dev
);
1022 dev
->agp_buffer_token
= init
->buffers_offset
;
1023 dev
->agp_buffer_map
= drm_core_findmap(dev
, init
->buffers_offset
);
1024 if (!dev
->agp_buffer_map
) {
1025 DRM_ERROR("could not find dma buffer region!\n");
1026 radeon_do_cleanup_cp(dev
);
1030 if (init
->gart_textures_offset
) {
1031 dev_priv
->gart_textures
=
1032 drm_core_findmap(dev
, init
->gart_textures_offset
);
1033 if (!dev_priv
->gart_textures
) {
1034 DRM_ERROR("could not find GART texture region!\n");
1035 radeon_do_cleanup_cp(dev
);
1041 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1042 drm_core_ioremap_wc(dev_priv
->cp_ring
, dev
);
1043 drm_core_ioremap_wc(dev_priv
->ring_rptr
, dev
);
1044 drm_core_ioremap_wc(dev
->agp_buffer_map
, dev
);
1045 if (!dev_priv
->cp_ring
->handle
||
1046 !dev_priv
->ring_rptr
->handle
||
1047 !dev
->agp_buffer_map
->handle
) {
1048 DRM_ERROR("could not find ioremap agp regions!\n");
1049 radeon_do_cleanup_cp(dev
);
1055 dev_priv
->cp_ring
->handle
= (void *)dev_priv
->cp_ring
->offset
;
1056 dev_priv
->ring_rptr
->handle
=
1057 (void *)dev_priv
->ring_rptr
->offset
;
1058 dev
->agp_buffer_map
->handle
=
1059 (void *)dev
->agp_buffer_map
->offset
;
1061 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1062 dev_priv
->cp_ring
->handle
);
1063 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1064 dev_priv
->ring_rptr
->handle
);
1065 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1066 dev
->agp_buffer_map
->handle
);
1069 dev_priv
->fb_location
= (radeon_read_fb_location(dev_priv
) & 0xffff) << 16;
1071 ((radeon_read_fb_location(dev_priv
) & 0xffff0000u
) + 0x10000)
1072 - dev_priv
->fb_location
;
1074 dev_priv
->front_pitch_offset
= (((dev_priv
->front_pitch
/ 64) << 22) |
1075 ((dev_priv
->front_offset
1076 + dev_priv
->fb_location
) >> 10));
1078 dev_priv
->back_pitch_offset
= (((dev_priv
->back_pitch
/ 64) << 22) |
1079 ((dev_priv
->back_offset
1080 + dev_priv
->fb_location
) >> 10));
1082 dev_priv
->depth_pitch_offset
= (((dev_priv
->depth_pitch
/ 64) << 22) |
1083 ((dev_priv
->depth_offset
1084 + dev_priv
->fb_location
) >> 10));
1086 dev_priv
->gart_size
= init
->gart_size
;
1088 /* New let's set the memory map ... */
1089 if (dev_priv
->new_memmap
) {
1092 DRM_INFO("Setting GART location based on new memory map\n");
1094 /* If using AGP, try to locate the AGP aperture at the same
1095 * location in the card and on the bus, though we have to
1099 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1100 base
= dev
->agp
->base
;
1101 /* Check if valid */
1102 if ((base
+ dev_priv
->gart_size
- 1) >= dev_priv
->fb_location
&&
1103 base
< (dev_priv
->fb_location
+ dev_priv
->fb_size
- 1)) {
1104 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1110 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1112 base
= dev_priv
->fb_location
+ dev_priv
->fb_size
;
1113 if (base
< dev_priv
->fb_location
||
1114 ((base
+ dev_priv
->gart_size
) & 0xfffffffful
) < base
)
1115 base
= dev_priv
->fb_location
1116 - dev_priv
->gart_size
;
1118 dev_priv
->gart_vm_start
= base
& 0xffc00000u
;
1119 if (dev_priv
->gart_vm_start
!= base
)
1120 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1121 base
, dev_priv
->gart_vm_start
);
1123 DRM_INFO("Setting GART location based on old memory map\n");
1124 dev_priv
->gart_vm_start
= dev_priv
->fb_location
+
1125 RADEON_READ(RADEON_CONFIG_APER_SIZE
);
1129 if (dev_priv
->flags
& RADEON_IS_AGP
)
1130 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
1132 + dev_priv
->gart_vm_start
);
1135 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
1136 - (unsigned long)dev
->sg
->virtual
1137 + dev_priv
->gart_vm_start
);
1139 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv
->gart_size
);
1140 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv
->gart_vm_start
);
1141 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1142 dev_priv
->gart_buffers_offset
);
1144 dev_priv
->ring
.start
= (u32
*) dev_priv
->cp_ring
->handle
;
1145 dev_priv
->ring
.end
= ((u32
*) dev_priv
->cp_ring
->handle
1146 + init
->ring_size
/ sizeof(u32
));
1147 dev_priv
->ring
.size
= init
->ring_size
;
1148 dev_priv
->ring
.size_l2qw
= drm_order(init
->ring_size
/ 8);
1150 dev_priv
->ring
.rptr_update
= /* init->rptr_update */ 4096;
1151 dev_priv
->ring
.rptr_update_l2qw
= drm_order( /* init->rptr_update */ 4096 / 8);
1153 dev_priv
->ring
.fetch_size
= /* init->fetch_size */ 32;
1154 dev_priv
->ring
.fetch_size_l2ow
= drm_order( /* init->fetch_size */ 32 / 16);
1155 dev_priv
->ring
.tail_mask
= (dev_priv
->ring
.size
/ sizeof(u32
)) - 1;
1157 dev_priv
->ring
.high_mark
= RADEON_RING_HIGH_MARK
;
1160 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1161 /* Turn off PCI GART */
1162 radeon_set_pcigart(dev_priv
, 0);
1166 dev_priv
->gart_info
.table_mask
= DMA_BIT_MASK(32);
1167 /* if we have an offset set from userspace */
1168 if (dev_priv
->pcigart_offset_set
) {
1169 dev_priv
->gart_info
.bus_addr
=
1170 dev_priv
->pcigart_offset
+ dev_priv
->fb_location
;
1171 dev_priv
->gart_info
.mapping
.offset
=
1172 dev_priv
->pcigart_offset
+ dev_priv
->fb_aper_offset
;
1173 dev_priv
->gart_info
.mapping
.size
=
1174 dev_priv
->gart_info
.table_size
;
1176 drm_core_ioremap_wc(&dev_priv
->gart_info
.mapping
, dev
);
1177 dev_priv
->gart_info
.addr
=
1178 dev_priv
->gart_info
.mapping
.handle
;
1180 if (dev_priv
->flags
& RADEON_IS_PCIE
)
1181 dev_priv
->gart_info
.gart_reg_if
= DRM_ATI_GART_PCIE
;
1183 dev_priv
->gart_info
.gart_reg_if
= DRM_ATI_GART_PCI
;
1184 dev_priv
->gart_info
.gart_table_location
=
1187 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1188 dev_priv
->gart_info
.addr
,
1189 dev_priv
->pcigart_offset
);
1191 if (dev_priv
->flags
& RADEON_IS_IGPGART
)
1192 dev_priv
->gart_info
.gart_reg_if
= DRM_ATI_GART_IGP
;
1194 dev_priv
->gart_info
.gart_reg_if
= DRM_ATI_GART_PCI
;
1195 dev_priv
->gart_info
.gart_table_location
=
1197 dev_priv
->gart_info
.addr
= NULL
;
1198 dev_priv
->gart_info
.bus_addr
= 0;
1199 if (dev_priv
->flags
& RADEON_IS_PCIE
) {
1201 ("Cannot use PCI Express without GART in FB memory\n");
1202 radeon_do_cleanup_cp(dev
);
1207 if (!drm_ati_pcigart_init(dev
, &dev_priv
->gart_info
)) {
1208 DRM_ERROR("failed to init PCI GART!\n");
1209 radeon_do_cleanup_cp(dev
);
1213 /* Turn on PCI GART */
1214 radeon_set_pcigart(dev_priv
, 1);
1217 radeon_cp_load_microcode(dev_priv
);
1218 radeon_cp_init_ring_buffer(dev
, dev_priv
);
1220 dev_priv
->last_buf
= 0;
1222 radeon_do_engine_reset(dev
);
1223 radeon_test_writeback(dev_priv
);
1228 static int radeon_do_cleanup_cp(struct drm_device
* dev
)
1230 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1233 /* Make sure interrupts are disabled here because the uninstall ioctl
1234 * may not have been called from userspace and after dev_private
1235 * is freed, it's too late.
1237 if (dev
->irq_enabled
)
1238 drm_irq_uninstall(dev
);
1241 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1242 if (dev_priv
->cp_ring
!= NULL
) {
1243 drm_core_ioremapfree(dev_priv
->cp_ring
, dev
);
1244 dev_priv
->cp_ring
= NULL
;
1246 if (dev_priv
->ring_rptr
!= NULL
) {
1247 drm_core_ioremapfree(dev_priv
->ring_rptr
, dev
);
1248 dev_priv
->ring_rptr
= NULL
;
1250 if (dev
->agp_buffer_map
!= NULL
) {
1251 drm_core_ioremapfree(dev
->agp_buffer_map
, dev
);
1252 dev
->agp_buffer_map
= NULL
;
1258 if (dev_priv
->gart_info
.bus_addr
) {
1259 /* Turn off PCI GART */
1260 radeon_set_pcigart(dev_priv
, 0);
1261 if (!drm_ati_pcigart_cleanup(dev
, &dev_priv
->gart_info
))
1262 DRM_ERROR("failed to cleanup PCI GART!\n");
1265 if (dev_priv
->gart_info
.gart_table_location
== DRM_ATI_GART_FB
)
1267 drm_core_ioremapfree(&dev_priv
->gart_info
.mapping
, dev
);
1268 dev_priv
->gart_info
.addr
= 0;
1271 /* only clear to the start of flags */
1272 memset(dev_priv
, 0, offsetof(drm_radeon_private_t
, flags
));
1277 /* This code will reinit the Radeon CP hardware after a resume from disc.
1278 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1279 * here we make sure that all Radeon hardware initialisation is re-done without
1280 * affecting running applications.
1282 * Charl P. Botha <http://cpbotha.net>
1284 static int radeon_do_resume_cp(struct drm_device
* dev
)
1286 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1289 DRM_ERROR("Called with no initialization\n");
1293 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1296 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1297 /* Turn off PCI GART */
1298 radeon_set_pcigart(dev_priv
, 0);
1302 /* Turn on PCI GART */
1303 radeon_set_pcigart(dev_priv
, 1);
1306 radeon_cp_load_microcode(dev_priv
);
1307 radeon_cp_init_ring_buffer(dev
, dev_priv
);
1309 radeon_do_engine_reset(dev
);
1310 radeon_irq_set_state(dev
, RADEON_SW_INT_ENABLE
, 1);
1312 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1317 int radeon_cp_init(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1319 drm_radeon_init_t
*init
= data
;
1321 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1323 if (init
->func
== RADEON_INIT_R300_CP
)
1324 r300_init_reg_flags(dev
);
1326 switch (init
->func
) {
1327 case RADEON_INIT_CP
:
1328 case RADEON_INIT_R200_CP
:
1329 case RADEON_INIT_R300_CP
:
1330 return radeon_do_init_cp(dev
, init
, file_priv
);
1331 case RADEON_CLEANUP_CP
:
1332 return radeon_do_cleanup_cp(dev
);
1338 int radeon_cp_start(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1340 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1343 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1345 if (dev_priv
->cp_running
) {
1346 DRM_DEBUG("while CP running\n");
1349 if (dev_priv
->cp_mode
== RADEON_CSQ_PRIDIS_INDDIS
) {
1350 DRM_DEBUG("called with bogus CP mode (%d)\n",
1355 radeon_do_cp_start(dev_priv
);
1360 /* Stop the CP. The engine must have been idled before calling this
1363 int radeon_cp_stop(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1365 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1366 drm_radeon_cp_stop_t
*stop
= data
;
1370 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1372 if (!dev_priv
->cp_running
)
1375 /* Flush any pending CP commands. This ensures any outstanding
1376 * commands are exectuted by the engine before we turn it off.
1379 radeon_do_cp_flush(dev_priv
);
1382 /* If we fail to make the engine go idle, we return an error
1383 * code so that the DRM ioctl wrapper can try again.
1386 ret
= radeon_do_cp_idle(dev_priv
);
1391 /* Finally, we can turn off the CP. If the engine isn't idle,
1392 * we will get some dropped triangles as they won't be fully
1393 * rendered before the CP is shut down.
1395 radeon_do_cp_stop(dev_priv
);
1397 /* Reset the engine */
1398 radeon_do_engine_reset(dev
);
1403 void radeon_do_release(struct drm_device
* dev
)
1405 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1409 if (dev_priv
->cp_running
) {
1411 while ((ret
= radeon_do_cp_idle(dev_priv
)) != 0) {
1412 DRM_DEBUG("radeon_do_cp_idle %d\n", ret
);
1416 tsleep(&ret
, PZERO
, "rdnrel", 1);
1419 radeon_do_cp_stop(dev_priv
);
1420 radeon_do_engine_reset(dev
);
1423 /* Disable *all* interrupts */
1424 if (dev_priv
->mmio
) /* remove this after permanent addmaps */
1425 RADEON_WRITE(RADEON_GEN_INT_CNTL
, 0);
1427 if (dev_priv
->mmio
) { /* remove all surfaces */
1428 for (i
= 0; i
< RADEON_MAX_SURFACES
; i
++) {
1429 RADEON_WRITE(RADEON_SURFACE0_INFO
+ 16 * i
, 0);
1430 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND
+
1432 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND
+
1437 /* Free memory heap structures */
1438 radeon_mem_takedown(&(dev_priv
->gart_heap
));
1439 radeon_mem_takedown(&(dev_priv
->fb_heap
));
1441 /* deallocate kernel resources */
1442 radeon_do_cleanup_cp(dev
);
1446 /* Just reset the CP ring. Called as part of an X Server engine reset.
1448 int radeon_cp_reset(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1450 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1453 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1456 DRM_DEBUG("called before init done\n");
1460 radeon_do_cp_reset(dev_priv
);
1462 /* The CP is no longer running after an engine reset */
1463 dev_priv
->cp_running
= 0;
1468 int radeon_cp_idle(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1470 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1473 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1475 return radeon_do_cp_idle(dev_priv
);
1478 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1480 int radeon_cp_resume(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1483 return radeon_do_resume_cp(dev
);
1486 int radeon_engine_reset(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1490 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1492 return radeon_do_engine_reset(dev
);
1495 /* ================================================================
1499 /* KW: Deprecated to say the least:
1501 int radeon_fullscreen(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1506 /* ================================================================
1507 * Freelist management
1510 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1511 * bufs until freelist code is used. Note this hides a problem with
1512 * the scratch register * (used to keep track of last buffer
1513 * completed) being written to before * the last buffer has actually
1514 * completed rendering.
1516 * KW: It's also a good way to find free buffers quickly.
1518 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1519 * sleep. However, bugs in older versions of radeon_accel.c mean that
1520 * we essentially have to do this, else old clients will break.
1522 * However, it does leave open a potential deadlock where all the
1523 * buffers are held by other clients, which can't release them because
1524 * they can't get the lock.
1527 struct drm_buf
*radeon_freelist_get(struct drm_device
* dev
)
1529 struct drm_device_dma
*dma
= dev
->dma
;
1530 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1531 drm_radeon_buf_priv_t
*buf_priv
;
1532 struct drm_buf
*buf
;
1536 if (++dev_priv
->last_buf
>= dma
->buf_count
)
1537 dev_priv
->last_buf
= 0;
1539 start
= dev_priv
->last_buf
;
1541 for (t
= 0; t
< dev_priv
->usec_timeout
; t
++) {
1542 u32 done_age
= GET_SCRATCH(1);
1543 DRM_DEBUG("done_age = %d\n", done_age
);
1544 for (i
= start
; i
< dma
->buf_count
; i
++) {
1545 buf
= dma
->buflist
[i
];
1546 buf_priv
= buf
->dev_private
;
1547 if (buf
->file_priv
== NULL
|| (buf
->pending
&&
1550 dev_priv
->stats
.requested_bufs
++;
1559 dev_priv
->stats
.freelist_loops
++;
1563 DRM_DEBUG("returning NULL!\n");
1568 struct drm_buf
*radeon_freelist_get(struct drm_device
* dev
)
1570 struct drm_device_dma
*dma
= dev
->dma
;
1571 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1572 drm_radeon_buf_priv_t
*buf_priv
;
1573 struct drm_buf
*buf
;
1576 u32 done_age
= DRM_READ32(dev_priv
->ring_rptr
, RADEON_SCRATCHOFF(1));
1578 if (++dev_priv
->last_buf
>= dma
->buf_count
)
1579 dev_priv
->last_buf
= 0;
1581 start
= dev_priv
->last_buf
;
1582 dev_priv
->stats
.freelist_loops
++;
1584 for (t
= 0; t
< 2; t
++) {
1585 for (i
= start
; i
< dma
->buf_count
; i
++) {
1586 buf
= dma
->buflist
[i
];
1587 buf_priv
= buf
->dev_private
;
1588 if (buf
->file_priv
== 0 || (buf
->pending
&&
1591 dev_priv
->stats
.requested_bufs
++;
1603 void radeon_freelist_reset(struct drm_device
* dev
)
1605 struct drm_device_dma
*dma
= dev
->dma
;
1606 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1609 dev_priv
->last_buf
= 0;
1610 for (i
= 0; i
< dma
->buf_count
; i
++) {
1611 struct drm_buf
*buf
= dma
->buflist
[i
];
1612 drm_radeon_buf_priv_t
*buf_priv
= buf
->dev_private
;
1617 /* ================================================================
1618 * CP command submission
1621 int radeon_wait_ring(drm_radeon_private_t
* dev_priv
, int n
)
1623 drm_radeon_ring_buffer_t
*ring
= &dev_priv
->ring
;
1625 u32 last_head
= GET_RING_HEAD(dev_priv
);
1627 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
1628 u32 head
= GET_RING_HEAD(dev_priv
);
1630 ring
->space
= (head
- ring
->tail
) * sizeof(u32
);
1631 if (ring
->space
<= 0)
1632 ring
->space
+= ring
->size
;
1633 if (ring
->space
> n
)
1636 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
1638 if (head
!= last_head
)
1645 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1646 #if RADEON_FIFO_DEBUG
1647 radeon_status(dev_priv
);
1648 DRM_ERROR("failed!\n");
1653 static int radeon_cp_get_buffers(struct drm_device
*dev
,
1654 struct drm_file
*file_priv
,
1658 struct drm_buf
*buf
;
1660 for (i
= d
->granted_count
; i
< d
->request_count
; i
++) {
1661 buf
= radeon_freelist_get(dev
);
1663 return -EBUSY
; /* NOTE: broken client */
1665 buf
->file_priv
= file_priv
;
1667 if (DRM_COPY_TO_USER(&d
->request_indices
[i
], &buf
->idx
,
1670 if (DRM_COPY_TO_USER(&d
->request_sizes
[i
], &buf
->total
,
1671 sizeof(buf
->total
)))
1679 int radeon_cp_buffers(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1681 struct drm_device_dma
*dma
= dev
->dma
;
1683 struct drm_dma
*d
= data
;
1685 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1687 /* Please don't send us buffers.
1689 if (d
->send_count
!= 0) {
1690 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1691 DRM_CURRENTPID
, d
->send_count
);
1695 /* We'll send you buffers.
1697 if (d
->request_count
< 0 || d
->request_count
> dma
->buf_count
) {
1698 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1699 DRM_CURRENTPID
, d
->request_count
, dma
->buf_count
);
1703 d
->granted_count
= 0;
1705 if (d
->request_count
) {
1706 ret
= radeon_cp_get_buffers(dev
, file_priv
, d
);
1712 int radeon_driver_load(struct drm_device
*dev
, unsigned long flags
)
1714 drm_radeon_private_t
*dev_priv
;
1717 dev_priv
= drm_alloc(sizeof(drm_radeon_private_t
), DRM_MEM_DRIVER
);
1718 if (dev_priv
== NULL
)
1721 memset(dev_priv
, 0, sizeof(drm_radeon_private_t
));
1722 dev
->dev_private
= (void *)dev_priv
;
1723 dev_priv
->flags
= flags
;
1725 switch (flags
& RADEON_FAMILY_MASK
) {
1738 dev_priv
->flags
|= RADEON_HAS_HIERZ
;
1741 /* all other chips have no hierarchical z buffer */
1745 if (drm_device_is_agp(dev
))
1746 dev_priv
->flags
|= RADEON_IS_AGP
;
1747 else if (drm_device_is_pcie(dev
))
1748 dev_priv
->flags
|= RADEON_IS_PCIE
;
1750 dev_priv
->flags
|= RADEON_IS_PCI
;
1752 ret
= drm_addmap(dev
, drm_get_resource_start(dev
, 2),
1753 drm_get_resource_len(dev
, 2), _DRM_REGISTERS
,
1754 _DRM_READ_ONLY
| _DRM_DRIVER
, &dev_priv
->mmio
);
1758 ret
= drm_vblank_init(dev
, 2);
1760 radeon_driver_unload(dev
);
1764 DRM_DEBUG("%s card detected\n",
1765 ((dev_priv
->flags
& RADEON_IS_AGP
) ? "AGP" : (((dev_priv
->flags
& RADEON_IS_PCIE
) ? "PCIE" : "PCI"))));
1769 int radeon_master_create(struct drm_device
*dev
, struct drm_master
*master
)
1771 struct drm_radeon_master_private
*master_priv
;
1772 unsigned long sareapage
;
1775 master_priv
= drm_calloc(1, sizeof(*master_priv
), DRM_MEM_DRIVER
);
1779 /* prebuild the SAREA */
1780 sareapage
= max_t(unsigned long, SAREA_MAX
, PAGE_SIZE
);
1781 ret
= drm_addmap(dev
, 0, sareapage
, _DRM_SHM
, _DRM_CONTAINS_LOCK
|_DRM_DRIVER
,
1782 &master_priv
->sarea
);
1784 DRM_ERROR("SAREA setup failed\n");
1787 master_priv
->sarea_priv
= master_priv
->sarea
->handle
+ sizeof(struct drm_sarea
);
1788 master_priv
->sarea_priv
->pfCurrentPage
= 0;
1790 master
->driver_priv
= master_priv
;
1794 void radeon_master_destroy(struct drm_device
*dev
, struct drm_master
*master
)
1796 struct drm_radeon_master_private
*master_priv
= master
->driver_priv
;
1801 if (master_priv
->sarea_priv
&&
1802 master_priv
->sarea_priv
->pfCurrentPage
!= 0)
1803 radeon_cp_dispatch_flip(dev
, master
);
1805 master_priv
->sarea_priv
= NULL
;
1806 if (master_priv
->sarea
)
1807 drm_rmmap_locked(dev
, master_priv
->sarea
);
1809 drm_free(master_priv
, sizeof(*master_priv
), DRM_MEM_DRIVER
);
1811 master
->driver_priv
= NULL
;
1814 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1815 * have to find them.
1817 int radeon_driver_firstopen(struct drm_device
*dev
)
1820 drm_local_map_t
*map
;
1821 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1823 dev_priv
->gart_info
.table_size
= RADEON_PCIGART_TABLE_SIZE
;
1825 dev_priv
->fb_aper_offset
= drm_get_resource_start(dev
, 0);
1826 ret
= drm_addmap(dev
, dev_priv
->fb_aper_offset
,
1827 drm_get_resource_len(dev
, 0), _DRM_FRAME_BUFFER
,
1828 _DRM_WRITE_COMBINING
, &map
);
1835 int radeon_driver_unload(struct drm_device
*dev
)
1837 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1841 drm_rmmap(dev
, dev_priv
->mmio
);
1843 drm_free(dev_priv
, sizeof(*dev_priv
), DRM_MEM_DRIVER
);
1845 dev
->dev_private
= NULL
;