drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <linux/efi.h>
  36 #include "radeon_reg.h"
  37 #include "radeon.h"
  38 #include "atom.h"
  39
  40 static const char radeon_family_name[][16] = {
  41         "R100",
  42         "RV100",
  43         "RS100",
  44         "RV200",
  45         "RS200",
  46         "R200",
  47         "RV250",
  48         "RS300",
  49         "RV280",
  50         "R300",
  51         "R350",
  52         "RV350",
  53         "RV380",
  54         "R420",
  55         "R423",
  56         "RV410",
  57         "RS400",
  58         "RS480",
  59         "RS600",
  60         "RS690",
  61         "RS740",
  62         "RV515",
  63         "R520",
  64         "RV530",
  65         "RV560",
  66         "RV570",
  67         "R580",
  68         "R600",
  69         "RV610",
  70         "RV630",
  71         "RV670",
  72         "RV620",
  73         "RV635",
  74         "RS780",
  75         "RS880",
  76         "RV770",
  77         "RV730",
  78         "RV710",
  79         "RV740",
  80         "CEDAR",
  81         "REDWOOD",
  82         "JUNIPER",
  83         "CYPRESS",
  84         "HEMLOCK",
  85         "PALM",
  86         "SUMO",
  87         "SUMO2",
  88         "BARTS",
  89         "TURKS",
  90         "CAICOS",
  91         "CAYMAN",
  92         "ARUBA",
  93         "TAHITI",
  94         "PITCAIRN",
  95         "VERDE",
  96         "LAST",
  97 };
  98
  99 /**
 100  * radeon_surface_init - Clear GPU surface registers.
 101  *
 102  * @rdev: radeon_device pointer
 103  *
 104  * Clear GPU surface registers (r1xx-r5xx).
 105  */
 106 void radeon_surface_init(struct radeon_device *rdev)
 107 {
 108         /* FIXME: check this out */
 109         if (rdev->family < CHIP_R600) {
 110                 int i;
 111
 112                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 113                         if (rdev->surface_regs[i].bo)
 114                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
 115                         else
 116                                 radeon_clear_surface_reg(rdev, i);
 117                 }
 118                 /* enable surfaces */
 119                 WREG32(RADEON_SURFACE_CNTL, 0);
 120         }
 121 }
 122
 123 /*
 124  * GPU scratch registers helpers function.
 125  */
 126 /**
 127  * radeon_scratch_init - Init scratch register driver information.
 128  *
 129  * @rdev: radeon_device pointer
 130  *
 131  * Init CP scratch register driver information (r1xx-r5xx)
 132  */
 133 void radeon_scratch_init(struct radeon_device *rdev)
 134 {
 135         int i;
 136
 137         /* FIXME: check this out */
 138         if (rdev->family < CHIP_R300) {
 139                 rdev->scratch.num_reg = 5;
 140         } else {
 141                 rdev->scratch.num_reg = 7;
 142         }
 143         rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
 144         for (i = 0; i < rdev->scratch.num_reg; i++) {
 145                 rdev->scratch.free[i] = true;
 146                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
 147         }
 148 }
 149
 150 /**
 151  * radeon_scratch_get - Allocate a scratch register
 152  *
 153  * @rdev: radeon_device pointer
 154  * @reg: scratch register mmio offset
 155  *
 156  * Allocate a CP scratch register for use by the driver (all asics).
 157  * Returns 0 on success or -EINVAL on failure.
 158  */
 159 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 160 {
 161         int i;
 162
 163         for (i = 0; i < rdev->scratch.num_reg; i++) {
 164                 if (rdev->scratch.free[i]) {
 165                         rdev->scratch.free[i] = false;
 166                         *reg = rdev->scratch.reg[i];
 167                         return 0;
 168                 }
 169         }
 170         return -EINVAL;
 171 }
 172
 173 /**
 174  * radeon_scratch_free - Free a scratch register
 175  *
 176  * @rdev: radeon_device pointer
 177  * @reg: scratch register mmio offset
 178  *
 179  * Free a CP scratch register allocated for use by the driver (all asics)
 180  */
 181 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 182 {
 183         int i;
 184
 185         for (i = 0; i < rdev->scratch.num_reg; i++) {
 186                 if (rdev->scratch.reg[i] == reg) {
 187                         rdev->scratch.free[i] = true;
 188                         return;
 189                 }
 190         }
 191 }
 192
 193 /*
 194  * radeon_wb_*()
 195  * Writeback is the the method by which the the GPU updates special pages
 196  * in memory with the status of certain GPU events (fences, ring pointers,
 197  * etc.).
 198  */
 199
 200 /**
 201  * radeon_wb_disable - Disable Writeback
 202  *
 203  * @rdev: radeon_device pointer
 204  *
 205  * Disables Writeback (all asics).  Used for suspend.
 206  */
 207 void radeon_wb_disable(struct radeon_device *rdev)
 208 {
 209         int r;
 210
 211         if (rdev->wb.wb_obj) {
 212                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 213                 if (unlikely(r != 0))
 214                         return;
 215                 radeon_bo_kunmap(rdev->wb.wb_obj);
 216                 radeon_bo_unpin(rdev->wb.wb_obj);
 217                 radeon_bo_unreserve(rdev->wb.wb_obj);
 218         }
 219         rdev->wb.enabled = false;
 220 }
 221
 222 /**
 223  * radeon_wb_fini - Disable Writeback and free memory
 224  *
 225  * @rdev: radeon_device pointer
 226  *
 227  * Disables Writeback and frees the Writeback memory (all asics).
 228  * Used at driver shutdown.
 229  */
 230 void radeon_wb_fini(struct radeon_device *rdev)
 231 {
 232         radeon_wb_disable(rdev);
 233         if (rdev->wb.wb_obj) {
 234                 radeon_bo_unref(&rdev->wb.wb_obj);
 235                 rdev->wb.wb = NULL;
 236                 rdev->wb.wb_obj = NULL;
 237         }
 238 }
 239
 240 /**
 241  * radeon_wb_init- Init Writeback driver info and allocate memory
 242  *
 243  * @rdev: radeon_device pointer
 244  *
 245  * Disables Writeback and frees the Writeback memory (all asics).
 246  * Used at driver startup.
 247  * Returns 0 on success or an -error on failure.
 248  */
 249 int radeon_wb_init(struct radeon_device *rdev)
 250 {
 251         int r;
 252
 253         if (rdev->wb.wb_obj == NULL) {
 254                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
 255                                      RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
 256                 if (r) {
 257                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 258                         return r;
 259                 }
 260         }
 261         r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 262         if (unlikely(r != 0)) {
 263                 radeon_wb_fini(rdev);
 264                 return r;
 265         }
 266         r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 267                           &rdev->wb.gpu_addr);
 268         if (r) {
 269                 radeon_bo_unreserve(rdev->wb.wb_obj);
 270                 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
 271                 radeon_wb_fini(rdev);
 272                 return r;
 273         }
 274         r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 275         radeon_bo_unreserve(rdev->wb.wb_obj);
 276         if (r) {
 277                 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 278                 radeon_wb_fini(rdev);
 279                 return r;
 280         }
 281
 282         /* clear wb memory */
 283         memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 284         /* disable event_write fences */
 285         rdev->wb.use_event = false;
 286         /* disabled via module param */
 287         if (radeon_no_wb == 1) {
 288                 rdev->wb.enabled = false;
 289         } else {
 290                 if (rdev->flags & RADEON_IS_AGP) {
 291                         /* often unreliable on AGP */
 292                         rdev->wb.enabled = false;
 293                 } else if (rdev->family < CHIP_R300) {
 294                         /* often unreliable on pre-r300 */
 295                         rdev->wb.enabled = false;
 296                 } else {
 297                         rdev->wb.enabled = true;
 298                         /* event_write fences are only available on r600+ */
 299                         if (rdev->family >= CHIP_R600) {
 300                                 rdev->wb.use_event = true;
 301                         }
 302                 }
 303         }
 304         /* always use writeback/events on NI, APUs */
 305         if (rdev->family >= CHIP_PALM) {
 306                 rdev->wb.enabled = true;
 307                 rdev->wb.use_event = true;
 308         }
 309
 310         dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 311
 312         return 0;
 313 }
 314
 315 /**
 316  * radeon_vram_location - try to find VRAM location
 317  * @rdev: radeon device structure holding all necessary informations
 318  * @mc: memory controller structure holding memory informations
 319  * @base: base address at which to put VRAM
 320  *
 321  * Function will place try to place VRAM at base address provided
 322  * as parameter (which is so far either PCI aperture address or
 323  * for IGP TOM base address).
 324  *
 325  * If there is not enough space to fit the unvisible VRAM in the 32bits
 326  * address space then we limit the VRAM size to the aperture.
 327  *
 328  * If we are using AGP and if the AGP aperture doesn't allow us to have
 329  * room for all the VRAM than we restrict the VRAM to the PCI aperture
 330  * size and print a warning.
 331  *
 332  * This function will never fails, worst case are limiting VRAM.
 333  *
 334  * Note: GTT start, end, size should be initialized before calling this
 335  * function on AGP platform.
 336  *
 337  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 338  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 339  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 340  * not IGP.
 341  *
 342  * Note: we use mc_vram_size as on some board we need to program the mc to
 343  * cover the whole aperture even if VRAM size is inferior to aperture size
 344  * Novell bug 204882 + along with lots of ubuntu ones
 345  *
 346  * Note: when limiting vram it's safe to overwritte real_vram_size because
 347  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 348  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 349  * ones)
 350  *
 351  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 352  * explicitly check for that thought.
 353  *
 354  * FIXME: when reducing VRAM size align new size on power of 2.
 355  */
 356 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 357 {
 358         uint64_t limit = (uint64_t)radeon_vram_limit << 20;
 359
 360         mc->vram_start = base;
 361         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
 362                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 363                 mc->real_vram_size = mc->aper_size;
 364                 mc->mc_vram_size = mc->aper_size;
 365         }
 366         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 367         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 368                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 369                 mc->real_vram_size = mc->aper_size;
 370                 mc->mc_vram_size = mc->aper_size;
 371         }
 372         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 373         if (limit && limit < mc->real_vram_size)
 374                 mc->real_vram_size = limit;
 375         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 376                         mc->mc_vram_size >> 20, mc->vram_start,
 377                         mc->vram_end, mc->real_vram_size >> 20);
 378 }
 379
 380 /**
 381  * radeon_gtt_location - try to find GTT location
 382  * @rdev: radeon device structure holding all necessary informations
 383  * @mc: memory controller structure holding memory informations
 384  *
 385  * Function will place try to place GTT before or after VRAM.
 386  *
 387  * If GTT size is bigger than space left then we ajust GTT size.
 388  * Thus function will never fails.
 389  *
 390  * FIXME: when reducing GTT size align new size on power of 2.
 391  */
 392 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 393 {
 394         u64 size_af, size_bf;
 395
 396         size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 397         size_bf = mc->vram_start & ~mc->gtt_base_align;
 398         if (size_bf > size_af) {
 399                 if (mc->gtt_size > size_bf) {
 400                         dev_warn(rdev->dev, "limiting GTT\n");
 401                         mc->gtt_size = size_bf;
 402                 }
 403                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 404         } else {
 405                 if (mc->gtt_size > size_af) {
 406                         dev_warn(rdev->dev, "limiting GTT\n");
 407                         mc->gtt_size = size_af;
 408                 }
 409                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 410         }
 411         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 412         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 413                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 414 }
 415
 416 /*
 417  * GPU helpers function.
 418  */
 419 /**
 420  * radeon_card_posted - check if the hw has already been initialized
 421  *
 422  * @rdev: radeon_device pointer
 423  *
 424  * Check if the asic has been initialized (all asics).
 425  * Used at driver startup.
 426  * Returns true if initialized or false if not.
 427  */
 428 bool radeon_card_posted(struct radeon_device *rdev)
 429 {
 430         uint32_t reg;
 431
 432         if (efi_enabled(EFI_BOOT) &&
 433             rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
 434                 return false;
 435
 436         /* first check CRTCs */
 437         if (ASIC_IS_DCE41(rdev)) {
 438                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 439                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 440                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 441                         return true;
 442         } else if (ASIC_IS_DCE4(rdev)) {
 443                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 444                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
 445                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 446                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
 447                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 448                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 449                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 450                         return true;
 451         } else if (ASIC_IS_AVIVO(rdev)) {
 452                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 453                       RREG32(AVIVO_D2CRTC_CONTROL);
 454                 if (reg & AVIVO_CRTC_EN) {
 455                         return true;
 456                 }
 457         } else {
 458                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 459                       RREG32(RADEON_CRTC2_GEN_CNTL);
 460                 if (reg & RADEON_CRTC_EN) {
 461                         return true;
 462                 }
 463         }
 464
 465         /* then check MEM_SIZE, in case the crtcs are off */
 466         if (rdev->family >= CHIP_R600)
 467                 reg = RREG32(R600_CONFIG_MEMSIZE);
 468         else
 469                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 470
 471         if (reg)
 472                 return true;
 473
 474         return false;
 475
 476 }
 477
 478 /**
 479  * radeon_update_bandwidth_info - update display bandwidth params
 480  *
 481  * @rdev: radeon_device pointer
 482  *
 483  * Used when sclk/mclk are switched or display modes are set.
 484  * params are used to calculate display watermarks (all asics)
 485  */
 486 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 487 {
 488         fixed20_12 a;
 489         u32 sclk = rdev->pm.current_sclk;
 490         u32 mclk = rdev->pm.current_mclk;
 491
 492         /* sclk/mclk in Mhz */
 493         a.full = dfixed_const(100);
 494         rdev->pm.sclk.full = dfixed_const(sclk);
 495         rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 496         rdev->pm.mclk.full = dfixed_const(mclk);
 497         rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 498
 499         if (rdev->flags & RADEON_IS_IGP) {
 500                 a.full = dfixed_const(16);
 501                 /* core_bandwidth = sclk(Mhz) * 16 */
 502                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 503         }
 504 }
 505
 506 /**
 507  * radeon_boot_test_post_card - check and possibly initialize the hw
 508  *
 509  * @rdev: radeon_device pointer
 510  *
 511  * Check if the asic is initialized and if not, attempt to initialize
 512  * it (all asics).
 513  * Returns true if initialized or false if not.
 514  */
 515 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 516 {
 517         if (radeon_card_posted(rdev))
 518                 return true;
 519
 520         if (rdev->bios) {
 521                 DRM_INFO("GPU not posted. posting now...\n");
 522                 if (rdev->is_atom_bios)
 523                         atom_asic_init(rdev->mode_info.atom_context);
 524                 else
 525                         radeon_combios_asic_init(rdev->ddev);
 526                 return true;
 527         } else {
 528                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 529                 return false;
 530         }
 531 }
 532
 533 /**
 534  * radeon_dummy_page_init - init dummy page used by the driver
 535  *
 536  * @rdev: radeon_device pointer
 537  *
 538  * Allocate the dummy page used by the driver (all asics).
 539  * This dummy page is used by the driver as a filler for gart entries
 540  * when pages are taken out of the GART
 541  * Returns 0 on sucess, -ENOMEM on failure.
 542  */
 543 int radeon_dummy_page_init(struct radeon_device *rdev)
 544 {
 545         if (rdev->dummy_page.page)
 546                 return 0;
 547         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 548         if (rdev->dummy_page.page == NULL)
 549                 return -ENOMEM;
 550         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 551                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 552         if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
 553                 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 554                 __free_page(rdev->dummy_page.page);
 555                 rdev->dummy_page.page = NULL;
 556                 return -ENOMEM;
 557         }
 558         return 0;
 559 }
 560
 561 /**
 562  * radeon_dummy_page_fini - free dummy page used by the driver
 563  *
 564  * @rdev: radeon_device pointer
 565  *
 566  * Frees the dummy page used by the driver (all asics).
 567  */
 568 void radeon_dummy_page_fini(struct radeon_device *rdev)
 569 {
 570         if (rdev->dummy_page.page == NULL)
 571                 return;
 572         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 573                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 574         __free_page(rdev->dummy_page.page);
 575         rdev->dummy_page.page = NULL;
 576 }
 577
 578
 579 /* ATOM accessor methods */
 580 /*
 581  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 582  * driver registers callbacks to access registers and the interpreter
 583  * in the driver parses the tables and executes then to program specific
 584  * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
 585  * atombios.h, and atom.c
 586  */
 587
 588 /**
 589  * cail_pll_read - read PLL register
 590  *
 591  * @info: atom card_info pointer
 592  * @reg: PLL register offset
 593  *
 594  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 595  * Returns the value of the PLL register.
 596  */
 597 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 598 {
 599         struct radeon_device *rdev = info->dev->dev_private;
 600         uint32_t r;
 601
 602         r = rdev->pll_rreg(rdev, reg);
 603         return r;
 604 }
 605
 606 /**
 607  * cail_pll_write - write PLL register
 608  *
 609  * @info: atom card_info pointer
 610  * @reg: PLL register offset
 611  * @val: value to write to the pll register
 612  *
 613  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 614  */
 615 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 616 {
 617         struct radeon_device *rdev = info->dev->dev_private;
 618
 619         rdev->pll_wreg(rdev, reg, val);
 620 }
 621
 622 /**
 623  * cail_mc_read - read MC (Memory Controller) register
 624  *
 625  * @info: atom card_info pointer
 626  * @reg: MC register offset
 627  *
 628  * Provides an MC register accessor for the atom interpreter (r4xx+).
 629  * Returns the value of the MC register.
 630  */
 631 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 632 {
 633         struct radeon_device *rdev = info->dev->dev_private;
 634         uint32_t r;
 635
 636         r = rdev->mc_rreg(rdev, reg);
 637         return r;
 638 }
 639
 640 /**
 641  * cail_mc_write - write MC (Memory Controller) register
 642  *
 643  * @info: atom card_info pointer
 644  * @reg: MC register offset
 645  * @val: value to write to the pll register
 646  *
 647  * Provides a MC register accessor for the atom interpreter (r4xx+).
 648  */
 649 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 650 {
 651         struct radeon_device *rdev = info->dev->dev_private;
 652
 653         rdev->mc_wreg(rdev, reg, val);
 654 }
 655
 656 /**
 657  * cail_reg_write - write MMIO register
 658  *
 659  * @info: atom card_info pointer
 660  * @reg: MMIO register offset
 661  * @val: value to write to the pll register
 662  *
 663  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 664  */
 665 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 666 {
 667         struct radeon_device *rdev = info->dev->dev_private;
 668
 669         WREG32(reg*4, val);
 670 }
 671
 672 /**
 673  * cail_reg_read - read MMIO register
 674  *
 675  * @info: atom card_info pointer
 676  * @reg: MMIO register offset
 677  *
 678  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 679  * Returns the value of the MMIO register.
 680  */
 681 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 682 {
 683         struct radeon_device *rdev = info->dev->dev_private;
 684         uint32_t r;
 685
 686         r = RREG32(reg*4);
 687         return r;
 688 }
 689
 690 /**
 691  * cail_ioreg_write - write IO register
 692  *
 693  * @info: atom card_info pointer
 694  * @reg: IO register offset
 695  * @val: value to write to the pll register
 696  *
 697  * Provides a IO register accessor for the atom interpreter (r4xx+).
 698  */
 699 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 700 {
 701         struct radeon_device *rdev = info->dev->dev_private;
 702
 703         WREG32_IO(reg*4, val);
 704 }
 705
 706 /**
 707  * cail_ioreg_read - read IO register
 708  *
 709  * @info: atom card_info pointer
 710  * @reg: IO register offset
 711  *
 712  * Provides an IO register accessor for the atom interpreter (r4xx+).
 713  * Returns the value of the IO register.
 714  */
 715 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 716 {
 717         struct radeon_device *rdev = info->dev->dev_private;
 718         uint32_t r;
 719
 720         r = RREG32_IO(reg*4);
 721         return r;
 722 }
 723
 724 /**
 725  * radeon_atombios_init - init the driver info and callbacks for atombios
 726  *
 727  * @rdev: radeon_device pointer
 728  *
 729  * Initializes the driver info and register access callbacks for the
 730  * ATOM interpreter (r4xx+).
 731  * Returns 0 on sucess, -ENOMEM on failure.
 732  * Called at driver startup.
 733  */
 734 int radeon_atombios_init(struct radeon_device *rdev)
 735 {
 736         struct card_info *atom_card_info =
 737             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 738
 739         if (!atom_card_info)
 740                 return -ENOMEM;
 741
 742         rdev->mode_info.atom_card_info = atom_card_info;
 743         atom_card_info->dev = rdev->ddev;
 744         atom_card_info->reg_read = cail_reg_read;
 745         atom_card_info->reg_write = cail_reg_write;
 746         /* needed for iio ops */
 747         if (rdev->rio_mem) {
 748                 atom_card_info->ioreg_read = cail_ioreg_read;
 749                 atom_card_info->ioreg_write = cail_ioreg_write;
 750         } else {
 751                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 752                 atom_card_info->ioreg_read = cail_reg_read;
 753                 atom_card_info->ioreg_write = cail_reg_write;
 754         }
 755         atom_card_info->mc_read = cail_mc_read;
 756         atom_card_info->mc_write = cail_mc_write;
 757         atom_card_info->pll_read = cail_pll_read;
 758         atom_card_info->pll_write = cail_pll_write;
 759
 760         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 761         mutex_init(&rdev->mode_info.atom_context->mutex);
 762         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 763         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 764         return 0;
 765 }
 766
 767 /**
 768  * radeon_atombios_fini - free the driver info and callbacks for atombios
 769  *
 770  * @rdev: radeon_device pointer
 771  *
 772  * Frees the driver info and register access callbacks for the ATOM
 773  * interpreter (r4xx+).
 774  * Called at driver shutdown.
 775  */
 776 void radeon_atombios_fini(struct radeon_device *rdev)
 777 {
 778         if (rdev->mode_info.atom_context) {
 779                 kfree(rdev->mode_info.atom_context->scratch);
 780                 kfree(rdev->mode_info.atom_context);
 781         }
 782         kfree(rdev->mode_info.atom_card_info);
 783 }
 784
 785 /* COMBIOS */
 786 /*
 787  * COMBIOS is the bios format prior to ATOM. It provides
 788  * command tables similar to ATOM, but doesn't have a unified
 789  * parser.  See radeon_combios.c
 790  */
 791
 792 /**
 793  * radeon_combios_init - init the driver info for combios
 794  *
 795  * @rdev: radeon_device pointer
 796  *
 797  * Initializes the driver info for combios (r1xx-r3xx).
 798  * Returns 0 on sucess.
 799  * Called at driver startup.
 800  */
 801 int radeon_combios_init(struct radeon_device *rdev)
 802 {
 803         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 804         return 0;
 805 }
 806
 807 /**
 808  * radeon_combios_fini - free the driver info for combios
 809  *
 810  * @rdev: radeon_device pointer
 811  *
 812  * Frees the driver info for combios (r1xx-r3xx).
 813  * Called at driver shutdown.
 814  */
 815 void radeon_combios_fini(struct radeon_device *rdev)
 816 {
 817 }
 818
 819 /* if we get transitioned to only one device, take VGA back */
 820 /**
 821  * radeon_vga_set_decode - enable/disable vga decode
 822  *
 823  * @cookie: radeon_device pointer
 824  * @state: enable/disable vga decode
 825  *
 826  * Enable/disable vga decode (all asics).
 827  * Returns VGA resource flags.
 828  */
 829 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 830 {
 831         struct radeon_device *rdev = cookie;
 832         radeon_vga_set_state(rdev, state);
 833         if (state)
 834                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 835                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 836         else
 837                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 838 }
 839
 840 /**
 841  * radeon_check_pot_argument - check that argument is a power of two
 842  *
 843  * @arg: value to check
 844  *
 845  * Validates that a certain argument is a power of two (all asics).
 846  * Returns true if argument is valid.
 847  */
 848 static bool radeon_check_pot_argument(int arg)
 849 {
 850         return (arg & (arg - 1)) == 0;
 851 }
 852
 853 /**
 854  * radeon_check_arguments - validate module params
 855  *
 856  * @rdev: radeon_device pointer
 857  *
 858  * Validates certain module parameters and updates
 859  * the associated values used by the driver (all asics).
 860  */
 861 static void radeon_check_arguments(struct radeon_device *rdev)
 862 {
 863         /* vramlimit must be a power of two */
 864         if (!radeon_check_pot_argument(radeon_vram_limit)) {
 865                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
 866                                 radeon_vram_limit);
 867                 radeon_vram_limit = 0;
 868         }
 869
 870         /* gtt size must be power of two and greater or equal to 32M */
 871         if (radeon_gart_size < 32) {
 872                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
 873                                 radeon_gart_size);
 874                 radeon_gart_size = 512;
 875
 876         } else if (!radeon_check_pot_argument(radeon_gart_size)) {
 877                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
 878                                 radeon_gart_size);
 879                 radeon_gart_size = 512;
 880         }
 881         rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
 882
 883         /* AGP mode can only be -1, 1, 2, 4, 8 */
 884         switch (radeon_agpmode) {
 885         case -1:
 886         case 0:
 887         case 1:
 888         case 2:
 889         case 4:
 890         case 8:
 891                 break;
 892         default:
 893                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
 894                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
 895                 radeon_agpmode = 0;
 896                 break;
 897         }
 898 }
 899
 900 /**
 901  * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
 902  * needed for waking up.
 903  *
 904  * @pdev: pci dev pointer
 905  */
 906 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
 907 {
 908
 909         /* 6600m in a macbook pro */
 910         if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
 911             pdev->subsystem_device == 0x00e2) {
 912                 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
 913                 return true;
 914         }
 915
 916         return false;
 917 }
 918
 919 /**
 920  * radeon_switcheroo_set_state - set switcheroo state
 921  *
 922  * @pdev: pci dev pointer
 923  * @state: vga switcheroo state
 924  *
 925  * Callback for the switcheroo driver.  Suspends or resumes the
 926  * the asics before or after it is powered up using ACPI methods.
 927  */
 928 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 929 {
 930         struct drm_device *dev = pci_get_drvdata(pdev);
 931         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 932         if (state == VGA_SWITCHEROO_ON) {
 933                 unsigned d3_delay = dev->pdev->d3_delay;
 934
 935                 printk(KERN_INFO "radeon: switched on\n");
 936                 /* don't suspend or resume card normally */
 937                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 938
 939                 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
 940                         dev->pdev->d3_delay = 20;
 941
 942                 radeon_resume_kms(dev);
 943
 944                 dev->pdev->d3_delay = d3_delay;
 945
 946                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 947                 drm_kms_helper_poll_enable(dev);
 948         } else {
 949                 printk(KERN_INFO "radeon: switched off\n");
 950                 drm_kms_helper_poll_disable(dev);
 951                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 952                 radeon_suspend_kms(dev, pmm);
 953                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 954         }
 955 }
 956
 957 /**
 958  * radeon_switcheroo_can_switch - see if switcheroo state can change
 959  *
 960  * @pdev: pci dev pointer
 961  *
 962  * Callback for the switcheroo driver.  Check of the switcheroo
 963  * state can be changed.
 964  * Returns true if the state can be changed, false if not.
 965  */
 966 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
 967 {
 968         struct drm_device *dev = pci_get_drvdata(pdev);
 969         bool can_switch;
 970
 971         spin_lock(&dev->count_lock);
 972         can_switch = (dev->open_count == 0);
 973         spin_unlock(&dev->count_lock);
 974         return can_switch;
 975 }
 976
 977 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
 978         .set_gpu_state = radeon_switcheroo_set_state,
 979         .reprobe = NULL,
 980         .can_switch = radeon_switcheroo_can_switch,
 981 };
 982
 983 /**
 984  * radeon_device_init - initialize the driver
 985  *
 986  * @rdev: radeon_device pointer
 987  * @pdev: drm dev pointer
 988  * @pdev: pci dev pointer
 989  * @flags: driver flags
 990  *
 991  * Initializes the driver info and hw (all asics).
 992  * Returns 0 for success or an error on failure.
 993  * Called at driver startup.
 994  */
 995 int radeon_device_init(struct radeon_device *rdev,
 996                        struct drm_device *ddev,
 997                        struct pci_dev *pdev,
 998                        uint32_t flags)
 999 {
1000         int r, i;
1001         int dma_bits;
1002
1003         rdev->shutdown = false;
1004         rdev->dev = &pdev->dev;
1005         rdev->ddev = ddev;
1006         rdev->pdev = pdev;
1007         rdev->flags = flags;
1008         rdev->family = flags & RADEON_FAMILY_MASK;
1009         rdev->is_atom_bios = false;
1010         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1011         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1012         rdev->accel_working = false;
1013         /* set up ring ids */
1014         for (i = 0; i < RADEON_NUM_RINGS; i++) {
1015                 rdev->ring[i].idx = i;
1016         }
1017
1018         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1019                 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1020                 pdev->subsystem_vendor, pdev->subsystem_device);
1021
1022         /* mutex initialization are all done here so we
1023          * can recall function without having locking issues */
1024         mutex_init(&rdev->ring_lock);
1025         mutex_init(&rdev->dc_hw_i2c_mutex);
1026         atomic_set(&rdev->ih.lock, 0);
1027         mutex_init(&rdev->gem.mutex);
1028         mutex_init(&rdev->pm.mutex);
1029         mutex_init(&rdev->gpu_clock_mutex);
1030         init_rwsem(&rdev->pm.mclk_lock);
1031         init_rwsem(&rdev->exclusive_lock);
1032         init_waitqueue_head(&rdev->irq.vblank_queue);
1033         r = radeon_gem_init(rdev);
1034         if (r)
1035                 return r;
1036         /* initialize vm here */
1037         mutex_init(&rdev->vm_manager.lock);
1038         /* Adjust VM size here.
1039          * Currently set to 4GB ((1 << 20) 4k pages).
1040          * Max GPUVM size for cayman and SI is 40 bits.
1041          */
1042         rdev->vm_manager.max_pfn = 1 << 20;
1043         INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1044
1045         /* Set asic functions */
1046         r = radeon_asic_init(rdev);
1047         if (r)
1048                 return r;
1049         radeon_check_arguments(rdev);
1050
1051         /* all of the newer IGP chips have an internal gart
1052          * However some rs4xx report as AGP, so remove that here.
1053          */
1054         if ((rdev->family >= CHIP_RS400) &&
1055             (rdev->flags & RADEON_IS_IGP)) {
1056                 rdev->flags &= ~RADEON_IS_AGP;
1057         }
1058
1059         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1060                 radeon_agp_disable(rdev);
1061         }
1062
1063         /* set DMA mask + need_dma32 flags.
1064          * PCIE - can handle 40-bits.
1065          * IGP - can handle 40-bits
1066          * AGP - generally dma32 is safest
1067          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1068          */
1069         rdev->need_dma32 = false;
1070         if (rdev->flags & RADEON_IS_AGP)
1071                 rdev->need_dma32 = true;
1072         if ((rdev->flags & RADEON_IS_PCI) &&
1073             (rdev->family <= CHIP_RS740))
1074                 rdev->need_dma32 = true;
1075
1076         dma_bits = rdev->need_dma32 ? 32 : 40;
1077         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1078         if (r) {
1079                 rdev->need_dma32 = true;
1080                 dma_bits = 32;
1081                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1082         }
1083         r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1084         if (r) {
1085                 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1086                 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1087         }
1088
1089         /* Registers mapping */
1090         /* TODO: block userspace mapping of io register */
1091         spin_lock_init(&rdev->mmio_idx_lock);
1092         rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1093         rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1094         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1095         if (rdev->rmmio == NULL) {
1096                 return -ENOMEM;
1097         }
1098         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1099         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1100
1101         /* io port mapping */
1102         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1103                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1104                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1105                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1106                         break;
1107                 }
1108         }
1109         if (rdev->rio_mem == NULL)
1110                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1111
1112         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1113         /* this will fail for cards that aren't VGA class devices, just
1114          * ignore it */
1115         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1116         vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops);
1117
1118         r = radeon_init(rdev);
1119         if (r)
1120                 return r;
1121
1122         r = radeon_ib_ring_tests(rdev);
1123         if (r)
1124                 DRM_ERROR("ib ring test failed (%d).\n", r);
1125
1126         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1127                 /* Acceleration not working on AGP card try again
1128                  * with fallback to PCI or PCIE GART
1129                  */
1130                 radeon_asic_reset(rdev);
1131                 radeon_fini(rdev);
1132                 radeon_agp_disable(rdev);
1133                 r = radeon_init(rdev);
1134                 if (r)
1135                         return r;
1136         }
1137         if ((radeon_testing & 1)) {
1138                 radeon_test_moves(rdev);
1139         }
1140         if ((radeon_testing & 2)) {
1141                 radeon_test_syncing(rdev);
1142         }
1143         if (radeon_benchmarking) {
1144                 radeon_benchmark(rdev, radeon_benchmarking);
1145         }
1146         return 0;
1147 }
1148
1149 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1150
1151 /**
1152  * radeon_device_fini - tear down the driver
1153  *
1154  * @rdev: radeon_device pointer
1155  *
1156  * Tear down the driver info (all asics).
1157  * Called at driver shutdown.
1158  */
1159 void radeon_device_fini(struct radeon_device *rdev)
1160 {
1161         DRM_INFO("radeon: finishing device.\n");
1162         rdev->shutdown = true;
1163         /* evict vram memory */
1164         radeon_bo_evict_vram(rdev);
1165         radeon_fini(rdev);
1166         vga_switcheroo_unregister_client(rdev->pdev);
1167         vga_client_register(rdev->pdev, NULL, NULL, NULL);
1168         if (rdev->rio_mem)
1169                 pci_iounmap(rdev->pdev, rdev->rio_mem);
1170         rdev->rio_mem = NULL;
1171         iounmap(rdev->rmmio);
1172         rdev->rmmio = NULL;
1173         radeon_debugfs_remove_files(rdev);
1174 }
1175
1176
1177 /*
1178  * Suspend & resume.
1179  */
1180 /**
1181  * radeon_suspend_kms - initiate device suspend
1182  *
1183  * @pdev: drm dev pointer
1184  * @state: suspend state
1185  *
1186  * Puts the hw in the suspend state (all asics).
1187  * Returns 0 for success or an error on failure.
1188  * Called at driver suspend.
1189  */
1190 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
1191 {
1192         struct radeon_device *rdev;
1193         struct drm_crtc *crtc;
1194         struct drm_connector *connector;
1195         int i, r;
1196         bool force_completion = false;
1197
1198         if (dev == NULL || dev->dev_private == NULL) {
1199                 return -ENODEV;
1200         }
1201         if (state.event == PM_EVENT_PRETHAW) {
1202                 return 0;
1203         }
1204         rdev = dev->dev_private;
1205
1206         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1207                 return 0;
1208
1209         drm_kms_helper_poll_disable(dev);
1210
1211         /* turn off display hw */
1212         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1213                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1214         }
1215
1216         /* unpin the front buffers */
1217         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1218                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1219                 struct radeon_bo *robj;
1220
1221                 if (rfb == NULL || rfb->obj == NULL) {
1222                         continue;
1223                 }
1224                 robj = gem_to_radeon_bo(rfb->obj);
1225                 /* don't unpin kernel fb objects */
1226                 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1227                         r = radeon_bo_reserve(robj, false);
1228                         if (r == 0) {
1229                                 radeon_bo_unpin(robj);
1230                                 radeon_bo_unreserve(robj);
1231                         }
1232                 }
1233         }
1234         /* evict vram memory */
1235         radeon_bo_evict_vram(rdev);
1236
1237         mutex_lock(&rdev->ring_lock);
1238         /* wait for gpu to finish processing current batch */
1239         for (i = 0; i < RADEON_NUM_RINGS; i++) {
1240                 r = radeon_fence_wait_empty_locked(rdev, i);
1241                 if (r) {
1242                         /* delay GPU reset to resume */
1243                         force_completion = true;
1244                 }
1245         }
1246         if (force_completion) {
1247                 radeon_fence_driver_force_completion(rdev);
1248         }
1249         mutex_unlock(&rdev->ring_lock);
1250
1251         radeon_save_bios_scratch_regs(rdev);
1252
1253         radeon_pm_suspend(rdev);
1254         radeon_suspend(rdev);
1255         radeon_hpd_fini(rdev);
1256         /* evict remaining vram memory */
1257         radeon_bo_evict_vram(rdev);
1258
1259         radeon_agp_suspend(rdev);
1260
1261         pci_save_state(dev->pdev);
1262         if (state.event == PM_EVENT_SUSPEND) {
1263                 /* Shut down the device */
1264                 pci_disable_device(dev->pdev);
1265                 pci_set_power_state(dev->pdev, PCI_D3hot);
1266         }
1267         console_lock();
1268         radeon_fbdev_set_suspend(rdev, 1);
1269         console_unlock();
1270         return 0;
1271 }
1272
1273 /**
1274  * radeon_resume_kms - initiate device resume
1275  *
1276  * @pdev: drm dev pointer
1277  *
1278  * Bring the hw back to operating state (all asics).
1279  * Returns 0 for success or an error on failure.
1280  * Called at driver resume.
1281  */
1282 int radeon_resume_kms(struct drm_device *dev)
1283 {
1284         struct drm_connector *connector;
1285         struct radeon_device *rdev = dev->dev_private;
1286         int r;
1287
1288         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1289                 return 0;
1290
1291         console_lock();
1292         pci_set_power_state(dev->pdev, PCI_D0);
1293         pci_restore_state(dev->pdev);
1294         if (pci_enable_device(dev->pdev)) {
1295                 console_unlock();
1296                 return -1;
1297         }
1298         /* resume AGP if in use */
1299         radeon_agp_resume(rdev);
1300         radeon_resume(rdev);
1301
1302         r = radeon_ib_ring_tests(rdev);
1303         if (r)
1304                 DRM_ERROR("ib ring test failed (%d).\n", r);
1305
1306         radeon_pm_resume(rdev);
1307         radeon_restore_bios_scratch_regs(rdev);
1308
1309         radeon_fbdev_set_suspend(rdev, 0);
1310         console_unlock();
1311
1312         /* init dig PHYs, disp eng pll */
1313         if (rdev->is_atom_bios) {
1314                 radeon_atom_encoder_init(rdev);
1315                 radeon_atom_disp_eng_pll_init(rdev);
1316                 /* turn on the BL */
1317                 if (rdev->mode_info.bl_encoder) {
1318                         u8 bl_level = radeon_get_backlight_level(rdev,
1319                                                                  rdev->mode_info.bl_encoder);
1320                         radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1321                                                    bl_level);
1322                 }
1323         }
1324         /* reset hpd state */
1325         radeon_hpd_init(rdev);
1326         /* blat the mode back in */
1327         drm_helper_resume_force_mode(dev);
1328         /* turn on display hw */
1329         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1330                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1331         }
1332
1333         drm_kms_helper_poll_enable(dev);
1334         return 0;
1335 }
1336
1337 /**
1338  * radeon_gpu_reset - reset the asic
1339  *
1340  * @rdev: radeon device pointer
1341  *
1342  * Attempt the reset the GPU if it has hung (all asics).
1343  * Returns 0 for success or an error on failure.
1344  */
1345 int radeon_gpu_reset(struct radeon_device *rdev)
1346 {
1347         unsigned ring_sizes[RADEON_NUM_RINGS];
1348         uint32_t *ring_data[RADEON_NUM_RINGS];
1349
1350         bool saved = false;
1351
1352         int i, r;
1353         int resched;
1354
1355         down_write(&rdev->exclusive_lock);
1356         radeon_save_bios_scratch_regs(rdev);
1357         /* block TTM */
1358         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1359         radeon_suspend(rdev);
1360
1361         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1362                 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1363                                                    &ring_data[i]);
1364                 if (ring_sizes[i]) {
1365                         saved = true;
1366                         dev_info(rdev->dev, "Saved %d dwords of commands "
1367                                  "on ring %d.\n", ring_sizes[i], i);
1368                 }
1369         }
1370
1371 retry:
1372         r = radeon_asic_reset(rdev);
1373         if (!r) {
1374                 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1375                 radeon_resume(rdev);
1376         }
1377
1378         radeon_restore_bios_scratch_regs(rdev);
1379
1380         if (!r) {
1381                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1382                         radeon_ring_restore(rdev, &rdev->ring[i],
1383                                             ring_sizes[i], ring_data[i]);
1384                         ring_sizes[i] = 0;
1385                         ring_data[i] = NULL;
1386                 }
1387
1388                 r = radeon_ib_ring_tests(rdev);
1389                 if (r) {
1390                         dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1391                         if (saved) {
1392                                 saved = false;
1393                                 radeon_suspend(rdev);
1394                                 goto retry;
1395                         }
1396                 }
1397         } else {
1398                 radeon_fence_driver_force_completion(rdev);
1399                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1400                         kfree(ring_data[i]);
1401                 }
1402         }
1403
1404         drm_helper_resume_force_mode(rdev->ddev);
1405
1406         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1407         if (r) {
1408                 /* bad news, how to tell it to userspace ? */
1409                 dev_info(rdev->dev, "GPU reset failed\n");
1410         }
1411
1412         up_write(&rdev->exclusive_lock);
1413         return r;
1414 }
1415
1416
1417 /*
1418  * Debugfs
1419  */
1420 int radeon_debugfs_add_files(struct radeon_device *rdev,
1421                              struct drm_info_list *files,
1422                              unsigned nfiles)
1423 {
1424         unsigned i;
1425
1426         for (i = 0; i < rdev->debugfs_count; i++) {
1427                 if (rdev->debugfs[i].files == files) {
1428                         /* Already registered */
1429                         return 0;
1430                 }
1431         }
1432
1433         i = rdev->debugfs_count + 1;
1434         if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1435                 DRM_ERROR("Reached maximum number of debugfs components.\n");
1436                 DRM_ERROR("Report so we increase "
1437                           "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1438                 return -EINVAL;
1439         }
1440         rdev->debugfs[rdev->debugfs_count].files = files;
1441         rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1442         rdev->debugfs_count = i;
1443 #if defined(CONFIG_DEBUG_FS)
1444         drm_debugfs_create_files(files, nfiles,
1445                                  rdev->ddev->control->debugfs_root,
1446                                  rdev->ddev->control);
1447         drm_debugfs_create_files(files, nfiles,
1448                                  rdev->ddev->primary->debugfs_root,
1449                                  rdev->ddev->primary);
1450 #endif
1451         return 0;
1452 }
1453
1454 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1455 {
1456 #if defined(CONFIG_DEBUG_FS)
1457         unsigned i;
1458
1459         for (i = 0; i < rdev->debugfs_count; i++) {
1460                 drm_debugfs_remove_files(rdev->debugfs[i].files,
1461                                          rdev->debugfs[i].num_files,
1462                                          rdev->ddev->control);
1463                 drm_debugfs_remove_files(rdev->debugfs[i].files,
1464                                          rdev->debugfs[i].num_files,
1465                                          rdev->ddev->primary);
1466         }
1467 #endif
1468 }
1469
1470 #if defined(CONFIG_DEBUG_FS)
1471 int radeon_debugfs_init(struct drm_minor *minor)
1472 {
1473         return 0;
1474 }
1475
1476 void radeon_debugfs_cleanup(struct drm_minor *minor)
1477 {
1478 }
1479 #endif