2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name
[][16] = {
106 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
107 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
109 struct radeon_px_quirk
{
117 static struct radeon_px_quirk radeon_px_quirk_list
[] = {
118 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
119 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
121 { PCI_VENDOR_ID_ATI
, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX
},
122 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
123 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
125 { PCI_VENDOR_ID_ATI
, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX
},
126 /* macbook pro 8.2 */
127 { PCI_VENDOR_ID_ATI
, 0x6741, PCI_VENDOR_ID_APPLE
, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP
},
131 bool radeon_is_px(struct drm_device
*dev
)
133 struct radeon_device
*rdev
= dev
->dev_private
;
135 if (rdev
->flags
& RADEON_IS_PX
)
140 static void radeon_device_handle_px_quirks(struct radeon_device
*rdev
)
142 struct radeon_px_quirk
*p
= radeon_px_quirk_list
;
144 /* Apply PX quirks */
145 while (p
&& p
->chip_device
!= 0) {
146 if (rdev
->pdev
->vendor
== p
->chip_vendor
&&
147 rdev
->pdev
->device
== p
->chip_device
&&
148 rdev
->pdev
->subsystem_vendor
== p
->subsys_vendor
&&
149 rdev
->pdev
->subsystem_device
== p
->subsys_device
) {
150 rdev
->px_quirk_flags
= p
->px_quirk_flags
;
156 if (rdev
->px_quirk_flags
& RADEON_PX_QUIRK_DISABLE_PX
)
157 rdev
->flags
&= ~RADEON_IS_PX
;
161 * radeon_program_register_sequence - program an array of registers.
163 * @rdev: radeon_device pointer
164 * @registers: pointer to the register array
165 * @array_size: size of the register array
167 * Programs an array or registers with and and or masks.
168 * This is a helper for setting golden registers.
170 void radeon_program_register_sequence(struct radeon_device
*rdev
,
171 const u32
*registers
,
172 const u32 array_size
)
174 u32 tmp
, reg
, and_mask
, or_mask
;
180 for (i
= 0; i
< array_size
; i
+=3) {
181 reg
= registers
[i
+ 0];
182 and_mask
= registers
[i
+ 1];
183 or_mask
= registers
[i
+ 2];
185 if (and_mask
== 0xffffffff) {
196 void radeon_pci_config_reset(struct radeon_device
*rdev
)
198 pci_write_config_dword(rdev
->pdev
, 0x7c, RADEON_ASIC_RESET_DATA
);
202 * radeon_surface_init - Clear GPU surface registers.
204 * @rdev: radeon_device pointer
206 * Clear GPU surface registers (r1xx-r5xx).
208 void radeon_surface_init(struct radeon_device
*rdev
)
210 /* FIXME: check this out */
211 if (rdev
->family
< CHIP_R600
) {
214 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
215 if (rdev
->surface_regs
[i
].bo
)
216 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
218 radeon_clear_surface_reg(rdev
, i
);
220 /* enable surfaces */
221 WREG32(RADEON_SURFACE_CNTL
, 0);
226 * GPU scratch registers helpers function.
229 * radeon_scratch_init - Init scratch register driver information.
231 * @rdev: radeon_device pointer
233 * Init CP scratch register driver information (r1xx-r5xx)
235 void radeon_scratch_init(struct radeon_device
*rdev
)
239 /* FIXME: check this out */
240 if (rdev
->family
< CHIP_R300
) {
241 rdev
->scratch
.num_reg
= 5;
243 rdev
->scratch
.num_reg
= 7;
245 rdev
->scratch
.reg_base
= RADEON_SCRATCH_REG0
;
246 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
247 rdev
->scratch
.free
[i
] = true;
248 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
253 * radeon_scratch_get - Allocate a scratch register
255 * @rdev: radeon_device pointer
256 * @reg: scratch register mmio offset
258 * Allocate a CP scratch register for use by the driver (all asics).
259 * Returns 0 on success or -EINVAL on failure.
261 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
265 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
266 if (rdev
->scratch
.free
[i
]) {
267 rdev
->scratch
.free
[i
] = false;
268 *reg
= rdev
->scratch
.reg
[i
];
276 * radeon_scratch_free - Free a scratch register
278 * @rdev: radeon_device pointer
279 * @reg: scratch register mmio offset
281 * Free a CP scratch register allocated for use by the driver (all asics)
283 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
287 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
288 if (rdev
->scratch
.reg
[i
] == reg
) {
289 rdev
->scratch
.free
[i
] = true;
296 * GPU doorbell aperture helpers function.
299 * radeon_doorbell_init - Init doorbell driver information.
301 * @rdev: radeon_device pointer
303 * Init doorbell driver information (CIK)
304 * Returns 0 on success, error on failure.
306 static int radeon_doorbell_init(struct radeon_device
*rdev
)
308 /* doorbell bar mapping */
309 rdev
->doorbell
.base
= pci_resource_start(rdev
->pdev
, 2);
310 rdev
->doorbell
.size
= pci_resource_len(rdev
->pdev
, 2);
312 rdev
->doorbell
.num_doorbells
= min_t(u32
, rdev
->doorbell
.size
/ sizeof(u32
), RADEON_MAX_DOORBELLS
);
313 if (rdev
->doorbell
.num_doorbells
== 0)
316 rdev
->doorbell
.ptr
= ioremap(rdev
->doorbell
.base
, rdev
->doorbell
.num_doorbells
* sizeof(u32
));
317 if (rdev
->doorbell
.ptr
== NULL
) {
320 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev
->doorbell
.base
);
321 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev
->doorbell
.size
);
323 memset(&rdev
->doorbell
.used
, 0, sizeof(rdev
->doorbell
.used
));
329 * radeon_doorbell_fini - Tear down doorbell driver information.
331 * @rdev: radeon_device pointer
333 * Tear down doorbell driver information (CIK)
335 static void radeon_doorbell_fini(struct radeon_device
*rdev
)
337 iounmap(rdev
->doorbell
.ptr
);
338 rdev
->doorbell
.ptr
= NULL
;
342 * radeon_doorbell_get - Allocate a doorbell entry
344 * @rdev: radeon_device pointer
345 * @doorbell: doorbell index
347 * Allocate a doorbell for use by the driver (all asics).
348 * Returns 0 on success or -EINVAL on failure.
350 int radeon_doorbell_get(struct radeon_device
*rdev
, u32
*doorbell
)
352 unsigned long offset
= find_first_zero_bit(rdev
->doorbell
.used
, rdev
->doorbell
.num_doorbells
);
353 if (offset
< rdev
->doorbell
.num_doorbells
) {
354 __set_bit(offset
, rdev
->doorbell
.used
);
363 * radeon_doorbell_free - Free a doorbell entry
365 * @rdev: radeon_device pointer
366 * @doorbell: doorbell index
368 * Free a doorbell allocated for use by the driver (all asics)
370 void radeon_doorbell_free(struct radeon_device
*rdev
, u32 doorbell
)
372 if (doorbell
< rdev
->doorbell
.num_doorbells
)
373 __clear_bit(doorbell
, rdev
->doorbell
.used
);
378 * Writeback is the the method by which the the GPU updates special pages
379 * in memory with the status of certain GPU events (fences, ring pointers,
384 * radeon_wb_disable - Disable Writeback
386 * @rdev: radeon_device pointer
388 * Disables Writeback (all asics). Used for suspend.
390 void radeon_wb_disable(struct radeon_device
*rdev
)
392 rdev
->wb
.enabled
= false;
396 * radeon_wb_fini - Disable Writeback and free memory
398 * @rdev: radeon_device pointer
400 * Disables Writeback and frees the Writeback memory (all asics).
401 * Used at driver shutdown.
403 void radeon_wb_fini(struct radeon_device
*rdev
)
405 radeon_wb_disable(rdev
);
406 if (rdev
->wb
.wb_obj
) {
407 if (!radeon_bo_reserve(rdev
->wb
.wb_obj
, false)) {
408 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
409 radeon_bo_unpin(rdev
->wb
.wb_obj
);
410 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
412 radeon_bo_unref(&rdev
->wb
.wb_obj
);
414 rdev
->wb
.wb_obj
= NULL
;
419 * radeon_wb_init- Init Writeback driver info and allocate memory
421 * @rdev: radeon_device pointer
423 * Disables Writeback and frees the Writeback memory (all asics).
424 * Used at driver startup.
425 * Returns 0 on success or an -error on failure.
427 int radeon_wb_init(struct radeon_device
*rdev
)
431 if (rdev
->wb
.wb_obj
== NULL
) {
432 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
, PAGE_SIZE
, true,
433 RADEON_GEM_DOMAIN_GTT
, 0, NULL
,
436 dev_warn(rdev
->dev
, "(%d) create WB bo failed\n", r
);
439 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
440 if (unlikely(r
!= 0)) {
441 radeon_wb_fini(rdev
);
444 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
447 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
448 dev_warn(rdev
->dev
, "(%d) pin WB bo failed\n", r
);
449 radeon_wb_fini(rdev
);
452 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
453 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
455 dev_warn(rdev
->dev
, "(%d) map WB bo failed\n", r
);
456 radeon_wb_fini(rdev
);
461 /* clear wb memory */
462 memset((char *)rdev
->wb
.wb
, 0, RADEON_GPU_PAGE_SIZE
);
463 /* disable event_write fences */
464 rdev
->wb
.use_event
= false;
465 /* disabled via module param */
466 if (radeon_no_wb
== 1) {
467 rdev
->wb
.enabled
= false;
469 if (rdev
->flags
& RADEON_IS_AGP
) {
470 /* often unreliable on AGP */
471 rdev
->wb
.enabled
= false;
472 } else if (rdev
->family
< CHIP_R300
) {
473 /* often unreliable on pre-r300 */
474 rdev
->wb
.enabled
= false;
476 rdev
->wb
.enabled
= true;
477 /* event_write fences are only available on r600+ */
478 if (rdev
->family
>= CHIP_R600
) {
479 rdev
->wb
.use_event
= true;
483 /* always use writeback/events on NI, APUs */
484 if (rdev
->family
>= CHIP_PALM
) {
485 rdev
->wb
.enabled
= true;
486 rdev
->wb
.use_event
= true;
489 dev_info(rdev
->dev
, "WB %sabled\n", rdev
->wb
.enabled
? "en" : "dis");
495 * radeon_vram_location - try to find VRAM location
496 * @rdev: radeon device structure holding all necessary informations
497 * @mc: memory controller structure holding memory informations
498 * @base: base address at which to put VRAM
500 * Function will place try to place VRAM at base address provided
501 * as parameter (which is so far either PCI aperture address or
502 * for IGP TOM base address).
504 * If there is not enough space to fit the unvisible VRAM in the 32bits
505 * address space then we limit the VRAM size to the aperture.
507 * If we are using AGP and if the AGP aperture doesn't allow us to have
508 * room for all the VRAM than we restrict the VRAM to the PCI aperture
509 * size and print a warning.
511 * This function will never fails, worst case are limiting VRAM.
513 * Note: GTT start, end, size should be initialized before calling this
514 * function on AGP platform.
516 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
517 * this shouldn't be a problem as we are using the PCI aperture as a reference.
518 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
521 * Note: we use mc_vram_size as on some board we need to program the mc to
522 * cover the whole aperture even if VRAM size is inferior to aperture size
523 * Novell bug 204882 + along with lots of ubuntu ones
525 * Note: when limiting vram it's safe to overwritte real_vram_size because
526 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
527 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
530 * Note: IGP TOM addr should be the same as the aperture addr, we don't
531 * explicitly check for that thought.
533 * FIXME: when reducing VRAM size align new size on power of 2.
535 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
537 uint64_t limit
= (uint64_t)radeon_vram_limit
<< 20;
539 mc
->vram_start
= base
;
540 if (mc
->mc_vram_size
> (rdev
->mc
.mc_mask
- base
+ 1)) {
541 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
542 mc
->real_vram_size
= mc
->aper_size
;
543 mc
->mc_vram_size
= mc
->aper_size
;
545 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
546 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_start
<= mc
->gtt_end
) {
547 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
548 mc
->real_vram_size
= mc
->aper_size
;
549 mc
->mc_vram_size
= mc
->aper_size
;
551 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
552 if (limit
&& limit
< mc
->real_vram_size
)
553 mc
->real_vram_size
= limit
;
554 dev_info(rdev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
555 mc
->mc_vram_size
>> 20, mc
->vram_start
,
556 mc
->vram_end
, mc
->real_vram_size
>> 20);
560 * radeon_gtt_location - try to find GTT location
561 * @rdev: radeon device structure holding all necessary informations
562 * @mc: memory controller structure holding memory informations
564 * Function will place try to place GTT before or after VRAM.
566 * If GTT size is bigger than space left then we ajust GTT size.
567 * Thus function will never fails.
569 * FIXME: when reducing GTT size align new size on power of 2.
571 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
573 u64 size_af
, size_bf
;
575 size_af
= ((rdev
->mc
.mc_mask
- mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
576 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
577 if (size_bf
> size_af
) {
578 if (mc
->gtt_size
> size_bf
) {
579 dev_warn(rdev
->dev
, "limiting GTT\n");
580 mc
->gtt_size
= size_bf
;
582 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
584 if (mc
->gtt_size
> size_af
) {
585 dev_warn(rdev
->dev
, "limiting GTT\n");
586 mc
->gtt_size
= size_af
;
588 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
590 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
591 dev_info(rdev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
592 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
596 * GPU helpers function.
599 * radeon_card_posted - check if the hw has already been initialized
601 * @rdev: radeon_device pointer
603 * Check if the asic has been initialized (all asics).
604 * Used at driver startup.
605 * Returns true if initialized or false if not.
607 bool radeon_card_posted(struct radeon_device
*rdev
)
611 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
612 if (efi_enabled(EFI_BOOT
) &&
613 (rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
614 (rdev
->family
< CHIP_R600
))
617 if (ASIC_IS_NODCE(rdev
))
620 /* first check CRTCs */
621 if (ASIC_IS_DCE4(rdev
)) {
622 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
623 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
624 if (rdev
->num_crtc
>= 4) {
625 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
626 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
628 if (rdev
->num_crtc
>= 6) {
629 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
630 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
632 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
634 } else if (ASIC_IS_AVIVO(rdev
)) {
635 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
636 RREG32(AVIVO_D2CRTC_CONTROL
);
637 if (reg
& AVIVO_CRTC_EN
) {
641 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
642 RREG32(RADEON_CRTC2_GEN_CNTL
);
643 if (reg
& RADEON_CRTC_EN
) {
649 /* then check MEM_SIZE, in case the crtcs are off */
650 if (rdev
->family
>= CHIP_R600
)
651 reg
= RREG32(R600_CONFIG_MEMSIZE
);
653 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
663 * radeon_update_bandwidth_info - update display bandwidth params
665 * @rdev: radeon_device pointer
667 * Used when sclk/mclk are switched or display modes are set.
668 * params are used to calculate display watermarks (all asics)
670 void radeon_update_bandwidth_info(struct radeon_device
*rdev
)
673 u32 sclk
= rdev
->pm
.current_sclk
;
674 u32 mclk
= rdev
->pm
.current_mclk
;
676 /* sclk/mclk in Mhz */
677 a
.full
= dfixed_const(100);
678 rdev
->pm
.sclk
.full
= dfixed_const(sclk
);
679 rdev
->pm
.sclk
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
680 rdev
->pm
.mclk
.full
= dfixed_const(mclk
);
681 rdev
->pm
.mclk
.full
= dfixed_div(rdev
->pm
.mclk
, a
);
683 if (rdev
->flags
& RADEON_IS_IGP
) {
684 a
.full
= dfixed_const(16);
685 /* core_bandwidth = sclk(Mhz) * 16 */
686 rdev
->pm
.core_bandwidth
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
691 * radeon_boot_test_post_card - check and possibly initialize the hw
693 * @rdev: radeon_device pointer
695 * Check if the asic is initialized and if not, attempt to initialize
697 * Returns true if initialized or false if not.
699 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
701 if (radeon_card_posted(rdev
))
705 DRM_INFO("GPU not posted. posting now...\n");
706 if (rdev
->is_atom_bios
)
707 atom_asic_init(rdev
->mode_info
.atom_context
);
709 radeon_combios_asic_init(rdev
->ddev
);
712 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
718 * radeon_dummy_page_init - init dummy page used by the driver
720 * @rdev: radeon_device pointer
722 * Allocate the dummy page used by the driver (all asics).
723 * This dummy page is used by the driver as a filler for gart entries
724 * when pages are taken out of the GART
725 * Returns 0 on sucess, -ENOMEM on failure.
727 int radeon_dummy_page_init(struct radeon_device
*rdev
)
729 if (rdev
->dummy_page
.page
)
731 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
732 if (rdev
->dummy_page
.page
== NULL
)
734 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
735 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
736 if (pci_dma_mapping_error(rdev
->pdev
, rdev
->dummy_page
.addr
)) {
737 dev_err(&rdev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
738 __free_page(rdev
->dummy_page
.page
);
739 rdev
->dummy_page
.page
= NULL
;
746 * radeon_dummy_page_fini - free dummy page used by the driver
748 * @rdev: radeon_device pointer
750 * Frees the dummy page used by the driver (all asics).
752 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
754 if (rdev
->dummy_page
.page
== NULL
)
756 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
757 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
758 __free_page(rdev
->dummy_page
.page
);
759 rdev
->dummy_page
.page
= NULL
;
763 /* ATOM accessor methods */
765 * ATOM is an interpreted byte code stored in tables in the vbios. The
766 * driver registers callbacks to access registers and the interpreter
767 * in the driver parses the tables and executes then to program specific
768 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
769 * atombios.h, and atom.c
773 * cail_pll_read - read PLL register
775 * @info: atom card_info pointer
776 * @reg: PLL register offset
778 * Provides a PLL register accessor for the atom interpreter (r4xx+).
779 * Returns the value of the PLL register.
781 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
783 struct radeon_device
*rdev
= info
->dev
->dev_private
;
786 r
= rdev
->pll_rreg(rdev
, reg
);
791 * cail_pll_write - write PLL register
793 * @info: atom card_info pointer
794 * @reg: PLL register offset
795 * @val: value to write to the pll register
797 * Provides a PLL register accessor for the atom interpreter (r4xx+).
799 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
801 struct radeon_device
*rdev
= info
->dev
->dev_private
;
803 rdev
->pll_wreg(rdev
, reg
, val
);
807 * cail_mc_read - read MC (Memory Controller) register
809 * @info: atom card_info pointer
810 * @reg: MC register offset
812 * Provides an MC register accessor for the atom interpreter (r4xx+).
813 * Returns the value of the MC register.
815 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
817 struct radeon_device
*rdev
= info
->dev
->dev_private
;
820 r
= rdev
->mc_rreg(rdev
, reg
);
825 * cail_mc_write - write MC (Memory Controller) register
827 * @info: atom card_info pointer
828 * @reg: MC register offset
829 * @val: value to write to the pll register
831 * Provides a MC register accessor for the atom interpreter (r4xx+).
833 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
835 struct radeon_device
*rdev
= info
->dev
->dev_private
;
837 rdev
->mc_wreg(rdev
, reg
, val
);
841 * cail_reg_write - write MMIO register
843 * @info: atom card_info pointer
844 * @reg: MMIO register offset
845 * @val: value to write to the pll register
847 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
849 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
851 struct radeon_device
*rdev
= info
->dev
->dev_private
;
857 * cail_reg_read - read MMIO register
859 * @info: atom card_info pointer
860 * @reg: MMIO register offset
862 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
863 * Returns the value of the MMIO register.
865 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
867 struct radeon_device
*rdev
= info
->dev
->dev_private
;
875 * cail_ioreg_write - write IO register
877 * @info: atom card_info pointer
878 * @reg: IO register offset
879 * @val: value to write to the pll register
881 * Provides a IO register accessor for the atom interpreter (r4xx+).
883 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
885 struct radeon_device
*rdev
= info
->dev
->dev_private
;
887 WREG32_IO(reg
*4, val
);
891 * cail_ioreg_read - read IO register
893 * @info: atom card_info pointer
894 * @reg: IO register offset
896 * Provides an IO register accessor for the atom interpreter (r4xx+).
897 * Returns the value of the IO register.
899 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
901 struct radeon_device
*rdev
= info
->dev
->dev_private
;
904 r
= RREG32_IO(reg
*4);
909 * radeon_atombios_init - init the driver info and callbacks for atombios
911 * @rdev: radeon_device pointer
913 * Initializes the driver info and register access callbacks for the
914 * ATOM interpreter (r4xx+).
915 * Returns 0 on sucess, -ENOMEM on failure.
916 * Called at driver startup.
918 int radeon_atombios_init(struct radeon_device
*rdev
)
920 struct card_info
*atom_card_info
=
921 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
926 rdev
->mode_info
.atom_card_info
= atom_card_info
;
927 atom_card_info
->dev
= rdev
->ddev
;
928 atom_card_info
->reg_read
= cail_reg_read
;
929 atom_card_info
->reg_write
= cail_reg_write
;
930 /* needed for iio ops */
932 atom_card_info
->ioreg_read
= cail_ioreg_read
;
933 atom_card_info
->ioreg_write
= cail_ioreg_write
;
935 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
936 atom_card_info
->ioreg_read
= cail_reg_read
;
937 atom_card_info
->ioreg_write
= cail_reg_write
;
939 atom_card_info
->mc_read
= cail_mc_read
;
940 atom_card_info
->mc_write
= cail_mc_write
;
941 atom_card_info
->pll_read
= cail_pll_read
;
942 atom_card_info
->pll_write
= cail_pll_write
;
944 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
945 if (!rdev
->mode_info
.atom_context
) {
946 radeon_atombios_fini(rdev
);
950 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
951 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
952 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
957 * radeon_atombios_fini - free the driver info and callbacks for atombios
959 * @rdev: radeon_device pointer
961 * Frees the driver info and register access callbacks for the ATOM
962 * interpreter (r4xx+).
963 * Called at driver shutdown.
965 void radeon_atombios_fini(struct radeon_device
*rdev
)
967 if (rdev
->mode_info
.atom_context
) {
968 kfree(rdev
->mode_info
.atom_context
->scratch
);
970 kfree(rdev
->mode_info
.atom_context
);
971 rdev
->mode_info
.atom_context
= NULL
;
972 kfree(rdev
->mode_info
.atom_card_info
);
973 rdev
->mode_info
.atom_card_info
= NULL
;
978 * COMBIOS is the bios format prior to ATOM. It provides
979 * command tables similar to ATOM, but doesn't have a unified
980 * parser. See radeon_combios.c
984 * radeon_combios_init - init the driver info for combios
986 * @rdev: radeon_device pointer
988 * Initializes the driver info for combios (r1xx-r3xx).
989 * Returns 0 on sucess.
990 * Called at driver startup.
992 int radeon_combios_init(struct radeon_device
*rdev
)
994 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
999 * radeon_combios_fini - free the driver info for combios
1001 * @rdev: radeon_device pointer
1003 * Frees the driver info for combios (r1xx-r3xx).
1004 * Called at driver shutdown.
1006 void radeon_combios_fini(struct radeon_device
*rdev
)
1010 /* if we get transitioned to only one device, take VGA back */
1012 * radeon_vga_set_decode - enable/disable vga decode
1014 * @cookie: radeon_device pointer
1015 * @state: enable/disable vga decode
1017 * Enable/disable vga decode (all asics).
1018 * Returns VGA resource flags.
1020 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
1022 struct radeon_device
*rdev
= cookie
;
1023 radeon_vga_set_state(rdev
, state
);
1025 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1026 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1028 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1032 * radeon_check_pot_argument - check that argument is a power of two
1034 * @arg: value to check
1036 * Validates that a certain argument is a power of two (all asics).
1037 * Returns true if argument is valid.
1039 static bool radeon_check_pot_argument(int arg
)
1041 return (arg
& (arg
- 1)) == 0;
1045 * radeon_check_arguments - validate module params
1047 * @rdev: radeon_device pointer
1049 * Validates certain module parameters and updates
1050 * the associated values used by the driver (all asics).
1052 static void radeon_check_arguments(struct radeon_device
*rdev
)
1054 /* vramlimit must be a power of two */
1055 if (!radeon_check_pot_argument(radeon_vram_limit
)) {
1056 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
1058 radeon_vram_limit
= 0;
1061 if (radeon_gart_size
== -1) {
1062 /* default to a larger gart size on newer asics */
1063 if (rdev
->family
>= CHIP_RV770
)
1064 radeon_gart_size
= 1024;
1066 radeon_gart_size
= 512;
1068 /* gtt size must be power of two and greater or equal to 32M */
1069 if (radeon_gart_size
< 32) {
1070 dev_warn(rdev
->dev
, "gart size (%d) too small\n",
1072 if (rdev
->family
>= CHIP_RV770
)
1073 radeon_gart_size
= 1024;
1075 radeon_gart_size
= 512;
1076 } else if (!radeon_check_pot_argument(radeon_gart_size
)) {
1077 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
1079 if (rdev
->family
>= CHIP_RV770
)
1080 radeon_gart_size
= 1024;
1082 radeon_gart_size
= 512;
1084 rdev
->mc
.gtt_size
= (uint64_t)radeon_gart_size
<< 20;
1086 /* AGP mode can only be -1, 1, 2, 4, 8 */
1087 switch (radeon_agpmode
) {
1096 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
1097 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
1102 if (!radeon_check_pot_argument(radeon_vm_size
)) {
1103 dev_warn(rdev
->dev
, "VM size (%d) must be a power of 2\n",
1108 if (radeon_vm_size
< 1) {
1109 dev_warn(rdev
->dev
, "VM size (%d) to small, min is 1GB\n",
1115 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1117 if (radeon_vm_size
> 1024) {
1118 dev_warn(rdev
->dev
, "VM size (%d) too large, max is 1TB\n",
1123 /* defines number of bits in page table versus page directory,
1124 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1125 * page table and the remaining bits are in the page directory */
1126 if (radeon_vm_block_size
== -1) {
1128 /* Total bits covered by PD + PTs */
1129 unsigned bits
= ilog2(radeon_vm_size
) + 17;
1131 /* Make sure the PD is 4K in size up to 8GB address space.
1132 Above that split equal between PD and PTs */
1133 if (radeon_vm_size
<= 8)
1134 radeon_vm_block_size
= bits
- 9;
1136 radeon_vm_block_size
= (bits
+ 3) / 2;
1138 } else if (radeon_vm_block_size
< 9) {
1139 dev_warn(rdev
->dev
, "VM page table size (%d) too small\n",
1140 radeon_vm_block_size
);
1141 radeon_vm_block_size
= 9;
1144 if (radeon_vm_block_size
> 24 ||
1145 (radeon_vm_size
* 1024) < (1ull << radeon_vm_block_size
)) {
1146 dev_warn(rdev
->dev
, "VM page table size (%d) too large\n",
1147 radeon_vm_block_size
);
1148 radeon_vm_block_size
= 9;
1153 * radeon_switcheroo_set_state - set switcheroo state
1155 * @pdev: pci dev pointer
1156 * @state: vga switcheroo state
1158 * Callback for the switcheroo driver. Suspends or resumes the
1159 * the asics before or after it is powered up using ACPI methods.
1161 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1163 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1164 struct radeon_device
*rdev
= dev
->dev_private
;
1166 if (radeon_is_px(dev
) && state
== VGA_SWITCHEROO_OFF
)
1169 if (state
== VGA_SWITCHEROO_ON
) {
1170 unsigned d3_delay
= dev
->pdev
->d3_delay
;
1172 printk(KERN_INFO
"radeon: switched on\n");
1173 /* don't suspend or resume card normally */
1174 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1176 if (d3_delay
< 20 && (rdev
->px_quirk_flags
& RADEON_PX_QUIRK_LONG_WAKEUP
))
1177 dev
->pdev
->d3_delay
= 20;
1179 radeon_resume_kms(dev
, true, true);
1181 dev
->pdev
->d3_delay
= d3_delay
;
1183 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1184 drm_kms_helper_poll_enable(dev
);
1186 printk(KERN_INFO
"radeon: switched off\n");
1187 drm_kms_helper_poll_disable(dev
);
1188 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1189 radeon_suspend_kms(dev
, true, true);
1190 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1195 * radeon_switcheroo_can_switch - see if switcheroo state can change
1197 * @pdev: pci dev pointer
1199 * Callback for the switcheroo driver. Check of the switcheroo
1200 * state can be changed.
1201 * Returns true if the state can be changed, false if not.
1203 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
1205 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1208 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1209 * locking inversion with the driver load path. And the access here is
1210 * completely racy anyway. So don't bother with locking for now.
1212 return dev
->open_count
== 0;
1215 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops
= {
1216 .set_gpu_state
= radeon_switcheroo_set_state
,
1218 .can_switch
= radeon_switcheroo_can_switch
,
1222 * radeon_device_init - initialize the driver
1224 * @rdev: radeon_device pointer
1225 * @pdev: drm dev pointer
1226 * @pdev: pci dev pointer
1227 * @flags: driver flags
1229 * Initializes the driver info and hw (all asics).
1230 * Returns 0 for success or an error on failure.
1231 * Called at driver startup.
1233 int radeon_device_init(struct radeon_device
*rdev
,
1234 struct drm_device
*ddev
,
1235 struct pci_dev
*pdev
,
1240 bool runtime
= false;
1242 rdev
->shutdown
= false;
1243 rdev
->dev
= &pdev
->dev
;
1246 rdev
->flags
= flags
;
1247 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
1248 rdev
->is_atom_bios
= false;
1249 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
1250 rdev
->mc
.gtt_size
= 512 * 1024 * 1024;
1251 rdev
->accel_working
= false;
1252 /* set up ring ids */
1253 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1254 rdev
->ring
[i
].idx
= i
;
1257 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1258 radeon_family_name
[rdev
->family
], pdev
->vendor
, pdev
->device
,
1259 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1261 /* mutex initialization are all done here so we
1262 * can recall function without having locking issues */
1263 mutex_init(&rdev
->ring_lock
);
1264 mutex_init(&rdev
->dc_hw_i2c_mutex
);
1265 atomic_set(&rdev
->ih
.lock
, 0);
1266 mutex_init(&rdev
->gem
.mutex
);
1267 mutex_init(&rdev
->pm
.mutex
);
1268 mutex_init(&rdev
->gpu_clock_mutex
);
1269 mutex_init(&rdev
->srbm_mutex
);
1270 init_rwsem(&rdev
->pm
.mclk_lock
);
1271 init_rwsem(&rdev
->exclusive_lock
);
1272 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
1273 mutex_init(&rdev
->mn_lock
);
1274 hash_init(rdev
->mn_hash
);
1275 r
= radeon_gem_init(rdev
);
1279 radeon_check_arguments(rdev
);
1280 /* Adjust VM size here.
1281 * Max GPUVM size for cayman+ is 40 bits.
1283 rdev
->vm_manager
.max_pfn
= radeon_vm_size
<< 18;
1285 /* Set asic functions */
1286 r
= radeon_asic_init(rdev
);
1290 /* all of the newer IGP chips have an internal gart
1291 * However some rs4xx report as AGP, so remove that here.
1293 if ((rdev
->family
>= CHIP_RS400
) &&
1294 (rdev
->flags
& RADEON_IS_IGP
)) {
1295 rdev
->flags
&= ~RADEON_IS_AGP
;
1298 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
1299 radeon_agp_disable(rdev
);
1302 /* Set the internal MC address mask
1303 * This is the max address of the GPU's
1304 * internal address space.
1306 if (rdev
->family
>= CHIP_CAYMAN
)
1307 rdev
->mc
.mc_mask
= 0xffffffffffULL
; /* 40 bit MC */
1308 else if (rdev
->family
>= CHIP_CEDAR
)
1309 rdev
->mc
.mc_mask
= 0xfffffffffULL
; /* 36 bit MC */
1311 rdev
->mc
.mc_mask
= 0xffffffffULL
; /* 32 bit MC */
1313 /* set DMA mask + need_dma32 flags.
1314 * PCIE - can handle 40-bits.
1315 * IGP - can handle 40-bits
1316 * AGP - generally dma32 is safest
1317 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1319 rdev
->need_dma32
= false;
1320 if (rdev
->flags
& RADEON_IS_AGP
)
1321 rdev
->need_dma32
= true;
1322 if ((rdev
->flags
& RADEON_IS_PCI
) &&
1323 (rdev
->family
<= CHIP_RS740
))
1324 rdev
->need_dma32
= true;
1326 dma_bits
= rdev
->need_dma32
? 32 : 40;
1327 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1329 rdev
->need_dma32
= true;
1331 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
1333 r
= pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1335 pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(32));
1336 printk(KERN_WARNING
"radeon: No coherent DMA available.\n");
1339 /* Registers mapping */
1340 /* TODO: block userspace mapping of io register */
1341 spin_lock_init(&rdev
->mmio_idx_lock
);
1342 spin_lock_init(&rdev
->smc_idx_lock
);
1343 spin_lock_init(&rdev
->pll_idx_lock
);
1344 spin_lock_init(&rdev
->mc_idx_lock
);
1345 spin_lock_init(&rdev
->pcie_idx_lock
);
1346 spin_lock_init(&rdev
->pciep_idx_lock
);
1347 spin_lock_init(&rdev
->pif_idx_lock
);
1348 spin_lock_init(&rdev
->cg_idx_lock
);
1349 spin_lock_init(&rdev
->uvd_idx_lock
);
1350 spin_lock_init(&rdev
->rcu_idx_lock
);
1351 spin_lock_init(&rdev
->didt_idx_lock
);
1352 spin_lock_init(&rdev
->end_idx_lock
);
1353 if (rdev
->family
>= CHIP_BONAIRE
) {
1354 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 5);
1355 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 5);
1357 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 2);
1358 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 2);
1360 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
1361 if (rdev
->rmmio
== NULL
) {
1364 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
1365 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
1367 /* doorbell bar mapping */
1368 if (rdev
->family
>= CHIP_BONAIRE
)
1369 radeon_doorbell_init(rdev
);
1371 /* io port mapping */
1372 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1373 if (pci_resource_flags(rdev
->pdev
, i
) & IORESOURCE_IO
) {
1374 rdev
->rio_mem_size
= pci_resource_len(rdev
->pdev
, i
);
1375 rdev
->rio_mem
= pci_iomap(rdev
->pdev
, i
, rdev
->rio_mem_size
);
1379 if (rdev
->rio_mem
== NULL
)
1380 DRM_ERROR("Unable to find PCI I/O BAR\n");
1382 if (rdev
->flags
& RADEON_IS_PX
)
1383 radeon_device_handle_px_quirks(rdev
);
1385 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1386 /* this will fail for cards that aren't VGA class devices, just
1388 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
1390 if (rdev
->flags
& RADEON_IS_PX
)
1392 vga_switcheroo_register_client(rdev
->pdev
, &radeon_switcheroo_ops
, runtime
);
1394 vga_switcheroo_init_domain_pm_ops(rdev
->dev
, &rdev
->vga_pm_domain
);
1396 r
= radeon_init(rdev
);
1400 r
= radeon_gem_debugfs_init(rdev
);
1402 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
1405 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
1406 /* Acceleration not working on AGP card try again
1407 * with fallback to PCI or PCIE GART
1409 radeon_asic_reset(rdev
);
1411 radeon_agp_disable(rdev
);
1412 r
= radeon_init(rdev
);
1417 r
= radeon_ib_ring_tests(rdev
);
1419 DRM_ERROR("ib ring test failed (%d).\n", r
);
1421 if ((radeon_testing
& 1)) {
1422 if (rdev
->accel_working
)
1423 radeon_test_moves(rdev
);
1425 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1427 if ((radeon_testing
& 2)) {
1428 if (rdev
->accel_working
)
1429 radeon_test_syncing(rdev
);
1431 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1433 if (radeon_benchmarking
) {
1434 if (rdev
->accel_working
)
1435 radeon_benchmark(rdev
, radeon_benchmarking
);
1437 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1442 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
);
1445 * radeon_device_fini - tear down the driver
1447 * @rdev: radeon_device pointer
1449 * Tear down the driver info (all asics).
1450 * Called at driver shutdown.
1452 void radeon_device_fini(struct radeon_device
*rdev
)
1454 DRM_INFO("radeon: finishing device.\n");
1455 rdev
->shutdown
= true;
1456 /* evict vram memory */
1457 radeon_bo_evict_vram(rdev
);
1459 vga_switcheroo_unregister_client(rdev
->pdev
);
1460 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
1462 pci_iounmap(rdev
->pdev
, rdev
->rio_mem
);
1463 rdev
->rio_mem
= NULL
;
1464 iounmap(rdev
->rmmio
);
1466 if (rdev
->family
>= CHIP_BONAIRE
)
1467 radeon_doorbell_fini(rdev
);
1468 radeon_debugfs_remove_files(rdev
);
1476 * radeon_suspend_kms - initiate device suspend
1478 * @pdev: drm dev pointer
1479 * @state: suspend state
1481 * Puts the hw in the suspend state (all asics).
1482 * Returns 0 for success or an error on failure.
1483 * Called at driver suspend.
1485 int radeon_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
)
1487 struct radeon_device
*rdev
;
1488 struct drm_crtc
*crtc
;
1489 struct drm_connector
*connector
;
1492 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
1496 rdev
= dev
->dev_private
;
1498 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1501 drm_kms_helper_poll_disable(dev
);
1503 /* turn off display hw */
1504 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1505 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
1508 /* unpin the front buffers */
1509 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1510 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->primary
->fb
);
1511 struct radeon_bo
*robj
;
1513 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
1516 robj
= gem_to_radeon_bo(rfb
->obj
);
1517 /* don't unpin kernel fb objects */
1518 if (!radeon_fbdev_robj_is_fb(rdev
, robj
)) {
1519 r
= radeon_bo_reserve(robj
, false);
1521 radeon_bo_unpin(robj
);
1522 radeon_bo_unreserve(robj
);
1526 /* evict vram memory */
1527 radeon_bo_evict_vram(rdev
);
1529 /* wait for gpu to finish processing current batch */
1530 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1531 r
= radeon_fence_wait_empty(rdev
, i
);
1533 /* delay GPU reset to resume */
1534 radeon_fence_driver_force_completion(rdev
, i
);
1538 radeon_save_bios_scratch_regs(rdev
);
1540 radeon_suspend(rdev
);
1541 radeon_hpd_fini(rdev
);
1542 /* evict remaining vram memory */
1543 radeon_bo_evict_vram(rdev
);
1545 radeon_agp_suspend(rdev
);
1547 pci_save_state(dev
->pdev
);
1549 /* Shut down the device */
1550 pci_disable_device(dev
->pdev
);
1551 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
1556 radeon_fbdev_set_suspend(rdev
, 1);
1563 * radeon_resume_kms - initiate device resume
1565 * @pdev: drm dev pointer
1567 * Bring the hw back to operating state (all asics).
1568 * Returns 0 for success or an error on failure.
1569 * Called at driver resume.
1571 int radeon_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
)
1573 struct drm_connector
*connector
;
1574 struct radeon_device
*rdev
= dev
->dev_private
;
1577 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1584 pci_set_power_state(dev
->pdev
, PCI_D0
);
1585 pci_restore_state(dev
->pdev
);
1586 if (pci_enable_device(dev
->pdev
)) {
1592 /* resume AGP if in use */
1593 radeon_agp_resume(rdev
);
1594 radeon_resume(rdev
);
1596 r
= radeon_ib_ring_tests(rdev
);
1598 DRM_ERROR("ib ring test failed (%d).\n", r
);
1600 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1601 /* do dpm late init */
1602 r
= radeon_pm_late_init(rdev
);
1604 rdev
->pm
.dpm_enabled
= false;
1605 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1608 /* resume old pm late */
1609 radeon_pm_resume(rdev
);
1612 radeon_restore_bios_scratch_regs(rdev
);
1614 /* init dig PHYs, disp eng pll */
1615 if (rdev
->is_atom_bios
) {
1616 radeon_atom_encoder_init(rdev
);
1617 radeon_atom_disp_eng_pll_init(rdev
);
1618 /* turn on the BL */
1619 if (rdev
->mode_info
.bl_encoder
) {
1620 u8 bl_level
= radeon_get_backlight_level(rdev
,
1621 rdev
->mode_info
.bl_encoder
);
1622 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1626 /* reset hpd state */
1627 radeon_hpd_init(rdev
);
1628 /* blat the mode back in */
1630 drm_helper_resume_force_mode(dev
);
1631 /* turn on display hw */
1632 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1633 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
1637 drm_kms_helper_poll_enable(dev
);
1639 /* set the power state here in case we are a PX system or headless */
1640 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1641 radeon_pm_compute_clocks(rdev
);
1644 radeon_fbdev_set_suspend(rdev
, 0);
1652 * radeon_gpu_reset - reset the asic
1654 * @rdev: radeon device pointer
1656 * Attempt the reset the GPU if it has hung (all asics).
1657 * Returns 0 for success or an error on failure.
1659 int radeon_gpu_reset(struct radeon_device
*rdev
)
1661 unsigned ring_sizes
[RADEON_NUM_RINGS
];
1662 uint32_t *ring_data
[RADEON_NUM_RINGS
];
1669 down_write(&rdev
->exclusive_lock
);
1671 if (!rdev
->needs_reset
) {
1672 up_write(&rdev
->exclusive_lock
);
1676 rdev
->in_reset
= true;
1677 rdev
->needs_reset
= false;
1679 radeon_save_bios_scratch_regs(rdev
);
1681 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1682 radeon_suspend(rdev
);
1683 radeon_hpd_fini(rdev
);
1685 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1686 ring_sizes
[i
] = radeon_ring_backup(rdev
, &rdev
->ring
[i
],
1688 if (ring_sizes
[i
]) {
1690 dev_info(rdev
->dev
, "Saved %d dwords of commands "
1691 "on ring %d.\n", ring_sizes
[i
], i
);
1695 r
= radeon_asic_reset(rdev
);
1697 dev_info(rdev
->dev
, "GPU reset succeeded, trying to resume\n");
1698 radeon_resume(rdev
);
1701 radeon_restore_bios_scratch_regs(rdev
);
1703 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1704 if (!r
&& ring_data
[i
]) {
1705 radeon_ring_restore(rdev
, &rdev
->ring
[i
],
1706 ring_sizes
[i
], ring_data
[i
]);
1708 radeon_fence_driver_force_completion(rdev
, i
);
1709 kfree(ring_data
[i
]);
1713 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1714 /* do dpm late init */
1715 r
= radeon_pm_late_init(rdev
);
1717 rdev
->pm
.dpm_enabled
= false;
1718 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1721 /* resume old pm late */
1722 radeon_pm_resume(rdev
);
1725 /* init dig PHYs, disp eng pll */
1726 if (rdev
->is_atom_bios
) {
1727 radeon_atom_encoder_init(rdev
);
1728 radeon_atom_disp_eng_pll_init(rdev
);
1729 /* turn on the BL */
1730 if (rdev
->mode_info
.bl_encoder
) {
1731 u8 bl_level
= radeon_get_backlight_level(rdev
,
1732 rdev
->mode_info
.bl_encoder
);
1733 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1737 /* reset hpd state */
1738 radeon_hpd_init(rdev
);
1740 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1741 downgrade_write(&rdev
->exclusive_lock
);
1743 drm_helper_resume_force_mode(rdev
->ddev
);
1745 /* set the power state here in case we are a PX system or headless */
1746 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1747 radeon_pm_compute_clocks(rdev
);
1750 r
= radeon_ib_ring_tests(rdev
);
1754 /* bad news, how to tell it to userspace ? */
1755 dev_info(rdev
->dev
, "GPU reset failed\n");
1758 rdev
->needs_reset
= r
== -EAGAIN
;
1759 rdev
->in_reset
= false;
1761 up_read(&rdev
->exclusive_lock
);
1769 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
1770 struct drm_info_list
*files
,
1775 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1776 if (rdev
->debugfs
[i
].files
== files
) {
1777 /* Already registered */
1782 i
= rdev
->debugfs_count
+ 1;
1783 if (i
> RADEON_DEBUGFS_MAX_COMPONENTS
) {
1784 DRM_ERROR("Reached maximum number of debugfs components.\n");
1785 DRM_ERROR("Report so we increase "
1786 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1789 rdev
->debugfs
[rdev
->debugfs_count
].files
= files
;
1790 rdev
->debugfs
[rdev
->debugfs_count
].num_files
= nfiles
;
1791 rdev
->debugfs_count
= i
;
1792 #if defined(CONFIG_DEBUG_FS)
1793 drm_debugfs_create_files(files
, nfiles
,
1794 rdev
->ddev
->control
->debugfs_root
,
1795 rdev
->ddev
->control
);
1796 drm_debugfs_create_files(files
, nfiles
,
1797 rdev
->ddev
->primary
->debugfs_root
,
1798 rdev
->ddev
->primary
);
1803 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
)
1805 #if defined(CONFIG_DEBUG_FS)
1808 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1809 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1810 rdev
->debugfs
[i
].num_files
,
1811 rdev
->ddev
->control
);
1812 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1813 rdev
->debugfs
[i
].num_files
,
1814 rdev
->ddev
->primary
);
1819 #if defined(CONFIG_DEBUG_FS)
1820 int radeon_debugfs_init(struct drm_minor
*minor
)
1825 void radeon_debugfs_cleanup(struct drm_minor
*minor
)