2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34 #include "radeon_reg.h"
36 #include "radeon_asic.h"
40 * Clear GPU surface registers.
42 void radeon_surface_init(struct radeon_device
*rdev
)
44 /* FIXME: check this out */
45 if (rdev
->family
< CHIP_R600
) {
48 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
49 if (rdev
->surface_regs
[i
].bo
)
50 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
52 radeon_clear_surface_reg(rdev
, i
);
55 WREG32(RADEON_SURFACE_CNTL
, 0);
60 * GPU scratch registers helpers function.
62 void radeon_scratch_init(struct radeon_device
*rdev
)
66 /* FIXME: check this out */
67 if (rdev
->family
< CHIP_R300
) {
68 rdev
->scratch
.num_reg
= 5;
70 rdev
->scratch
.num_reg
= 7;
72 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
73 rdev
->scratch
.free
[i
] = true;
74 rdev
->scratch
.reg
[i
] = RADEON_SCRATCH_REG0
+ (i
* 4);
78 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
82 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
83 if (rdev
->scratch
.free
[i
]) {
84 rdev
->scratch
.free
[i
] = false;
85 *reg
= rdev
->scratch
.reg
[i
];
92 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
96 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
97 if (rdev
->scratch
.reg
[i
] == reg
) {
98 rdev
->scratch
.free
[i
] = true;
105 * radeon_vram_location - try to find VRAM location
106 * @rdev: radeon device structure holding all necessary informations
107 * @mc: memory controller structure holding memory informations
108 * @base: base address at which to put VRAM
110 * Function will place try to place VRAM at base address provided
111 * as parameter (which is so far either PCI aperture address or
112 * for IGP TOM base address).
114 * If there is not enough space to fit the unvisible VRAM in the 32bits
115 * address space then we limit the VRAM size to the aperture.
117 * If we are using AGP and if the AGP aperture doesn't allow us to have
118 * room for all the VRAM than we restrict the VRAM to the PCI aperture
119 * size and print a warning.
121 * This function will never fails, worst case are limiting VRAM.
123 * Note: GTT start, end, size should be initialized before calling this
124 * function on AGP platform.
126 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
127 * this shouldn't be a problem as we are using the PCI aperture as a reference.
128 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
131 * Note: we use mc_vram_size as on some board we need to program the mc to
132 * cover the whole aperture even if VRAM size is inferior to aperture size
133 * Novell bug 204882 + along with lots of ubuntu ones
135 * Note: when limiting vram it's safe to overwritte real_vram_size because
136 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
137 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
140 * Note: IGP TOM addr should be the same as the aperture addr, we don't
141 * explicitly check for that thought.
143 * FIXME: when reducing VRAM size align new size on power of 2.
145 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
147 mc
->vram_start
= base
;
148 if (mc
->mc_vram_size
> (0xFFFFFFFF - base
+ 1)) {
149 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
150 mc
->real_vram_size
= mc
->aper_size
;
151 mc
->mc_vram_size
= mc
->aper_size
;
153 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
154 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_end
<= mc
->gtt_end
) {
155 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
156 mc
->real_vram_size
= mc
->aper_size
;
157 mc
->mc_vram_size
= mc
->aper_size
;
159 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
160 dev_info(rdev
->dev
, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
161 mc
->mc_vram_size
>> 20, mc
->vram_start
,
162 mc
->vram_end
, mc
->real_vram_size
>> 20);
166 * radeon_gtt_location - try to find GTT location
167 * @rdev: radeon device structure holding all necessary informations
168 * @mc: memory controller structure holding memory informations
170 * Function will place try to place GTT before or after VRAM.
172 * If GTT size is bigger than space left then we ajust GTT size.
173 * Thus function will never fails.
175 * FIXME: when reducing GTT size align new size on power of 2.
177 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
179 u64 size_af
, size_bf
;
181 size_af
= 0xFFFFFFFF - mc
->vram_end
;
182 size_bf
= mc
->vram_start
;
183 if (size_bf
> size_af
) {
184 if (mc
->gtt_size
> size_bf
) {
185 dev_warn(rdev
->dev
, "limiting GTT\n");
186 mc
->gtt_size
= size_bf
;
188 mc
->gtt_start
= mc
->vram_start
- mc
->gtt_size
;
190 if (mc
->gtt_size
> size_af
) {
191 dev_warn(rdev
->dev
, "limiting GTT\n");
192 mc
->gtt_size
= size_af
;
194 mc
->gtt_start
= mc
->vram_end
+ 1;
196 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
197 dev_info(rdev
->dev
, "GTT: %lluM 0x%08llX - 0x%08llX\n",
198 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
202 * GPU helpers function.
204 bool radeon_card_posted(struct radeon_device
*rdev
)
208 /* first check CRTCs */
209 if (ASIC_IS_DCE4(rdev
)) {
210 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
211 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) |
212 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
213 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) |
214 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
215 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
216 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
218 } else if (ASIC_IS_AVIVO(rdev
)) {
219 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
220 RREG32(AVIVO_D2CRTC_CONTROL
);
221 if (reg
& AVIVO_CRTC_EN
) {
225 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
226 RREG32(RADEON_CRTC2_GEN_CNTL
);
227 if (reg
& RADEON_CRTC_EN
) {
232 /* then check MEM_SIZE, in case the crtcs are off */
233 if (rdev
->family
>= CHIP_R600
)
234 reg
= RREG32(R600_CONFIG_MEMSIZE
);
236 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
245 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
247 if (radeon_card_posted(rdev
))
251 DRM_INFO("GPU not posted. posting now...\n");
252 if (rdev
->is_atom_bios
)
253 atom_asic_init(rdev
->mode_info
.atom_context
);
255 radeon_combios_asic_init(rdev
->ddev
);
258 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
263 int radeon_dummy_page_init(struct radeon_device
*rdev
)
265 if (rdev
->dummy_page
.page
)
267 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
268 if (rdev
->dummy_page
.page
== NULL
)
270 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
271 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
272 if (!rdev
->dummy_page
.addr
) {
273 __free_page(rdev
->dummy_page
.page
);
274 rdev
->dummy_page
.page
= NULL
;
280 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
282 if (rdev
->dummy_page
.page
== NULL
)
284 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
285 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
286 __free_page(rdev
->dummy_page
.page
);
287 rdev
->dummy_page
.page
= NULL
;
292 * Registers accessors functions.
294 uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
296 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
301 void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
303 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
308 void radeon_register_accessor_init(struct radeon_device
*rdev
)
310 rdev
->mc_rreg
= &radeon_invalid_rreg
;
311 rdev
->mc_wreg
= &radeon_invalid_wreg
;
312 rdev
->pll_rreg
= &radeon_invalid_rreg
;
313 rdev
->pll_wreg
= &radeon_invalid_wreg
;
314 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
315 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
317 /* Don't change order as we are overridding accessor. */
318 if (rdev
->family
< CHIP_RV515
) {
319 rdev
->pcie_reg_mask
= 0xff;
321 rdev
->pcie_reg_mask
= 0x7ff;
323 /* FIXME: not sure here */
324 if (rdev
->family
<= CHIP_R580
) {
325 rdev
->pll_rreg
= &r100_pll_rreg
;
326 rdev
->pll_wreg
= &r100_pll_wreg
;
328 if (rdev
->family
>= CHIP_R420
) {
329 rdev
->mc_rreg
= &r420_mc_rreg
;
330 rdev
->mc_wreg
= &r420_mc_wreg
;
332 if (rdev
->family
>= CHIP_RV515
) {
333 rdev
->mc_rreg
= &rv515_mc_rreg
;
334 rdev
->mc_wreg
= &rv515_mc_wreg
;
336 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
337 rdev
->mc_rreg
= &rs400_mc_rreg
;
338 rdev
->mc_wreg
= &rs400_mc_wreg
;
340 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
341 rdev
->mc_rreg
= &rs690_mc_rreg
;
342 rdev
->mc_wreg
= &rs690_mc_wreg
;
344 if (rdev
->family
== CHIP_RS600
) {
345 rdev
->mc_rreg
= &rs600_mc_rreg
;
346 rdev
->mc_wreg
= &rs600_mc_wreg
;
348 if ((rdev
->family
>= CHIP_R600
) && (rdev
->family
<= CHIP_RV740
)) {
349 rdev
->pciep_rreg
= &r600_pciep_rreg
;
350 rdev
->pciep_wreg
= &r600_pciep_wreg
;
358 int radeon_asic_init(struct radeon_device
*rdev
)
360 radeon_register_accessor_init(rdev
);
361 switch (rdev
->family
) {
367 rdev
->asic
= &r100_asic
;
373 rdev
->asic
= &r200_asic
;
379 if (rdev
->flags
& RADEON_IS_PCIE
)
380 rdev
->asic
= &r300_asic_pcie
;
382 rdev
->asic
= &r300_asic
;
387 rdev
->asic
= &r420_asic
;
391 rdev
->asic
= &rs400_asic
;
394 rdev
->asic
= &rs600_asic
;
398 rdev
->asic
= &rs690_asic
;
401 rdev
->asic
= &rv515_asic
;
408 rdev
->asic
= &r520_asic
;
418 rdev
->asic
= &r600_asic
;
424 rdev
->asic
= &rv770_asic
;
431 rdev
->asic
= &evergreen_asic
;
434 /* FIXME: not supported yet */
438 if (rdev
->flags
& RADEON_IS_IGP
) {
439 rdev
->asic
->get_memory_clock
= NULL
;
440 rdev
->asic
->set_memory_clock
= NULL
;
448 * Wrapper around modesetting bits.
450 int radeon_clocks_init(struct radeon_device
*rdev
)
454 r
= radeon_static_clocks_init(rdev
->ddev
);
458 DRM_INFO("Clocks initialized !\n");
462 void radeon_clocks_fini(struct radeon_device
*rdev
)
466 /* ATOM accessor methods */
467 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
469 struct radeon_device
*rdev
= info
->dev
->dev_private
;
472 r
= rdev
->pll_rreg(rdev
, reg
);
476 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
478 struct radeon_device
*rdev
= info
->dev
->dev_private
;
480 rdev
->pll_wreg(rdev
, reg
, val
);
483 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
485 struct radeon_device
*rdev
= info
->dev
->dev_private
;
488 r
= rdev
->mc_rreg(rdev
, reg
);
492 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
494 struct radeon_device
*rdev
= info
->dev
->dev_private
;
496 rdev
->mc_wreg(rdev
, reg
, val
);
499 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
501 struct radeon_device
*rdev
= info
->dev
->dev_private
;
506 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
508 struct radeon_device
*rdev
= info
->dev
->dev_private
;
515 int radeon_atombios_init(struct radeon_device
*rdev
)
517 struct card_info
*atom_card_info
=
518 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
523 rdev
->mode_info
.atom_card_info
= atom_card_info
;
524 atom_card_info
->dev
= rdev
->ddev
;
525 atom_card_info
->reg_read
= cail_reg_read
;
526 atom_card_info
->reg_write
= cail_reg_write
;
527 atom_card_info
->mc_read
= cail_mc_read
;
528 atom_card_info
->mc_write
= cail_mc_write
;
529 atom_card_info
->pll_read
= cail_pll_read
;
530 atom_card_info
->pll_write
= cail_pll_write
;
532 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
533 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
534 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
535 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
539 void radeon_atombios_fini(struct radeon_device
*rdev
)
541 if (rdev
->mode_info
.atom_context
) {
542 kfree(rdev
->mode_info
.atom_context
->scratch
);
543 kfree(rdev
->mode_info
.atom_context
);
545 kfree(rdev
->mode_info
.atom_card_info
);
548 int radeon_combios_init(struct radeon_device
*rdev
)
550 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
554 void radeon_combios_fini(struct radeon_device
*rdev
)
558 /* if we get transitioned to only one device, tak VGA back */
559 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
561 struct radeon_device
*rdev
= cookie
;
562 radeon_vga_set_state(rdev
, state
);
564 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
565 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
567 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
570 void radeon_agp_disable(struct radeon_device
*rdev
)
572 rdev
->flags
&= ~RADEON_IS_AGP
;
573 if (rdev
->family
>= CHIP_R600
) {
574 DRM_INFO("Forcing AGP to PCIE mode\n");
575 rdev
->flags
|= RADEON_IS_PCIE
;
576 } else if (rdev
->family
>= CHIP_RV515
||
577 rdev
->family
== CHIP_RV380
||
578 rdev
->family
== CHIP_RV410
||
579 rdev
->family
== CHIP_R423
) {
580 DRM_INFO("Forcing AGP to PCIE mode\n");
581 rdev
->flags
|= RADEON_IS_PCIE
;
582 rdev
->asic
->gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
;
583 rdev
->asic
->gart_set_page
= &rv370_pcie_gart_set_page
;
585 DRM_INFO("Forcing AGP to PCI mode\n");
586 rdev
->flags
|= RADEON_IS_PCI
;
587 rdev
->asic
->gart_tlb_flush
= &r100_pci_gart_tlb_flush
;
588 rdev
->asic
->gart_set_page
= &r100_pci_gart_set_page
;
590 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
593 void radeon_check_arguments(struct radeon_device
*rdev
)
595 /* vramlimit must be a power of two */
596 switch (radeon_vram_limit
) {
611 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
613 radeon_vram_limit
= 0;
616 radeon_vram_limit
= radeon_vram_limit
<< 20;
617 /* gtt size must be power of two and greater or equal to 32M */
618 switch (radeon_gart_size
) {
622 dev_warn(rdev
->dev
, "gart size (%d) too small forcing to 512M\n",
624 radeon_gart_size
= 512;
636 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
638 radeon_gart_size
= 512;
641 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
642 /* AGP mode can only be -1, 1, 2, 4, 8 */
643 switch (radeon_agpmode
) {
652 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
653 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
659 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
661 struct drm_device
*dev
= pci_get_drvdata(pdev
);
662 struct radeon_device
*rdev
= dev
->dev_private
;
663 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
664 if (state
== VGA_SWITCHEROO_ON
) {
665 printk(KERN_INFO
"radeon: switched on\n");
666 /* don't suspend or resume card normally */
667 rdev
->powered_down
= false;
668 radeon_resume_kms(dev
);
670 printk(KERN_INFO
"radeon: switched off\n");
671 radeon_suspend_kms(dev
, pmm
);
672 /* don't suspend or resume card normally */
673 rdev
->powered_down
= true;
677 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
679 struct drm_device
*dev
= pci_get_drvdata(pdev
);
682 spin_lock(&dev
->count_lock
);
683 can_switch
= (dev
->open_count
== 0);
684 spin_unlock(&dev
->count_lock
);
689 int radeon_device_init(struct radeon_device
*rdev
,
690 struct drm_device
*ddev
,
691 struct pci_dev
*pdev
,
697 DRM_INFO("radeon: Initializing kernel modesetting.\n");
698 rdev
->shutdown
= false;
699 rdev
->dev
= &pdev
->dev
;
703 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
704 rdev
->is_atom_bios
= false;
705 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
706 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
707 rdev
->gpu_lockup
= false;
708 rdev
->accel_working
= false;
709 /* mutex initialization are all done here so we
710 * can recall function without having locking issues */
711 mutex_init(&rdev
->cs_mutex
);
712 mutex_init(&rdev
->ib_pool
.mutex
);
713 mutex_init(&rdev
->cp
.mutex
);
714 mutex_init(&rdev
->dc_hw_i2c_mutex
);
715 if (rdev
->family
>= CHIP_R600
)
716 spin_lock_init(&rdev
->ih
.lock
);
717 mutex_init(&rdev
->gem
.mutex
);
718 mutex_init(&rdev
->pm
.mutex
);
719 rwlock_init(&rdev
->fence_drv
.lock
);
720 INIT_LIST_HEAD(&rdev
->gem
.objects
);
721 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
723 /* setup workqueue */
724 rdev
->wq
= create_workqueue("radeon");
725 if (rdev
->wq
== NULL
)
728 /* Set asic functions */
729 r
= radeon_asic_init(rdev
);
732 radeon_check_arguments(rdev
);
734 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
735 radeon_agp_disable(rdev
);
738 /* set DMA mask + need_dma32 flags.
739 * PCIE - can handle 40-bits.
740 * IGP - can handle 40-bits (in theory)
741 * AGP - generally dma32 is safest
744 rdev
->need_dma32
= false;
745 if (rdev
->flags
& RADEON_IS_AGP
)
746 rdev
->need_dma32
= true;
747 if (rdev
->flags
& RADEON_IS_PCI
)
748 rdev
->need_dma32
= true;
750 dma_bits
= rdev
->need_dma32
? 32 : 40;
751 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
753 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
756 /* Registers mapping */
757 /* TODO: block userspace mapping of io register */
758 rdev
->rmmio_base
= drm_get_resource_start(rdev
->ddev
, 2);
759 rdev
->rmmio_size
= drm_get_resource_len(rdev
->ddev
, 2);
760 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
761 if (rdev
->rmmio
== NULL
) {
764 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
765 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
767 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
768 /* this will fail for cards that aren't VGA class devices, just
770 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
771 vga_switcheroo_register_client(rdev
->pdev
,
772 radeon_switcheroo_set_state
,
773 radeon_switcheroo_can_switch
);
775 r
= radeon_init(rdev
);
779 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
780 /* Acceleration not working on AGP card try again
781 * with fallback to PCI or PCIE GART
783 radeon_gpu_reset(rdev
);
785 radeon_agp_disable(rdev
);
786 r
= radeon_init(rdev
);
790 if (radeon_testing
) {
791 radeon_test_moves(rdev
);
793 if (radeon_benchmarking
) {
794 radeon_benchmark(rdev
);
799 void radeon_device_fini(struct radeon_device
*rdev
)
801 DRM_INFO("radeon: finishing device.\n");
802 rdev
->shutdown
= true;
804 destroy_workqueue(rdev
->wq
);
805 vga_switcheroo_unregister_client(rdev
->pdev
);
806 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
807 iounmap(rdev
->rmmio
);
815 int radeon_suspend_kms(struct drm_device
*dev
, pm_message_t state
)
817 struct radeon_device
*rdev
;
818 struct drm_crtc
*crtc
;
821 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
824 if (state
.event
== PM_EVENT_PRETHAW
) {
827 rdev
= dev
->dev_private
;
829 if (rdev
->powered_down
)
831 /* unpin the front buffers */
832 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
833 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->fb
);
834 struct radeon_bo
*robj
;
836 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
839 robj
= rfb
->obj
->driver_private
;
840 if (robj
!= rdev
->fbdev_rbo
) {
841 r
= radeon_bo_reserve(robj
, false);
842 if (unlikely(r
== 0)) {
843 radeon_bo_unpin(robj
);
844 radeon_bo_unreserve(robj
);
848 /* evict vram memory */
849 radeon_bo_evict_vram(rdev
);
850 /* wait for gpu to finish processing current batch */
851 radeon_fence_wait_last(rdev
);
853 radeon_save_bios_scratch_regs(rdev
);
855 radeon_suspend(rdev
);
856 radeon_hpd_fini(rdev
);
857 /* evict remaining vram memory */
858 radeon_bo_evict_vram(rdev
);
860 pci_save_state(dev
->pdev
);
861 if (state
.event
== PM_EVENT_SUSPEND
) {
862 /* Shut down the device */
863 pci_disable_device(dev
->pdev
);
864 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
866 acquire_console_sem();
867 fb_set_suspend(rdev
->fbdev_info
, 1);
868 release_console_sem();
872 int radeon_resume_kms(struct drm_device
*dev
)
874 struct radeon_device
*rdev
= dev
->dev_private
;
876 if (rdev
->powered_down
)
879 acquire_console_sem();
880 pci_set_power_state(dev
->pdev
, PCI_D0
);
881 pci_restore_state(dev
->pdev
);
882 if (pci_enable_device(dev
->pdev
)) {
883 release_console_sem();
886 pci_set_master(dev
->pdev
);
887 /* resume AGP if in use */
888 radeon_agp_resume(rdev
);
890 radeon_restore_bios_scratch_regs(rdev
);
891 fb_set_suspend(rdev
->fbdev_info
, 0);
892 release_console_sem();
894 /* reset hpd state */
895 radeon_hpd_init(rdev
);
896 /* blat the mode back in */
897 drm_helper_resume_force_mode(dev
);
905 struct radeon_debugfs
{
906 struct drm_info_list
*files
;
909 static struct radeon_debugfs _radeon_debugfs
[RADEON_DEBUGFS_MAX_NUM_FILES
];
910 static unsigned _radeon_debugfs_count
= 0;
912 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
913 struct drm_info_list
*files
,
918 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
919 if (_radeon_debugfs
[i
].files
== files
) {
920 /* Already registered */
924 if ((_radeon_debugfs_count
+ nfiles
) > RADEON_DEBUGFS_MAX_NUM_FILES
) {
925 DRM_ERROR("Reached maximum number of debugfs files.\n");
926 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
929 _radeon_debugfs
[_radeon_debugfs_count
].files
= files
;
930 _radeon_debugfs
[_radeon_debugfs_count
].num_files
= nfiles
;
931 _radeon_debugfs_count
++;
932 #if defined(CONFIG_DEBUG_FS)
933 drm_debugfs_create_files(files
, nfiles
,
934 rdev
->ddev
->control
->debugfs_root
,
935 rdev
->ddev
->control
);
936 drm_debugfs_create_files(files
, nfiles
,
937 rdev
->ddev
->primary
->debugfs_root
,
938 rdev
->ddev
->primary
);
943 #if defined(CONFIG_DEBUG_FS)
944 int radeon_debugfs_init(struct drm_minor
*minor
)
949 void radeon_debugfs_cleanup(struct drm_minor
*minor
)
953 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
954 drm_debugfs_remove_files(_radeon_debugfs
[i
].files
,
955 _radeon_debugfs
[i
].num_files
, minor
);