2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include <linux/vgaarb.h>
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
39 * Clear GPU surface registers.
41 void radeon_surface_init(struct radeon_device
*rdev
)
43 /* FIXME: check this out */
44 if (rdev
->family
< CHIP_R600
) {
47 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
48 if (rdev
->surface_regs
[i
].bo
)
49 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
51 radeon_clear_surface_reg(rdev
, i
);
54 WREG32(RADEON_SURFACE_CNTL
, 0);
59 * GPU scratch registers helpers function.
61 void radeon_scratch_init(struct radeon_device
*rdev
)
65 /* FIXME: check this out */
66 if (rdev
->family
< CHIP_R300
) {
67 rdev
->scratch
.num_reg
= 5;
69 rdev
->scratch
.num_reg
= 7;
71 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
72 rdev
->scratch
.free
[i
] = true;
73 rdev
->scratch
.reg
[i
] = RADEON_SCRATCH_REG0
+ (i
* 4);
77 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
81 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
82 if (rdev
->scratch
.free
[i
]) {
83 rdev
->scratch
.free
[i
] = false;
84 *reg
= rdev
->scratch
.reg
[i
];
91 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
95 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
96 if (rdev
->scratch
.reg
[i
] == reg
) {
97 rdev
->scratch
.free
[i
] = true;
104 * MC common functions
106 int radeon_mc_setup(struct radeon_device
*rdev
)
110 /* Some chips have an "issue" with the memory controller, the
111 * location must be aligned to the size. We just align it down,
112 * too bad if we walk over the top of system memory, we don't
113 * use DMA without a remapped anyway.
114 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
116 /* FGLRX seems to setup like this, VRAM a 0, then GART.
119 * Note: from R6xx the address space is 40bits but here we only
120 * use 32bits (still have to see a card which would exhaust 4G
123 if (rdev
->mc
.vram_location
!= 0xFFFFFFFFUL
) {
124 /* vram location was already setup try to put gtt after
126 tmp
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
;
127 tmp
= (tmp
+ rdev
->mc
.gtt_size
- 1) & ~(rdev
->mc
.gtt_size
- 1);
128 if ((0xFFFFFFFFUL
- tmp
) >= rdev
->mc
.gtt_size
) {
129 rdev
->mc
.gtt_location
= tmp
;
131 if (rdev
->mc
.gtt_size
>= rdev
->mc
.vram_location
) {
132 printk(KERN_ERR
"[drm] GTT too big to fit "
133 "before or after vram location.\n");
136 rdev
->mc
.gtt_location
= 0;
138 } else if (rdev
->mc
.gtt_location
!= 0xFFFFFFFFUL
) {
139 /* gtt location was already setup try to put vram before
141 if (rdev
->mc
.mc_vram_size
< rdev
->mc
.gtt_location
) {
142 rdev
->mc
.vram_location
= 0;
144 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
;
145 tmp
+= (rdev
->mc
.mc_vram_size
- 1);
146 tmp
&= ~(rdev
->mc
.mc_vram_size
- 1);
147 if ((0xFFFFFFFFUL
- tmp
) >= rdev
->mc
.mc_vram_size
) {
148 rdev
->mc
.vram_location
= tmp
;
150 printk(KERN_ERR
"[drm] vram too big to fit "
151 "before or after GTT location.\n");
156 rdev
->mc
.vram_location
= 0;
157 tmp
= rdev
->mc
.mc_vram_size
;
158 tmp
= (tmp
+ rdev
->mc
.gtt_size
- 1) & ~(rdev
->mc
.gtt_size
- 1);
159 rdev
->mc
.gtt_location
= tmp
;
161 rdev
->mc
.vram_start
= rdev
->mc
.vram_location
;
162 rdev
->mc
.vram_end
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
- 1;
163 rdev
->mc
.gtt_start
= rdev
->mc
.gtt_location
;
164 rdev
->mc
.gtt_end
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1;
165 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev
->mc
.mc_vram_size
>> 20));
166 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
167 (unsigned)rdev
->mc
.vram_location
,
168 (unsigned)(rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
- 1));
169 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev
->mc
.gtt_size
>> 20));
170 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
171 (unsigned)rdev
->mc
.gtt_location
,
172 (unsigned)(rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1));
178 * GPU helpers function.
180 bool radeon_card_posted(struct radeon_device
*rdev
)
184 /* first check CRTCs */
185 if (ASIC_IS_AVIVO(rdev
)) {
186 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
187 RREG32(AVIVO_D2CRTC_CONTROL
);
188 if (reg
& AVIVO_CRTC_EN
) {
192 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
193 RREG32(RADEON_CRTC2_GEN_CNTL
);
194 if (reg
& RADEON_CRTC_EN
) {
199 /* then check MEM_SIZE, in case the crtcs are off */
200 if (rdev
->family
>= CHIP_R600
)
201 reg
= RREG32(R600_CONFIG_MEMSIZE
);
203 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
212 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
214 if (radeon_card_posted(rdev
))
218 DRM_INFO("GPU not posted. posting now...\n");
219 if (rdev
->is_atom_bios
)
220 atom_asic_init(rdev
->mode_info
.atom_context
);
222 radeon_combios_asic_init(rdev
->ddev
);
225 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
230 int radeon_dummy_page_init(struct radeon_device
*rdev
)
232 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
233 if (rdev
->dummy_page
.page
== NULL
)
235 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
236 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
237 if (!rdev
->dummy_page
.addr
) {
238 __free_page(rdev
->dummy_page
.page
);
239 rdev
->dummy_page
.page
= NULL
;
245 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
247 if (rdev
->dummy_page
.page
== NULL
)
249 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
250 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
251 __free_page(rdev
->dummy_page
.page
);
252 rdev
->dummy_page
.page
= NULL
;
257 * Registers accessors functions.
259 uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
261 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
266 void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
268 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
273 void radeon_register_accessor_init(struct radeon_device
*rdev
)
275 rdev
->mc_rreg
= &radeon_invalid_rreg
;
276 rdev
->mc_wreg
= &radeon_invalid_wreg
;
277 rdev
->pll_rreg
= &radeon_invalid_rreg
;
278 rdev
->pll_wreg
= &radeon_invalid_wreg
;
279 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
280 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
282 /* Don't change order as we are overridding accessor. */
283 if (rdev
->family
< CHIP_RV515
) {
284 rdev
->pcie_reg_mask
= 0xff;
286 rdev
->pcie_reg_mask
= 0x7ff;
288 /* FIXME: not sure here */
289 if (rdev
->family
<= CHIP_R580
) {
290 rdev
->pll_rreg
= &r100_pll_rreg
;
291 rdev
->pll_wreg
= &r100_pll_wreg
;
293 if (rdev
->family
>= CHIP_R420
) {
294 rdev
->mc_rreg
= &r420_mc_rreg
;
295 rdev
->mc_wreg
= &r420_mc_wreg
;
297 if (rdev
->family
>= CHIP_RV515
) {
298 rdev
->mc_rreg
= &rv515_mc_rreg
;
299 rdev
->mc_wreg
= &rv515_mc_wreg
;
301 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
302 rdev
->mc_rreg
= &rs400_mc_rreg
;
303 rdev
->mc_wreg
= &rs400_mc_wreg
;
305 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
306 rdev
->mc_rreg
= &rs690_mc_rreg
;
307 rdev
->mc_wreg
= &rs690_mc_wreg
;
309 if (rdev
->family
== CHIP_RS600
) {
310 rdev
->mc_rreg
= &rs600_mc_rreg
;
311 rdev
->mc_wreg
= &rs600_mc_wreg
;
313 if (rdev
->family
>= CHIP_R600
) {
314 rdev
->pciep_rreg
= &r600_pciep_rreg
;
315 rdev
->pciep_wreg
= &r600_pciep_wreg
;
323 int radeon_asic_init(struct radeon_device
*rdev
)
325 radeon_register_accessor_init(rdev
);
326 switch (rdev
->family
) {
336 rdev
->asic
= &r100_asic
;
342 rdev
->asic
= &r300_asic
;
343 if (rdev
->flags
& RADEON_IS_PCIE
) {
344 rdev
->asic
->gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
;
345 rdev
->asic
->gart_set_page
= &rv370_pcie_gart_set_page
;
351 rdev
->asic
= &r420_asic
;
355 rdev
->asic
= &rs400_asic
;
358 rdev
->asic
= &rs600_asic
;
362 rdev
->asic
= &rs690_asic
;
365 rdev
->asic
= &rv515_asic
;
372 rdev
->asic
= &r520_asic
;
382 rdev
->asic
= &r600_asic
;
388 rdev
->asic
= &rv770_asic
;
391 /* FIXME: not supported yet */
395 if (rdev
->flags
& RADEON_IS_IGP
) {
396 rdev
->asic
->get_memory_clock
= NULL
;
397 rdev
->asic
->set_memory_clock
= NULL
;
405 * Wrapper around modesetting bits.
407 int radeon_clocks_init(struct radeon_device
*rdev
)
411 r
= radeon_static_clocks_init(rdev
->ddev
);
415 DRM_INFO("Clocks initialized !\n");
419 void radeon_clocks_fini(struct radeon_device
*rdev
)
423 /* ATOM accessor methods */
424 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
426 struct radeon_device
*rdev
= info
->dev
->dev_private
;
429 r
= rdev
->pll_rreg(rdev
, reg
);
433 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
435 struct radeon_device
*rdev
= info
->dev
->dev_private
;
437 rdev
->pll_wreg(rdev
, reg
, val
);
440 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
442 struct radeon_device
*rdev
= info
->dev
->dev_private
;
445 r
= rdev
->mc_rreg(rdev
, reg
);
449 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
451 struct radeon_device
*rdev
= info
->dev
->dev_private
;
453 rdev
->mc_wreg(rdev
, reg
, val
);
456 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
458 struct radeon_device
*rdev
= info
->dev
->dev_private
;
463 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
465 struct radeon_device
*rdev
= info
->dev
->dev_private
;
472 int radeon_atombios_init(struct radeon_device
*rdev
)
474 struct card_info
*atom_card_info
=
475 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
480 rdev
->mode_info
.atom_card_info
= atom_card_info
;
481 atom_card_info
->dev
= rdev
->ddev
;
482 atom_card_info
->reg_read
= cail_reg_read
;
483 atom_card_info
->reg_write
= cail_reg_write
;
484 atom_card_info
->mc_read
= cail_mc_read
;
485 atom_card_info
->mc_write
= cail_mc_write
;
486 atom_card_info
->pll_read
= cail_pll_read
;
487 atom_card_info
->pll_write
= cail_pll_write
;
489 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
490 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
491 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
492 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
496 void radeon_atombios_fini(struct radeon_device
*rdev
)
498 if (rdev
->mode_info
.atom_context
) {
499 kfree(rdev
->mode_info
.atom_context
->scratch
);
500 kfree(rdev
->mode_info
.atom_context
);
502 kfree(rdev
->mode_info
.atom_card_info
);
505 int radeon_combios_init(struct radeon_device
*rdev
)
507 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
511 void radeon_combios_fini(struct radeon_device
*rdev
)
515 /* if we get transitioned to only one device, tak VGA back */
516 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
518 struct radeon_device
*rdev
= cookie
;
519 radeon_vga_set_state(rdev
, state
);
521 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
522 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
524 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
527 void radeon_agp_disable(struct radeon_device
*rdev
)
529 rdev
->flags
&= ~RADEON_IS_AGP
;
530 if (rdev
->family
>= CHIP_R600
) {
531 DRM_INFO("Forcing AGP to PCIE mode\n");
532 rdev
->flags
|= RADEON_IS_PCIE
;
533 } else if (rdev
->family
>= CHIP_RV515
||
534 rdev
->family
== CHIP_RV380
||
535 rdev
->family
== CHIP_RV410
||
536 rdev
->family
== CHIP_R423
) {
537 DRM_INFO("Forcing AGP to PCIE mode\n");
538 rdev
->flags
|= RADEON_IS_PCIE
;
539 rdev
->asic
->gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
;
540 rdev
->asic
->gart_set_page
= &rv370_pcie_gart_set_page
;
542 DRM_INFO("Forcing AGP to PCI mode\n");
543 rdev
->flags
|= RADEON_IS_PCI
;
544 rdev
->asic
->gart_tlb_flush
= &r100_pci_gart_tlb_flush
;
545 rdev
->asic
->gart_set_page
= &r100_pci_gart_set_page
;
549 void radeon_check_arguments(struct radeon_device
*rdev
)
551 /* vramlimit must be a power of two */
552 switch (radeon_vram_limit
) {
567 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
569 radeon_vram_limit
= 0;
572 radeon_vram_limit
= radeon_vram_limit
<< 20;
573 /* gtt size must be power of two and greater or equal to 32M */
574 switch (radeon_gart_size
) {
578 dev_warn(rdev
->dev
, "gart size (%d) too small forcing to 512M\n",
580 radeon_gart_size
= 512;
592 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
594 radeon_gart_size
= 512;
597 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
598 /* AGP mode can only be -1, 1, 2, 4, 8 */
599 switch (radeon_agpmode
) {
608 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
609 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
615 int radeon_device_init(struct radeon_device
*rdev
,
616 struct drm_device
*ddev
,
617 struct pci_dev
*pdev
,
623 DRM_INFO("radeon: Initializing kernel modesetting.\n");
624 rdev
->shutdown
= false;
625 rdev
->dev
= &pdev
->dev
;
629 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
630 rdev
->is_atom_bios
= false;
631 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
632 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
633 rdev
->gpu_lockup
= false;
634 rdev
->accel_working
= false;
635 /* mutex initialization are all done here so we
636 * can recall function without having locking issues */
637 mutex_init(&rdev
->cs_mutex
);
638 mutex_init(&rdev
->ib_pool
.mutex
);
639 mutex_init(&rdev
->cp
.mutex
);
640 if (rdev
->family
>= CHIP_R600
)
641 spin_lock_init(&rdev
->ih
.lock
);
642 mutex_init(&rdev
->gem
.mutex
);
643 rwlock_init(&rdev
->fence_drv
.lock
);
644 INIT_LIST_HEAD(&rdev
->gem
.objects
);
646 /* setup workqueue */
647 rdev
->wq
= create_workqueue("radeon");
648 if (rdev
->wq
== NULL
)
651 /* Set asic functions */
652 r
= radeon_asic_init(rdev
);
655 radeon_check_arguments(rdev
);
657 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
658 radeon_agp_disable(rdev
);
661 /* set DMA mask + need_dma32 flags.
662 * PCIE - can handle 40-bits.
663 * IGP - can handle 40-bits (in theory)
664 * AGP - generally dma32 is safest
667 rdev
->need_dma32
= false;
668 if (rdev
->flags
& RADEON_IS_AGP
)
669 rdev
->need_dma32
= true;
670 if (rdev
->flags
& RADEON_IS_PCI
)
671 rdev
->need_dma32
= true;
673 dma_bits
= rdev
->need_dma32
? 32 : 40;
674 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
676 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
679 /* Registers mapping */
680 /* TODO: block userspace mapping of io register */
681 rdev
->rmmio_base
= drm_get_resource_start(rdev
->ddev
, 2);
682 rdev
->rmmio_size
= drm_get_resource_len(rdev
->ddev
, 2);
683 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
684 if (rdev
->rmmio
== NULL
) {
687 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
688 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
690 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
691 /* this will fail for cards that aren't VGA class devices, just
693 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
695 r
= radeon_init(rdev
);
699 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
700 /* Acceleration not working on AGP card try again
701 * with fallback to PCI or PCIE GART
703 radeon_gpu_reset(rdev
);
705 radeon_agp_disable(rdev
);
706 r
= radeon_init(rdev
);
710 if (radeon_testing
) {
711 radeon_test_moves(rdev
);
713 if (radeon_benchmarking
) {
714 radeon_benchmark(rdev
);
719 void radeon_device_fini(struct radeon_device
*rdev
)
721 DRM_INFO("radeon: finishing device.\n");
722 rdev
->shutdown
= true;
724 destroy_workqueue(rdev
->wq
);
725 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
726 iounmap(rdev
->rmmio
);
734 int radeon_suspend_kms(struct drm_device
*dev
, pm_message_t state
)
736 struct radeon_device
*rdev
;
737 struct drm_crtc
*crtc
;
740 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
743 if (state
.event
== PM_EVENT_PRETHAW
) {
746 rdev
= dev
->dev_private
;
748 /* unpin the front buffers */
749 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
750 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->fb
);
751 struct radeon_bo
*robj
;
753 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
756 robj
= rfb
->obj
->driver_private
;
757 if (robj
!= rdev
->fbdev_rbo
) {
758 r
= radeon_bo_reserve(robj
, false);
759 if (unlikely(r
== 0)) {
760 radeon_bo_unpin(robj
);
761 radeon_bo_unreserve(robj
);
765 /* evict vram memory */
766 radeon_bo_evict_vram(rdev
);
767 /* wait for gpu to finish processing current batch */
768 radeon_fence_wait_last(rdev
);
770 radeon_save_bios_scratch_regs(rdev
);
772 radeon_suspend(rdev
);
773 radeon_hpd_fini(rdev
);
774 /* evict remaining vram memory */
775 radeon_bo_evict_vram(rdev
);
777 pci_save_state(dev
->pdev
);
778 if (state
.event
== PM_EVENT_SUSPEND
) {
779 /* Shut down the device */
780 pci_disable_device(dev
->pdev
);
781 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
783 acquire_console_sem();
784 fb_set_suspend(rdev
->fbdev_info
, 1);
785 release_console_sem();
789 int radeon_resume_kms(struct drm_device
*dev
)
791 struct radeon_device
*rdev
= dev
->dev_private
;
793 acquire_console_sem();
794 pci_set_power_state(dev
->pdev
, PCI_D0
);
795 pci_restore_state(dev
->pdev
);
796 if (pci_enable_device(dev
->pdev
)) {
797 release_console_sem();
800 pci_set_master(dev
->pdev
);
801 /* resume AGP if in use */
802 radeon_agp_resume(rdev
);
804 radeon_restore_bios_scratch_regs(rdev
);
805 fb_set_suspend(rdev
->fbdev_info
, 0);
806 release_console_sem();
808 /* reset hpd state */
809 radeon_hpd_init(rdev
);
810 /* blat the mode back in */
811 drm_helper_resume_force_mode(dev
);
819 struct radeon_debugfs
{
820 struct drm_info_list
*files
;
823 static struct radeon_debugfs _radeon_debugfs
[RADEON_DEBUGFS_MAX_NUM_FILES
];
824 static unsigned _radeon_debugfs_count
= 0;
826 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
827 struct drm_info_list
*files
,
832 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
833 if (_radeon_debugfs
[i
].files
== files
) {
834 /* Already registered */
838 if ((_radeon_debugfs_count
+ nfiles
) > RADEON_DEBUGFS_MAX_NUM_FILES
) {
839 DRM_ERROR("Reached maximum number of debugfs files.\n");
840 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
843 _radeon_debugfs
[_radeon_debugfs_count
].files
= files
;
844 _radeon_debugfs
[_radeon_debugfs_count
].num_files
= nfiles
;
845 _radeon_debugfs_count
++;
846 #if defined(CONFIG_DEBUG_FS)
847 drm_debugfs_create_files(files
, nfiles
,
848 rdev
->ddev
->control
->debugfs_root
,
849 rdev
->ddev
->control
);
850 drm_debugfs_create_files(files
, nfiles
,
851 rdev
->ddev
->primary
->debugfs_root
,
852 rdev
->ddev
->primary
);
857 #if defined(CONFIG_DEBUG_FS)
858 int radeon_debugfs_init(struct drm_minor
*minor
)
863 void radeon_debugfs_cleanup(struct drm_minor
*minor
)
867 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
868 drm_debugfs_remove_files(_radeon_debugfs
[i
].files
,
869 _radeon_debugfs
[i
].num_files
, minor
);