2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
39 static const char radeon_family_name
[][16] = {
88 * Clear GPU surface registers.
90 void radeon_surface_init(struct radeon_device
*rdev
)
92 /* FIXME: check this out */
93 if (rdev
->family
< CHIP_R600
) {
96 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
97 if (rdev
->surface_regs
[i
].bo
)
98 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
100 radeon_clear_surface_reg(rdev
, i
);
102 /* enable surfaces */
103 WREG32(RADEON_SURFACE_CNTL
, 0);
108 * GPU scratch registers helpers function.
110 void radeon_scratch_init(struct radeon_device
*rdev
)
114 /* FIXME: check this out */
115 if (rdev
->family
< CHIP_R300
) {
116 rdev
->scratch
.num_reg
= 5;
118 rdev
->scratch
.num_reg
= 7;
120 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
121 rdev
->scratch
.free
[i
] = true;
122 rdev
->scratch
.reg
[i
] = RADEON_SCRATCH_REG0
+ (i
* 4);
126 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
130 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
131 if (rdev
->scratch
.free
[i
]) {
132 rdev
->scratch
.free
[i
] = false;
133 *reg
= rdev
->scratch
.reg
[i
];
140 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
144 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
145 if (rdev
->scratch
.reg
[i
] == reg
) {
146 rdev
->scratch
.free
[i
] = true;
153 * radeon_vram_location - try to find VRAM location
154 * @rdev: radeon device structure holding all necessary informations
155 * @mc: memory controller structure holding memory informations
156 * @base: base address at which to put VRAM
158 * Function will place try to place VRAM at base address provided
159 * as parameter (which is so far either PCI aperture address or
160 * for IGP TOM base address).
162 * If there is not enough space to fit the unvisible VRAM in the 32bits
163 * address space then we limit the VRAM size to the aperture.
165 * If we are using AGP and if the AGP aperture doesn't allow us to have
166 * room for all the VRAM than we restrict the VRAM to the PCI aperture
167 * size and print a warning.
169 * This function will never fails, worst case are limiting VRAM.
171 * Note: GTT start, end, size should be initialized before calling this
172 * function on AGP platform.
174 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
175 * this shouldn't be a problem as we are using the PCI aperture as a reference.
176 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
179 * Note: we use mc_vram_size as on some board we need to program the mc to
180 * cover the whole aperture even if VRAM size is inferior to aperture size
181 * Novell bug 204882 + along with lots of ubuntu ones
183 * Note: when limiting vram it's safe to overwritte real_vram_size because
184 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
185 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
188 * Note: IGP TOM addr should be the same as the aperture addr, we don't
189 * explicitly check for that thought.
191 * FIXME: when reducing VRAM size align new size on power of 2.
193 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
195 mc
->vram_start
= base
;
196 if (mc
->mc_vram_size
> (0xFFFFFFFF - base
+ 1)) {
197 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
198 mc
->real_vram_size
= mc
->aper_size
;
199 mc
->mc_vram_size
= mc
->aper_size
;
201 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
202 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_end
<= mc
->gtt_end
) {
203 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
204 mc
->real_vram_size
= mc
->aper_size
;
205 mc
->mc_vram_size
= mc
->aper_size
;
207 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
208 dev_info(rdev
->dev
, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
209 mc
->mc_vram_size
>> 20, mc
->vram_start
,
210 mc
->vram_end
, mc
->real_vram_size
>> 20);
214 * radeon_gtt_location - try to find GTT location
215 * @rdev: radeon device structure holding all necessary informations
216 * @mc: memory controller structure holding memory informations
218 * Function will place try to place GTT before or after VRAM.
220 * If GTT size is bigger than space left then we ajust GTT size.
221 * Thus function will never fails.
223 * FIXME: when reducing GTT size align new size on power of 2.
225 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
227 u64 size_af
, size_bf
;
229 size_af
= ((0xFFFFFFFF - mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
230 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
231 if (size_bf
> size_af
) {
232 if (mc
->gtt_size
> size_bf
) {
233 dev_warn(rdev
->dev
, "limiting GTT\n");
234 mc
->gtt_size
= size_bf
;
236 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
238 if (mc
->gtt_size
> size_af
) {
239 dev_warn(rdev
->dev
, "limiting GTT\n");
240 mc
->gtt_size
= size_af
;
242 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
244 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
245 dev_info(rdev
->dev
, "GTT: %lluM 0x%08llX - 0x%08llX\n",
246 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
250 * GPU helpers function.
252 bool radeon_card_posted(struct radeon_device
*rdev
)
256 /* first check CRTCs */
257 if (ASIC_IS_DCE4(rdev
)) {
258 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
259 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) |
260 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
261 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) |
262 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
263 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
264 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
266 } else if (ASIC_IS_AVIVO(rdev
)) {
267 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
268 RREG32(AVIVO_D2CRTC_CONTROL
);
269 if (reg
& AVIVO_CRTC_EN
) {
273 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
274 RREG32(RADEON_CRTC2_GEN_CNTL
);
275 if (reg
& RADEON_CRTC_EN
) {
280 /* then check MEM_SIZE, in case the crtcs are off */
281 if (rdev
->family
>= CHIP_R600
)
282 reg
= RREG32(R600_CONFIG_MEMSIZE
);
284 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
293 void radeon_update_bandwidth_info(struct radeon_device
*rdev
)
298 if (rdev
->flags
& RADEON_IS_IGP
) {
299 sclk
= radeon_get_engine_clock(rdev
);
300 mclk
= rdev
->clock
.default_mclk
;
302 a
.full
= dfixed_const(100);
303 rdev
->pm
.sclk
.full
= dfixed_const(sclk
);
304 rdev
->pm
.sclk
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
305 rdev
->pm
.mclk
.full
= dfixed_const(mclk
);
306 rdev
->pm
.mclk
.full
= dfixed_div(rdev
->pm
.mclk
, a
);
308 a
.full
= dfixed_const(16);
309 /* core_bandwidth = sclk(Mhz) * 16 */
310 rdev
->pm
.core_bandwidth
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
312 sclk
= radeon_get_engine_clock(rdev
);
313 mclk
= radeon_get_memory_clock(rdev
);
315 a
.full
= dfixed_const(100);
316 rdev
->pm
.sclk
.full
= dfixed_const(sclk
);
317 rdev
->pm
.sclk
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
318 rdev
->pm
.mclk
.full
= dfixed_const(mclk
);
319 rdev
->pm
.mclk
.full
= dfixed_div(rdev
->pm
.mclk
, a
);
323 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
325 if (radeon_card_posted(rdev
))
329 DRM_INFO("GPU not posted. posting now...\n");
330 if (rdev
->is_atom_bios
)
331 atom_asic_init(rdev
->mode_info
.atom_context
);
333 radeon_combios_asic_init(rdev
->ddev
);
336 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
341 int radeon_dummy_page_init(struct radeon_device
*rdev
)
343 if (rdev
->dummy_page
.page
)
345 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
346 if (rdev
->dummy_page
.page
== NULL
)
348 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
349 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
350 if (pci_dma_mapping_error(rdev
->pdev
, rdev
->dummy_page
.addr
)) {
351 dev_err(&rdev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
352 __free_page(rdev
->dummy_page
.page
);
353 rdev
->dummy_page
.page
= NULL
;
359 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
361 if (rdev
->dummy_page
.page
== NULL
)
363 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
364 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
365 __free_page(rdev
->dummy_page
.page
);
366 rdev
->dummy_page
.page
= NULL
;
370 /* ATOM accessor methods */
371 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
373 struct radeon_device
*rdev
= info
->dev
->dev_private
;
376 r
= rdev
->pll_rreg(rdev
, reg
);
380 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
382 struct radeon_device
*rdev
= info
->dev
->dev_private
;
384 rdev
->pll_wreg(rdev
, reg
, val
);
387 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
389 struct radeon_device
*rdev
= info
->dev
->dev_private
;
392 r
= rdev
->mc_rreg(rdev
, reg
);
396 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
398 struct radeon_device
*rdev
= info
->dev
->dev_private
;
400 rdev
->mc_wreg(rdev
, reg
, val
);
403 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
405 struct radeon_device
*rdev
= info
->dev
->dev_private
;
410 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
412 struct radeon_device
*rdev
= info
->dev
->dev_private
;
419 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
421 struct radeon_device
*rdev
= info
->dev
->dev_private
;
423 WREG32_IO(reg
*4, val
);
426 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
428 struct radeon_device
*rdev
= info
->dev
->dev_private
;
431 r
= RREG32_IO(reg
*4);
435 int radeon_atombios_init(struct radeon_device
*rdev
)
437 struct card_info
*atom_card_info
=
438 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
443 rdev
->mode_info
.atom_card_info
= atom_card_info
;
444 atom_card_info
->dev
= rdev
->ddev
;
445 atom_card_info
->reg_read
= cail_reg_read
;
446 atom_card_info
->reg_write
= cail_reg_write
;
447 /* needed for iio ops */
449 atom_card_info
->ioreg_read
= cail_ioreg_read
;
450 atom_card_info
->ioreg_write
= cail_ioreg_write
;
452 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
453 atom_card_info
->ioreg_read
= cail_reg_read
;
454 atom_card_info
->ioreg_write
= cail_reg_write
;
456 atom_card_info
->mc_read
= cail_mc_read
;
457 atom_card_info
->mc_write
= cail_mc_write
;
458 atom_card_info
->pll_read
= cail_pll_read
;
459 atom_card_info
->pll_write
= cail_pll_write
;
461 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
462 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
463 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
464 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
468 void radeon_atombios_fini(struct radeon_device
*rdev
)
470 if (rdev
->mode_info
.atom_context
) {
471 kfree(rdev
->mode_info
.atom_context
->scratch
);
472 kfree(rdev
->mode_info
.atom_context
);
474 kfree(rdev
->mode_info
.atom_card_info
);
477 int radeon_combios_init(struct radeon_device
*rdev
)
479 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
483 void radeon_combios_fini(struct radeon_device
*rdev
)
487 /* if we get transitioned to only one device, tak VGA back */
488 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
490 struct radeon_device
*rdev
= cookie
;
491 radeon_vga_set_state(rdev
, state
);
493 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
494 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
496 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
499 void radeon_check_arguments(struct radeon_device
*rdev
)
501 /* vramlimit must be a power of two */
502 switch (radeon_vram_limit
) {
517 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
519 radeon_vram_limit
= 0;
522 radeon_vram_limit
= radeon_vram_limit
<< 20;
523 /* gtt size must be power of two and greater or equal to 32M */
524 switch (radeon_gart_size
) {
528 dev_warn(rdev
->dev
, "gart size (%d) too small forcing to 512M\n",
530 radeon_gart_size
= 512;
542 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
544 radeon_gart_size
= 512;
547 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
548 /* AGP mode can only be -1, 1, 2, 4, 8 */
549 switch (radeon_agpmode
) {
558 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
559 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
565 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
567 struct drm_device
*dev
= pci_get_drvdata(pdev
);
568 struct radeon_device
*rdev
= dev
->dev_private
;
569 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
570 if (state
== VGA_SWITCHEROO_ON
) {
571 printk(KERN_INFO
"radeon: switched on\n");
572 /* don't suspend or resume card normally */
573 rdev
->powered_down
= false;
574 radeon_resume_kms(dev
);
575 drm_kms_helper_poll_enable(dev
);
577 printk(KERN_INFO
"radeon: switched off\n");
578 drm_kms_helper_poll_disable(dev
);
579 radeon_suspend_kms(dev
, pmm
);
580 /* don't suspend or resume card normally */
581 rdev
->powered_down
= true;
585 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
587 struct drm_device
*dev
= pci_get_drvdata(pdev
);
590 spin_lock(&dev
->count_lock
);
591 can_switch
= (dev
->open_count
== 0);
592 spin_unlock(&dev
->count_lock
);
597 int radeon_device_init(struct radeon_device
*rdev
,
598 struct drm_device
*ddev
,
599 struct pci_dev
*pdev
,
605 rdev
->shutdown
= false;
606 rdev
->dev
= &pdev
->dev
;
610 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
611 rdev
->is_atom_bios
= false;
612 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
613 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
614 rdev
->gpu_lockup
= false;
615 rdev
->accel_working
= false;
617 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
618 radeon_family_name
[rdev
->family
], pdev
->vendor
, pdev
->device
);
620 /* mutex initialization are all done here so we
621 * can recall function without having locking issues */
622 mutex_init(&rdev
->cs_mutex
);
623 mutex_init(&rdev
->ib_pool
.mutex
);
624 mutex_init(&rdev
->cp
.mutex
);
625 mutex_init(&rdev
->dc_hw_i2c_mutex
);
626 if (rdev
->family
>= CHIP_R600
)
627 spin_lock_init(&rdev
->ih
.lock
);
628 mutex_init(&rdev
->gem
.mutex
);
629 mutex_init(&rdev
->pm
.mutex
);
630 mutex_init(&rdev
->vram_mutex
);
631 rwlock_init(&rdev
->fence_drv
.lock
);
632 INIT_LIST_HEAD(&rdev
->gem
.objects
);
633 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
634 init_waitqueue_head(&rdev
->irq
.idle_queue
);
636 /* setup workqueue */
637 rdev
->wq
= create_workqueue("radeon");
638 if (rdev
->wq
== NULL
)
641 /* Set asic functions */
642 r
= radeon_asic_init(rdev
);
645 radeon_check_arguments(rdev
);
647 /* all of the newer IGP chips have an internal gart
648 * However some rs4xx report as AGP, so remove that here.
650 if ((rdev
->family
>= CHIP_RS400
) &&
651 (rdev
->flags
& RADEON_IS_IGP
)) {
652 rdev
->flags
&= ~RADEON_IS_AGP
;
655 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
656 radeon_agp_disable(rdev
);
659 /* set DMA mask + need_dma32 flags.
660 * PCIE - can handle 40-bits.
661 * IGP - can handle 40-bits (in theory)
662 * AGP - generally dma32 is safest
665 rdev
->need_dma32
= false;
666 if (rdev
->flags
& RADEON_IS_AGP
)
667 rdev
->need_dma32
= true;
668 if (rdev
->flags
& RADEON_IS_PCI
)
669 rdev
->need_dma32
= true;
671 dma_bits
= rdev
->need_dma32
? 32 : 40;
672 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
674 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
677 /* Registers mapping */
678 /* TODO: block userspace mapping of io register */
679 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 2);
680 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 2);
681 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
682 if (rdev
->rmmio
== NULL
) {
685 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
686 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
688 /* io port mapping */
689 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
690 if (pci_resource_flags(rdev
->pdev
, i
) & IORESOURCE_IO
) {
691 rdev
->rio_mem_size
= pci_resource_len(rdev
->pdev
, i
);
692 rdev
->rio_mem
= pci_iomap(rdev
->pdev
, i
, rdev
->rio_mem_size
);
696 if (rdev
->rio_mem
== NULL
)
697 DRM_ERROR("Unable to find PCI I/O BAR\n");
699 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
700 /* this will fail for cards that aren't VGA class devices, just
702 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
703 vga_switcheroo_register_client(rdev
->pdev
,
704 radeon_switcheroo_set_state
,
705 radeon_switcheroo_can_switch
);
707 r
= radeon_init(rdev
);
711 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
712 /* Acceleration not working on AGP card try again
713 * with fallback to PCI or PCIE GART
715 radeon_asic_reset(rdev
);
717 radeon_agp_disable(rdev
);
718 r
= radeon_init(rdev
);
722 if (radeon_testing
) {
723 radeon_test_moves(rdev
);
725 if (radeon_benchmarking
) {
726 radeon_benchmark(rdev
);
731 void radeon_device_fini(struct radeon_device
*rdev
)
733 DRM_INFO("radeon: finishing device.\n");
734 rdev
->shutdown
= true;
735 /* evict vram memory */
736 radeon_bo_evict_vram(rdev
);
738 destroy_workqueue(rdev
->wq
);
739 vga_switcheroo_unregister_client(rdev
->pdev
);
740 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
742 pci_iounmap(rdev
->pdev
, rdev
->rio_mem
);
743 rdev
->rio_mem
= NULL
;
744 iounmap(rdev
->rmmio
);
752 int radeon_suspend_kms(struct drm_device
*dev
, pm_message_t state
)
754 struct radeon_device
*rdev
;
755 struct drm_crtc
*crtc
;
756 struct drm_connector
*connector
;
759 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
762 if (state
.event
== PM_EVENT_PRETHAW
) {
765 rdev
= dev
->dev_private
;
767 if (rdev
->powered_down
)
770 /* turn off display hw */
771 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
772 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
775 /* unpin the front buffers */
776 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
777 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->fb
);
778 struct radeon_bo
*robj
;
780 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
783 robj
= rfb
->obj
->driver_private
;
784 /* don't unpin kernel fb objects */
785 if (!radeon_fbdev_robj_is_fb(rdev
, robj
)) {
786 r
= radeon_bo_reserve(robj
, false);
788 radeon_bo_unpin(robj
);
789 radeon_bo_unreserve(robj
);
793 /* evict vram memory */
794 radeon_bo_evict_vram(rdev
);
795 /* wait for gpu to finish processing current batch */
796 radeon_fence_wait_last(rdev
);
798 radeon_save_bios_scratch_regs(rdev
);
800 radeon_pm_suspend(rdev
);
801 radeon_suspend(rdev
);
802 radeon_hpd_fini(rdev
);
803 /* evict remaining vram memory */
804 radeon_bo_evict_vram(rdev
);
806 radeon_agp_suspend(rdev
);
808 pci_save_state(dev
->pdev
);
809 if (state
.event
== PM_EVENT_SUSPEND
) {
810 /* Shut down the device */
811 pci_disable_device(dev
->pdev
);
812 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
814 acquire_console_sem();
815 radeon_fbdev_set_suspend(rdev
, 1);
816 release_console_sem();
820 int radeon_resume_kms(struct drm_device
*dev
)
822 struct drm_connector
*connector
;
823 struct radeon_device
*rdev
= dev
->dev_private
;
825 if (rdev
->powered_down
)
828 acquire_console_sem();
829 pci_set_power_state(dev
->pdev
, PCI_D0
);
830 pci_restore_state(dev
->pdev
);
831 if (pci_enable_device(dev
->pdev
)) {
832 release_console_sem();
835 pci_set_master(dev
->pdev
);
836 /* resume AGP if in use */
837 radeon_agp_resume(rdev
);
839 radeon_pm_resume(rdev
);
840 radeon_restore_bios_scratch_regs(rdev
);
842 /* turn on display hw */
843 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
844 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
847 radeon_fbdev_set_suspend(rdev
, 0);
848 release_console_sem();
850 /* reset hpd state */
851 radeon_hpd_init(rdev
);
852 /* blat the mode back in */
853 drm_helper_resume_force_mode(dev
);
857 int radeon_gpu_reset(struct radeon_device
*rdev
)
861 radeon_save_bios_scratch_regs(rdev
);
862 radeon_suspend(rdev
);
864 r
= radeon_asic_reset(rdev
);
866 dev_info(rdev
->dev
, "GPU reset succeed\n");
868 radeon_restore_bios_scratch_regs(rdev
);
869 drm_helper_resume_force_mode(rdev
->ddev
);
872 /* bad news, how to tell it to userspace ? */
873 dev_info(rdev
->dev
, "GPU reset failed\n");
881 struct radeon_debugfs
{
882 struct drm_info_list
*files
;
885 static struct radeon_debugfs _radeon_debugfs
[RADEON_DEBUGFS_MAX_NUM_FILES
];
886 static unsigned _radeon_debugfs_count
= 0;
888 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
889 struct drm_info_list
*files
,
894 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
895 if (_radeon_debugfs
[i
].files
== files
) {
896 /* Already registered */
900 if ((_radeon_debugfs_count
+ nfiles
) > RADEON_DEBUGFS_MAX_NUM_FILES
) {
901 DRM_ERROR("Reached maximum number of debugfs files.\n");
902 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
905 _radeon_debugfs
[_radeon_debugfs_count
].files
= files
;
906 _radeon_debugfs
[_radeon_debugfs_count
].num_files
= nfiles
;
907 _radeon_debugfs_count
++;
908 #if defined(CONFIG_DEBUG_FS)
909 drm_debugfs_create_files(files
, nfiles
,
910 rdev
->ddev
->control
->debugfs_root
,
911 rdev
->ddev
->control
);
912 drm_debugfs_create_files(files
, nfiles
,
913 rdev
->ddev
->primary
->debugfs_root
,
914 rdev
->ddev
->primary
);
919 #if defined(CONFIG_DEBUG_FS)
920 int radeon_debugfs_init(struct drm_minor
*minor
)
925 void radeon_debugfs_cleanup(struct drm_minor
*minor
)
929 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
930 drm_debugfs_remove_files(_radeon_debugfs
[i
].files
,
931 _radeon_debugfs
[i
].num_files
, minor
);