2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
31 #include <asm/div64.h>
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_plane_helper.h>
36 #include <drm/drm_edid.h>
38 #include <linux/gcd.h>
40 static void avivo_crtc_load_lut(struct drm_crtc
*crtc
)
42 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
43 struct drm_device
*dev
= crtc
->dev
;
44 struct radeon_device
*rdev
= dev
->dev_private
;
47 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
48 WREG32(AVIVO_DC_LUTA_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
58 WREG32(AVIVO_DC_LUT_RW_SELECT
, radeon_crtc
->crtc_id
);
59 WREG32(AVIVO_DC_LUT_RW_MODE
, 0);
60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK
, 0x0000003f);
62 WREG8(AVIVO_DC_LUT_RW_INDEX
, 0);
63 for (i
= 0; i
< 256; i
++) {
64 WREG32(AVIVO_DC_LUT_30_COLOR
,
65 (radeon_crtc
->lut_r
[i
] << 20) |
66 (radeon_crtc
->lut_g
[i
] << 10) |
67 (radeon_crtc
->lut_b
[i
] << 0));
70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
71 WREG32_P(AVIVO_D1GRPH_LUT_SEL
+ radeon_crtc
->crtc_offset
, radeon_crtc
->crtc_id
, ~1);
74 static void dce4_crtc_load_lut(struct drm_crtc
*crtc
)
76 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
77 struct drm_device
*dev
= crtc
->dev
;
78 struct radeon_device
*rdev
= dev
->dev_private
;
81 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
82 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
92 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
95 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
96 for (i
= 0; i
< 256; i
++) {
97 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
98 (radeon_crtc
->lut_r
[i
] << 20) |
99 (radeon_crtc
->lut_g
[i
] << 10) |
100 (radeon_crtc
->lut_b
[i
] << 0));
104 static void dce5_crtc_load_lut(struct drm_crtc
*crtc
)
106 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
107 struct drm_device
*dev
= crtc
->dev
;
108 struct radeon_device
*rdev
= dev
->dev_private
;
111 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
113 WREG32(NI_INPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
114 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS
) |
115 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS
)));
116 WREG32(NI_PRESCALE_GRPH_CONTROL
+ radeon_crtc
->crtc_offset
,
117 NI_GRPH_PRESCALE_BYPASS
);
118 WREG32(NI_PRESCALE_OVL_CONTROL
+ radeon_crtc
->crtc_offset
,
119 NI_OVL_PRESCALE_BYPASS
);
120 WREG32(NI_INPUT_GAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
121 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
) |
122 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
)));
124 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
134 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
135 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
137 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
138 for (i
= 0; i
< 256; i
++) {
139 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
140 (radeon_crtc
->lut_r
[i
] << 20) |
141 (radeon_crtc
->lut_g
[i
] << 10) |
142 (radeon_crtc
->lut_b
[i
] << 0));
145 WREG32(NI_DEGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
146 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
147 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
148 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
149 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
)));
150 WREG32(NI_GAMUT_REMAP_CONTROL
+ radeon_crtc
->crtc_offset
,
151 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
) |
152 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
)));
153 WREG32(NI_REGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
154 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS
) |
155 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS
)));
156 WREG32(NI_OUTPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
157 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS
) |
158 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS
)));
159 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
160 WREG32(0x6940 + radeon_crtc
->crtc_offset
, 0);
161 if (ASIC_IS_DCE8(rdev
)) {
162 /* XXX this only needs to be programmed once per crtc at startup,
163 * not sure where the best place for it is
165 WREG32(CIK_ALPHA_CONTROL
+ radeon_crtc
->crtc_offset
,
166 CIK_CURSOR_ALPHA_BLND_ENA
);
170 static void legacy_crtc_load_lut(struct drm_crtc
*crtc
)
172 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
173 struct drm_device
*dev
= crtc
->dev
;
174 struct radeon_device
*rdev
= dev
->dev_private
;
178 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
179 if (radeon_crtc
->crtc_id
== 0)
180 dac2_cntl
&= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL
;
182 dac2_cntl
|= RADEON_DAC2_PALETTE_ACC_CTL
;
183 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
185 WREG8(RADEON_PALETTE_INDEX
, 0);
186 for (i
= 0; i
< 256; i
++) {
187 WREG32(RADEON_PALETTE_30_DATA
,
188 (radeon_crtc
->lut_r
[i
] << 20) |
189 (radeon_crtc
->lut_g
[i
] << 10) |
190 (radeon_crtc
->lut_b
[i
] << 0));
194 void radeon_crtc_load_lut(struct drm_crtc
*crtc
)
196 struct drm_device
*dev
= crtc
->dev
;
197 struct radeon_device
*rdev
= dev
->dev_private
;
202 if (ASIC_IS_DCE5(rdev
))
203 dce5_crtc_load_lut(crtc
);
204 else if (ASIC_IS_DCE4(rdev
))
205 dce4_crtc_load_lut(crtc
);
206 else if (ASIC_IS_AVIVO(rdev
))
207 avivo_crtc_load_lut(crtc
);
209 legacy_crtc_load_lut(crtc
);
212 /** Sets the color ramps on behalf of fbcon */
213 void radeon_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
216 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
218 radeon_crtc
->lut_r
[regno
] = red
>> 6;
219 radeon_crtc
->lut_g
[regno
] = green
>> 6;
220 radeon_crtc
->lut_b
[regno
] = blue
>> 6;
223 /** Gets the color ramps on behalf of fbcon */
224 void radeon_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
225 u16
*blue
, int regno
)
227 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
229 *red
= radeon_crtc
->lut_r
[regno
] << 6;
230 *green
= radeon_crtc
->lut_g
[regno
] << 6;
231 *blue
= radeon_crtc
->lut_b
[regno
] << 6;
234 static void radeon_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
235 u16
*blue
, uint32_t start
, uint32_t size
)
237 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
238 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
240 /* userspace palettes are always correct as is */
241 for (i
= start
; i
< end
; i
++) {
242 radeon_crtc
->lut_r
[i
] = red
[i
] >> 6;
243 radeon_crtc
->lut_g
[i
] = green
[i
] >> 6;
244 radeon_crtc
->lut_b
[i
] = blue
[i
] >> 6;
246 radeon_crtc_load_lut(crtc
);
249 static void radeon_crtc_destroy(struct drm_crtc
*crtc
)
251 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
253 drm_crtc_cleanup(crtc
);
254 destroy_workqueue(radeon_crtc
->flip_queue
);
259 * radeon_unpin_work_func - unpin old buffer object
261 * @__work - kernel work item
263 * Unpin the old frame buffer object outside of the interrupt handler
265 static void radeon_unpin_work_func(struct work_struct
*__work
)
267 struct radeon_flip_work
*work
=
268 container_of(__work
, struct radeon_flip_work
, unpin_work
);
271 /* unpin of the old buffer */
272 r
= radeon_bo_reserve(work
->old_rbo
, false);
273 if (likely(r
== 0)) {
274 r
= radeon_bo_unpin(work
->old_rbo
);
275 if (unlikely(r
!= 0)) {
276 DRM_ERROR("failed to unpin buffer after flip\n");
278 radeon_bo_unreserve(work
->old_rbo
);
280 DRM_ERROR("failed to reserve buffer after flip\n");
282 drm_gem_object_unreference_unlocked(&work
->old_rbo
->gem_base
);
286 void radeon_crtc_handle_vblank(struct radeon_device
*rdev
, int crtc_id
)
288 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
293 /* can happen during initialization */
294 if (radeon_crtc
== NULL
)
297 /* Skip the pageflip completion check below (based on polling) on
298 * asics which reliably support hw pageflip completion irqs. pflip
299 * irqs are a reliable and race-free method of handling pageflip
300 * completion detection. A use_pflipirq module parameter < 2 allows
301 * to override this in case of asics with faulty pflip irqs.
302 * A module parameter of 0 would only use this polling based path,
303 * a parameter of 1 would use pflip irq only as a backup to this
304 * path, as in Linux 3.16.
306 if ((radeon_use_pflipirq
== 2) && ASIC_IS_DCE4(rdev
))
309 spin_lock_irqsave(&rdev
->ddev
->event_lock
, flags
);
310 if (radeon_crtc
->flip_status
!= RADEON_FLIP_SUBMITTED
) {
311 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
312 "RADEON_FLIP_SUBMITTED(%d)\n",
313 radeon_crtc
->flip_status
,
314 RADEON_FLIP_SUBMITTED
);
315 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
319 update_pending
= radeon_page_flip_pending(rdev
, crtc_id
);
321 /* Has the pageflip already completed in crtc, or is it certain
322 * to complete in this vblank?
324 if (update_pending
&&
325 (DRM_SCANOUTPOS_VALID
& radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc_id
, 0,
326 &vpos
, &hpos
, NULL
, NULL
)) &&
327 ((vpos
>= (99 * rdev
->mode_info
.crtcs
[crtc_id
]->base
.hwmode
.crtc_vdisplay
)/100) ||
328 (vpos
< 0 && !ASIC_IS_AVIVO(rdev
)))) {
329 /* crtc didn't flip in this target vblank interval,
330 * but flip is pending in crtc. Based on the current
331 * scanout position we know that the current frame is
332 * (nearly) complete and the flip will (likely)
333 * complete before the start of the next frame.
337 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
339 radeon_crtc_handle_flip(rdev
, crtc_id
);
343 * radeon_crtc_handle_flip - page flip completed
345 * @rdev: radeon device pointer
346 * @crtc_id: crtc number this event is for
348 * Called when we are sure that a page flip for this crtc is completed.
350 void radeon_crtc_handle_flip(struct radeon_device
*rdev
, int crtc_id
)
352 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
353 struct radeon_flip_work
*work
;
356 /* this can happen at init */
357 if (radeon_crtc
== NULL
)
360 spin_lock_irqsave(&rdev
->ddev
->event_lock
, flags
);
361 work
= radeon_crtc
->flip_work
;
362 if (radeon_crtc
->flip_status
!= RADEON_FLIP_SUBMITTED
) {
363 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
364 "RADEON_FLIP_SUBMITTED(%d)\n",
365 radeon_crtc
->flip_status
,
366 RADEON_FLIP_SUBMITTED
);
367 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
371 /* Pageflip completed. Clean up. */
372 radeon_crtc
->flip_status
= RADEON_FLIP_NONE
;
373 radeon_crtc
->flip_work
= NULL
;
375 /* wakeup userspace */
377 drm_send_vblank_event(rdev
->ddev
, crtc_id
, work
->event
);
379 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
381 drm_vblank_put(rdev
->ddev
, radeon_crtc
->crtc_id
);
382 radeon_irq_kms_pflip_irq_put(rdev
, work
->crtc_id
);
383 queue_work(radeon_crtc
->flip_queue
, &work
->unpin_work
);
387 * radeon_flip_work_func - page flip framebuffer
389 * @work - kernel work item
391 * Wait for the buffer object to become idle and do the actual page flip
393 static void radeon_flip_work_func(struct work_struct
*__work
)
395 struct radeon_flip_work
*work
=
396 container_of(__work
, struct radeon_flip_work
, flip_work
);
397 struct radeon_device
*rdev
= work
->rdev
;
398 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[work
->crtc_id
];
400 struct drm_crtc
*crtc
= &radeon_crtc
->base
;
404 down_read(&rdev
->exclusive_lock
);
406 struct radeon_fence
*fence
;
408 fence
= to_radeon_fence(work
->fence
);
409 if (fence
&& fence
->rdev
== rdev
) {
410 r
= radeon_fence_wait(fence
, false);
412 up_read(&rdev
->exclusive_lock
);
414 r
= radeon_gpu_reset(rdev
);
415 } while (r
== -EAGAIN
);
416 down_read(&rdev
->exclusive_lock
);
419 r
= fence_wait(work
->fence
, false);
422 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r
);
424 /* We continue with the page flip even if we failed to wait on
425 * the fence, otherwise the DRM core and userspace will be
426 * confused about which BO the CRTC is scanning out
429 fence_put(work
->fence
);
433 /* We borrow the event spin lock for protecting flip_status */
434 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
436 /* set the proper interrupt */
437 radeon_irq_kms_pflip_irq_get(rdev
, radeon_crtc
->crtc_id
);
439 /* do the flip (mmio) */
440 radeon_page_flip(rdev
, radeon_crtc
->crtc_id
, work
->base
);
442 radeon_crtc
->flip_status
= RADEON_FLIP_SUBMITTED
;
443 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
444 up_read(&rdev
->exclusive_lock
);
447 static int radeon_crtc_page_flip(struct drm_crtc
*crtc
,
448 struct drm_framebuffer
*fb
,
449 struct drm_pending_vblank_event
*event
,
450 uint32_t page_flip_flags
)
452 struct drm_device
*dev
= crtc
->dev
;
453 struct radeon_device
*rdev
= dev
->dev_private
;
454 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
455 struct radeon_framebuffer
*old_radeon_fb
;
456 struct radeon_framebuffer
*new_radeon_fb
;
457 struct drm_gem_object
*obj
;
458 struct radeon_flip_work
*work
;
459 struct radeon_bo
*new_rbo
;
460 uint32_t tiling_flags
, pitch_pixels
;
465 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
469 INIT_WORK(&work
->flip_work
, radeon_flip_work_func
);
470 INIT_WORK(&work
->unpin_work
, radeon_unpin_work_func
);
473 work
->crtc_id
= radeon_crtc
->crtc_id
;
476 /* schedule unpin of the old buffer */
477 old_radeon_fb
= to_radeon_framebuffer(crtc
->primary
->fb
);
478 obj
= old_radeon_fb
->obj
;
480 /* take a reference to the old object */
481 drm_gem_object_reference(obj
);
482 work
->old_rbo
= gem_to_radeon_bo(obj
);
484 new_radeon_fb
= to_radeon_framebuffer(fb
);
485 obj
= new_radeon_fb
->obj
;
486 new_rbo
= gem_to_radeon_bo(obj
);
488 /* pin the new buffer */
489 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
490 work
->old_rbo
, new_rbo
);
492 r
= radeon_bo_reserve(new_rbo
, false);
493 if (unlikely(r
!= 0)) {
494 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
497 /* Only 27 bit offset for legacy CRTC */
498 r
= radeon_bo_pin_restricted(new_rbo
, RADEON_GEM_DOMAIN_VRAM
,
499 ASIC_IS_AVIVO(rdev
) ? 0 : 1 << 27, &base
);
500 if (unlikely(r
!= 0)) {
501 radeon_bo_unreserve(new_rbo
);
503 DRM_ERROR("failed to pin new rbo buffer before flip\n");
506 work
->fence
= fence_get(reservation_object_get_excl(new_rbo
->tbo
.resv
));
507 radeon_bo_get_tiling_flags(new_rbo
, &tiling_flags
, NULL
);
508 radeon_bo_unreserve(new_rbo
);
510 if (!ASIC_IS_AVIVO(rdev
)) {
511 /* crtc offset is from display base addr not FB location */
512 base
-= radeon_crtc
->legacy_display_base_addr
;
513 pitch_pixels
= fb
->pitches
[0] / (fb
->bits_per_pixel
/ 8);
515 if (tiling_flags
& RADEON_TILING_MACRO
) {
516 if (ASIC_IS_R300(rdev
)) {
519 int byteshift
= fb
->bits_per_pixel
>> 4;
520 int tile_addr
= (((crtc
->y
>> 3) * pitch_pixels
+ crtc
->x
) >> (8 - byteshift
)) << 11;
521 base
+= tile_addr
+ ((crtc
->x
<< byteshift
) % 256) + ((crtc
->y
% 8) << 8);
524 int offset
= crtc
->y
* pitch_pixels
+ crtc
->x
;
525 switch (fb
->bits_per_pixel
) {
547 r
= drm_vblank_get(crtc
->dev
, radeon_crtc
->crtc_id
);
549 DRM_ERROR("failed to get vblank before flip\n");
553 /* We borrow the event spin lock for protecting flip_work */
554 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
556 if (radeon_crtc
->flip_status
!= RADEON_FLIP_NONE
) {
557 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
558 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
562 radeon_crtc
->flip_status
= RADEON_FLIP_PENDING
;
563 radeon_crtc
->flip_work
= work
;
566 crtc
->primary
->fb
= fb
;
568 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
570 queue_work(radeon_crtc
->flip_queue
, &work
->flip_work
);
574 drm_vblank_put(crtc
->dev
, radeon_crtc
->crtc_id
);
577 if (unlikely(radeon_bo_reserve(new_rbo
, false) != 0)) {
578 DRM_ERROR("failed to reserve new rbo in error path\n");
581 if (unlikely(radeon_bo_unpin(new_rbo
) != 0)) {
582 DRM_ERROR("failed to unpin new rbo in error path\n");
584 radeon_bo_unreserve(new_rbo
);
587 drm_gem_object_unreference_unlocked(&work
->old_rbo
->gem_base
);
588 fence_put(work
->fence
);
594 radeon_crtc_set_config(struct drm_mode_set
*set
)
596 struct drm_device
*dev
;
597 struct radeon_device
*rdev
;
598 struct drm_crtc
*crtc
;
602 if (!set
|| !set
->crtc
)
605 dev
= set
->crtc
->dev
;
607 ret
= pm_runtime_get_sync(dev
->dev
);
611 ret
= drm_crtc_helper_set_config(set
);
613 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
617 pm_runtime_mark_last_busy(dev
->dev
);
619 rdev
= dev
->dev_private
;
620 /* if we have active crtcs and we don't have a power ref,
621 take the current one */
622 if (active
&& !rdev
->have_disp_power_ref
) {
623 rdev
->have_disp_power_ref
= true;
626 /* if we have no active crtcs, then drop the power ref
628 if (!active
&& rdev
->have_disp_power_ref
) {
629 pm_runtime_put_autosuspend(dev
->dev
);
630 rdev
->have_disp_power_ref
= false;
633 /* drop the power reference we got coming in here */
634 pm_runtime_put_autosuspend(dev
->dev
);
637 static const struct drm_crtc_funcs radeon_crtc_funcs
= {
638 .cursor_set2
= radeon_crtc_cursor_set2
,
639 .cursor_move
= radeon_crtc_cursor_move
,
640 .gamma_set
= radeon_crtc_gamma_set
,
641 .set_config
= radeon_crtc_set_config
,
642 .destroy
= radeon_crtc_destroy
,
643 .page_flip
= radeon_crtc_page_flip
,
646 static void radeon_crtc_init(struct drm_device
*dev
, int index
)
648 struct radeon_device
*rdev
= dev
->dev_private
;
649 struct radeon_crtc
*radeon_crtc
;
652 radeon_crtc
= kzalloc(sizeof(struct radeon_crtc
) + (RADEONFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
653 if (radeon_crtc
== NULL
)
656 drm_crtc_init(dev
, &radeon_crtc
->base
, &radeon_crtc_funcs
);
658 drm_mode_crtc_set_gamma_size(&radeon_crtc
->base
, 256);
659 radeon_crtc
->crtc_id
= index
;
660 radeon_crtc
->flip_queue
= create_singlethread_workqueue("radeon-crtc");
661 rdev
->mode_info
.crtcs
[index
] = radeon_crtc
;
663 if (rdev
->family
>= CHIP_BONAIRE
) {
664 radeon_crtc
->max_cursor_width
= CIK_CURSOR_WIDTH
;
665 radeon_crtc
->max_cursor_height
= CIK_CURSOR_HEIGHT
;
667 radeon_crtc
->max_cursor_width
= CURSOR_WIDTH
;
668 radeon_crtc
->max_cursor_height
= CURSOR_HEIGHT
;
670 dev
->mode_config
.cursor_width
= radeon_crtc
->max_cursor_width
;
671 dev
->mode_config
.cursor_height
= radeon_crtc
->max_cursor_height
;
674 radeon_crtc
->mode_set
.crtc
= &radeon_crtc
->base
;
675 radeon_crtc
->mode_set
.connectors
= (struct drm_connector
**)(radeon_crtc
+ 1);
676 radeon_crtc
->mode_set
.num_connectors
= 0;
679 for (i
= 0; i
< 256; i
++) {
680 radeon_crtc
->lut_r
[i
] = i
<< 2;
681 radeon_crtc
->lut_g
[i
] = i
<< 2;
682 radeon_crtc
->lut_b
[i
] = i
<< 2;
685 if (rdev
->is_atom_bios
&& (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
))
686 radeon_atombios_init_crtc(dev
, radeon_crtc
);
688 radeon_legacy_init_crtc(dev
, radeon_crtc
);
691 static const char *encoder_names
[38] = {
711 "INTERNAL_KLDSCP_TMDS1",
712 "INTERNAL_KLDSCP_DVO1",
713 "INTERNAL_KLDSCP_DAC1",
714 "INTERNAL_KLDSCP_DAC2",
723 "INTERNAL_KLDSCP_LVTMA",
732 static const char *hpd_names
[6] = {
741 static void radeon_print_display_setup(struct drm_device
*dev
)
743 struct drm_connector
*connector
;
744 struct radeon_connector
*radeon_connector
;
745 struct drm_encoder
*encoder
;
746 struct radeon_encoder
*radeon_encoder
;
750 DRM_INFO("Radeon Display Connectors\n");
751 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
752 radeon_connector
= to_radeon_connector(connector
);
753 DRM_INFO("Connector %d:\n", i
);
754 DRM_INFO(" %s\n", connector
->name
);
755 if (radeon_connector
->hpd
.hpd
!= RADEON_HPD_NONE
)
756 DRM_INFO(" %s\n", hpd_names
[radeon_connector
->hpd
.hpd
]);
757 if (radeon_connector
->ddc_bus
) {
758 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
759 radeon_connector
->ddc_bus
->rec
.mask_clk_reg
,
760 radeon_connector
->ddc_bus
->rec
.mask_data_reg
,
761 radeon_connector
->ddc_bus
->rec
.a_clk_reg
,
762 radeon_connector
->ddc_bus
->rec
.a_data_reg
,
763 radeon_connector
->ddc_bus
->rec
.en_clk_reg
,
764 radeon_connector
->ddc_bus
->rec
.en_data_reg
,
765 radeon_connector
->ddc_bus
->rec
.y_clk_reg
,
766 radeon_connector
->ddc_bus
->rec
.y_data_reg
);
767 if (radeon_connector
->router
.ddc_valid
)
768 DRM_INFO(" DDC Router 0x%x/0x%x\n",
769 radeon_connector
->router
.ddc_mux_control_pin
,
770 radeon_connector
->router
.ddc_mux_state
);
771 if (radeon_connector
->router
.cd_valid
)
772 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
773 radeon_connector
->router
.cd_mux_control_pin
,
774 radeon_connector
->router
.cd_mux_state
);
776 if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
||
777 connector
->connector_type
== DRM_MODE_CONNECTOR_DVII
||
778 connector
->connector_type
== DRM_MODE_CONNECTOR_DVID
||
779 connector
->connector_type
== DRM_MODE_CONNECTOR_DVIA
||
780 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIA
||
781 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIB
)
782 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
784 DRM_INFO(" Encoders:\n");
785 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
786 radeon_encoder
= to_radeon_encoder(encoder
);
787 devices
= radeon_encoder
->devices
& radeon_connector
->devices
;
789 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
790 DRM_INFO(" CRT1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
791 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
792 DRM_INFO(" CRT2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
793 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
794 DRM_INFO(" LCD1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
795 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
796 DRM_INFO(" DFP1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
797 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
798 DRM_INFO(" DFP2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
799 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
800 DRM_INFO(" DFP3: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
801 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
802 DRM_INFO(" DFP4: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
803 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
804 DRM_INFO(" DFP5: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
805 if (devices
& ATOM_DEVICE_DFP6_SUPPORT
)
806 DRM_INFO(" DFP6: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
807 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
808 DRM_INFO(" TV1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
809 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
810 DRM_INFO(" CV: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
817 static bool radeon_setup_enc_conn(struct drm_device
*dev
)
819 struct radeon_device
*rdev
= dev
->dev_private
;
823 if (rdev
->is_atom_bios
) {
824 ret
= radeon_get_atom_connector_info_from_supported_devices_table(dev
);
826 ret
= radeon_get_atom_connector_info_from_object_table(dev
);
828 ret
= radeon_get_legacy_connector_info_from_bios(dev
);
830 ret
= radeon_get_legacy_connector_info_from_table(dev
);
833 if (!ASIC_IS_AVIVO(rdev
))
834 ret
= radeon_get_legacy_connector_info_from_table(dev
);
837 radeon_setup_encoder_clones(dev
);
838 radeon_print_display_setup(dev
);
847 * avivo_reduce_ratio - fractional number reduction
851 * @nom_min: minimum value for nominator
852 * @den_min: minimum value for denominator
854 * Find the greatest common divisor and apply it on both nominator and
855 * denominator, but make nominator and denominator are at least as large
856 * as their minimum values.
858 static void avivo_reduce_ratio(unsigned *nom
, unsigned *den
,
859 unsigned nom_min
, unsigned den_min
)
863 /* reduce the numbers to a simpler ratio */
864 tmp
= gcd(*nom
, *den
);
868 /* make sure nominator is large enough */
869 if (*nom
< nom_min
) {
870 tmp
= DIV_ROUND_UP(nom_min
, *nom
);
875 /* make sure the denominator is large enough */
876 if (*den
< den_min
) {
877 tmp
= DIV_ROUND_UP(den_min
, *den
);
884 * avivo_get_fb_ref_div - feedback and ref divider calculation
888 * @post_div: post divider
889 * @fb_div_max: feedback divider maximum
890 * @ref_div_max: reference divider maximum
891 * @fb_div: resulting feedback divider
892 * @ref_div: resulting reference divider
894 * Calculate feedback and reference divider for a given post divider. Makes
895 * sure we stay within the limits.
897 static void avivo_get_fb_ref_div(unsigned nom
, unsigned den
, unsigned post_div
,
898 unsigned fb_div_max
, unsigned ref_div_max
,
899 unsigned *fb_div
, unsigned *ref_div
)
901 /* limit reference * post divider to a maximum */
902 ref_div_max
= max(min(100 / post_div
, ref_div_max
), 1u);
904 /* get matching reference and feedback divider */
905 *ref_div
= min(max(DIV_ROUND_CLOSEST(den
, post_div
), 1u), ref_div_max
);
906 *fb_div
= DIV_ROUND_CLOSEST(nom
* *ref_div
* post_div
, den
);
908 /* limit fb divider to its maximum */
909 if (*fb_div
> fb_div_max
) {
910 *ref_div
= DIV_ROUND_CLOSEST(*ref_div
* fb_div_max
, *fb_div
);
911 *fb_div
= fb_div_max
;
916 * radeon_compute_pll_avivo - compute PLL paramaters
918 * @pll: information about the PLL
919 * @dot_clock_p: resulting pixel clock
920 * fb_div_p: resulting feedback divider
921 * frac_fb_div_p: fractional part of the feedback divider
922 * ref_div_p: resulting reference divider
923 * post_div_p: resulting reference divider
925 * Try to calculate the PLL parameters to generate the given frequency:
926 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
928 void radeon_compute_pll_avivo(struct radeon_pll
*pll
,
936 unsigned target_clock
= pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
?
939 unsigned fb_div_min
, fb_div_max
, fb_div
;
940 unsigned post_div_min
, post_div_max
, post_div
;
941 unsigned ref_div_min
, ref_div_max
, ref_div
;
942 unsigned post_div_best
, diff_best
;
945 /* determine allowed feedback divider range */
946 fb_div_min
= pll
->min_feedback_div
;
947 fb_div_max
= pll
->max_feedback_div
;
949 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
954 /* determine allowed ref divider range */
955 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
956 ref_div_min
= pll
->reference_div
;
958 ref_div_min
= pll
->min_ref_div
;
960 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
&&
961 pll
->flags
& RADEON_PLL_USE_REF_DIV
)
962 ref_div_max
= pll
->reference_div
;
964 ref_div_max
= pll
->max_ref_div
;
966 /* determine allowed post divider range */
967 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
) {
968 post_div_min
= pll
->post_div
;
969 post_div_max
= pll
->post_div
;
971 unsigned vco_min
, vco_max
;
973 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
974 vco_min
= pll
->lcd_pll_out_min
;
975 vco_max
= pll
->lcd_pll_out_max
;
977 vco_min
= pll
->pll_out_min
;
978 vco_max
= pll
->pll_out_max
;
981 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
986 post_div_min
= vco_min
/ target_clock
;
987 if ((target_clock
* post_div_min
) < vco_min
)
989 if (post_div_min
< pll
->min_post_div
)
990 post_div_min
= pll
->min_post_div
;
992 post_div_max
= vco_max
/ target_clock
;
993 if ((target_clock
* post_div_max
) > vco_max
)
995 if (post_div_max
> pll
->max_post_div
)
996 post_div_max
= pll
->max_post_div
;
999 /* represent the searched ratio as fractional number */
1001 den
= pll
->reference_freq
;
1003 /* reduce the numbers to a simpler ratio */
1004 avivo_reduce_ratio(&nom
, &den
, fb_div_min
, post_div_min
);
1006 /* now search for a post divider */
1007 if (pll
->flags
& RADEON_PLL_PREFER_MINM_OVER_MAXP
)
1008 post_div_best
= post_div_min
;
1010 post_div_best
= post_div_max
;
1013 for (post_div
= post_div_min
; post_div
<= post_div_max
; ++post_div
) {
1015 avivo_get_fb_ref_div(nom
, den
, post_div
, fb_div_max
,
1016 ref_div_max
, &fb_div
, &ref_div
);
1017 diff
= abs(target_clock
- (pll
->reference_freq
* fb_div
) /
1018 (ref_div
* post_div
));
1020 if (diff
< diff_best
|| (diff
== diff_best
&&
1021 !(pll
->flags
& RADEON_PLL_PREFER_MINM_OVER_MAXP
))) {
1023 post_div_best
= post_div
;
1027 post_div
= post_div_best
;
1029 /* get the feedback and reference divider for the optimal value */
1030 avivo_get_fb_ref_div(nom
, den
, post_div
, fb_div_max
, ref_div_max
,
1033 /* reduce the numbers to a simpler ratio once more */
1034 /* this also makes sure that the reference divider is large enough */
1035 avivo_reduce_ratio(&fb_div
, &ref_div
, fb_div_min
, ref_div_min
);
1037 /* avoid high jitter with small fractional dividers */
1038 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
&& (fb_div
% 10)) {
1039 fb_div_min
= max(fb_div_min
, (9 - (fb_div
% 10)) * 20 + 50);
1040 if (fb_div
< fb_div_min
) {
1041 unsigned tmp
= DIV_ROUND_UP(fb_div_min
, fb_div
);
1047 /* and finally save the result */
1048 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
1049 *fb_div_p
= fb_div
/ 10;
1050 *frac_fb_div_p
= fb_div
% 10;
1056 *dot_clock_p
= ((pll
->reference_freq
* *fb_div_p
* 10) +
1057 (pll
->reference_freq
* *frac_fb_div_p
)) /
1058 (ref_div
* post_div
* 10);
1059 *ref_div_p
= ref_div
;
1060 *post_div_p
= post_div
;
1062 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1063 freq
, *dot_clock_p
* 10, *fb_div_p
, *frac_fb_div_p
,
1068 static inline uint32_t radeon_div(uint64_t n
, uint32_t d
)
1078 void radeon_compute_pll_legacy(struct radeon_pll
*pll
,
1080 uint32_t *dot_clock_p
,
1082 uint32_t *frac_fb_div_p
,
1083 uint32_t *ref_div_p
,
1084 uint32_t *post_div_p
)
1086 uint32_t min_ref_div
= pll
->min_ref_div
;
1087 uint32_t max_ref_div
= pll
->max_ref_div
;
1088 uint32_t min_post_div
= pll
->min_post_div
;
1089 uint32_t max_post_div
= pll
->max_post_div
;
1090 uint32_t min_fractional_feed_div
= 0;
1091 uint32_t max_fractional_feed_div
= 0;
1092 uint32_t best_vco
= pll
->best_vco
;
1093 uint32_t best_post_div
= 1;
1094 uint32_t best_ref_div
= 1;
1095 uint32_t best_feedback_div
= 1;
1096 uint32_t best_frac_feedback_div
= 0;
1097 uint32_t best_freq
= -1;
1098 uint32_t best_error
= 0xffffffff;
1099 uint32_t best_vco_diff
= 1;
1101 u32 pll_out_min
, pll_out_max
;
1103 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq
, pll
->min_ref_div
, pll
->max_ref_div
);
1106 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
1107 pll_out_min
= pll
->lcd_pll_out_min
;
1108 pll_out_max
= pll
->lcd_pll_out_max
;
1110 pll_out_min
= pll
->pll_out_min
;
1111 pll_out_max
= pll
->pll_out_max
;
1114 if (pll_out_min
> 64800)
1115 pll_out_min
= 64800;
1117 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
1118 min_ref_div
= max_ref_div
= pll
->reference_div
;
1120 while (min_ref_div
< max_ref_div
-1) {
1121 uint32_t mid
= (min_ref_div
+ max_ref_div
) / 2;
1122 uint32_t pll_in
= pll
->reference_freq
/ mid
;
1123 if (pll_in
< pll
->pll_in_min
)
1125 else if (pll_in
> pll
->pll_in_max
)
1132 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
1133 min_post_div
= max_post_div
= pll
->post_div
;
1135 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
1136 min_fractional_feed_div
= pll
->min_frac_feedback_div
;
1137 max_fractional_feed_div
= pll
->max_frac_feedback_div
;
1140 for (post_div
= max_post_div
; post_div
>= min_post_div
; --post_div
) {
1143 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
1146 /* legacy radeons only have a few post_divs */
1147 if (pll
->flags
& RADEON_PLL_LEGACY
) {
1148 if ((post_div
== 5) ||
1159 for (ref_div
= min_ref_div
; ref_div
<= max_ref_div
; ++ref_div
) {
1160 uint32_t feedback_div
, current_freq
= 0, error
, vco_diff
;
1161 uint32_t pll_in
= pll
->reference_freq
/ ref_div
;
1162 uint32_t min_feed_div
= pll
->min_feedback_div
;
1163 uint32_t max_feed_div
= pll
->max_feedback_div
+ 1;
1165 if (pll_in
< pll
->pll_in_min
|| pll_in
> pll
->pll_in_max
)
1168 while (min_feed_div
< max_feed_div
) {
1170 uint32_t min_frac_feed_div
= min_fractional_feed_div
;
1171 uint32_t max_frac_feed_div
= max_fractional_feed_div
+ 1;
1172 uint32_t frac_feedback_div
;
1175 feedback_div
= (min_feed_div
+ max_feed_div
) / 2;
1177 tmp
= (uint64_t)pll
->reference_freq
* feedback_div
;
1178 vco
= radeon_div(tmp
, ref_div
);
1180 if (vco
< pll_out_min
) {
1181 min_feed_div
= feedback_div
+ 1;
1183 } else if (vco
> pll_out_max
) {
1184 max_feed_div
= feedback_div
;
1188 while (min_frac_feed_div
< max_frac_feed_div
) {
1189 frac_feedback_div
= (min_frac_feed_div
+ max_frac_feed_div
) / 2;
1190 tmp
= (uint64_t)pll
->reference_freq
* 10000 * feedback_div
;
1191 tmp
+= (uint64_t)pll
->reference_freq
* 1000 * frac_feedback_div
;
1192 current_freq
= radeon_div(tmp
, ref_div
* post_div
);
1194 if (pll
->flags
& RADEON_PLL_PREFER_CLOSEST_LOWER
) {
1195 if (freq
< current_freq
)
1198 error
= freq
- current_freq
;
1200 error
= abs(current_freq
- freq
);
1201 vco_diff
= abs(vco
- best_vco
);
1203 if ((best_vco
== 0 && error
< best_error
) ||
1205 ((best_error
> 100 && error
< best_error
- 100) ||
1206 (abs(error
- best_error
) < 100 && vco_diff
< best_vco_diff
)))) {
1207 best_post_div
= post_div
;
1208 best_ref_div
= ref_div
;
1209 best_feedback_div
= feedback_div
;
1210 best_frac_feedback_div
= frac_feedback_div
;
1211 best_freq
= current_freq
;
1213 best_vco_diff
= vco_diff
;
1214 } else if (current_freq
== freq
) {
1215 if (best_freq
== -1) {
1216 best_post_div
= post_div
;
1217 best_ref_div
= ref_div
;
1218 best_feedback_div
= feedback_div
;
1219 best_frac_feedback_div
= frac_feedback_div
;
1220 best_freq
= current_freq
;
1222 best_vco_diff
= vco_diff
;
1223 } else if (((pll
->flags
& RADEON_PLL_PREFER_LOW_REF_DIV
) && (ref_div
< best_ref_div
)) ||
1224 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_REF_DIV
) && (ref_div
> best_ref_div
)) ||
1225 ((pll
->flags
& RADEON_PLL_PREFER_LOW_FB_DIV
) && (feedback_div
< best_feedback_div
)) ||
1226 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_FB_DIV
) && (feedback_div
> best_feedback_div
)) ||
1227 ((pll
->flags
& RADEON_PLL_PREFER_LOW_POST_DIV
) && (post_div
< best_post_div
)) ||
1228 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_POST_DIV
) && (post_div
> best_post_div
))) {
1229 best_post_div
= post_div
;
1230 best_ref_div
= ref_div
;
1231 best_feedback_div
= feedback_div
;
1232 best_frac_feedback_div
= frac_feedback_div
;
1233 best_freq
= current_freq
;
1235 best_vco_diff
= vco_diff
;
1238 if (current_freq
< freq
)
1239 min_frac_feed_div
= frac_feedback_div
+ 1;
1241 max_frac_feed_div
= frac_feedback_div
;
1243 if (current_freq
< freq
)
1244 min_feed_div
= feedback_div
+ 1;
1246 max_feed_div
= feedback_div
;
1251 *dot_clock_p
= best_freq
/ 10000;
1252 *fb_div_p
= best_feedback_div
;
1253 *frac_fb_div_p
= best_frac_feedback_div
;
1254 *ref_div_p
= best_ref_div
;
1255 *post_div_p
= best_post_div
;
1256 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1258 best_freq
/ 1000, best_feedback_div
, best_frac_feedback_div
,
1259 best_ref_div
, best_post_div
);
1263 static void radeon_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
1265 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
1267 if (radeon_fb
->obj
) {
1268 drm_gem_object_unreference_unlocked(radeon_fb
->obj
);
1270 drm_framebuffer_cleanup(fb
);
1274 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
1275 struct drm_file
*file_priv
,
1276 unsigned int *handle
)
1278 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
1280 return drm_gem_handle_create(file_priv
, radeon_fb
->obj
, handle
);
1283 static const struct drm_framebuffer_funcs radeon_fb_funcs
= {
1284 .destroy
= radeon_user_framebuffer_destroy
,
1285 .create_handle
= radeon_user_framebuffer_create_handle
,
1289 radeon_framebuffer_init(struct drm_device
*dev
,
1290 struct radeon_framebuffer
*rfb
,
1291 struct drm_mode_fb_cmd2
*mode_cmd
,
1292 struct drm_gem_object
*obj
)
1296 drm_helper_mode_fill_fb_struct(&rfb
->base
, mode_cmd
);
1297 ret
= drm_framebuffer_init(dev
, &rfb
->base
, &radeon_fb_funcs
);
1305 static struct drm_framebuffer
*
1306 radeon_user_framebuffer_create(struct drm_device
*dev
,
1307 struct drm_file
*file_priv
,
1308 struct drm_mode_fb_cmd2
*mode_cmd
)
1310 struct drm_gem_object
*obj
;
1311 struct radeon_framebuffer
*radeon_fb
;
1314 obj
= drm_gem_object_lookup(dev
, file_priv
, mode_cmd
->handles
[0]);
1316 dev_err(&dev
->pdev
->dev
, "No GEM object associated to handle 0x%08X, "
1317 "can't create framebuffer\n", mode_cmd
->handles
[0]);
1318 return ERR_PTR(-ENOENT
);
1321 radeon_fb
= kzalloc(sizeof(*radeon_fb
), GFP_KERNEL
);
1322 if (radeon_fb
== NULL
) {
1323 drm_gem_object_unreference_unlocked(obj
);
1324 return ERR_PTR(-ENOMEM
);
1327 ret
= radeon_framebuffer_init(dev
, radeon_fb
, mode_cmd
, obj
);
1330 drm_gem_object_unreference_unlocked(obj
);
1331 return ERR_PTR(ret
);
1334 return &radeon_fb
->base
;
1337 static void radeon_output_poll_changed(struct drm_device
*dev
)
1339 struct radeon_device
*rdev
= dev
->dev_private
;
1340 radeon_fb_output_poll_changed(rdev
);
1343 static const struct drm_mode_config_funcs radeon_mode_funcs
= {
1344 .fb_create
= radeon_user_framebuffer_create
,
1345 .output_poll_changed
= radeon_output_poll_changed
1348 static struct drm_prop_enum_list radeon_tmds_pll_enum_list
[] =
1353 static struct drm_prop_enum_list radeon_tv_std_enum_list
[] =
1354 { { TV_STD_NTSC
, "ntsc" },
1355 { TV_STD_PAL
, "pal" },
1356 { TV_STD_PAL_M
, "pal-m" },
1357 { TV_STD_PAL_60
, "pal-60" },
1358 { TV_STD_NTSC_J
, "ntsc-j" },
1359 { TV_STD_SCART_PAL
, "scart-pal" },
1360 { TV_STD_PAL_CN
, "pal-cn" },
1361 { TV_STD_SECAM
, "secam" },
1364 static struct drm_prop_enum_list radeon_underscan_enum_list
[] =
1365 { { UNDERSCAN_OFF
, "off" },
1366 { UNDERSCAN_ON
, "on" },
1367 { UNDERSCAN_AUTO
, "auto" },
1370 static struct drm_prop_enum_list radeon_audio_enum_list
[] =
1371 { { RADEON_AUDIO_DISABLE
, "off" },
1372 { RADEON_AUDIO_ENABLE
, "on" },
1373 { RADEON_AUDIO_AUTO
, "auto" },
1376 /* XXX support different dither options? spatial, temporal, both, etc. */
1377 static struct drm_prop_enum_list radeon_dither_enum_list
[] =
1378 { { RADEON_FMT_DITHER_DISABLE
, "off" },
1379 { RADEON_FMT_DITHER_ENABLE
, "on" },
1382 static int radeon_modeset_create_props(struct radeon_device
*rdev
)
1386 if (rdev
->is_atom_bios
) {
1387 rdev
->mode_info
.coherent_mode_property
=
1388 drm_property_create_range(rdev
->ddev
, 0 , "coherent", 0, 1);
1389 if (!rdev
->mode_info
.coherent_mode_property
)
1393 if (!ASIC_IS_AVIVO(rdev
)) {
1394 sz
= ARRAY_SIZE(radeon_tmds_pll_enum_list
);
1395 rdev
->mode_info
.tmds_pll_property
=
1396 drm_property_create_enum(rdev
->ddev
, 0,
1398 radeon_tmds_pll_enum_list
, sz
);
1401 rdev
->mode_info
.load_detect_property
=
1402 drm_property_create_range(rdev
->ddev
, 0, "load detection", 0, 1);
1403 if (!rdev
->mode_info
.load_detect_property
)
1406 drm_mode_create_scaling_mode_property(rdev
->ddev
);
1408 sz
= ARRAY_SIZE(radeon_tv_std_enum_list
);
1409 rdev
->mode_info
.tv_std_property
=
1410 drm_property_create_enum(rdev
->ddev
, 0,
1412 radeon_tv_std_enum_list
, sz
);
1414 sz
= ARRAY_SIZE(radeon_underscan_enum_list
);
1415 rdev
->mode_info
.underscan_property
=
1416 drm_property_create_enum(rdev
->ddev
, 0,
1418 radeon_underscan_enum_list
, sz
);
1420 rdev
->mode_info
.underscan_hborder_property
=
1421 drm_property_create_range(rdev
->ddev
, 0,
1422 "underscan hborder", 0, 128);
1423 if (!rdev
->mode_info
.underscan_hborder_property
)
1426 rdev
->mode_info
.underscan_vborder_property
=
1427 drm_property_create_range(rdev
->ddev
, 0,
1428 "underscan vborder", 0, 128);
1429 if (!rdev
->mode_info
.underscan_vborder_property
)
1432 sz
= ARRAY_SIZE(radeon_audio_enum_list
);
1433 rdev
->mode_info
.audio_property
=
1434 drm_property_create_enum(rdev
->ddev
, 0,
1436 radeon_audio_enum_list
, sz
);
1438 sz
= ARRAY_SIZE(radeon_dither_enum_list
);
1439 rdev
->mode_info
.dither_property
=
1440 drm_property_create_enum(rdev
->ddev
, 0,
1442 radeon_dither_enum_list
, sz
);
1447 void radeon_update_display_priority(struct radeon_device
*rdev
)
1449 /* adjustment options for the display watermarks */
1450 if ((radeon_disp_priority
== 0) || (radeon_disp_priority
> 2)) {
1451 /* set display priority to high for r3xx, rv515 chips
1452 * this avoids flickering due to underflow to the
1453 * display controllers during heavy acceleration.
1454 * Don't force high on rs4xx igp chips as it seems to
1455 * affect the sound card. See kernel bug 15982.
1457 if ((ASIC_IS_R300(rdev
) || (rdev
->family
== CHIP_RV515
)) &&
1458 !(rdev
->flags
& RADEON_IS_IGP
))
1459 rdev
->disp_priority
= 2;
1461 rdev
->disp_priority
= 0;
1463 rdev
->disp_priority
= radeon_disp_priority
;
1468 * Allocate hdmi structs and determine register offsets
1470 static void radeon_afmt_init(struct radeon_device
*rdev
)
1474 for (i
= 0; i
< RADEON_MAX_AFMT_BLOCKS
; i
++)
1475 rdev
->mode_info
.afmt
[i
] = NULL
;
1477 if (ASIC_IS_NODCE(rdev
)) {
1479 } else if (ASIC_IS_DCE4(rdev
)) {
1480 static uint32_t eg_offsets
[] = {
1481 EVERGREEN_CRTC0_REGISTER_OFFSET
,
1482 EVERGREEN_CRTC1_REGISTER_OFFSET
,
1483 EVERGREEN_CRTC2_REGISTER_OFFSET
,
1484 EVERGREEN_CRTC3_REGISTER_OFFSET
,
1485 EVERGREEN_CRTC4_REGISTER_OFFSET
,
1486 EVERGREEN_CRTC5_REGISTER_OFFSET
,
1491 /* DCE8 has 7 audio blocks tied to DIG encoders */
1492 /* DCE6 has 6 audio blocks tied to DIG encoders */
1493 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1494 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1495 if (ASIC_IS_DCE8(rdev
))
1497 else if (ASIC_IS_DCE6(rdev
))
1499 else if (ASIC_IS_DCE5(rdev
))
1501 else if (ASIC_IS_DCE41(rdev
))
1506 BUG_ON(num_afmt
> ARRAY_SIZE(eg_offsets
));
1507 for (i
= 0; i
< num_afmt
; i
++) {
1508 rdev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1509 if (rdev
->mode_info
.afmt
[i
]) {
1510 rdev
->mode_info
.afmt
[i
]->offset
= eg_offsets
[i
];
1511 rdev
->mode_info
.afmt
[i
]->id
= i
;
1514 } else if (ASIC_IS_DCE3(rdev
)) {
1515 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1516 rdev
->mode_info
.afmt
[0] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1517 if (rdev
->mode_info
.afmt
[0]) {
1518 rdev
->mode_info
.afmt
[0]->offset
= DCE3_HDMI_OFFSET0
;
1519 rdev
->mode_info
.afmt
[0]->id
= 0;
1521 rdev
->mode_info
.afmt
[1] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1522 if (rdev
->mode_info
.afmt
[1]) {
1523 rdev
->mode_info
.afmt
[1]->offset
= DCE3_HDMI_OFFSET1
;
1524 rdev
->mode_info
.afmt
[1]->id
= 1;
1526 } else if (ASIC_IS_DCE2(rdev
)) {
1527 /* DCE2 has at least 1 routable audio block */
1528 rdev
->mode_info
.afmt
[0] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1529 if (rdev
->mode_info
.afmt
[0]) {
1530 rdev
->mode_info
.afmt
[0]->offset
= DCE2_HDMI_OFFSET0
;
1531 rdev
->mode_info
.afmt
[0]->id
= 0;
1533 /* r6xx has 2 routable audio blocks */
1534 if (rdev
->family
>= CHIP_R600
) {
1535 rdev
->mode_info
.afmt
[1] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1536 if (rdev
->mode_info
.afmt
[1]) {
1537 rdev
->mode_info
.afmt
[1]->offset
= DCE2_HDMI_OFFSET1
;
1538 rdev
->mode_info
.afmt
[1]->id
= 1;
1544 static void radeon_afmt_fini(struct radeon_device
*rdev
)
1548 for (i
= 0; i
< RADEON_MAX_AFMT_BLOCKS
; i
++) {
1549 kfree(rdev
->mode_info
.afmt
[i
]);
1550 rdev
->mode_info
.afmt
[i
] = NULL
;
1554 int radeon_modeset_init(struct radeon_device
*rdev
)
1559 drm_mode_config_init(rdev
->ddev
);
1560 rdev
->mode_info
.mode_config_initialized
= true;
1562 rdev
->ddev
->mode_config
.funcs
= &radeon_mode_funcs
;
1564 if (ASIC_IS_DCE5(rdev
)) {
1565 rdev
->ddev
->mode_config
.max_width
= 16384;
1566 rdev
->ddev
->mode_config
.max_height
= 16384;
1567 } else if (ASIC_IS_AVIVO(rdev
)) {
1568 rdev
->ddev
->mode_config
.max_width
= 8192;
1569 rdev
->ddev
->mode_config
.max_height
= 8192;
1571 rdev
->ddev
->mode_config
.max_width
= 4096;
1572 rdev
->ddev
->mode_config
.max_height
= 4096;
1575 rdev
->ddev
->mode_config
.preferred_depth
= 24;
1576 rdev
->ddev
->mode_config
.prefer_shadow
= 1;
1578 rdev
->ddev
->mode_config
.fb_base
= rdev
->mc
.aper_base
;
1580 ret
= radeon_modeset_create_props(rdev
);
1585 /* init i2c buses */
1586 radeon_i2c_init(rdev
);
1588 /* check combios for a valid hardcoded EDID - Sun servers */
1589 if (!rdev
->is_atom_bios
) {
1590 /* check for hardcoded EDID in BIOS */
1591 radeon_combios_check_hardcoded_edid(rdev
);
1594 /* allocate crtcs */
1595 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1596 radeon_crtc_init(rdev
->ddev
, i
);
1599 /* okay we should have all the bios connectors */
1600 ret
= radeon_setup_enc_conn(rdev
->ddev
);
1605 /* init dig PHYs, disp eng pll */
1606 if (rdev
->is_atom_bios
) {
1607 radeon_atom_encoder_init(rdev
);
1608 radeon_atom_disp_eng_pll_init(rdev
);
1611 /* initialize hpd */
1612 radeon_hpd_init(rdev
);
1615 radeon_afmt_init(rdev
);
1617 radeon_fbdev_init(rdev
);
1618 drm_kms_helper_poll_init(rdev
->ddev
);
1620 if (rdev
->pm
.dpm_enabled
) {
1621 /* do dpm late init */
1622 ret
= radeon_pm_late_init(rdev
);
1624 rdev
->pm
.dpm_enabled
= false;
1625 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1627 /* set the dpm state for PX since there won't be
1628 * a modeset to call this.
1630 radeon_pm_compute_clocks(rdev
);
1636 void radeon_modeset_fini(struct radeon_device
*rdev
)
1638 radeon_fbdev_fini(rdev
);
1639 kfree(rdev
->mode_info
.bios_hardcoded_edid
);
1641 if (rdev
->mode_info
.mode_config_initialized
) {
1642 radeon_afmt_fini(rdev
);
1643 drm_kms_helper_poll_fini(rdev
->ddev
);
1644 radeon_hpd_fini(rdev
);
1645 drm_mode_config_cleanup(rdev
->ddev
);
1646 rdev
->mode_info
.mode_config_initialized
= false;
1648 /* free i2c buses */
1649 radeon_i2c_fini(rdev
);
1652 static bool is_hdtv_mode(const struct drm_display_mode
*mode
)
1654 /* try and guess if this is a tv or a monitor */
1655 if ((mode
->vdisplay
== 480 && mode
->hdisplay
== 720) || /* 480p */
1656 (mode
->vdisplay
== 576) || /* 576p */
1657 (mode
->vdisplay
== 720) || /* 720p */
1658 (mode
->vdisplay
== 1080)) /* 1080p */
1664 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
1665 const struct drm_display_mode
*mode
,
1666 struct drm_display_mode
*adjusted_mode
)
1668 struct drm_device
*dev
= crtc
->dev
;
1669 struct radeon_device
*rdev
= dev
->dev_private
;
1670 struct drm_encoder
*encoder
;
1671 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1672 struct radeon_encoder
*radeon_encoder
;
1673 struct drm_connector
*connector
;
1674 struct radeon_connector
*radeon_connector
;
1676 u32 src_v
= 1, dst_v
= 1;
1677 u32 src_h
= 1, dst_h
= 1;
1679 radeon_crtc
->h_border
= 0;
1680 radeon_crtc
->v_border
= 0;
1682 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1683 if (encoder
->crtc
!= crtc
)
1685 radeon_encoder
= to_radeon_encoder(encoder
);
1686 connector
= radeon_get_connector_for_encoder(encoder
);
1687 radeon_connector
= to_radeon_connector(connector
);
1691 if (radeon_encoder
->rmx_type
== RMX_OFF
)
1692 radeon_crtc
->rmx_type
= RMX_OFF
;
1693 else if (mode
->hdisplay
< radeon_encoder
->native_mode
.hdisplay
||
1694 mode
->vdisplay
< radeon_encoder
->native_mode
.vdisplay
)
1695 radeon_crtc
->rmx_type
= radeon_encoder
->rmx_type
;
1697 radeon_crtc
->rmx_type
= RMX_OFF
;
1698 /* copy native mode */
1699 memcpy(&radeon_crtc
->native_mode
,
1700 &radeon_encoder
->native_mode
,
1701 sizeof(struct drm_display_mode
));
1702 src_v
= crtc
->mode
.vdisplay
;
1703 dst_v
= radeon_crtc
->native_mode
.vdisplay
;
1704 src_h
= crtc
->mode
.hdisplay
;
1705 dst_h
= radeon_crtc
->native_mode
.hdisplay
;
1707 /* fix up for overscan on hdmi */
1708 if (ASIC_IS_AVIVO(rdev
) &&
1709 (!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
)) &&
1710 ((radeon_encoder
->underscan_type
== UNDERSCAN_ON
) ||
1711 ((radeon_encoder
->underscan_type
== UNDERSCAN_AUTO
) &&
1712 drm_detect_hdmi_monitor(radeon_connector_edid(connector
)) &&
1713 is_hdtv_mode(mode
)))) {
1714 if (radeon_encoder
->underscan_hborder
!= 0)
1715 radeon_crtc
->h_border
= radeon_encoder
->underscan_hborder
;
1717 radeon_crtc
->h_border
= (mode
->hdisplay
>> 5) + 16;
1718 if (radeon_encoder
->underscan_vborder
!= 0)
1719 radeon_crtc
->v_border
= radeon_encoder
->underscan_vborder
;
1721 radeon_crtc
->v_border
= (mode
->vdisplay
>> 5) + 16;
1722 radeon_crtc
->rmx_type
= RMX_FULL
;
1723 src_v
= crtc
->mode
.vdisplay
;
1724 dst_v
= crtc
->mode
.vdisplay
- (radeon_crtc
->v_border
* 2);
1725 src_h
= crtc
->mode
.hdisplay
;
1726 dst_h
= crtc
->mode
.hdisplay
- (radeon_crtc
->h_border
* 2);
1730 if (radeon_crtc
->rmx_type
!= radeon_encoder
->rmx_type
) {
1731 /* WARNING: Right now this can't happen but
1732 * in the future we need to check that scaling
1733 * are consistent across different encoder
1734 * (ie all encoder can work with the same
1737 DRM_ERROR("Scaling not consistent across encoder.\n");
1742 if (radeon_crtc
->rmx_type
!= RMX_OFF
) {
1744 a
.full
= dfixed_const(src_v
);
1745 b
.full
= dfixed_const(dst_v
);
1746 radeon_crtc
->vsc
.full
= dfixed_div(a
, b
);
1747 a
.full
= dfixed_const(src_h
);
1748 b
.full
= dfixed_const(dst_h
);
1749 radeon_crtc
->hsc
.full
= dfixed_div(a
, b
);
1751 radeon_crtc
->vsc
.full
= dfixed_const(1);
1752 radeon_crtc
->hsc
.full
= dfixed_const(1);
1758 * Retrieve current video scanout position of crtc on a given gpu, and
1759 * an optional accurate timestamp of when query happened.
1761 * \param dev Device to query.
1762 * \param crtc Crtc to query.
1763 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1764 * \param *vpos Location where vertical scanout position should be stored.
1765 * \param *hpos Location where horizontal scanout position should go.
1766 * \param *stime Target location for timestamp taken immediately before
1767 * scanout position query. Can be NULL to skip timestamp.
1768 * \param *etime Target location for timestamp taken immediately after
1769 * scanout position query. Can be NULL to skip timestamp.
1771 * Returns vpos as a positive number while in active scanout area.
1772 * Returns vpos as a negative number inside vblank, counting the number
1773 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1774 * until start of active scanout / end of vblank."
1776 * \return Flags, or'ed together as follows:
1778 * DRM_SCANOUTPOS_VALID = Query successful.
1779 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1780 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1781 * this flag means that returned position may be offset by a constant but
1782 * unknown small number of scanlines wrt. real scanout position.
1785 int radeon_get_crtc_scanoutpos(struct drm_device
*dev
, int crtc
, unsigned int flags
,
1786 int *vpos
, int *hpos
, ktime_t
*stime
, ktime_t
*etime
)
1788 u32 stat_crtc
= 0, vbl
= 0, position
= 0;
1789 int vbl_start
, vbl_end
, vtotal
, ret
= 0;
1792 struct radeon_device
*rdev
= dev
->dev_private
;
1794 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1796 /* Get optional system timestamp before query. */
1798 *stime
= ktime_get();
1800 if (ASIC_IS_DCE4(rdev
)) {
1802 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1803 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1804 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1805 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1806 ret
|= DRM_SCANOUTPOS_VALID
;
1809 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1810 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1811 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1812 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1813 ret
|= DRM_SCANOUTPOS_VALID
;
1816 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1817 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1818 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1819 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1820 ret
|= DRM_SCANOUTPOS_VALID
;
1823 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1824 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1825 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1826 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1827 ret
|= DRM_SCANOUTPOS_VALID
;
1830 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1831 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1832 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1833 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1834 ret
|= DRM_SCANOUTPOS_VALID
;
1837 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1838 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1839 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1840 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1841 ret
|= DRM_SCANOUTPOS_VALID
;
1843 } else if (ASIC_IS_AVIVO(rdev
)) {
1845 vbl
= RREG32(AVIVO_D1CRTC_V_BLANK_START_END
);
1846 position
= RREG32(AVIVO_D1CRTC_STATUS_POSITION
);
1847 ret
|= DRM_SCANOUTPOS_VALID
;
1850 vbl
= RREG32(AVIVO_D2CRTC_V_BLANK_START_END
);
1851 position
= RREG32(AVIVO_D2CRTC_STATUS_POSITION
);
1852 ret
|= DRM_SCANOUTPOS_VALID
;
1855 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1857 /* Assume vbl_end == 0, get vbl_start from
1860 vbl
= (RREG32(RADEON_CRTC_V_TOTAL_DISP
) &
1861 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1862 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1863 position
= (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1864 stat_crtc
= RREG32(RADEON_CRTC_STATUS
);
1865 if (!(stat_crtc
& 1))
1868 ret
|= DRM_SCANOUTPOS_VALID
;
1871 vbl
= (RREG32(RADEON_CRTC2_V_TOTAL_DISP
) &
1872 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1873 position
= (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1874 stat_crtc
= RREG32(RADEON_CRTC2_STATUS
);
1875 if (!(stat_crtc
& 1))
1878 ret
|= DRM_SCANOUTPOS_VALID
;
1882 /* Get optional system timestamp after query. */
1884 *etime
= ktime_get();
1886 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1888 /* Decode into vertical and horizontal scanout position. */
1889 *vpos
= position
& 0x1fff;
1890 *hpos
= (position
>> 16) & 0x1fff;
1892 /* Valid vblank area boundaries from gpu retrieved? */
1895 ret
|= DRM_SCANOUTPOS_ACCURATE
;
1896 vbl_start
= vbl
& 0x1fff;
1897 vbl_end
= (vbl
>> 16) & 0x1fff;
1900 /* No: Fake something reasonable which gives at least ok results. */
1901 vbl_start
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vdisplay
;
1905 /* Test scanout position against vblank region. */
1906 if ((*vpos
< vbl_start
) && (*vpos
>= vbl_end
))
1909 /* Check if inside vblank area and apply corrective offsets:
1910 * vpos will then be >=0 in video scanout area, but negative
1911 * within vblank area, counting down the number of lines until
1915 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1916 if (in_vbl
&& (*vpos
>= vbl_start
)) {
1917 vtotal
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vtotal
;
1918 *vpos
= *vpos
- vtotal
;
1921 /* Correct for shifted end of vbl at vbl_end. */
1922 *vpos
= *vpos
- vbl_end
;
1926 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
1928 /* Is vpos outside nominal vblank area, but less than
1929 * 1/100 of a frame height away from start of vblank?
1930 * If so, assume this isn't a massively delayed vblank
1931 * interrupt, but a vblank interrupt that fired a few
1932 * microseconds before true start of vblank. Compensate
1933 * by adding a full frame duration to the final timestamp.
1934 * Happens, e.g., on ATI R500, R600.
1936 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1938 if ((flags
& DRM_CALLED_FROM_VBLIRQ
) && !in_vbl
) {
1939 vbl_start
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vdisplay
;
1940 vtotal
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vtotal
;
1942 if (vbl_start
- *vpos
< vtotal
/ 100) {
1945 /* Signal this correction as "applied". */