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Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static int radeon_ddc_dump(struct drm_connector *connector);
37
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39 {
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 }
70
71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
72 {
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77
78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
91
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
98 }
99 }
100
101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
102 {
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107 uint32_t dac2_cntl;
108
109 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
110 if (radeon_crtc->crtc_id == 0)
111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
112 else
113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
114 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
115
116 WREG8(RADEON_PALETTE_INDEX, 0);
117 for (i = 0; i < 256; i++) {
118 WREG32(RADEON_PALETTE_30_DATA,
119 (radeon_crtc->lut_r[i] << 20) |
120 (radeon_crtc->lut_g[i] << 10) |
121 (radeon_crtc->lut_b[i] << 0));
122 }
123 }
124
125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
126 {
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
129
130 if (!crtc->enabled)
131 return;
132
133 if (ASIC_IS_DCE4(rdev))
134 evergreen_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev))
136 avivo_crtc_load_lut(crtc);
137 else
138 legacy_crtc_load_lut(crtc);
139 }
140
141 /** Sets the color ramps on behalf of fbcon */
142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
143 u16 blue, int regno)
144 {
145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
146
147 radeon_crtc->lut_r[regno] = red >> 6;
148 radeon_crtc->lut_g[regno] = green >> 6;
149 radeon_crtc->lut_b[regno] = blue >> 6;
150 }
151
152 /** Gets the color ramps on behalf of fbcon */
153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
154 u16 *blue, int regno)
155 {
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
157
158 *red = radeon_crtc->lut_r[regno] << 6;
159 *green = radeon_crtc->lut_g[regno] << 6;
160 *blue = radeon_crtc->lut_b[regno] << 6;
161 }
162
163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
164 u16 *blue, uint32_t start, uint32_t size)
165 {
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 int end = (start + size > 256) ? 256 : start + size, i;
168
169 /* userspace palettes are always correct as is */
170 for (i = start; i < end; i++) {
171 radeon_crtc->lut_r[i] = red[i] >> 6;
172 radeon_crtc->lut_g[i] = green[i] >> 6;
173 radeon_crtc->lut_b[i] = blue[i] >> 6;
174 }
175 radeon_crtc_load_lut(crtc);
176 }
177
178 static void radeon_crtc_destroy(struct drm_crtc *crtc)
179 {
180 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
181
182 drm_crtc_cleanup(crtc);
183 kfree(radeon_crtc);
184 }
185
186 static const struct drm_crtc_funcs radeon_crtc_funcs = {
187 .cursor_set = radeon_crtc_cursor_set,
188 .cursor_move = radeon_crtc_cursor_move,
189 .gamma_set = radeon_crtc_gamma_set,
190 .set_config = drm_crtc_helper_set_config,
191 .destroy = radeon_crtc_destroy,
192 };
193
194 static void radeon_crtc_init(struct drm_device *dev, int index)
195 {
196 struct radeon_device *rdev = dev->dev_private;
197 struct radeon_crtc *radeon_crtc;
198 int i;
199
200 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
201 if (radeon_crtc == NULL)
202 return;
203
204 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
205
206 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
207 radeon_crtc->crtc_id = index;
208 rdev->mode_info.crtcs[index] = radeon_crtc;
209
210 #if 0
211 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
212 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
213 radeon_crtc->mode_set.num_connectors = 0;
214 #endif
215
216 for (i = 0; i < 256; i++) {
217 radeon_crtc->lut_r[i] = i << 2;
218 radeon_crtc->lut_g[i] = i << 2;
219 radeon_crtc->lut_b[i] = i << 2;
220 }
221
222 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
223 radeon_atombios_init_crtc(dev, radeon_crtc);
224 else
225 radeon_legacy_init_crtc(dev, radeon_crtc);
226 }
227
228 static const char *encoder_names[34] = {
229 "NONE",
230 "INTERNAL_LVDS",
231 "INTERNAL_TMDS1",
232 "INTERNAL_TMDS2",
233 "INTERNAL_DAC1",
234 "INTERNAL_DAC2",
235 "INTERNAL_SDVOA",
236 "INTERNAL_SDVOB",
237 "SI170B",
238 "CH7303",
239 "CH7301",
240 "INTERNAL_DVO1",
241 "EXTERNAL_SDVOA",
242 "EXTERNAL_SDVOB",
243 "TITFP513",
244 "INTERNAL_LVTM1",
245 "VT1623",
246 "HDMI_SI1930",
247 "HDMI_INTERNAL",
248 "INTERNAL_KLDSCP_TMDS1",
249 "INTERNAL_KLDSCP_DVO1",
250 "INTERNAL_KLDSCP_DAC1",
251 "INTERNAL_KLDSCP_DAC2",
252 "SI178",
253 "MVPU_FPGA",
254 "INTERNAL_DDI",
255 "VT1625",
256 "HDMI_SI1932",
257 "DP_AN9801",
258 "DP_DP501",
259 "INTERNAL_UNIPHY",
260 "INTERNAL_KLDSCP_LVTMA",
261 "INTERNAL_UNIPHY1",
262 "INTERNAL_UNIPHY2",
263 };
264
265 static const char *connector_names[15] = {
266 "Unknown",
267 "VGA",
268 "DVI-I",
269 "DVI-D",
270 "DVI-A",
271 "Composite",
272 "S-video",
273 "LVDS",
274 "Component",
275 "DIN",
276 "DisplayPort",
277 "HDMI-A",
278 "HDMI-B",
279 "TV",
280 "eDP",
281 };
282
283 static const char *hpd_names[6] = {
284 "HPD1",
285 "HPD2",
286 "HPD3",
287 "HPD4",
288 "HPD5",
289 "HPD6",
290 };
291
292 static void radeon_print_display_setup(struct drm_device *dev)
293 {
294 struct drm_connector *connector;
295 struct radeon_connector *radeon_connector;
296 struct drm_encoder *encoder;
297 struct radeon_encoder *radeon_encoder;
298 uint32_t devices;
299 int i = 0;
300
301 DRM_INFO("Radeon Display Connectors\n");
302 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
303 radeon_connector = to_radeon_connector(connector);
304 DRM_INFO("Connector %d:\n", i);
305 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
306 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
307 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
308 if (radeon_connector->ddc_bus) {
309 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
310 radeon_connector->ddc_bus->rec.mask_clk_reg,
311 radeon_connector->ddc_bus->rec.mask_data_reg,
312 radeon_connector->ddc_bus->rec.a_clk_reg,
313 radeon_connector->ddc_bus->rec.a_data_reg,
314 radeon_connector->ddc_bus->rec.en_clk_reg,
315 radeon_connector->ddc_bus->rec.en_data_reg,
316 radeon_connector->ddc_bus->rec.y_clk_reg,
317 radeon_connector->ddc_bus->rec.y_data_reg);
318 if (radeon_connector->router_bus)
319 DRM_INFO(" DDC Router 0x%x/0x%x\n",
320 radeon_connector->router.mux_control_pin,
321 radeon_connector->router.mux_state);
322 } else {
323 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
324 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
325 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
326 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
327 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
328 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
329 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
330 }
331 DRM_INFO(" Encoders:\n");
332 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
333 radeon_encoder = to_radeon_encoder(encoder);
334 devices = radeon_encoder->devices & radeon_connector->devices;
335 if (devices) {
336 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
337 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
338 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
339 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
340 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
341 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
342 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
343 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
344 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
345 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
346 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
347 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
348 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
349 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
350 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
351 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
352 if (devices & ATOM_DEVICE_TV1_SUPPORT)
353 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
354 if (devices & ATOM_DEVICE_CV_SUPPORT)
355 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
356 }
357 }
358 i++;
359 }
360 }
361
362 static bool radeon_setup_enc_conn(struct drm_device *dev)
363 {
364 struct radeon_device *rdev = dev->dev_private;
365 struct drm_connector *drm_connector;
366 bool ret = false;
367
368 if (rdev->bios) {
369 if (rdev->is_atom_bios) {
370 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
371 if (ret == false)
372 ret = radeon_get_atom_connector_info_from_object_table(dev);
373 } else {
374 ret = radeon_get_legacy_connector_info_from_bios(dev);
375 if (ret == false)
376 ret = radeon_get_legacy_connector_info_from_table(dev);
377 }
378 } else {
379 if (!ASIC_IS_AVIVO(rdev))
380 ret = radeon_get_legacy_connector_info_from_table(dev);
381 }
382 if (ret) {
383 radeon_setup_encoder_clones(dev);
384 radeon_print_display_setup(dev);
385 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
386 radeon_ddc_dump(drm_connector);
387 }
388
389 return ret;
390 }
391
392 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
393 {
394 struct drm_device *dev = radeon_connector->base.dev;
395 struct radeon_device *rdev = dev->dev_private;
396 int ret = 0;
397
398 /* on hw with routers, select right port */
399 if (radeon_connector->router.valid)
400 radeon_router_select_port(radeon_connector);
401
402 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
403 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
404 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
405 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
406 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
407 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
408 }
409 if (!radeon_connector->ddc_bus)
410 return -1;
411 if (!radeon_connector->edid) {
412 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
413 }
414 /* some servers provide a hardcoded edid in rom for KVMs */
415 if (!radeon_connector->edid)
416 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
417 if (radeon_connector->edid) {
418 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
419 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
420 return ret;
421 }
422 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
423 return 0;
424 }
425
426 static int radeon_ddc_dump(struct drm_connector *connector)
427 {
428 struct edid *edid;
429 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
430 int ret = 0;
431
432 /* on hw with routers, select right port */
433 if (radeon_connector->router.valid)
434 radeon_router_select_port(radeon_connector);
435
436 if (!radeon_connector->ddc_bus)
437 return -1;
438 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
439 if (edid) {
440 kfree(edid);
441 }
442 return ret;
443 }
444
445 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
446 {
447 uint64_t mod;
448
449 n += d / 2;
450
451 mod = do_div(n, d);
452 return n;
453 }
454
455 static void radeon_compute_pll_legacy(struct radeon_pll *pll,
456 uint64_t freq,
457 uint32_t *dot_clock_p,
458 uint32_t *fb_div_p,
459 uint32_t *frac_fb_div_p,
460 uint32_t *ref_div_p,
461 uint32_t *post_div_p)
462 {
463 uint32_t min_ref_div = pll->min_ref_div;
464 uint32_t max_ref_div = pll->max_ref_div;
465 uint32_t min_post_div = pll->min_post_div;
466 uint32_t max_post_div = pll->max_post_div;
467 uint32_t min_fractional_feed_div = 0;
468 uint32_t max_fractional_feed_div = 0;
469 uint32_t best_vco = pll->best_vco;
470 uint32_t best_post_div = 1;
471 uint32_t best_ref_div = 1;
472 uint32_t best_feedback_div = 1;
473 uint32_t best_frac_feedback_div = 0;
474 uint32_t best_freq = -1;
475 uint32_t best_error = 0xffffffff;
476 uint32_t best_vco_diff = 1;
477 uint32_t post_div;
478 u32 pll_out_min, pll_out_max;
479
480 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
481 freq = freq * 1000;
482
483 if (pll->flags & RADEON_PLL_IS_LCD) {
484 pll_out_min = pll->lcd_pll_out_min;
485 pll_out_max = pll->lcd_pll_out_max;
486 } else {
487 pll_out_min = pll->pll_out_min;
488 pll_out_max = pll->pll_out_max;
489 }
490
491 if (pll->flags & RADEON_PLL_USE_REF_DIV)
492 min_ref_div = max_ref_div = pll->reference_div;
493 else {
494 while (min_ref_div < max_ref_div-1) {
495 uint32_t mid = (min_ref_div + max_ref_div) / 2;
496 uint32_t pll_in = pll->reference_freq / mid;
497 if (pll_in < pll->pll_in_min)
498 max_ref_div = mid;
499 else if (pll_in > pll->pll_in_max)
500 min_ref_div = mid;
501 else
502 break;
503 }
504 }
505
506 if (pll->flags & RADEON_PLL_USE_POST_DIV)
507 min_post_div = max_post_div = pll->post_div;
508
509 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
510 min_fractional_feed_div = pll->min_frac_feedback_div;
511 max_fractional_feed_div = pll->max_frac_feedback_div;
512 }
513
514 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
515 uint32_t ref_div;
516
517 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
518 continue;
519
520 /* legacy radeons only have a few post_divs */
521 if (pll->flags & RADEON_PLL_LEGACY) {
522 if ((post_div == 5) ||
523 (post_div == 7) ||
524 (post_div == 9) ||
525 (post_div == 10) ||
526 (post_div == 11) ||
527 (post_div == 13) ||
528 (post_div == 14) ||
529 (post_div == 15))
530 continue;
531 }
532
533 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
534 uint32_t feedback_div, current_freq = 0, error, vco_diff;
535 uint32_t pll_in = pll->reference_freq / ref_div;
536 uint32_t min_feed_div = pll->min_feedback_div;
537 uint32_t max_feed_div = pll->max_feedback_div + 1;
538
539 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
540 continue;
541
542 while (min_feed_div < max_feed_div) {
543 uint32_t vco;
544 uint32_t min_frac_feed_div = min_fractional_feed_div;
545 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
546 uint32_t frac_feedback_div;
547 uint64_t tmp;
548
549 feedback_div = (min_feed_div + max_feed_div) / 2;
550
551 tmp = (uint64_t)pll->reference_freq * feedback_div;
552 vco = radeon_div(tmp, ref_div);
553
554 if (vco < pll_out_min) {
555 min_feed_div = feedback_div + 1;
556 continue;
557 } else if (vco > pll_out_max) {
558 max_feed_div = feedback_div;
559 continue;
560 }
561
562 while (min_frac_feed_div < max_frac_feed_div) {
563 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
564 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
565 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
566 current_freq = radeon_div(tmp, ref_div * post_div);
567
568 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
569 if (freq < current_freq)
570 error = 0xffffffff;
571 else
572 error = freq - current_freq;
573 } else
574 error = abs(current_freq - freq);
575 vco_diff = abs(vco - best_vco);
576
577 if ((best_vco == 0 && error < best_error) ||
578 (best_vco != 0 &&
579 ((best_error > 100 && error < best_error - 100) ||
580 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
581 best_post_div = post_div;
582 best_ref_div = ref_div;
583 best_feedback_div = feedback_div;
584 best_frac_feedback_div = frac_feedback_div;
585 best_freq = current_freq;
586 best_error = error;
587 best_vco_diff = vco_diff;
588 } else if (current_freq == freq) {
589 if (best_freq == -1) {
590 best_post_div = post_div;
591 best_ref_div = ref_div;
592 best_feedback_div = feedback_div;
593 best_frac_feedback_div = frac_feedback_div;
594 best_freq = current_freq;
595 best_error = error;
596 best_vco_diff = vco_diff;
597 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
598 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
599 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
600 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
601 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
602 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
603 best_post_div = post_div;
604 best_ref_div = ref_div;
605 best_feedback_div = feedback_div;
606 best_frac_feedback_div = frac_feedback_div;
607 best_freq = current_freq;
608 best_error = error;
609 best_vco_diff = vco_diff;
610 }
611 }
612 if (current_freq < freq)
613 min_frac_feed_div = frac_feedback_div + 1;
614 else
615 max_frac_feed_div = frac_feedback_div;
616 }
617 if (current_freq < freq)
618 min_feed_div = feedback_div + 1;
619 else
620 max_feed_div = feedback_div;
621 }
622 }
623 }
624
625 *dot_clock_p = best_freq / 10000;
626 *fb_div_p = best_feedback_div;
627 *frac_fb_div_p = best_frac_feedback_div;
628 *ref_div_p = best_ref_div;
629 *post_div_p = best_post_div;
630 }
631
632 static bool
633 calc_fb_div(struct radeon_pll *pll,
634 uint32_t freq,
635 uint32_t post_div,
636 uint32_t ref_div,
637 uint32_t *fb_div,
638 uint32_t *fb_div_frac)
639 {
640 fixed20_12 feedback_divider, a, b;
641 u32 vco_freq;
642
643 vco_freq = freq * post_div;
644 /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
645 a.full = dfixed_const(pll->reference_freq);
646 feedback_divider.full = dfixed_const(vco_freq);
647 feedback_divider.full = dfixed_div(feedback_divider, a);
648 a.full = dfixed_const(ref_div);
649 feedback_divider.full = dfixed_mul(feedback_divider, a);
650
651 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
652 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
653 a.full = dfixed_const(10);
654 feedback_divider.full = dfixed_mul(feedback_divider, a);
655 feedback_divider.full += dfixed_const_half(0);
656 feedback_divider.full = dfixed_floor(feedback_divider);
657 feedback_divider.full = dfixed_div(feedback_divider, a);
658
659 /* *fb_div = floor(feedback_divider); */
660 a.full = dfixed_floor(feedback_divider);
661 *fb_div = dfixed_trunc(a);
662 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
663 a.full = dfixed_const(10);
664 b.full = dfixed_mul(feedback_divider, a);
665
666 feedback_divider.full = dfixed_floor(feedback_divider);
667 feedback_divider.full = dfixed_mul(feedback_divider, a);
668 feedback_divider.full = b.full - feedback_divider.full;
669 *fb_div_frac = dfixed_trunc(feedback_divider);
670 } else {
671 /* *fb_div = floor(feedback_divider + 0.5); */
672 feedback_divider.full += dfixed_const_half(0);
673 feedback_divider.full = dfixed_floor(feedback_divider);
674
675 *fb_div = dfixed_trunc(feedback_divider);
676 *fb_div_frac = 0;
677 }
678
679 if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
680 return false;
681 else
682 return true;
683 }
684
685 static bool
686 calc_fb_ref_div(struct radeon_pll *pll,
687 uint32_t freq,
688 uint32_t post_div,
689 uint32_t *fb_div,
690 uint32_t *fb_div_frac,
691 uint32_t *ref_div)
692 {
693 fixed20_12 ffreq, max_error, error, pll_out, a;
694 u32 vco;
695 u32 pll_out_min, pll_out_max;
696
697 if (pll->flags & RADEON_PLL_IS_LCD) {
698 pll_out_min = pll->lcd_pll_out_min;
699 pll_out_max = pll->lcd_pll_out_max;
700 } else {
701 pll_out_min = pll->pll_out_min;
702 pll_out_max = pll->pll_out_max;
703 }
704
705 ffreq.full = dfixed_const(freq);
706 /* max_error = ffreq * 0.0025; */
707 a.full = dfixed_const(400);
708 max_error.full = dfixed_div(ffreq, a);
709
710 for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
711 if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
712 vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
713 vco = vco / ((*ref_div) * 10);
714
715 if ((vco < pll_out_min) || (vco > pll_out_max))
716 continue;
717
718 /* pll_out = vco / post_div; */
719 a.full = dfixed_const(post_div);
720 pll_out.full = dfixed_const(vco);
721 pll_out.full = dfixed_div(pll_out, a);
722
723 if (pll_out.full >= ffreq.full) {
724 error.full = pll_out.full - ffreq.full;
725 if (error.full <= max_error.full)
726 return true;
727 }
728 }
729 }
730 return false;
731 }
732
733 static void radeon_compute_pll_new(struct radeon_pll *pll,
734 uint64_t freq,
735 uint32_t *dot_clock_p,
736 uint32_t *fb_div_p,
737 uint32_t *frac_fb_div_p,
738 uint32_t *ref_div_p,
739 uint32_t *post_div_p)
740 {
741 u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
742 u32 best_freq = 0, vco_frequency;
743 u32 pll_out_min, pll_out_max;
744
745 if (pll->flags & RADEON_PLL_IS_LCD) {
746 pll_out_min = pll->lcd_pll_out_min;
747 pll_out_max = pll->lcd_pll_out_max;
748 } else {
749 pll_out_min = pll->pll_out_min;
750 pll_out_max = pll->pll_out_max;
751 }
752
753 /* freq = freq / 10; */
754 do_div(freq, 10);
755
756 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
757 post_div = pll->post_div;
758 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
759 goto done;
760
761 vco_frequency = freq * post_div;
762 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
763 goto done;
764
765 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
766 ref_div = pll->reference_div;
767 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
768 goto done;
769 if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
770 goto done;
771 }
772 } else {
773 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
774 if (pll->flags & RADEON_PLL_LEGACY) {
775 if ((post_div == 5) ||
776 (post_div == 7) ||
777 (post_div == 9) ||
778 (post_div == 10) ||
779 (post_div == 11))
780 continue;
781 }
782
783 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
784 continue;
785
786 vco_frequency = freq * post_div;
787 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
788 continue;
789 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
790 ref_div = pll->reference_div;
791 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
792 goto done;
793 if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
794 break;
795 } else {
796 if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
797 break;
798 }
799 }
800 }
801
802 best_freq = pll->reference_freq * 10 * fb_div;
803 best_freq += pll->reference_freq * fb_div_frac;
804 best_freq = best_freq / (ref_div * post_div);
805
806 done:
807 if (best_freq == 0)
808 DRM_ERROR("Couldn't find valid PLL dividers\n");
809
810 *dot_clock_p = best_freq / 10;
811 *fb_div_p = fb_div;
812 *frac_fb_div_p = fb_div_frac;
813 *ref_div_p = ref_div;
814 *post_div_p = post_div;
815
816 DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
817 }
818
819 void radeon_compute_pll(struct radeon_pll *pll,
820 uint64_t freq,
821 uint32_t *dot_clock_p,
822 uint32_t *fb_div_p,
823 uint32_t *frac_fb_div_p,
824 uint32_t *ref_div_p,
825 uint32_t *post_div_p)
826 {
827 switch (pll->algo) {
828 case PLL_ALGO_NEW:
829 radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
830 frac_fb_div_p, ref_div_p, post_div_p);
831 break;
832 case PLL_ALGO_LEGACY:
833 default:
834 radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
835 frac_fb_div_p, ref_div_p, post_div_p);
836 break;
837 }
838 }
839
840 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
841 {
842 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
843
844 if (radeon_fb->obj)
845 drm_gem_object_unreference_unlocked(radeon_fb->obj);
846 drm_framebuffer_cleanup(fb);
847 kfree(radeon_fb);
848 }
849
850 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
851 struct drm_file *file_priv,
852 unsigned int *handle)
853 {
854 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
855
856 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
857 }
858
859 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
860 .destroy = radeon_user_framebuffer_destroy,
861 .create_handle = radeon_user_framebuffer_create_handle,
862 };
863
864 void
865 radeon_framebuffer_init(struct drm_device *dev,
866 struct radeon_framebuffer *rfb,
867 struct drm_mode_fb_cmd *mode_cmd,
868 struct drm_gem_object *obj)
869 {
870 rfb->obj = obj;
871 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
872 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
873 }
874
875 static struct drm_framebuffer *
876 radeon_user_framebuffer_create(struct drm_device *dev,
877 struct drm_file *file_priv,
878 struct drm_mode_fb_cmd *mode_cmd)
879 {
880 struct drm_gem_object *obj;
881 struct radeon_framebuffer *radeon_fb;
882
883 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
884 if (obj == NULL) {
885 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
886 "can't create framebuffer\n", mode_cmd->handle);
887 return ERR_PTR(-ENOENT);
888 }
889
890 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
891 if (radeon_fb == NULL)
892 return ERR_PTR(-ENOMEM);
893
894 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
895
896 return &radeon_fb->base;
897 }
898
899 static void radeon_output_poll_changed(struct drm_device *dev)
900 {
901 struct radeon_device *rdev = dev->dev_private;
902 radeon_fb_output_poll_changed(rdev);
903 }
904
905 static const struct drm_mode_config_funcs radeon_mode_funcs = {
906 .fb_create = radeon_user_framebuffer_create,
907 .output_poll_changed = radeon_output_poll_changed
908 };
909
910 struct drm_prop_enum_list {
911 int type;
912 char *name;
913 };
914
915 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
916 { { 0, "driver" },
917 { 1, "bios" },
918 };
919
920 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
921 { { TV_STD_NTSC, "ntsc" },
922 { TV_STD_PAL, "pal" },
923 { TV_STD_PAL_M, "pal-m" },
924 { TV_STD_PAL_60, "pal-60" },
925 { TV_STD_NTSC_J, "ntsc-j" },
926 { TV_STD_SCART_PAL, "scart-pal" },
927 { TV_STD_PAL_CN, "pal-cn" },
928 { TV_STD_SECAM, "secam" },
929 };
930
931 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
932 { { UNDERSCAN_OFF, "off" },
933 { UNDERSCAN_ON, "on" },
934 { UNDERSCAN_AUTO, "auto" },
935 };
936
937 static int radeon_modeset_create_props(struct radeon_device *rdev)
938 {
939 int i, sz;
940
941 if (rdev->is_atom_bios) {
942 rdev->mode_info.coherent_mode_property =
943 drm_property_create(rdev->ddev,
944 DRM_MODE_PROP_RANGE,
945 "coherent", 2);
946 if (!rdev->mode_info.coherent_mode_property)
947 return -ENOMEM;
948
949 rdev->mode_info.coherent_mode_property->values[0] = 0;
950 rdev->mode_info.coherent_mode_property->values[1] = 1;
951 }
952
953 if (!ASIC_IS_AVIVO(rdev)) {
954 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
955 rdev->mode_info.tmds_pll_property =
956 drm_property_create(rdev->ddev,
957 DRM_MODE_PROP_ENUM,
958 "tmds_pll", sz);
959 for (i = 0; i < sz; i++) {
960 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
961 i,
962 radeon_tmds_pll_enum_list[i].type,
963 radeon_tmds_pll_enum_list[i].name);
964 }
965 }
966
967 rdev->mode_info.load_detect_property =
968 drm_property_create(rdev->ddev,
969 DRM_MODE_PROP_RANGE,
970 "load detection", 2);
971 if (!rdev->mode_info.load_detect_property)
972 return -ENOMEM;
973 rdev->mode_info.load_detect_property->values[0] = 0;
974 rdev->mode_info.load_detect_property->values[1] = 1;
975
976 drm_mode_create_scaling_mode_property(rdev->ddev);
977
978 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
979 rdev->mode_info.tv_std_property =
980 drm_property_create(rdev->ddev,
981 DRM_MODE_PROP_ENUM,
982 "tv standard", sz);
983 for (i = 0; i < sz; i++) {
984 drm_property_add_enum(rdev->mode_info.tv_std_property,
985 i,
986 radeon_tv_std_enum_list[i].type,
987 radeon_tv_std_enum_list[i].name);
988 }
989
990 sz = ARRAY_SIZE(radeon_underscan_enum_list);
991 rdev->mode_info.underscan_property =
992 drm_property_create(rdev->ddev,
993 DRM_MODE_PROP_ENUM,
994 "underscan", sz);
995 for (i = 0; i < sz; i++) {
996 drm_property_add_enum(rdev->mode_info.underscan_property,
997 i,
998 radeon_underscan_enum_list[i].type,
999 radeon_underscan_enum_list[i].name);
1000 }
1001
1002 return 0;
1003 }
1004
1005 void radeon_update_display_priority(struct radeon_device *rdev)
1006 {
1007 /* adjustment options for the display watermarks */
1008 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1009 /* set display priority to high for r3xx, rv515 chips
1010 * this avoids flickering due to underflow to the
1011 * display controllers during heavy acceleration.
1012 * Don't force high on rs4xx igp chips as it seems to
1013 * affect the sound card. See kernel bug 15982.
1014 */
1015 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1016 !(rdev->flags & RADEON_IS_IGP))
1017 rdev->disp_priority = 2;
1018 else
1019 rdev->disp_priority = 0;
1020 } else
1021 rdev->disp_priority = radeon_disp_priority;
1022
1023 }
1024
1025 int radeon_modeset_init(struct radeon_device *rdev)
1026 {
1027 int i;
1028 int ret;
1029
1030 drm_mode_config_init(rdev->ddev);
1031 rdev->mode_info.mode_config_initialized = true;
1032
1033 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1034
1035 if (ASIC_IS_AVIVO(rdev)) {
1036 rdev->ddev->mode_config.max_width = 8192;
1037 rdev->ddev->mode_config.max_height = 8192;
1038 } else {
1039 rdev->ddev->mode_config.max_width = 4096;
1040 rdev->ddev->mode_config.max_height = 4096;
1041 }
1042
1043 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1044
1045 ret = radeon_modeset_create_props(rdev);
1046 if (ret) {
1047 return ret;
1048 }
1049
1050 /* init i2c buses */
1051 radeon_i2c_init(rdev);
1052
1053 /* check combios for a valid hardcoded EDID - Sun servers */
1054 if (!rdev->is_atom_bios) {
1055 /* check for hardcoded EDID in BIOS */
1056 radeon_combios_check_hardcoded_edid(rdev);
1057 }
1058
1059 /* allocate crtcs */
1060 for (i = 0; i < rdev->num_crtc; i++) {
1061 radeon_crtc_init(rdev->ddev, i);
1062 }
1063
1064 /* okay we should have all the bios connectors */
1065 ret = radeon_setup_enc_conn(rdev->ddev);
1066 if (!ret) {
1067 return ret;
1068 }
1069 /* initialize hpd */
1070 radeon_hpd_init(rdev);
1071
1072 /* Initialize power management */
1073 radeon_pm_init(rdev);
1074
1075 radeon_fbdev_init(rdev);
1076 drm_kms_helper_poll_init(rdev->ddev);
1077
1078 return 0;
1079 }
1080
1081 void radeon_modeset_fini(struct radeon_device *rdev)
1082 {
1083 radeon_fbdev_fini(rdev);
1084 kfree(rdev->mode_info.bios_hardcoded_edid);
1085 radeon_pm_fini(rdev);
1086
1087 if (rdev->mode_info.mode_config_initialized) {
1088 drm_kms_helper_poll_fini(rdev->ddev);
1089 radeon_hpd_fini(rdev);
1090 drm_mode_config_cleanup(rdev->ddev);
1091 rdev->mode_info.mode_config_initialized = false;
1092 }
1093 /* free i2c buses */
1094 radeon_i2c_fini(rdev);
1095 }
1096
1097 static bool is_hdtv_mode(struct drm_display_mode *mode)
1098 {
1099 /* try and guess if this is a tv or a monitor */
1100 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1101 (mode->vdisplay == 576) || /* 576p */
1102 (mode->vdisplay == 720) || /* 720p */
1103 (mode->vdisplay == 1080)) /* 1080p */
1104 return true;
1105 else
1106 return false;
1107 }
1108
1109 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1110 struct drm_display_mode *mode,
1111 struct drm_display_mode *adjusted_mode)
1112 {
1113 struct drm_device *dev = crtc->dev;
1114 struct radeon_device *rdev = dev->dev_private;
1115 struct drm_encoder *encoder;
1116 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1117 struct radeon_encoder *radeon_encoder;
1118 struct drm_connector *connector;
1119 struct radeon_connector *radeon_connector;
1120 bool first = true;
1121 u32 src_v = 1, dst_v = 1;
1122 u32 src_h = 1, dst_h = 1;
1123
1124 radeon_crtc->h_border = 0;
1125 radeon_crtc->v_border = 0;
1126
1127 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1128 if (encoder->crtc != crtc)
1129 continue;
1130 radeon_encoder = to_radeon_encoder(encoder);
1131 connector = radeon_get_connector_for_encoder(encoder);
1132 radeon_connector = to_radeon_connector(connector);
1133
1134 if (first) {
1135 /* set scaling */
1136 if (radeon_encoder->rmx_type == RMX_OFF)
1137 radeon_crtc->rmx_type = RMX_OFF;
1138 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1139 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1140 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1141 else
1142 radeon_crtc->rmx_type = RMX_OFF;
1143 src_v = crtc->mode.vdisplay;
1144 dst_v = radeon_crtc->native_mode.vdisplay;
1145 src_h = crtc->mode.hdisplay;
1146 dst_h = radeon_crtc->native_mode.vdisplay;
1147 /* copy native mode */
1148 memcpy(&radeon_crtc->native_mode,
1149 &radeon_encoder->native_mode,
1150 sizeof(struct drm_display_mode));
1151
1152 /* fix up for overscan on hdmi */
1153 if (ASIC_IS_AVIVO(rdev) &&
1154 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1155 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1156 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1157 is_hdtv_mode(mode)))) {
1158 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1159 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1160 radeon_crtc->rmx_type = RMX_FULL;
1161 src_v = crtc->mode.vdisplay;
1162 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1163 src_h = crtc->mode.hdisplay;
1164 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1165 }
1166 first = false;
1167 } else {
1168 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1169 /* WARNING: Right now this can't happen but
1170 * in the future we need to check that scaling
1171 * are consistent across different encoder
1172 * (ie all encoder can work with the same
1173 * scaling).
1174 */
1175 DRM_ERROR("Scaling not consistent across encoder.\n");
1176 return false;
1177 }
1178 }
1179 }
1180 if (radeon_crtc->rmx_type != RMX_OFF) {
1181 fixed20_12 a, b;
1182 a.full = dfixed_const(src_v);
1183 b.full = dfixed_const(dst_v);
1184 radeon_crtc->vsc.full = dfixed_div(a, b);
1185 a.full = dfixed_const(src_h);
1186 b.full = dfixed_const(dst_h);
1187 radeon_crtc->hsc.full = dfixed_div(a, b);
1188 } else {
1189 radeon_crtc->vsc.full = dfixed_const(1);
1190 radeon_crtc->hsc.full = dfixed_const(1);
1191 }
1192 return true;
1193 }
Linux kernel - Deliverables
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