2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
31 #include <asm/div64.h>
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_plane_helper.h>
36 #include <drm/drm_edid.h>
38 #include <linux/gcd.h>
40 static void avivo_crtc_load_lut(struct drm_crtc
*crtc
)
42 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
43 struct drm_device
*dev
= crtc
->dev
;
44 struct radeon_device
*rdev
= dev
->dev_private
;
47 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
48 WREG32(AVIVO_DC_LUTA_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
58 WREG32(AVIVO_DC_LUT_RW_SELECT
, radeon_crtc
->crtc_id
);
59 WREG32(AVIVO_DC_LUT_RW_MODE
, 0);
60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK
, 0x0000003f);
62 WREG8(AVIVO_DC_LUT_RW_INDEX
, 0);
63 for (i
= 0; i
< 256; i
++) {
64 WREG32(AVIVO_DC_LUT_30_COLOR
,
65 (radeon_crtc
->lut_r
[i
] << 20) |
66 (radeon_crtc
->lut_g
[i
] << 10) |
67 (radeon_crtc
->lut_b
[i
] << 0));
70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
71 WREG32_P(AVIVO_D1GRPH_LUT_SEL
+ radeon_crtc
->crtc_offset
, radeon_crtc
->crtc_id
, ~1);
74 static void dce4_crtc_load_lut(struct drm_crtc
*crtc
)
76 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
77 struct drm_device
*dev
= crtc
->dev
;
78 struct radeon_device
*rdev
= dev
->dev_private
;
81 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
82 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
92 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
95 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
96 for (i
= 0; i
< 256; i
++) {
97 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
98 (radeon_crtc
->lut_r
[i
] << 20) |
99 (radeon_crtc
->lut_g
[i
] << 10) |
100 (radeon_crtc
->lut_b
[i
] << 0));
104 static void dce5_crtc_load_lut(struct drm_crtc
*crtc
)
106 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
107 struct drm_device
*dev
= crtc
->dev
;
108 struct radeon_device
*rdev
= dev
->dev_private
;
111 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
113 WREG32(NI_INPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
114 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS
) |
115 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS
)));
116 WREG32(NI_PRESCALE_GRPH_CONTROL
+ radeon_crtc
->crtc_offset
,
117 NI_GRPH_PRESCALE_BYPASS
);
118 WREG32(NI_PRESCALE_OVL_CONTROL
+ radeon_crtc
->crtc_offset
,
119 NI_OVL_PRESCALE_BYPASS
);
120 WREG32(NI_INPUT_GAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
121 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
) |
122 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
)));
124 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
134 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
135 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
137 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
138 for (i
= 0; i
< 256; i
++) {
139 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
140 (radeon_crtc
->lut_r
[i
] << 20) |
141 (radeon_crtc
->lut_g
[i
] << 10) |
142 (radeon_crtc
->lut_b
[i
] << 0));
145 WREG32(NI_DEGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
146 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
147 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
148 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
149 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
)));
150 WREG32(NI_GAMUT_REMAP_CONTROL
+ radeon_crtc
->crtc_offset
,
151 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
) |
152 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
)));
153 WREG32(NI_REGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
154 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS
) |
155 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS
)));
156 WREG32(NI_OUTPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
157 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc
->output_csc
) |
158 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS
)));
159 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
160 WREG32(0x6940 + radeon_crtc
->crtc_offset
, 0);
161 if (ASIC_IS_DCE8(rdev
)) {
162 /* XXX this only needs to be programmed once per crtc at startup,
163 * not sure where the best place for it is
165 WREG32(CIK_ALPHA_CONTROL
+ radeon_crtc
->crtc_offset
,
166 CIK_CURSOR_ALPHA_BLND_ENA
);
170 static void legacy_crtc_load_lut(struct drm_crtc
*crtc
)
172 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
173 struct drm_device
*dev
= crtc
->dev
;
174 struct radeon_device
*rdev
= dev
->dev_private
;
178 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
179 if (radeon_crtc
->crtc_id
== 0)
180 dac2_cntl
&= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL
;
182 dac2_cntl
|= RADEON_DAC2_PALETTE_ACC_CTL
;
183 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
185 WREG8(RADEON_PALETTE_INDEX
, 0);
186 for (i
= 0; i
< 256; i
++) {
187 WREG32(RADEON_PALETTE_30_DATA
,
188 (radeon_crtc
->lut_r
[i
] << 20) |
189 (radeon_crtc
->lut_g
[i
] << 10) |
190 (radeon_crtc
->lut_b
[i
] << 0));
194 void radeon_crtc_load_lut(struct drm_crtc
*crtc
)
196 struct drm_device
*dev
= crtc
->dev
;
197 struct radeon_device
*rdev
= dev
->dev_private
;
202 if (ASIC_IS_DCE5(rdev
))
203 dce5_crtc_load_lut(crtc
);
204 else if (ASIC_IS_DCE4(rdev
))
205 dce4_crtc_load_lut(crtc
);
206 else if (ASIC_IS_AVIVO(rdev
))
207 avivo_crtc_load_lut(crtc
);
209 legacy_crtc_load_lut(crtc
);
212 /** Sets the color ramps on behalf of fbcon */
213 void radeon_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
216 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
218 radeon_crtc
->lut_r
[regno
] = red
>> 6;
219 radeon_crtc
->lut_g
[regno
] = green
>> 6;
220 radeon_crtc
->lut_b
[regno
] = blue
>> 6;
223 /** Gets the color ramps on behalf of fbcon */
224 void radeon_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
225 u16
*blue
, int regno
)
227 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
229 *red
= radeon_crtc
->lut_r
[regno
] << 6;
230 *green
= radeon_crtc
->lut_g
[regno
] << 6;
231 *blue
= radeon_crtc
->lut_b
[regno
] << 6;
234 static int radeon_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
235 u16
*blue
, uint32_t size
)
237 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
240 /* userspace palettes are always correct as is */
241 for (i
= 0; i
< size
; i
++) {
242 radeon_crtc
->lut_r
[i
] = red
[i
] >> 6;
243 radeon_crtc
->lut_g
[i
] = green
[i
] >> 6;
244 radeon_crtc
->lut_b
[i
] = blue
[i
] >> 6;
246 radeon_crtc_load_lut(crtc
);
251 static void radeon_crtc_destroy(struct drm_crtc
*crtc
)
253 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
255 drm_crtc_cleanup(crtc
);
256 destroy_workqueue(radeon_crtc
->flip_queue
);
261 * radeon_unpin_work_func - unpin old buffer object
263 * @__work - kernel work item
265 * Unpin the old frame buffer object outside of the interrupt handler
267 static void radeon_unpin_work_func(struct work_struct
*__work
)
269 struct radeon_flip_work
*work
=
270 container_of(__work
, struct radeon_flip_work
, unpin_work
);
273 /* unpin of the old buffer */
274 r
= radeon_bo_reserve(work
->old_rbo
, false);
275 if (likely(r
== 0)) {
276 r
= radeon_bo_unpin(work
->old_rbo
);
277 if (unlikely(r
!= 0)) {
278 DRM_ERROR("failed to unpin buffer after flip\n");
280 radeon_bo_unreserve(work
->old_rbo
);
282 DRM_ERROR("failed to reserve buffer after flip\n");
284 drm_gem_object_unreference_unlocked(&work
->old_rbo
->gem_base
);
288 void radeon_crtc_handle_vblank(struct radeon_device
*rdev
, int crtc_id
)
290 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
295 /* can happen during initialization */
296 if (radeon_crtc
== NULL
)
299 /* Skip the pageflip completion check below (based on polling) on
300 * asics which reliably support hw pageflip completion irqs. pflip
301 * irqs are a reliable and race-free method of handling pageflip
302 * completion detection. A use_pflipirq module parameter < 2 allows
303 * to override this in case of asics with faulty pflip irqs.
304 * A module parameter of 0 would only use this polling based path,
305 * a parameter of 1 would use pflip irq only as a backup to this
306 * path, as in Linux 3.16.
308 if ((radeon_use_pflipirq
== 2) && ASIC_IS_DCE4(rdev
))
311 spin_lock_irqsave(&rdev
->ddev
->event_lock
, flags
);
312 if (radeon_crtc
->flip_status
!= RADEON_FLIP_SUBMITTED
) {
313 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
314 "RADEON_FLIP_SUBMITTED(%d)\n",
315 radeon_crtc
->flip_status
,
316 RADEON_FLIP_SUBMITTED
);
317 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
321 update_pending
= radeon_page_flip_pending(rdev
, crtc_id
);
323 /* Has the pageflip already completed in crtc, or is it certain
324 * to complete in this vblank?
326 if (update_pending
&&
327 (DRM_SCANOUTPOS_VALID
& radeon_get_crtc_scanoutpos(rdev
->ddev
,
329 USE_REAL_VBLANKSTART
,
330 &vpos
, &hpos
, NULL
, NULL
,
331 &rdev
->mode_info
.crtcs
[crtc_id
]->base
.hwmode
)) &&
332 ((vpos
>= (99 * rdev
->mode_info
.crtcs
[crtc_id
]->base
.hwmode
.crtc_vdisplay
)/100) ||
333 (vpos
< 0 && !ASIC_IS_AVIVO(rdev
)))) {
334 /* crtc didn't flip in this target vblank interval,
335 * but flip is pending in crtc. Based on the current
336 * scanout position we know that the current frame is
337 * (nearly) complete and the flip will (likely)
338 * complete before the start of the next frame.
342 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
344 radeon_crtc_handle_flip(rdev
, crtc_id
);
348 * radeon_crtc_handle_flip - page flip completed
350 * @rdev: radeon device pointer
351 * @crtc_id: crtc number this event is for
353 * Called when we are sure that a page flip for this crtc is completed.
355 void radeon_crtc_handle_flip(struct radeon_device
*rdev
, int crtc_id
)
357 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
358 struct radeon_flip_work
*work
;
361 /* this can happen at init */
362 if (radeon_crtc
== NULL
)
365 spin_lock_irqsave(&rdev
->ddev
->event_lock
, flags
);
366 work
= radeon_crtc
->flip_work
;
367 if (radeon_crtc
->flip_status
!= RADEON_FLIP_SUBMITTED
) {
368 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
369 "RADEON_FLIP_SUBMITTED(%d)\n",
370 radeon_crtc
->flip_status
,
371 RADEON_FLIP_SUBMITTED
);
372 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
376 /* Pageflip completed. Clean up. */
377 radeon_crtc
->flip_status
= RADEON_FLIP_NONE
;
378 radeon_crtc
->flip_work
= NULL
;
380 /* wakeup userspace */
382 drm_crtc_send_vblank_event(&radeon_crtc
->base
, work
->event
);
384 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
386 drm_crtc_vblank_put(&radeon_crtc
->base
);
387 radeon_irq_kms_pflip_irq_put(rdev
, work
->crtc_id
);
388 queue_work(radeon_crtc
->flip_queue
, &work
->unpin_work
);
392 * radeon_flip_work_func - page flip framebuffer
394 * @work - kernel work item
396 * Wait for the buffer object to become idle and do the actual page flip
398 static void radeon_flip_work_func(struct work_struct
*__work
)
400 struct radeon_flip_work
*work
=
401 container_of(__work
, struct radeon_flip_work
, flip_work
);
402 struct radeon_device
*rdev
= work
->rdev
;
403 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[work
->crtc_id
];
405 struct drm_crtc
*crtc
= &radeon_crtc
->base
;
408 int vpos
, hpos
, stat
, min_udelay
= 0;
410 struct drm_vblank_crtc
*vblank
= &crtc
->dev
->vblank
[work
->crtc_id
];
412 down_read(&rdev
->exclusive_lock
);
414 struct radeon_fence
*fence
;
416 fence
= to_radeon_fence(work
->fence
);
417 if (fence
&& fence
->rdev
== rdev
) {
418 r
= radeon_fence_wait(fence
, false);
420 up_read(&rdev
->exclusive_lock
);
422 r
= radeon_gpu_reset(rdev
);
423 } while (r
== -EAGAIN
);
424 down_read(&rdev
->exclusive_lock
);
427 r
= fence_wait(work
->fence
, false);
430 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r
);
432 /* We continue with the page flip even if we failed to wait on
433 * the fence, otherwise the DRM core and userspace will be
434 * confused about which BO the CRTC is scanning out
437 fence_put(work
->fence
);
441 /* We borrow the event spin lock for protecting flip_status */
442 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
444 /* set the proper interrupt */
445 radeon_irq_kms_pflip_irq_get(rdev
, radeon_crtc
->crtc_id
);
447 /* If this happens to execute within the "virtually extended" vblank
448 * interval before the start of the real vblank interval then it needs
449 * to delay programming the mmio flip until the real vblank is entered.
450 * This prevents completing a flip too early due to the way we fudge
451 * our vblank counter and vblank timestamps in order to work around the
452 * problem that the hw fires vblank interrupts before actual start of
453 * vblank (when line buffer refilling is done for a frame). It
454 * complements the fudging logic in radeon_get_crtc_scanoutpos() for
455 * timestamping and radeon_get_vblank_counter_kms() for vblank counts.
457 * In practice this won't execute very often unless on very fast
458 * machines because the time window for this to happen is very small.
460 while (radeon_crtc
->enabled
&& --repcnt
) {
461 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
462 * start in hpos, and to the "fudged earlier" vblank start in
465 stat
= radeon_get_crtc_scanoutpos(rdev
->ddev
, work
->crtc_id
,
466 GET_DISTANCE_TO_VBLANKSTART
,
467 &vpos
, &hpos
, NULL
, NULL
,
470 if ((stat
& (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
)) !=
471 (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
) ||
472 !(vpos
>= 0 && hpos
<= 0))
475 /* Sleep at least until estimated real start of hw vblank */
476 min_udelay
= (-hpos
+ 1) * max(vblank
->linedur_ns
/ 1000, 5);
477 if (min_udelay
> vblank
->framedur_ns
/ 2000) {
478 /* Don't wait ridiculously long - something is wrong */
482 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
483 usleep_range(min_udelay
, 2 * min_udelay
);
484 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
488 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, "
489 "framedur %d, linedur %d, stat %d, vpos %d, "
490 "hpos %d\n", work
->crtc_id
, min_udelay
,
491 vblank
->framedur_ns
/ 1000,
492 vblank
->linedur_ns
/ 1000, stat
, vpos
, hpos
);
494 /* do the flip (mmio) */
495 radeon_page_flip(rdev
, radeon_crtc
->crtc_id
, work
->base
, work
->async
);
497 radeon_crtc
->flip_status
= RADEON_FLIP_SUBMITTED
;
498 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
499 up_read(&rdev
->exclusive_lock
);
502 static int radeon_crtc_page_flip(struct drm_crtc
*crtc
,
503 struct drm_framebuffer
*fb
,
504 struct drm_pending_vblank_event
*event
,
505 uint32_t page_flip_flags
)
507 struct drm_device
*dev
= crtc
->dev
;
508 struct radeon_device
*rdev
= dev
->dev_private
;
509 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
510 struct radeon_framebuffer
*old_radeon_fb
;
511 struct radeon_framebuffer
*new_radeon_fb
;
512 struct drm_gem_object
*obj
;
513 struct radeon_flip_work
*work
;
514 struct radeon_bo
*new_rbo
;
515 uint32_t tiling_flags
, pitch_pixels
;
520 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
524 INIT_WORK(&work
->flip_work
, radeon_flip_work_func
);
525 INIT_WORK(&work
->unpin_work
, radeon_unpin_work_func
);
528 work
->crtc_id
= radeon_crtc
->crtc_id
;
530 work
->async
= (page_flip_flags
& DRM_MODE_PAGE_FLIP_ASYNC
) != 0;
532 /* schedule unpin of the old buffer */
533 old_radeon_fb
= to_radeon_framebuffer(crtc
->primary
->fb
);
534 obj
= old_radeon_fb
->obj
;
536 /* take a reference to the old object */
537 drm_gem_object_reference(obj
);
538 work
->old_rbo
= gem_to_radeon_bo(obj
);
540 new_radeon_fb
= to_radeon_framebuffer(fb
);
541 obj
= new_radeon_fb
->obj
;
542 new_rbo
= gem_to_radeon_bo(obj
);
544 /* pin the new buffer */
545 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
546 work
->old_rbo
, new_rbo
);
548 r
= radeon_bo_reserve(new_rbo
, false);
549 if (unlikely(r
!= 0)) {
550 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
553 /* Only 27 bit offset for legacy CRTC */
554 r
= radeon_bo_pin_restricted(new_rbo
, RADEON_GEM_DOMAIN_VRAM
,
555 ASIC_IS_AVIVO(rdev
) ? 0 : 1 << 27, &base
);
556 if (unlikely(r
!= 0)) {
557 radeon_bo_unreserve(new_rbo
);
559 DRM_ERROR("failed to pin new rbo buffer before flip\n");
562 work
->fence
= fence_get(reservation_object_get_excl(new_rbo
->tbo
.resv
));
563 radeon_bo_get_tiling_flags(new_rbo
, &tiling_flags
, NULL
);
564 radeon_bo_unreserve(new_rbo
);
566 if (!ASIC_IS_AVIVO(rdev
)) {
567 /* crtc offset is from display base addr not FB location */
568 base
-= radeon_crtc
->legacy_display_base_addr
;
569 pitch_pixels
= fb
->pitches
[0] / (fb
->bits_per_pixel
/ 8);
571 if (tiling_flags
& RADEON_TILING_MACRO
) {
572 if (ASIC_IS_R300(rdev
)) {
575 int byteshift
= fb
->bits_per_pixel
>> 4;
576 int tile_addr
= (((crtc
->y
>> 3) * pitch_pixels
+ crtc
->x
) >> (8 - byteshift
)) << 11;
577 base
+= tile_addr
+ ((crtc
->x
<< byteshift
) % 256) + ((crtc
->y
% 8) << 8);
580 int offset
= crtc
->y
* pitch_pixels
+ crtc
->x
;
581 switch (fb
->bits_per_pixel
) {
603 r
= drm_crtc_vblank_get(crtc
);
605 DRM_ERROR("failed to get vblank before flip\n");
609 /* We borrow the event spin lock for protecting flip_work */
610 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
612 if (radeon_crtc
->flip_status
!= RADEON_FLIP_NONE
) {
613 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
614 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
618 radeon_crtc
->flip_status
= RADEON_FLIP_PENDING
;
619 radeon_crtc
->flip_work
= work
;
622 crtc
->primary
->fb
= fb
;
624 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
626 queue_work(radeon_crtc
->flip_queue
, &work
->flip_work
);
630 drm_crtc_vblank_put(crtc
);
633 if (unlikely(radeon_bo_reserve(new_rbo
, false) != 0)) {
634 DRM_ERROR("failed to reserve new rbo in error path\n");
637 if (unlikely(radeon_bo_unpin(new_rbo
) != 0)) {
638 DRM_ERROR("failed to unpin new rbo in error path\n");
640 radeon_bo_unreserve(new_rbo
);
643 drm_gem_object_unreference_unlocked(&work
->old_rbo
->gem_base
);
644 fence_put(work
->fence
);
650 radeon_crtc_set_config(struct drm_mode_set
*set
)
652 struct drm_device
*dev
;
653 struct radeon_device
*rdev
;
654 struct drm_crtc
*crtc
;
658 if (!set
|| !set
->crtc
)
661 dev
= set
->crtc
->dev
;
663 ret
= pm_runtime_get_sync(dev
->dev
);
667 ret
= drm_crtc_helper_set_config(set
);
669 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
673 pm_runtime_mark_last_busy(dev
->dev
);
675 rdev
= dev
->dev_private
;
676 /* if we have active crtcs and we don't have a power ref,
677 take the current one */
678 if (active
&& !rdev
->have_disp_power_ref
) {
679 rdev
->have_disp_power_ref
= true;
682 /* if we have no active crtcs, then drop the power ref
684 if (!active
&& rdev
->have_disp_power_ref
) {
685 pm_runtime_put_autosuspend(dev
->dev
);
686 rdev
->have_disp_power_ref
= false;
689 /* drop the power reference we got coming in here */
690 pm_runtime_put_autosuspend(dev
->dev
);
694 static const struct drm_crtc_funcs radeon_crtc_funcs
= {
695 .cursor_set2
= radeon_crtc_cursor_set2
,
696 .cursor_move
= radeon_crtc_cursor_move
,
697 .gamma_set
= radeon_crtc_gamma_set
,
698 .set_config
= radeon_crtc_set_config
,
699 .destroy
= radeon_crtc_destroy
,
700 .page_flip
= radeon_crtc_page_flip
,
703 static void radeon_crtc_init(struct drm_device
*dev
, int index
)
705 struct radeon_device
*rdev
= dev
->dev_private
;
706 struct radeon_crtc
*radeon_crtc
;
709 radeon_crtc
= kzalloc(sizeof(struct radeon_crtc
) + (RADEONFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
710 if (radeon_crtc
== NULL
)
713 drm_crtc_init(dev
, &radeon_crtc
->base
, &radeon_crtc_funcs
);
715 drm_mode_crtc_set_gamma_size(&radeon_crtc
->base
, 256);
716 radeon_crtc
->crtc_id
= index
;
717 radeon_crtc
->flip_queue
= alloc_workqueue("radeon-crtc", WQ_HIGHPRI
, 0);
718 rdev
->mode_info
.crtcs
[index
] = radeon_crtc
;
720 if (rdev
->family
>= CHIP_BONAIRE
) {
721 radeon_crtc
->max_cursor_width
= CIK_CURSOR_WIDTH
;
722 radeon_crtc
->max_cursor_height
= CIK_CURSOR_HEIGHT
;
724 radeon_crtc
->max_cursor_width
= CURSOR_WIDTH
;
725 radeon_crtc
->max_cursor_height
= CURSOR_HEIGHT
;
727 dev
->mode_config
.cursor_width
= radeon_crtc
->max_cursor_width
;
728 dev
->mode_config
.cursor_height
= radeon_crtc
->max_cursor_height
;
731 radeon_crtc
->mode_set
.crtc
= &radeon_crtc
->base
;
732 radeon_crtc
->mode_set
.connectors
= (struct drm_connector
**)(radeon_crtc
+ 1);
733 radeon_crtc
->mode_set
.num_connectors
= 0;
736 for (i
= 0; i
< 256; i
++) {
737 radeon_crtc
->lut_r
[i
] = i
<< 2;
738 radeon_crtc
->lut_g
[i
] = i
<< 2;
739 radeon_crtc
->lut_b
[i
] = i
<< 2;
742 if (rdev
->is_atom_bios
&& (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
))
743 radeon_atombios_init_crtc(dev
, radeon_crtc
);
745 radeon_legacy_init_crtc(dev
, radeon_crtc
);
748 static const char *encoder_names
[38] = {
768 "INTERNAL_KLDSCP_TMDS1",
769 "INTERNAL_KLDSCP_DVO1",
770 "INTERNAL_KLDSCP_DAC1",
771 "INTERNAL_KLDSCP_DAC2",
780 "INTERNAL_KLDSCP_LVTMA",
789 static const char *hpd_names
[6] = {
798 static void radeon_print_display_setup(struct drm_device
*dev
)
800 struct drm_connector
*connector
;
801 struct radeon_connector
*radeon_connector
;
802 struct drm_encoder
*encoder
;
803 struct radeon_encoder
*radeon_encoder
;
807 DRM_INFO("Radeon Display Connectors\n");
808 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
809 radeon_connector
= to_radeon_connector(connector
);
810 DRM_INFO("Connector %d:\n", i
);
811 DRM_INFO(" %s\n", connector
->name
);
812 if (radeon_connector
->hpd
.hpd
!= RADEON_HPD_NONE
)
813 DRM_INFO(" %s\n", hpd_names
[radeon_connector
->hpd
.hpd
]);
814 if (radeon_connector
->ddc_bus
) {
815 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
816 radeon_connector
->ddc_bus
->rec
.mask_clk_reg
,
817 radeon_connector
->ddc_bus
->rec
.mask_data_reg
,
818 radeon_connector
->ddc_bus
->rec
.a_clk_reg
,
819 radeon_connector
->ddc_bus
->rec
.a_data_reg
,
820 radeon_connector
->ddc_bus
->rec
.en_clk_reg
,
821 radeon_connector
->ddc_bus
->rec
.en_data_reg
,
822 radeon_connector
->ddc_bus
->rec
.y_clk_reg
,
823 radeon_connector
->ddc_bus
->rec
.y_data_reg
);
824 if (radeon_connector
->router
.ddc_valid
)
825 DRM_INFO(" DDC Router 0x%x/0x%x\n",
826 radeon_connector
->router
.ddc_mux_control_pin
,
827 radeon_connector
->router
.ddc_mux_state
);
828 if (radeon_connector
->router
.cd_valid
)
829 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
830 radeon_connector
->router
.cd_mux_control_pin
,
831 radeon_connector
->router
.cd_mux_state
);
833 if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
||
834 connector
->connector_type
== DRM_MODE_CONNECTOR_DVII
||
835 connector
->connector_type
== DRM_MODE_CONNECTOR_DVID
||
836 connector
->connector_type
== DRM_MODE_CONNECTOR_DVIA
||
837 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIA
||
838 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIB
)
839 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
841 DRM_INFO(" Encoders:\n");
842 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
843 radeon_encoder
= to_radeon_encoder(encoder
);
844 devices
= radeon_encoder
->devices
& radeon_connector
->devices
;
846 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
847 DRM_INFO(" CRT1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
848 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
849 DRM_INFO(" CRT2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
850 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
851 DRM_INFO(" LCD1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
852 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
853 DRM_INFO(" DFP1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
854 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
855 DRM_INFO(" DFP2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
856 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
857 DRM_INFO(" DFP3: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
858 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
859 DRM_INFO(" DFP4: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
860 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
861 DRM_INFO(" DFP5: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
862 if (devices
& ATOM_DEVICE_DFP6_SUPPORT
)
863 DRM_INFO(" DFP6: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
864 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
865 DRM_INFO(" TV1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
866 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
867 DRM_INFO(" CV: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
874 static bool radeon_setup_enc_conn(struct drm_device
*dev
)
876 struct radeon_device
*rdev
= dev
->dev_private
;
880 if (rdev
->is_atom_bios
) {
881 ret
= radeon_get_atom_connector_info_from_supported_devices_table(dev
);
883 ret
= radeon_get_atom_connector_info_from_object_table(dev
);
885 ret
= radeon_get_legacy_connector_info_from_bios(dev
);
887 ret
= radeon_get_legacy_connector_info_from_table(dev
);
890 if (!ASIC_IS_AVIVO(rdev
))
891 ret
= radeon_get_legacy_connector_info_from_table(dev
);
894 radeon_setup_encoder_clones(dev
);
895 radeon_print_display_setup(dev
);
904 * avivo_reduce_ratio - fractional number reduction
908 * @nom_min: minimum value for nominator
909 * @den_min: minimum value for denominator
911 * Find the greatest common divisor and apply it on both nominator and
912 * denominator, but make nominator and denominator are at least as large
913 * as their minimum values.
915 static void avivo_reduce_ratio(unsigned *nom
, unsigned *den
,
916 unsigned nom_min
, unsigned den_min
)
920 /* reduce the numbers to a simpler ratio */
921 tmp
= gcd(*nom
, *den
);
925 /* make sure nominator is large enough */
926 if (*nom
< nom_min
) {
927 tmp
= DIV_ROUND_UP(nom_min
, *nom
);
932 /* make sure the denominator is large enough */
933 if (*den
< den_min
) {
934 tmp
= DIV_ROUND_UP(den_min
, *den
);
941 * avivo_get_fb_ref_div - feedback and ref divider calculation
945 * @post_div: post divider
946 * @fb_div_max: feedback divider maximum
947 * @ref_div_max: reference divider maximum
948 * @fb_div: resulting feedback divider
949 * @ref_div: resulting reference divider
951 * Calculate feedback and reference divider for a given post divider. Makes
952 * sure we stay within the limits.
954 static void avivo_get_fb_ref_div(unsigned nom
, unsigned den
, unsigned post_div
,
955 unsigned fb_div_max
, unsigned ref_div_max
,
956 unsigned *fb_div
, unsigned *ref_div
)
958 /* limit reference * post divider to a maximum */
959 ref_div_max
= max(min(100 / post_div
, ref_div_max
), 1u);
961 /* get matching reference and feedback divider */
962 *ref_div
= min(max(DIV_ROUND_CLOSEST(den
, post_div
), 1u), ref_div_max
);
963 *fb_div
= DIV_ROUND_CLOSEST(nom
* *ref_div
* post_div
, den
);
965 /* limit fb divider to its maximum */
966 if (*fb_div
> fb_div_max
) {
967 *ref_div
= DIV_ROUND_CLOSEST(*ref_div
* fb_div_max
, *fb_div
);
968 *fb_div
= fb_div_max
;
973 * radeon_compute_pll_avivo - compute PLL paramaters
975 * @pll: information about the PLL
976 * @dot_clock_p: resulting pixel clock
977 * fb_div_p: resulting feedback divider
978 * frac_fb_div_p: fractional part of the feedback divider
979 * ref_div_p: resulting reference divider
980 * post_div_p: resulting reference divider
982 * Try to calculate the PLL parameters to generate the given frequency:
983 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
985 void radeon_compute_pll_avivo(struct radeon_pll
*pll
,
993 unsigned target_clock
= pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
?
996 unsigned fb_div_min
, fb_div_max
, fb_div
;
997 unsigned post_div_min
, post_div_max
, post_div
;
998 unsigned ref_div_min
, ref_div_max
, ref_div
;
999 unsigned post_div_best
, diff_best
;
1002 /* determine allowed feedback divider range */
1003 fb_div_min
= pll
->min_feedback_div
;
1004 fb_div_max
= pll
->max_feedback_div
;
1006 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
1011 /* determine allowed ref divider range */
1012 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
1013 ref_div_min
= pll
->reference_div
;
1015 ref_div_min
= pll
->min_ref_div
;
1017 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
&&
1018 pll
->flags
& RADEON_PLL_USE_REF_DIV
)
1019 ref_div_max
= pll
->reference_div
;
1020 else if (pll
->flags
& RADEON_PLL_PREFER_MINM_OVER_MAXP
)
1021 /* fix for problems on RS880 */
1022 ref_div_max
= min(pll
->max_ref_div
, 7u);
1024 ref_div_max
= pll
->max_ref_div
;
1026 /* determine allowed post divider range */
1027 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
) {
1028 post_div_min
= pll
->post_div
;
1029 post_div_max
= pll
->post_div
;
1031 unsigned vco_min
, vco_max
;
1033 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
1034 vco_min
= pll
->lcd_pll_out_min
;
1035 vco_max
= pll
->lcd_pll_out_max
;
1037 vco_min
= pll
->pll_out_min
;
1038 vco_max
= pll
->pll_out_max
;
1041 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
1046 post_div_min
= vco_min
/ target_clock
;
1047 if ((target_clock
* post_div_min
) < vco_min
)
1049 if (post_div_min
< pll
->min_post_div
)
1050 post_div_min
= pll
->min_post_div
;
1052 post_div_max
= vco_max
/ target_clock
;
1053 if ((target_clock
* post_div_max
) > vco_max
)
1055 if (post_div_max
> pll
->max_post_div
)
1056 post_div_max
= pll
->max_post_div
;
1059 /* represent the searched ratio as fractional number */
1061 den
= pll
->reference_freq
;
1063 /* reduce the numbers to a simpler ratio */
1064 avivo_reduce_ratio(&nom
, &den
, fb_div_min
, post_div_min
);
1066 /* now search for a post divider */
1067 if (pll
->flags
& RADEON_PLL_PREFER_MINM_OVER_MAXP
)
1068 post_div_best
= post_div_min
;
1070 post_div_best
= post_div_max
;
1073 for (post_div
= post_div_min
; post_div
<= post_div_max
; ++post_div
) {
1075 avivo_get_fb_ref_div(nom
, den
, post_div
, fb_div_max
,
1076 ref_div_max
, &fb_div
, &ref_div
);
1077 diff
= abs(target_clock
- (pll
->reference_freq
* fb_div
) /
1078 (ref_div
* post_div
));
1080 if (diff
< diff_best
|| (diff
== diff_best
&&
1081 !(pll
->flags
& RADEON_PLL_PREFER_MINM_OVER_MAXP
))) {
1083 post_div_best
= post_div
;
1087 post_div
= post_div_best
;
1089 /* get the feedback and reference divider for the optimal value */
1090 avivo_get_fb_ref_div(nom
, den
, post_div
, fb_div_max
, ref_div_max
,
1093 /* reduce the numbers to a simpler ratio once more */
1094 /* this also makes sure that the reference divider is large enough */
1095 avivo_reduce_ratio(&fb_div
, &ref_div
, fb_div_min
, ref_div_min
);
1097 /* avoid high jitter with small fractional dividers */
1098 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
&& (fb_div
% 10)) {
1099 fb_div_min
= max(fb_div_min
, (9 - (fb_div
% 10)) * 20 + 50);
1100 if (fb_div
< fb_div_min
) {
1101 unsigned tmp
= DIV_ROUND_UP(fb_div_min
, fb_div
);
1107 /* and finally save the result */
1108 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
1109 *fb_div_p
= fb_div
/ 10;
1110 *frac_fb_div_p
= fb_div
% 10;
1116 *dot_clock_p
= ((pll
->reference_freq
* *fb_div_p
* 10) +
1117 (pll
->reference_freq
* *frac_fb_div_p
)) /
1118 (ref_div
* post_div
* 10);
1119 *ref_div_p
= ref_div
;
1120 *post_div_p
= post_div
;
1122 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1123 freq
, *dot_clock_p
* 10, *fb_div_p
, *frac_fb_div_p
,
1128 static inline uint32_t radeon_div(uint64_t n
, uint32_t d
)
1138 void radeon_compute_pll_legacy(struct radeon_pll
*pll
,
1140 uint32_t *dot_clock_p
,
1142 uint32_t *frac_fb_div_p
,
1143 uint32_t *ref_div_p
,
1144 uint32_t *post_div_p
)
1146 uint32_t min_ref_div
= pll
->min_ref_div
;
1147 uint32_t max_ref_div
= pll
->max_ref_div
;
1148 uint32_t min_post_div
= pll
->min_post_div
;
1149 uint32_t max_post_div
= pll
->max_post_div
;
1150 uint32_t min_fractional_feed_div
= 0;
1151 uint32_t max_fractional_feed_div
= 0;
1152 uint32_t best_vco
= pll
->best_vco
;
1153 uint32_t best_post_div
= 1;
1154 uint32_t best_ref_div
= 1;
1155 uint32_t best_feedback_div
= 1;
1156 uint32_t best_frac_feedback_div
= 0;
1157 uint32_t best_freq
= -1;
1158 uint32_t best_error
= 0xffffffff;
1159 uint32_t best_vco_diff
= 1;
1161 u32 pll_out_min
, pll_out_max
;
1163 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq
, pll
->min_ref_div
, pll
->max_ref_div
);
1166 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
1167 pll_out_min
= pll
->lcd_pll_out_min
;
1168 pll_out_max
= pll
->lcd_pll_out_max
;
1170 pll_out_min
= pll
->pll_out_min
;
1171 pll_out_max
= pll
->pll_out_max
;
1174 if (pll_out_min
> 64800)
1175 pll_out_min
= 64800;
1177 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
1178 min_ref_div
= max_ref_div
= pll
->reference_div
;
1180 while (min_ref_div
< max_ref_div
-1) {
1181 uint32_t mid
= (min_ref_div
+ max_ref_div
) / 2;
1182 uint32_t pll_in
= pll
->reference_freq
/ mid
;
1183 if (pll_in
< pll
->pll_in_min
)
1185 else if (pll_in
> pll
->pll_in_max
)
1192 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
1193 min_post_div
= max_post_div
= pll
->post_div
;
1195 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
1196 min_fractional_feed_div
= pll
->min_frac_feedback_div
;
1197 max_fractional_feed_div
= pll
->max_frac_feedback_div
;
1200 for (post_div
= max_post_div
; post_div
>= min_post_div
; --post_div
) {
1203 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
1206 /* legacy radeons only have a few post_divs */
1207 if (pll
->flags
& RADEON_PLL_LEGACY
) {
1208 if ((post_div
== 5) ||
1219 for (ref_div
= min_ref_div
; ref_div
<= max_ref_div
; ++ref_div
) {
1220 uint32_t feedback_div
, current_freq
= 0, error
, vco_diff
;
1221 uint32_t pll_in
= pll
->reference_freq
/ ref_div
;
1222 uint32_t min_feed_div
= pll
->min_feedback_div
;
1223 uint32_t max_feed_div
= pll
->max_feedback_div
+ 1;
1225 if (pll_in
< pll
->pll_in_min
|| pll_in
> pll
->pll_in_max
)
1228 while (min_feed_div
< max_feed_div
) {
1230 uint32_t min_frac_feed_div
= min_fractional_feed_div
;
1231 uint32_t max_frac_feed_div
= max_fractional_feed_div
+ 1;
1232 uint32_t frac_feedback_div
;
1235 feedback_div
= (min_feed_div
+ max_feed_div
) / 2;
1237 tmp
= (uint64_t)pll
->reference_freq
* feedback_div
;
1238 vco
= radeon_div(tmp
, ref_div
);
1240 if (vco
< pll_out_min
) {
1241 min_feed_div
= feedback_div
+ 1;
1243 } else if (vco
> pll_out_max
) {
1244 max_feed_div
= feedback_div
;
1248 while (min_frac_feed_div
< max_frac_feed_div
) {
1249 frac_feedback_div
= (min_frac_feed_div
+ max_frac_feed_div
) / 2;
1250 tmp
= (uint64_t)pll
->reference_freq
* 10000 * feedback_div
;
1251 tmp
+= (uint64_t)pll
->reference_freq
* 1000 * frac_feedback_div
;
1252 current_freq
= radeon_div(tmp
, ref_div
* post_div
);
1254 if (pll
->flags
& RADEON_PLL_PREFER_CLOSEST_LOWER
) {
1255 if (freq
< current_freq
)
1258 error
= freq
- current_freq
;
1260 error
= abs(current_freq
- freq
);
1261 vco_diff
= abs(vco
- best_vco
);
1263 if ((best_vco
== 0 && error
< best_error
) ||
1265 ((best_error
> 100 && error
< best_error
- 100) ||
1266 (abs(error
- best_error
) < 100 && vco_diff
< best_vco_diff
)))) {
1267 best_post_div
= post_div
;
1268 best_ref_div
= ref_div
;
1269 best_feedback_div
= feedback_div
;
1270 best_frac_feedback_div
= frac_feedback_div
;
1271 best_freq
= current_freq
;
1273 best_vco_diff
= vco_diff
;
1274 } else if (current_freq
== freq
) {
1275 if (best_freq
== -1) {
1276 best_post_div
= post_div
;
1277 best_ref_div
= ref_div
;
1278 best_feedback_div
= feedback_div
;
1279 best_frac_feedback_div
= frac_feedback_div
;
1280 best_freq
= current_freq
;
1282 best_vco_diff
= vco_diff
;
1283 } else if (((pll
->flags
& RADEON_PLL_PREFER_LOW_REF_DIV
) && (ref_div
< best_ref_div
)) ||
1284 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_REF_DIV
) && (ref_div
> best_ref_div
)) ||
1285 ((pll
->flags
& RADEON_PLL_PREFER_LOW_FB_DIV
) && (feedback_div
< best_feedback_div
)) ||
1286 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_FB_DIV
) && (feedback_div
> best_feedback_div
)) ||
1287 ((pll
->flags
& RADEON_PLL_PREFER_LOW_POST_DIV
) && (post_div
< best_post_div
)) ||
1288 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_POST_DIV
) && (post_div
> best_post_div
))) {
1289 best_post_div
= post_div
;
1290 best_ref_div
= ref_div
;
1291 best_feedback_div
= feedback_div
;
1292 best_frac_feedback_div
= frac_feedback_div
;
1293 best_freq
= current_freq
;
1295 best_vco_diff
= vco_diff
;
1298 if (current_freq
< freq
)
1299 min_frac_feed_div
= frac_feedback_div
+ 1;
1301 max_frac_feed_div
= frac_feedback_div
;
1303 if (current_freq
< freq
)
1304 min_feed_div
= feedback_div
+ 1;
1306 max_feed_div
= feedback_div
;
1311 *dot_clock_p
= best_freq
/ 10000;
1312 *fb_div_p
= best_feedback_div
;
1313 *frac_fb_div_p
= best_frac_feedback_div
;
1314 *ref_div_p
= best_ref_div
;
1315 *post_div_p
= best_post_div
;
1316 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1318 best_freq
/ 1000, best_feedback_div
, best_frac_feedback_div
,
1319 best_ref_div
, best_post_div
);
1323 static void radeon_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
1325 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
1327 drm_gem_object_unreference_unlocked(radeon_fb
->obj
);
1328 drm_framebuffer_cleanup(fb
);
1332 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
1333 struct drm_file
*file_priv
,
1334 unsigned int *handle
)
1336 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
1338 return drm_gem_handle_create(file_priv
, radeon_fb
->obj
, handle
);
1341 static const struct drm_framebuffer_funcs radeon_fb_funcs
= {
1342 .destroy
= radeon_user_framebuffer_destroy
,
1343 .create_handle
= radeon_user_framebuffer_create_handle
,
1347 radeon_framebuffer_init(struct drm_device
*dev
,
1348 struct radeon_framebuffer
*rfb
,
1349 const struct drm_mode_fb_cmd2
*mode_cmd
,
1350 struct drm_gem_object
*obj
)
1354 drm_helper_mode_fill_fb_struct(&rfb
->base
, mode_cmd
);
1355 ret
= drm_framebuffer_init(dev
, &rfb
->base
, &radeon_fb_funcs
);
1363 static struct drm_framebuffer
*
1364 radeon_user_framebuffer_create(struct drm_device
*dev
,
1365 struct drm_file
*file_priv
,
1366 const struct drm_mode_fb_cmd2
*mode_cmd
)
1368 struct drm_gem_object
*obj
;
1369 struct radeon_framebuffer
*radeon_fb
;
1372 obj
= drm_gem_object_lookup(file_priv
, mode_cmd
->handles
[0]);
1374 dev_err(&dev
->pdev
->dev
, "No GEM object associated to handle 0x%08X, "
1375 "can't create framebuffer\n", mode_cmd
->handles
[0]);
1376 return ERR_PTR(-ENOENT
);
1379 radeon_fb
= kzalloc(sizeof(*radeon_fb
), GFP_KERNEL
);
1380 if (radeon_fb
== NULL
) {
1381 drm_gem_object_unreference_unlocked(obj
);
1382 return ERR_PTR(-ENOMEM
);
1385 ret
= radeon_framebuffer_init(dev
, radeon_fb
, mode_cmd
, obj
);
1388 drm_gem_object_unreference_unlocked(obj
);
1389 return ERR_PTR(ret
);
1392 return &radeon_fb
->base
;
1395 static void radeon_output_poll_changed(struct drm_device
*dev
)
1397 struct radeon_device
*rdev
= dev
->dev_private
;
1398 radeon_fb_output_poll_changed(rdev
);
1401 static const struct drm_mode_config_funcs radeon_mode_funcs
= {
1402 .fb_create
= radeon_user_framebuffer_create
,
1403 .output_poll_changed
= radeon_output_poll_changed
1406 static struct drm_prop_enum_list radeon_tmds_pll_enum_list
[] =
1411 static struct drm_prop_enum_list radeon_tv_std_enum_list
[] =
1412 { { TV_STD_NTSC
, "ntsc" },
1413 { TV_STD_PAL
, "pal" },
1414 { TV_STD_PAL_M
, "pal-m" },
1415 { TV_STD_PAL_60
, "pal-60" },
1416 { TV_STD_NTSC_J
, "ntsc-j" },
1417 { TV_STD_SCART_PAL
, "scart-pal" },
1418 { TV_STD_PAL_CN
, "pal-cn" },
1419 { TV_STD_SECAM
, "secam" },
1422 static struct drm_prop_enum_list radeon_underscan_enum_list
[] =
1423 { { UNDERSCAN_OFF
, "off" },
1424 { UNDERSCAN_ON
, "on" },
1425 { UNDERSCAN_AUTO
, "auto" },
1428 static struct drm_prop_enum_list radeon_audio_enum_list
[] =
1429 { { RADEON_AUDIO_DISABLE
, "off" },
1430 { RADEON_AUDIO_ENABLE
, "on" },
1431 { RADEON_AUDIO_AUTO
, "auto" },
1434 /* XXX support different dither options? spatial, temporal, both, etc. */
1435 static struct drm_prop_enum_list radeon_dither_enum_list
[] =
1436 { { RADEON_FMT_DITHER_DISABLE
, "off" },
1437 { RADEON_FMT_DITHER_ENABLE
, "on" },
1440 static struct drm_prop_enum_list radeon_output_csc_enum_list
[] =
1441 { { RADEON_OUTPUT_CSC_BYPASS
, "bypass" },
1442 { RADEON_OUTPUT_CSC_TVRGB
, "tvrgb" },
1443 { RADEON_OUTPUT_CSC_YCBCR601
, "ycbcr601" },
1444 { RADEON_OUTPUT_CSC_YCBCR709
, "ycbcr709" },
1447 static int radeon_modeset_create_props(struct radeon_device
*rdev
)
1451 if (rdev
->is_atom_bios
) {
1452 rdev
->mode_info
.coherent_mode_property
=
1453 drm_property_create_range(rdev
->ddev
, 0 , "coherent", 0, 1);
1454 if (!rdev
->mode_info
.coherent_mode_property
)
1458 if (!ASIC_IS_AVIVO(rdev
)) {
1459 sz
= ARRAY_SIZE(radeon_tmds_pll_enum_list
);
1460 rdev
->mode_info
.tmds_pll_property
=
1461 drm_property_create_enum(rdev
->ddev
, 0,
1463 radeon_tmds_pll_enum_list
, sz
);
1466 rdev
->mode_info
.load_detect_property
=
1467 drm_property_create_range(rdev
->ddev
, 0, "load detection", 0, 1);
1468 if (!rdev
->mode_info
.load_detect_property
)
1471 drm_mode_create_scaling_mode_property(rdev
->ddev
);
1473 sz
= ARRAY_SIZE(radeon_tv_std_enum_list
);
1474 rdev
->mode_info
.tv_std_property
=
1475 drm_property_create_enum(rdev
->ddev
, 0,
1477 radeon_tv_std_enum_list
, sz
);
1479 sz
= ARRAY_SIZE(radeon_underscan_enum_list
);
1480 rdev
->mode_info
.underscan_property
=
1481 drm_property_create_enum(rdev
->ddev
, 0,
1483 radeon_underscan_enum_list
, sz
);
1485 rdev
->mode_info
.underscan_hborder_property
=
1486 drm_property_create_range(rdev
->ddev
, 0,
1487 "underscan hborder", 0, 128);
1488 if (!rdev
->mode_info
.underscan_hborder_property
)
1491 rdev
->mode_info
.underscan_vborder_property
=
1492 drm_property_create_range(rdev
->ddev
, 0,
1493 "underscan vborder", 0, 128);
1494 if (!rdev
->mode_info
.underscan_vborder_property
)
1497 sz
= ARRAY_SIZE(radeon_audio_enum_list
);
1498 rdev
->mode_info
.audio_property
=
1499 drm_property_create_enum(rdev
->ddev
, 0,
1501 radeon_audio_enum_list
, sz
);
1503 sz
= ARRAY_SIZE(radeon_dither_enum_list
);
1504 rdev
->mode_info
.dither_property
=
1505 drm_property_create_enum(rdev
->ddev
, 0,
1507 radeon_dither_enum_list
, sz
);
1509 sz
= ARRAY_SIZE(radeon_output_csc_enum_list
);
1510 rdev
->mode_info
.output_csc_property
=
1511 drm_property_create_enum(rdev
->ddev
, 0,
1513 radeon_output_csc_enum_list
, sz
);
1518 void radeon_update_display_priority(struct radeon_device
*rdev
)
1520 /* adjustment options for the display watermarks */
1521 if ((radeon_disp_priority
== 0) || (radeon_disp_priority
> 2)) {
1522 /* set display priority to high for r3xx, rv515 chips
1523 * this avoids flickering due to underflow to the
1524 * display controllers during heavy acceleration.
1525 * Don't force high on rs4xx igp chips as it seems to
1526 * affect the sound card. See kernel bug 15982.
1528 if ((ASIC_IS_R300(rdev
) || (rdev
->family
== CHIP_RV515
)) &&
1529 !(rdev
->flags
& RADEON_IS_IGP
))
1530 rdev
->disp_priority
= 2;
1532 rdev
->disp_priority
= 0;
1534 rdev
->disp_priority
= radeon_disp_priority
;
1539 * Allocate hdmi structs and determine register offsets
1541 static void radeon_afmt_init(struct radeon_device
*rdev
)
1545 for (i
= 0; i
< RADEON_MAX_AFMT_BLOCKS
; i
++)
1546 rdev
->mode_info
.afmt
[i
] = NULL
;
1548 if (ASIC_IS_NODCE(rdev
)) {
1550 } else if (ASIC_IS_DCE4(rdev
)) {
1551 static uint32_t eg_offsets
[] = {
1552 EVERGREEN_CRTC0_REGISTER_OFFSET
,
1553 EVERGREEN_CRTC1_REGISTER_OFFSET
,
1554 EVERGREEN_CRTC2_REGISTER_OFFSET
,
1555 EVERGREEN_CRTC3_REGISTER_OFFSET
,
1556 EVERGREEN_CRTC4_REGISTER_OFFSET
,
1557 EVERGREEN_CRTC5_REGISTER_OFFSET
,
1562 /* DCE8 has 7 audio blocks tied to DIG encoders */
1563 /* DCE6 has 6 audio blocks tied to DIG encoders */
1564 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1565 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1566 if (ASIC_IS_DCE8(rdev
))
1568 else if (ASIC_IS_DCE6(rdev
))
1570 else if (ASIC_IS_DCE5(rdev
))
1572 else if (ASIC_IS_DCE41(rdev
))
1577 BUG_ON(num_afmt
> ARRAY_SIZE(eg_offsets
));
1578 for (i
= 0; i
< num_afmt
; i
++) {
1579 rdev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1580 if (rdev
->mode_info
.afmt
[i
]) {
1581 rdev
->mode_info
.afmt
[i
]->offset
= eg_offsets
[i
];
1582 rdev
->mode_info
.afmt
[i
]->id
= i
;
1585 } else if (ASIC_IS_DCE3(rdev
)) {
1586 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1587 rdev
->mode_info
.afmt
[0] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1588 if (rdev
->mode_info
.afmt
[0]) {
1589 rdev
->mode_info
.afmt
[0]->offset
= DCE3_HDMI_OFFSET0
;
1590 rdev
->mode_info
.afmt
[0]->id
= 0;
1592 rdev
->mode_info
.afmt
[1] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1593 if (rdev
->mode_info
.afmt
[1]) {
1594 rdev
->mode_info
.afmt
[1]->offset
= DCE3_HDMI_OFFSET1
;
1595 rdev
->mode_info
.afmt
[1]->id
= 1;
1597 } else if (ASIC_IS_DCE2(rdev
)) {
1598 /* DCE2 has at least 1 routable audio block */
1599 rdev
->mode_info
.afmt
[0] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1600 if (rdev
->mode_info
.afmt
[0]) {
1601 rdev
->mode_info
.afmt
[0]->offset
= DCE2_HDMI_OFFSET0
;
1602 rdev
->mode_info
.afmt
[0]->id
= 0;
1604 /* r6xx has 2 routable audio blocks */
1605 if (rdev
->family
>= CHIP_R600
) {
1606 rdev
->mode_info
.afmt
[1] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1607 if (rdev
->mode_info
.afmt
[1]) {
1608 rdev
->mode_info
.afmt
[1]->offset
= DCE2_HDMI_OFFSET1
;
1609 rdev
->mode_info
.afmt
[1]->id
= 1;
1615 static void radeon_afmt_fini(struct radeon_device
*rdev
)
1619 for (i
= 0; i
< RADEON_MAX_AFMT_BLOCKS
; i
++) {
1620 kfree(rdev
->mode_info
.afmt
[i
]);
1621 rdev
->mode_info
.afmt
[i
] = NULL
;
1625 int radeon_modeset_init(struct radeon_device
*rdev
)
1630 drm_mode_config_init(rdev
->ddev
);
1631 rdev
->mode_info
.mode_config_initialized
= true;
1633 rdev
->ddev
->mode_config
.funcs
= &radeon_mode_funcs
;
1635 if (radeon_use_pflipirq
== 2 && rdev
->family
>= CHIP_R600
)
1636 rdev
->ddev
->mode_config
.async_page_flip
= true;
1638 if (ASIC_IS_DCE5(rdev
)) {
1639 rdev
->ddev
->mode_config
.max_width
= 16384;
1640 rdev
->ddev
->mode_config
.max_height
= 16384;
1641 } else if (ASIC_IS_AVIVO(rdev
)) {
1642 rdev
->ddev
->mode_config
.max_width
= 8192;
1643 rdev
->ddev
->mode_config
.max_height
= 8192;
1645 rdev
->ddev
->mode_config
.max_width
= 4096;
1646 rdev
->ddev
->mode_config
.max_height
= 4096;
1649 rdev
->ddev
->mode_config
.preferred_depth
= 24;
1650 rdev
->ddev
->mode_config
.prefer_shadow
= 1;
1652 rdev
->ddev
->mode_config
.fb_base
= rdev
->mc
.aper_base
;
1654 ret
= radeon_modeset_create_props(rdev
);
1659 /* init i2c buses */
1660 radeon_i2c_init(rdev
);
1662 /* check combios for a valid hardcoded EDID - Sun servers */
1663 if (!rdev
->is_atom_bios
) {
1664 /* check for hardcoded EDID in BIOS */
1665 radeon_combios_check_hardcoded_edid(rdev
);
1668 /* allocate crtcs */
1669 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1670 radeon_crtc_init(rdev
->ddev
, i
);
1673 /* okay we should have all the bios connectors */
1674 ret
= radeon_setup_enc_conn(rdev
->ddev
);
1679 /* init dig PHYs, disp eng pll */
1680 if (rdev
->is_atom_bios
) {
1681 radeon_atom_encoder_init(rdev
);
1682 radeon_atom_disp_eng_pll_init(rdev
);
1685 /* initialize hpd */
1686 radeon_hpd_init(rdev
);
1689 radeon_afmt_init(rdev
);
1691 radeon_fbdev_init(rdev
);
1692 drm_kms_helper_poll_init(rdev
->ddev
);
1694 /* do pm late init */
1695 ret
= radeon_pm_late_init(rdev
);
1700 void radeon_modeset_fini(struct radeon_device
*rdev
)
1702 radeon_fbdev_fini(rdev
);
1703 kfree(rdev
->mode_info
.bios_hardcoded_edid
);
1705 /* free i2c buses */
1706 radeon_i2c_fini(rdev
);
1708 if (rdev
->mode_info
.mode_config_initialized
) {
1709 radeon_afmt_fini(rdev
);
1710 drm_kms_helper_poll_fini(rdev
->ddev
);
1711 radeon_hpd_fini(rdev
);
1712 drm_crtc_force_disable_all(rdev
->ddev
);
1713 drm_mode_config_cleanup(rdev
->ddev
);
1714 rdev
->mode_info
.mode_config_initialized
= false;
1718 static bool is_hdtv_mode(const struct drm_display_mode
*mode
)
1720 /* try and guess if this is a tv or a monitor */
1721 if ((mode
->vdisplay
== 480 && mode
->hdisplay
== 720) || /* 480p */
1722 (mode
->vdisplay
== 576) || /* 576p */
1723 (mode
->vdisplay
== 720) || /* 720p */
1724 (mode
->vdisplay
== 1080)) /* 1080p */
1730 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
1731 const struct drm_display_mode
*mode
,
1732 struct drm_display_mode
*adjusted_mode
)
1734 struct drm_device
*dev
= crtc
->dev
;
1735 struct radeon_device
*rdev
= dev
->dev_private
;
1736 struct drm_encoder
*encoder
;
1737 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1738 struct radeon_encoder
*radeon_encoder
;
1739 struct drm_connector
*connector
;
1740 struct radeon_connector
*radeon_connector
;
1742 u32 src_v
= 1, dst_v
= 1;
1743 u32 src_h
= 1, dst_h
= 1;
1745 radeon_crtc
->h_border
= 0;
1746 radeon_crtc
->v_border
= 0;
1748 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1749 if (encoder
->crtc
!= crtc
)
1751 radeon_encoder
= to_radeon_encoder(encoder
);
1752 connector
= radeon_get_connector_for_encoder(encoder
);
1753 radeon_connector
= to_radeon_connector(connector
);
1757 if (radeon_encoder
->rmx_type
== RMX_OFF
)
1758 radeon_crtc
->rmx_type
= RMX_OFF
;
1759 else if (mode
->hdisplay
< radeon_encoder
->native_mode
.hdisplay
||
1760 mode
->vdisplay
< radeon_encoder
->native_mode
.vdisplay
)
1761 radeon_crtc
->rmx_type
= radeon_encoder
->rmx_type
;
1763 radeon_crtc
->rmx_type
= RMX_OFF
;
1764 /* copy native mode */
1765 memcpy(&radeon_crtc
->native_mode
,
1766 &radeon_encoder
->native_mode
,
1767 sizeof(struct drm_display_mode
));
1768 src_v
= crtc
->mode
.vdisplay
;
1769 dst_v
= radeon_crtc
->native_mode
.vdisplay
;
1770 src_h
= crtc
->mode
.hdisplay
;
1771 dst_h
= radeon_crtc
->native_mode
.hdisplay
;
1773 /* fix up for overscan on hdmi */
1774 if (ASIC_IS_AVIVO(rdev
) &&
1775 (!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
)) &&
1776 ((radeon_encoder
->underscan_type
== UNDERSCAN_ON
) ||
1777 ((radeon_encoder
->underscan_type
== UNDERSCAN_AUTO
) &&
1778 drm_detect_hdmi_monitor(radeon_connector_edid(connector
)) &&
1779 is_hdtv_mode(mode
)))) {
1780 if (radeon_encoder
->underscan_hborder
!= 0)
1781 radeon_crtc
->h_border
= radeon_encoder
->underscan_hborder
;
1783 radeon_crtc
->h_border
= (mode
->hdisplay
>> 5) + 16;
1784 if (radeon_encoder
->underscan_vborder
!= 0)
1785 radeon_crtc
->v_border
= radeon_encoder
->underscan_vborder
;
1787 radeon_crtc
->v_border
= (mode
->vdisplay
>> 5) + 16;
1788 radeon_crtc
->rmx_type
= RMX_FULL
;
1789 src_v
= crtc
->mode
.vdisplay
;
1790 dst_v
= crtc
->mode
.vdisplay
- (radeon_crtc
->v_border
* 2);
1791 src_h
= crtc
->mode
.hdisplay
;
1792 dst_h
= crtc
->mode
.hdisplay
- (radeon_crtc
->h_border
* 2);
1796 if (radeon_crtc
->rmx_type
!= radeon_encoder
->rmx_type
) {
1797 /* WARNING: Right now this can't happen but
1798 * in the future we need to check that scaling
1799 * are consistent across different encoder
1800 * (ie all encoder can work with the same
1803 DRM_ERROR("Scaling not consistent across encoder.\n");
1808 if (radeon_crtc
->rmx_type
!= RMX_OFF
) {
1810 a
.full
= dfixed_const(src_v
);
1811 b
.full
= dfixed_const(dst_v
);
1812 radeon_crtc
->vsc
.full
= dfixed_div(a
, b
);
1813 a
.full
= dfixed_const(src_h
);
1814 b
.full
= dfixed_const(dst_h
);
1815 radeon_crtc
->hsc
.full
= dfixed_div(a
, b
);
1817 radeon_crtc
->vsc
.full
= dfixed_const(1);
1818 radeon_crtc
->hsc
.full
= dfixed_const(1);
1824 * Retrieve current video scanout position of crtc on a given gpu, and
1825 * an optional accurate timestamp of when query happened.
1827 * \param dev Device to query.
1828 * \param crtc Crtc to query.
1829 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1830 * For driver internal use only also supports these flags:
1832 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1833 * of a fudged earlier start of vblank.
1835 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1836 * fudged earlier start of vblank in *vpos and the distance
1837 * to true start of vblank in *hpos.
1839 * \param *vpos Location where vertical scanout position should be stored.
1840 * \param *hpos Location where horizontal scanout position should go.
1841 * \param *stime Target location for timestamp taken immediately before
1842 * scanout position query. Can be NULL to skip timestamp.
1843 * \param *etime Target location for timestamp taken immediately after
1844 * scanout position query. Can be NULL to skip timestamp.
1846 * Returns vpos as a positive number while in active scanout area.
1847 * Returns vpos as a negative number inside vblank, counting the number
1848 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1849 * until start of active scanout / end of vblank."
1851 * \return Flags, or'ed together as follows:
1853 * DRM_SCANOUTPOS_VALID = Query successful.
1854 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1855 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1856 * this flag means that returned position may be offset by a constant but
1857 * unknown small number of scanlines wrt. real scanout position.
1860 int radeon_get_crtc_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
1861 unsigned int flags
, int *vpos
, int *hpos
,
1862 ktime_t
*stime
, ktime_t
*etime
,
1863 const struct drm_display_mode
*mode
)
1865 u32 stat_crtc
= 0, vbl
= 0, position
= 0;
1866 int vbl_start
, vbl_end
, vtotal
, ret
= 0;
1869 struct radeon_device
*rdev
= dev
->dev_private
;
1871 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1873 /* Get optional system timestamp before query. */
1875 *stime
= ktime_get();
1877 if (ASIC_IS_DCE4(rdev
)) {
1879 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1880 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1881 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1882 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1883 ret
|= DRM_SCANOUTPOS_VALID
;
1886 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1887 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1888 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1889 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1890 ret
|= DRM_SCANOUTPOS_VALID
;
1893 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1894 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1895 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1896 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1897 ret
|= DRM_SCANOUTPOS_VALID
;
1900 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1901 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1902 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1903 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1904 ret
|= DRM_SCANOUTPOS_VALID
;
1907 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1908 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1909 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1910 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1911 ret
|= DRM_SCANOUTPOS_VALID
;
1914 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1915 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1916 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1917 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1918 ret
|= DRM_SCANOUTPOS_VALID
;
1920 } else if (ASIC_IS_AVIVO(rdev
)) {
1922 vbl
= RREG32(AVIVO_D1CRTC_V_BLANK_START_END
);
1923 position
= RREG32(AVIVO_D1CRTC_STATUS_POSITION
);
1924 ret
|= DRM_SCANOUTPOS_VALID
;
1927 vbl
= RREG32(AVIVO_D2CRTC_V_BLANK_START_END
);
1928 position
= RREG32(AVIVO_D2CRTC_STATUS_POSITION
);
1929 ret
|= DRM_SCANOUTPOS_VALID
;
1932 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1934 /* Assume vbl_end == 0, get vbl_start from
1937 vbl
= (RREG32(RADEON_CRTC_V_TOTAL_DISP
) &
1938 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1939 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1940 position
= (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1941 stat_crtc
= RREG32(RADEON_CRTC_STATUS
);
1942 if (!(stat_crtc
& 1))
1945 ret
|= DRM_SCANOUTPOS_VALID
;
1948 vbl
= (RREG32(RADEON_CRTC2_V_TOTAL_DISP
) &
1949 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1950 position
= (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1951 stat_crtc
= RREG32(RADEON_CRTC2_STATUS
);
1952 if (!(stat_crtc
& 1))
1955 ret
|= DRM_SCANOUTPOS_VALID
;
1959 /* Get optional system timestamp after query. */
1961 *etime
= ktime_get();
1963 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1965 /* Decode into vertical and horizontal scanout position. */
1966 *vpos
= position
& 0x1fff;
1967 *hpos
= (position
>> 16) & 0x1fff;
1969 /* Valid vblank area boundaries from gpu retrieved? */
1972 ret
|= DRM_SCANOUTPOS_ACCURATE
;
1973 vbl_start
= vbl
& 0x1fff;
1974 vbl_end
= (vbl
>> 16) & 0x1fff;
1977 /* No: Fake something reasonable which gives at least ok results. */
1978 vbl_start
= mode
->crtc_vdisplay
;
1982 /* Called from driver internal vblank counter query code? */
1983 if (flags
& GET_DISTANCE_TO_VBLANKSTART
) {
1984 /* Caller wants distance from real vbl_start in *hpos */
1985 *hpos
= *vpos
- vbl_start
;
1988 /* Fudge vblank to start a few scanlines earlier to handle the
1989 * problem that vblank irqs fire a few scanlines before start
1990 * of vblank. Some driver internal callers need the true vblank
1991 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1993 * The cause of the "early" vblank irq is that the irq is triggered
1994 * by the line buffer logic when the line buffer read position enters
1995 * the vblank, whereas our crtc scanout position naturally lags the
1996 * line buffer read position.
1998 if (!(flags
& USE_REAL_VBLANKSTART
))
1999 vbl_start
-= rdev
->mode_info
.crtcs
[pipe
]->lb_vblank_lead_lines
;
2001 /* Test scanout position against vblank region. */
2002 if ((*vpos
< vbl_start
) && (*vpos
>= vbl_end
))
2007 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
2009 /* Called from driver internal vblank counter query code? */
2010 if (flags
& GET_DISTANCE_TO_VBLANKSTART
) {
2011 /* Caller wants distance from fudged earlier vbl_start */
2016 /* Check if inside vblank area and apply corrective offsets:
2017 * vpos will then be >=0 in video scanout area, but negative
2018 * within vblank area, counting down the number of lines until
2022 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
2023 if (in_vbl
&& (*vpos
>= vbl_start
)) {
2024 vtotal
= mode
->crtc_vtotal
;
2025 *vpos
= *vpos
- vtotal
;
2028 /* Correct for shifted end of vbl at vbl_end. */
2029 *vpos
= *vpos
- vbl_end
;