2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
35 bool radeon_ddc_probe(struct radeon_connector
*radeon_connector
)
37 u8 out_buf
[] = { 0x0, 0x0};
40 struct i2c_msg msgs
[] = {
55 /* on hw with routers, select right port */
56 if (radeon_connector
->router
.valid
)
57 radeon_router_select_port(radeon_connector
);
59 ret
= i2c_transfer(&radeon_connector
->ddc_bus
->adapter
, msgs
, 2);
68 static void radeon_i2c_do_lock(struct radeon_i2c_chan
*i2c
, int lock_state
)
70 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
71 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
74 /* RV410 appears to have a bug where the hw i2c in reset
75 * holds the i2c port in a bad state - switch hw i2c away before
76 * doing DDC - do this for all r200s/r300s/r400s for safety sake
78 if (rec
->hw_capable
) {
79 if ((rdev
->family
>= CHIP_R200
) && !ASIC_IS_AVIVO(rdev
)) {
82 if (rdev
->family
>= CHIP_RV350
)
83 reg
= RADEON_GPIO_MONID
;
84 else if ((rdev
->family
== CHIP_R300
) ||
85 (rdev
->family
== CHIP_R350
))
86 reg
= RADEON_GPIO_DVI_DDC
;
88 reg
= RADEON_GPIO_CRT2_DDC
;
90 mutex_lock(&rdev
->dc_hw_i2c_mutex
);
91 if (rec
->a_clk_reg
== reg
) {
92 WREG32(RADEON_DVI_I2C_CNTL_0
, (RADEON_I2C_SOFT_RST
|
93 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
)));
95 WREG32(RADEON_DVI_I2C_CNTL_0
, (RADEON_I2C_SOFT_RST
|
96 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
)));
98 mutex_unlock(&rdev
->dc_hw_i2c_mutex
);
102 /* clear the output pin values */
103 temp
= RREG32(rec
->a_clk_reg
) & ~rec
->a_clk_mask
;
104 WREG32(rec
->a_clk_reg
, temp
);
106 temp
= RREG32(rec
->a_data_reg
) & ~rec
->a_data_mask
;
107 WREG32(rec
->a_data_reg
, temp
);
109 /* set the pins to input */
110 temp
= RREG32(rec
->en_clk_reg
) & ~rec
->en_clk_mask
;
111 WREG32(rec
->en_clk_reg
, temp
);
113 temp
= RREG32(rec
->en_data_reg
) & ~rec
->en_data_mask
;
114 WREG32(rec
->en_data_reg
, temp
);
116 /* mask the gpio pins for software use */
117 temp
= RREG32(rec
->mask_clk_reg
);
119 temp
|= rec
->mask_clk_mask
;
121 temp
&= ~rec
->mask_clk_mask
;
122 WREG32(rec
->mask_clk_reg
, temp
);
123 temp
= RREG32(rec
->mask_clk_reg
);
125 temp
= RREG32(rec
->mask_data_reg
);
127 temp
|= rec
->mask_data_mask
;
129 temp
&= ~rec
->mask_data_mask
;
130 WREG32(rec
->mask_data_reg
, temp
);
131 temp
= RREG32(rec
->mask_data_reg
);
134 static int get_clock(void *i2c_priv
)
136 struct radeon_i2c_chan
*i2c
= i2c_priv
;
137 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
138 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
141 /* read the value off the pin */
142 val
= RREG32(rec
->y_clk_reg
);
143 val
&= rec
->y_clk_mask
;
149 static int get_data(void *i2c_priv
)
151 struct radeon_i2c_chan
*i2c
= i2c_priv
;
152 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
153 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
156 /* read the value off the pin */
157 val
= RREG32(rec
->y_data_reg
);
158 val
&= rec
->y_data_mask
;
163 static void set_clock(void *i2c_priv
, int clock
)
165 struct radeon_i2c_chan
*i2c
= i2c_priv
;
166 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
167 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
170 /* set pin direction */
171 val
= RREG32(rec
->en_clk_reg
) & ~rec
->en_clk_mask
;
172 val
|= clock
? 0 : rec
->en_clk_mask
;
173 WREG32(rec
->en_clk_reg
, val
);
176 static void set_data(void *i2c_priv
, int data
)
178 struct radeon_i2c_chan
*i2c
= i2c_priv
;
179 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
180 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
183 /* set pin direction */
184 val
= RREG32(rec
->en_data_reg
) & ~rec
->en_data_mask
;
185 val
|= data
? 0 : rec
->en_data_mask
;
186 WREG32(rec
->en_data_reg
, val
);
189 static int pre_xfer(struct i2c_adapter
*i2c_adap
)
191 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
193 radeon_i2c_do_lock(i2c
, 1);
198 static void post_xfer(struct i2c_adapter
*i2c_adap
)
200 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
202 radeon_i2c_do_lock(i2c
, 0);
207 static u32
radeon_get_i2c_prescale(struct radeon_device
*rdev
)
209 u32 sclk
= radeon_get_engine_clock(rdev
);
215 switch (rdev
->family
) {
229 nm
= (sclk
* 10) / (i2c_clock
* 4);
230 for (loop
= 1; loop
< 255; loop
++) {
231 if ((nm
/ loop
) < loop
)
236 prescale
= m
| (n
<< 8);
244 prescale
= (((sclk
* 10)/(4 * 128 * 100) + 1) << 8) + 128;
258 if (rdev
->family
== CHIP_R520
)
259 prescale
= (127 << 8) + ((sclk
* 10) / (4 * 127 * i2c_clock
));
261 prescale
= (((sclk
* 10)/(4 * 128 * 100) + 1) << 8) + 128;
287 DRM_ERROR("i2c: unhandled radeon chip\n");
294 /* hw i2c engine for r1xx-4xx hardware
295 * hw can buffer up to 15 bytes
297 static int r100_hw_i2c_xfer(struct i2c_adapter
*i2c_adap
,
298 struct i2c_msg
*msgs
, int num
)
300 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
301 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
302 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
304 int i
, j
, k
, ret
= num
;
306 u32 i2c_cntl_0
, i2c_cntl_1
, i2c_data
;
309 mutex_lock(&rdev
->dc_hw_i2c_mutex
);
310 /* take the pm lock since we need a constant sclk */
311 mutex_lock(&rdev
->pm
.mutex
);
313 prescale
= radeon_get_i2c_prescale(rdev
);
315 reg
= ((prescale
<< RADEON_I2C_PRESCALE_SHIFT
) |
316 RADEON_I2C_DRIVE_EN
|
321 if (rdev
->is_atom_bios
) {
322 tmp
= RREG32(RADEON_BIOS_6_SCRATCH
);
323 WREG32(RADEON_BIOS_6_SCRATCH
, tmp
| ATOM_S6_HW_I2C_BUSY_STATE
);
327 i2c_cntl_0
= RADEON_I2C_CNTL_0
;
328 i2c_cntl_1
= RADEON_I2C_CNTL_1
;
329 i2c_data
= RADEON_I2C_DATA
;
331 i2c_cntl_0
= RADEON_DVI_I2C_CNTL_0
;
332 i2c_cntl_1
= RADEON_DVI_I2C_CNTL_1
;
333 i2c_data
= RADEON_DVI_I2C_DATA
;
335 switch (rdev
->family
) {
342 switch (rec
->mask_clk_reg
) {
343 case RADEON_GPIO_DVI_DDC
:
344 /* no gpio select bit */
347 DRM_ERROR("gpio not supported with hw i2c\n");
353 /* only bit 4 on r200 */
354 switch (rec
->mask_clk_reg
) {
355 case RADEON_GPIO_DVI_DDC
:
356 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
);
358 case RADEON_GPIO_MONID
:
359 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
);
362 DRM_ERROR("gpio not supported with hw i2c\n");
370 switch (rec
->mask_clk_reg
) {
371 case RADEON_GPIO_DVI_DDC
:
372 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
);
374 case RADEON_GPIO_VGA_DDC
:
375 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2
);
377 case RADEON_GPIO_CRT2_DDC
:
378 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
);
381 DRM_ERROR("gpio not supported with hw i2c\n");
388 /* only bit 4 on r300/r350 */
389 switch (rec
->mask_clk_reg
) {
390 case RADEON_GPIO_VGA_DDC
:
391 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
);
393 case RADEON_GPIO_DVI_DDC
:
394 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
);
397 DRM_ERROR("gpio not supported with hw i2c\n");
410 switch (rec
->mask_clk_reg
) {
411 case RADEON_GPIO_VGA_DDC
:
412 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
);
414 case RADEON_GPIO_DVI_DDC
:
415 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2
);
417 case RADEON_GPIO_MONID
:
418 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
);
421 DRM_ERROR("gpio not supported with hw i2c\n");
427 DRM_ERROR("unsupported asic\n");
434 /* check for bus probe */
436 if ((num
== 1) && (p
->len
== 0)) {
437 WREG32(i2c_cntl_0
, (RADEON_I2C_DONE
|
440 RADEON_I2C_SOFT_RST
));
441 WREG32(i2c_data
, (p
->addr
<< 1) & 0xff);
443 WREG32(i2c_cntl_1
, ((1 << RADEON_I2C_DATA_COUNT_SHIFT
) |
444 (1 << RADEON_I2C_ADDR_COUNT_SHIFT
) |
446 (48 << RADEON_I2C_TIME_LIMIT_SHIFT
)));
447 WREG32(i2c_cntl_0
, reg
);
448 for (k
= 0; k
< 32; k
++) {
450 tmp
= RREG32(i2c_cntl_0
);
451 if (tmp
& RADEON_I2C_GO
)
453 tmp
= RREG32(i2c_cntl_0
);
454 if (tmp
& RADEON_I2C_DONE
)
457 DRM_DEBUG("i2c write error 0x%08x\n", tmp
);
458 WREG32(i2c_cntl_0
, tmp
| RADEON_I2C_ABORT
);
466 for (i
= 0; i
< num
; i
++) {
468 for (j
= 0; j
< p
->len
; j
++) {
469 if (p
->flags
& I2C_M_RD
) {
470 WREG32(i2c_cntl_0
, (RADEON_I2C_DONE
|
473 RADEON_I2C_SOFT_RST
));
474 WREG32(i2c_data
, ((p
->addr
<< 1) & 0xff) | 0x1);
475 WREG32(i2c_cntl_1
, ((1 << RADEON_I2C_DATA_COUNT_SHIFT
) |
476 (1 << RADEON_I2C_ADDR_COUNT_SHIFT
) |
478 (48 << RADEON_I2C_TIME_LIMIT_SHIFT
)));
479 WREG32(i2c_cntl_0
, reg
| RADEON_I2C_RECEIVE
);
480 for (k
= 0; k
< 32; k
++) {
482 tmp
= RREG32(i2c_cntl_0
);
483 if (tmp
& RADEON_I2C_GO
)
485 tmp
= RREG32(i2c_cntl_0
);
486 if (tmp
& RADEON_I2C_DONE
)
489 DRM_DEBUG("i2c read error 0x%08x\n", tmp
);
490 WREG32(i2c_cntl_0
, tmp
| RADEON_I2C_ABORT
);
495 p
->buf
[j
] = RREG32(i2c_data
) & 0xff;
497 WREG32(i2c_cntl_0
, (RADEON_I2C_DONE
|
500 RADEON_I2C_SOFT_RST
));
501 WREG32(i2c_data
, (p
->addr
<< 1) & 0xff);
502 WREG32(i2c_data
, p
->buf
[j
]);
503 WREG32(i2c_cntl_1
, ((1 << RADEON_I2C_DATA_COUNT_SHIFT
) |
504 (1 << RADEON_I2C_ADDR_COUNT_SHIFT
) |
506 (48 << RADEON_I2C_TIME_LIMIT_SHIFT
)));
507 WREG32(i2c_cntl_0
, reg
);
508 for (k
= 0; k
< 32; k
++) {
510 tmp
= RREG32(i2c_cntl_0
);
511 if (tmp
& RADEON_I2C_GO
)
513 tmp
= RREG32(i2c_cntl_0
);
514 if (tmp
& RADEON_I2C_DONE
)
517 DRM_DEBUG("i2c write error 0x%08x\n", tmp
);
518 WREG32(i2c_cntl_0
, tmp
| RADEON_I2C_ABORT
);
528 WREG32(i2c_cntl_0
, 0);
529 WREG32(i2c_cntl_1
, 0);
530 WREG32(i2c_cntl_0
, (RADEON_I2C_DONE
|
533 RADEON_I2C_SOFT_RST
));
535 if (rdev
->is_atom_bios
) {
536 tmp
= RREG32(RADEON_BIOS_6_SCRATCH
);
537 tmp
&= ~ATOM_S6_HW_I2C_BUSY_STATE
;
538 WREG32(RADEON_BIOS_6_SCRATCH
, tmp
);
541 mutex_unlock(&rdev
->pm
.mutex
);
542 mutex_unlock(&rdev
->dc_hw_i2c_mutex
);
547 /* hw i2c engine for r5xx hardware
548 * hw can buffer up to 15 bytes
550 static int r500_hw_i2c_xfer(struct i2c_adapter
*i2c_adap
,
551 struct i2c_msg
*msgs
, int num
)
553 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
554 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
555 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
557 int i
, j
, remaining
, current_count
, buffer_offset
, ret
= num
;
562 mutex_lock(&rdev
->dc_hw_i2c_mutex
);
563 /* take the pm lock since we need a constant sclk */
564 mutex_lock(&rdev
->pm
.mutex
);
566 prescale
= radeon_get_i2c_prescale(rdev
);
568 /* clear gpio mask bits */
569 tmp
= RREG32(rec
->mask_clk_reg
);
570 tmp
&= ~rec
->mask_clk_mask
;
571 WREG32(rec
->mask_clk_reg
, tmp
);
572 tmp
= RREG32(rec
->mask_clk_reg
);
574 tmp
= RREG32(rec
->mask_data_reg
);
575 tmp
&= ~rec
->mask_data_mask
;
576 WREG32(rec
->mask_data_reg
, tmp
);
577 tmp
= RREG32(rec
->mask_data_reg
);
579 /* clear pin values */
580 tmp
= RREG32(rec
->a_clk_reg
);
581 tmp
&= ~rec
->a_clk_mask
;
582 WREG32(rec
->a_clk_reg
, tmp
);
583 tmp
= RREG32(rec
->a_clk_reg
);
585 tmp
= RREG32(rec
->a_data_reg
);
586 tmp
&= ~rec
->a_data_mask
;
587 WREG32(rec
->a_data_reg
, tmp
);
588 tmp
= RREG32(rec
->a_data_reg
);
590 /* set the pins to input */
591 tmp
= RREG32(rec
->en_clk_reg
);
592 tmp
&= ~rec
->en_clk_mask
;
593 WREG32(rec
->en_clk_reg
, tmp
);
594 tmp
= RREG32(rec
->en_clk_reg
);
596 tmp
= RREG32(rec
->en_data_reg
);
597 tmp
&= ~rec
->en_data_mask
;
598 WREG32(rec
->en_data_reg
, tmp
);
599 tmp
= RREG32(rec
->en_data_reg
);
602 tmp
= RREG32(RADEON_BIOS_6_SCRATCH
);
603 WREG32(RADEON_BIOS_6_SCRATCH
, tmp
| ATOM_S6_HW_I2C_BUSY_STATE
);
604 saved1
= RREG32(AVIVO_DC_I2C_CONTROL1
);
605 saved2
= RREG32(0x494);
606 WREG32(0x494, saved2
| 0x1);
608 WREG32(AVIVO_DC_I2C_ARBITRATION
, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C
);
609 for (i
= 0; i
< 50; i
++) {
611 if (RREG32(AVIVO_DC_I2C_ARBITRATION
) & AVIVO_DC_I2C_SW_CAN_USE_I2C
)
615 DRM_ERROR("failed to get i2c bus\n");
620 reg
= AVIVO_DC_I2C_START
| AVIVO_DC_I2C_STOP
| AVIVO_DC_I2C_EN
;
621 switch (rec
->mask_clk_reg
) {
622 case AVIVO_DC_GPIO_DDC1_MASK
:
623 reg
|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1
);
625 case AVIVO_DC_GPIO_DDC2_MASK
:
626 reg
|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2
);
628 case AVIVO_DC_GPIO_DDC3_MASK
:
629 reg
|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3
);
632 DRM_ERROR("gpio not supported with hw i2c\n");
637 /* check for bus probe */
639 if ((num
== 1) && (p
->len
== 0)) {
640 WREG32(AVIVO_DC_I2C_STATUS1
, (AVIVO_DC_I2C_DONE
|
643 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_SOFT_RESET
);
645 WREG32(AVIVO_DC_I2C_RESET
, 0);
647 WREG32(AVIVO_DC_I2C_DATA
, (p
->addr
<< 1) & 0xff);
648 WREG32(AVIVO_DC_I2C_DATA
, 0);
650 WREG32(AVIVO_DC_I2C_CONTROL3
, AVIVO_DC_I2C_TIME_LIMIT(48));
651 WREG32(AVIVO_DC_I2C_CONTROL2
, (AVIVO_DC_I2C_ADDR_COUNT(1) |
652 AVIVO_DC_I2C_DATA_COUNT(1) |
654 WREG32(AVIVO_DC_I2C_CONTROL1
, reg
);
655 WREG32(AVIVO_DC_I2C_STATUS1
, AVIVO_DC_I2C_GO
);
656 for (j
= 0; j
< 200; j
++) {
658 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
659 if (tmp
& AVIVO_DC_I2C_GO
)
661 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
662 if (tmp
& AVIVO_DC_I2C_DONE
)
665 DRM_DEBUG("i2c write error 0x%08x\n", tmp
);
666 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_ABORT
);
674 for (i
= 0; i
< num
; i
++) {
678 if (p
->flags
& I2C_M_RD
) {
683 current_count
= remaining
;
684 WREG32(AVIVO_DC_I2C_STATUS1
, (AVIVO_DC_I2C_DONE
|
687 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_SOFT_RESET
);
689 WREG32(AVIVO_DC_I2C_RESET
, 0);
691 WREG32(AVIVO_DC_I2C_DATA
, ((p
->addr
<< 1) & 0xff) | 0x1);
692 WREG32(AVIVO_DC_I2C_CONTROL3
, AVIVO_DC_I2C_TIME_LIMIT(48));
693 WREG32(AVIVO_DC_I2C_CONTROL2
, (AVIVO_DC_I2C_ADDR_COUNT(1) |
694 AVIVO_DC_I2C_DATA_COUNT(current_count
) |
696 WREG32(AVIVO_DC_I2C_CONTROL1
, reg
| AVIVO_DC_I2C_RECEIVE
);
697 WREG32(AVIVO_DC_I2C_STATUS1
, AVIVO_DC_I2C_GO
);
698 for (j
= 0; j
< 200; j
++) {
700 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
701 if (tmp
& AVIVO_DC_I2C_GO
)
703 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
704 if (tmp
& AVIVO_DC_I2C_DONE
)
707 DRM_DEBUG("i2c read error 0x%08x\n", tmp
);
708 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_ABORT
);
713 for (j
= 0; j
< current_count
; j
++)
714 p
->buf
[buffer_offset
+ j
] = RREG32(AVIVO_DC_I2C_DATA
) & 0xff;
715 remaining
-= current_count
;
716 buffer_offset
+= current_count
;
723 current_count
= remaining
;
724 WREG32(AVIVO_DC_I2C_STATUS1
, (AVIVO_DC_I2C_DONE
|
727 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_SOFT_RESET
);
729 WREG32(AVIVO_DC_I2C_RESET
, 0);
731 WREG32(AVIVO_DC_I2C_DATA
, (p
->addr
<< 1) & 0xff);
732 for (j
= 0; j
< current_count
; j
++)
733 WREG32(AVIVO_DC_I2C_DATA
, p
->buf
[buffer_offset
+ j
]);
735 WREG32(AVIVO_DC_I2C_CONTROL3
, AVIVO_DC_I2C_TIME_LIMIT(48));
736 WREG32(AVIVO_DC_I2C_CONTROL2
, (AVIVO_DC_I2C_ADDR_COUNT(1) |
737 AVIVO_DC_I2C_DATA_COUNT(current_count
) |
739 WREG32(AVIVO_DC_I2C_CONTROL1
, reg
);
740 WREG32(AVIVO_DC_I2C_STATUS1
, AVIVO_DC_I2C_GO
);
741 for (j
= 0; j
< 200; j
++) {
743 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
744 if (tmp
& AVIVO_DC_I2C_GO
)
746 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
747 if (tmp
& AVIVO_DC_I2C_DONE
)
750 DRM_DEBUG("i2c write error 0x%08x\n", tmp
);
751 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_ABORT
);
756 remaining
-= current_count
;
757 buffer_offset
+= current_count
;
763 WREG32(AVIVO_DC_I2C_STATUS1
, (AVIVO_DC_I2C_DONE
|
766 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_SOFT_RESET
);
768 WREG32(AVIVO_DC_I2C_RESET
, 0);
770 WREG32(AVIVO_DC_I2C_ARBITRATION
, AVIVO_DC_I2C_SW_DONE_USING_I2C
);
771 WREG32(AVIVO_DC_I2C_CONTROL1
, saved1
);
772 WREG32(0x494, saved2
);
773 tmp
= RREG32(RADEON_BIOS_6_SCRATCH
);
774 tmp
&= ~ATOM_S6_HW_I2C_BUSY_STATE
;
775 WREG32(RADEON_BIOS_6_SCRATCH
, tmp
);
777 mutex_unlock(&rdev
->pm
.mutex
);
778 mutex_unlock(&rdev
->dc_hw_i2c_mutex
);
783 static int radeon_hw_i2c_xfer(struct i2c_adapter
*i2c_adap
,
784 struct i2c_msg
*msgs
, int num
)
786 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
787 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
788 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
791 switch (rdev
->family
) {
810 ret
= r100_hw_i2c_xfer(i2c_adap
, msgs
, num
);
815 /* XXX fill in hw i2c implementation */
824 ret
= r100_hw_i2c_xfer(i2c_adap
, msgs
, num
);
826 ret
= r500_hw_i2c_xfer(i2c_adap
, msgs
, num
);
832 /* XXX fill in hw i2c implementation */
842 /* XXX fill in hw i2c implementation */
849 /* XXX fill in hw i2c implementation */
852 DRM_ERROR("i2c: unhandled radeon chip\n");
860 static u32
radeon_hw_i2c_func(struct i2c_adapter
*adap
)
862 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
865 static const struct i2c_algorithm radeon_i2c_algo
= {
866 .master_xfer
= radeon_hw_i2c_xfer
,
867 .functionality
= radeon_hw_i2c_func
,
870 struct radeon_i2c_chan
*radeon_i2c_create(struct drm_device
*dev
,
871 struct radeon_i2c_bus_rec
*rec
,
874 struct radeon_device
*rdev
= dev
->dev_private
;
875 struct radeon_i2c_chan
*i2c
;
878 i2c
= kzalloc(sizeof(struct radeon_i2c_chan
), GFP_KERNEL
);
883 i2c
->adapter
.owner
= THIS_MODULE
;
885 i2c_set_adapdata(&i2c
->adapter
, i2c
);
889 ((rdev
->family
<= CHIP_RS480
) ||
890 ((rdev
->family
>= CHIP_RV515
) && (rdev
->family
<= CHIP_R580
))))) {
891 /* set the radeon hw i2c adapter */
892 sprintf(i2c
->adapter
.name
, "Radeon i2c hw bus %s", name
);
893 i2c
->adapter
.algo
= &radeon_i2c_algo
;
894 ret
= i2c_add_adapter(&i2c
->adapter
);
896 DRM_ERROR("Failed to register hw i2c %s\n", name
);
900 /* set the radeon bit adapter */
901 sprintf(i2c
->adapter
.name
, "Radeon i2c bit bus %s", name
);
902 i2c
->adapter
.algo_data
= &i2c
->algo
.bit
;
903 i2c
->algo
.bit
.pre_xfer
= pre_xfer
;
904 i2c
->algo
.bit
.post_xfer
= post_xfer
;
905 i2c
->algo
.bit
.setsda
= set_data
;
906 i2c
->algo
.bit
.setscl
= set_clock
;
907 i2c
->algo
.bit
.getsda
= get_data
;
908 i2c
->algo
.bit
.getscl
= get_clock
;
909 i2c
->algo
.bit
.udelay
= 20;
910 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
911 * make this, 2 jiffies is a lot more reliable */
912 i2c
->algo
.bit
.timeout
= 2;
913 i2c
->algo
.bit
.data
= i2c
;
914 ret
= i2c_bit_add_bus(&i2c
->adapter
);
916 DRM_ERROR("Failed to register bit i2c %s\n", name
);
928 struct radeon_i2c_chan
*radeon_i2c_create_dp(struct drm_device
*dev
,
929 struct radeon_i2c_bus_rec
*rec
,
932 struct radeon_i2c_chan
*i2c
;
935 i2c
= kzalloc(sizeof(struct radeon_i2c_chan
), GFP_KERNEL
);
940 i2c
->adapter
.owner
= THIS_MODULE
;
942 i2c_set_adapdata(&i2c
->adapter
, i2c
);
943 i2c
->adapter
.algo_data
= &i2c
->algo
.dp
;
944 i2c
->algo
.dp
.aux_ch
= radeon_dp_i2c_aux_ch
;
945 i2c
->algo
.dp
.address
= 0;
946 ret
= i2c_dp_aux_add_bus(&i2c
->adapter
);
948 DRM_INFO("Failed to register i2c %s\n", name
);
959 void radeon_i2c_destroy(struct radeon_i2c_chan
*i2c
)
963 i2c_del_adapter(&i2c
->adapter
);
967 /* Add the default buses */
968 void radeon_i2c_init(struct radeon_device
*rdev
)
970 if (rdev
->is_atom_bios
)
971 radeon_atombios_i2c_init(rdev
);
973 radeon_combios_i2c_init(rdev
);
976 /* remove all the buses */
977 void radeon_i2c_fini(struct radeon_device
*rdev
)
981 for (i
= 0; i
< RADEON_MAX_I2C_BUS
; i
++) {
982 if (rdev
->i2c_bus
[i
]) {
983 radeon_i2c_destroy(rdev
->i2c_bus
[i
]);
984 rdev
->i2c_bus
[i
] = NULL
;
989 /* Add additional buses */
990 void radeon_i2c_add(struct radeon_device
*rdev
,
991 struct radeon_i2c_bus_rec
*rec
,
994 struct drm_device
*dev
= rdev
->ddev
;
997 for (i
= 0; i
< RADEON_MAX_I2C_BUS
; i
++) {
998 if (!rdev
->i2c_bus
[i
]) {
999 rdev
->i2c_bus
[i
] = radeon_i2c_create(dev
, rec
, name
);
1005 /* looks up bus based on id */
1006 struct radeon_i2c_chan
*radeon_i2c_lookup(struct radeon_device
*rdev
,
1007 struct radeon_i2c_bus_rec
*i2c_bus
)
1011 for (i
= 0; i
< RADEON_MAX_I2C_BUS
; i
++) {
1012 if (rdev
->i2c_bus
[i
] &&
1013 (rdev
->i2c_bus
[i
]->rec
.i2c_id
== i2c_bus
->i2c_id
)) {
1014 return rdev
->i2c_bus
[i
];
1020 struct drm_encoder
*radeon_best_encoder(struct drm_connector
*connector
)
1025 void radeon_i2c_get_byte(struct radeon_i2c_chan
*i2c_bus
,
1032 struct i2c_msg msgs
[] = {
1050 if (i2c_transfer(&i2c_bus
->adapter
, msgs
, 2) == 2) {
1052 DRM_DEBUG("val = 0x%02x\n", *val
);
1054 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
1059 void radeon_i2c_put_byte(struct radeon_i2c_chan
*i2c_bus
,
1065 struct i2c_msg msg
= {
1075 if (i2c_transfer(&i2c_bus
->adapter
, &msg
, 1) != 1)
1076 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",
1080 /* router switching */
1081 void radeon_router_select_port(struct radeon_connector
*radeon_connector
)
1085 if (!radeon_connector
->router
.valid
)
1088 radeon_i2c_get_byte(radeon_connector
->router_bus
,
1089 radeon_connector
->router
.i2c_addr
,
1091 val
&= radeon_connector
->router
.mux_control_pin
;
1092 radeon_i2c_put_byte(radeon_connector
->router_bus
,
1093 radeon_connector
->router
.i2c_addr
,
1095 radeon_i2c_get_byte(radeon_connector
->router_bus
,
1096 radeon_connector
->router
.i2c_addr
,
1098 val
&= radeon_connector
->router
.mux_control_pin
;
1099 val
|= radeon_connector
->router
.mux_state
;
1100 radeon_i2c_put_byte(radeon_connector
->router_bus
,
1101 radeon_connector
->router
.i2c_addr
,