drivers/gpu/drm/radeon/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  33 {
  34         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  35         struct drm_encoder_helper_funcs *encoder_funcs;
  36
  37         encoder_funcs = encoder->helper_private;
  38         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  39         radeon_encoder->active_device = 0;
  40 }
  41
  42 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  43 {
  44         struct drm_device *dev = encoder->dev;
  45         struct radeon_device *rdev = dev->dev_private;
  46         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  47         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  48         int panel_pwr_delay = 2000;
  49         DRM_DEBUG("\n");
  50
  51         if (radeon_encoder->enc_priv) {
  52                 if (rdev->is_atom_bios) {
  53                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  54                         panel_pwr_delay = lvds->panel_pwr_delay;
  55                 } else {
  56                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  57                         panel_pwr_delay = lvds->panel_pwr_delay;
  58                 }
  59         }
  60
  61         switch (mode) {
  62         case DRM_MODE_DPMS_ON:
  63                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  64                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  65                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  66                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  67                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  68                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  69                 udelay(1000);
  70
  71                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  72                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  73                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  74
  75                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  76                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
  77                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
  78                 udelay(panel_pwr_delay * 1000);
  79                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  80                 break;
  81         case DRM_MODE_DPMS_STANDBY:
  82         case DRM_MODE_DPMS_SUSPEND:
  83         case DRM_MODE_DPMS_OFF:
  84                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  85                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  86                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  87                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  88                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
  89                 udelay(panel_pwr_delay * 1000);
  90                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  91                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  92                 break;
  93         }
  94
  95         if (rdev->is_atom_bios)
  96                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  97         else
  98                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  99 }
 100
 101 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 102 {
 103         struct radeon_device *rdev = encoder->dev->dev_private;
 104
 105         if (rdev->is_atom_bios)
 106                 radeon_atom_output_lock(encoder, true);
 107         else
 108                 radeon_combios_output_lock(encoder, true);
 109         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 110 }
 111
 112 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 113 {
 114         struct radeon_device *rdev = encoder->dev->dev_private;
 115
 116         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 117         if (rdev->is_atom_bios)
 118                 radeon_atom_output_lock(encoder, false);
 119         else
 120                 radeon_combios_output_lock(encoder, false);
 121 }
 122
 123 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 124                                         struct drm_display_mode *mode,
 125                                         struct drm_display_mode *adjusted_mode)
 126 {
 127         struct drm_device *dev = encoder->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 130         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 131         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 132
 133         DRM_DEBUG("\n");
 134
 135         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
 136         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 137
 138         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 139         if ((!rdev->is_atom_bios)) {
 140                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 141                 if (lvds) {
 142                         DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
 143                         lvds_gen_cntl = lvds->lvds_gen_cntl;
 144                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 145                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 146                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 147                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 148                 } else
 149                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 150         } else
 151                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 152         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 153         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 154                            RADEON_LVDS_BLON |
 155                            RADEON_LVDS_EN |
 156                            RADEON_LVDS_RST_FM);
 157
 158         if (ASIC_IS_R300(rdev))
 159                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 160
 161         if (radeon_crtc->crtc_id == 0) {
 162                 if (ASIC_IS_R300(rdev)) {
 163                         if (radeon_encoder->rmx_type != RMX_OFF)
 164                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 165                 } else
 166                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 167         } else {
 168                 if (ASIC_IS_R300(rdev))
 169                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 170                 else
 171                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 172         }
 173
 174         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 175         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 176         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 177
 178         if (rdev->family == CHIP_RV410)
 179                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
 180
 181         if (rdev->is_atom_bios)
 182                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 183         else
 184                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 185 }
 186
 187 static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
 188                                           struct drm_display_mode *mode,
 189                                           struct drm_display_mode *adjusted_mode)
 190 {
 191         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 192
 193         /* set the active encoder to connector routing */
 194         radeon_encoder_set_active_device(encoder);
 195         drm_mode_set_crtcinfo(adjusted_mode, 0);
 196
 197         if (radeon_encoder->rmx_type != RMX_OFF)
 198                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 199
 200         return true;
 201 }
 202
 203 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 204         .dpms = radeon_legacy_lvds_dpms,
 205         .mode_fixup = radeon_legacy_lvds_mode_fixup,
 206         .prepare = radeon_legacy_lvds_prepare,
 207         .mode_set = radeon_legacy_lvds_mode_set,
 208         .commit = radeon_legacy_lvds_commit,
 209         .disable = radeon_legacy_encoder_disable,
 210 };
 211
 212
 213 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 214         .destroy = radeon_enc_destroy,
 215 };
 216
 217 static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
 218                                                  struct drm_display_mode *mode,
 219                                                  struct drm_display_mode *adjusted_mode)
 220 {
 221         /* set the active encoder to connector routing */
 222         radeon_encoder_set_active_device(encoder);
 223         drm_mode_set_crtcinfo(adjusted_mode, 0);
 224
 225         return true;
 226 }
 227
 228 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 229 {
 230         struct drm_device *dev = encoder->dev;
 231         struct radeon_device *rdev = dev->dev_private;
 232         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 233         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
 234         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 235
 236         DRM_DEBUG("\n");
 237
 238         switch (mode) {
 239         case DRM_MODE_DPMS_ON:
 240                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 241                 dac_cntl &= ~RADEON_DAC_PDWN;
 242                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 243                                     RADEON_DAC_PDWN_G |
 244                                     RADEON_DAC_PDWN_B);
 245                 break;
 246         case DRM_MODE_DPMS_STANDBY:
 247         case DRM_MODE_DPMS_SUSPEND:
 248         case DRM_MODE_DPMS_OFF:
 249                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 250                 dac_cntl |= RADEON_DAC_PDWN;
 251                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 252                                    RADEON_DAC_PDWN_G |
 253                                    RADEON_DAC_PDWN_B);
 254                 break;
 255         }
 256
 257         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 258         WREG32(RADEON_DAC_CNTL, dac_cntl);
 259         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 260
 261         if (rdev->is_atom_bios)
 262                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 263         else
 264                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 265 }
 266
 267 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 268 {
 269         struct radeon_device *rdev = encoder->dev->dev_private;
 270
 271         if (rdev->is_atom_bios)
 272                 radeon_atom_output_lock(encoder, true);
 273         else
 274                 radeon_combios_output_lock(encoder, true);
 275         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 276 }
 277
 278 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 279 {
 280         struct radeon_device *rdev = encoder->dev->dev_private;
 281
 282         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 283
 284         if (rdev->is_atom_bios)
 285                 radeon_atom_output_lock(encoder, false);
 286         else
 287                 radeon_combios_output_lock(encoder, false);
 288 }
 289
 290 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 291                                                struct drm_display_mode *mode,
 292                                                struct drm_display_mode *adjusted_mode)
 293 {
 294         struct drm_device *dev = encoder->dev;
 295         struct radeon_device *rdev = dev->dev_private;
 296         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 297         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 298         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 299
 300         DRM_DEBUG("\n");
 301
 302         if (radeon_crtc->crtc_id == 0) {
 303                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 304                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 305                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 306                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 307                 } else {
 308                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 309                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 310                 }
 311         } else {
 312                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 313                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 314                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 315                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 316                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 317                 } else {
 318                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 319                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 320                 }
 321         }
 322
 323         dac_cntl = (RADEON_DAC_MASK_ALL |
 324                     RADEON_DAC_VGA_ADR_EN |
 325                     /* TODO 6-bits */
 326                     RADEON_DAC_8BIT_EN);
 327
 328         WREG32_P(RADEON_DAC_CNTL,
 329                        dac_cntl,
 330                        RADEON_DAC_RANGE_CNTL |
 331                        RADEON_DAC_BLANKING);
 332
 333         if (radeon_encoder->enc_priv) {
 334                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
 335                 dac_macro_cntl = p_dac->ps2_pdac_adj;
 336         } else
 337                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 338         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 339         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 340
 341         if (rdev->is_atom_bios)
 342                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 343         else
 344                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 345 }
 346
 347 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 348                                                                   struct drm_connector *connector)
 349 {
 350         struct drm_device *dev = encoder->dev;
 351         struct radeon_device *rdev = dev->dev_private;
 352         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 353         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 354         enum drm_connector_status found = connector_status_disconnected;
 355         bool color = true;
 356
 357         /* save the regs we need */
 358         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
 359         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 360         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
 361         dac_cntl = RREG32(RADEON_DAC_CNTL);
 362         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 363
 364         tmp = vclk_ecp_cntl &
 365                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 366         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
 367
 368         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 369         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
 370
 371         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 372                 RADEON_DAC_FORCE_DATA_EN;
 373
 374         if (color)
 375                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 376         else
 377                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 378
 379         if (ASIC_IS_R300(rdev))
 380                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 381         else
 382                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 383
 384         WREG32(RADEON_DAC_EXT_CNTL, tmp);
 385
 386         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 387         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 388         WREG32(RADEON_DAC_CNTL, tmp);
 389
 390         tmp &= ~(RADEON_DAC_PDWN_R |
 391                  RADEON_DAC_PDWN_G |
 392                  RADEON_DAC_PDWN_B);
 393
 394         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
 395
 396         udelay(2000);
 397
 398         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 399                 found = connector_status_connected;
 400
 401         /* restore the regs we used */
 402         WREG32(RADEON_DAC_CNTL, dac_cntl);
 403         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 404         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 405         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 406         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 407
 408         return found;
 409 }
 410
 411 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 412         .dpms = radeon_legacy_primary_dac_dpms,
 413         .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
 414         .prepare = radeon_legacy_primary_dac_prepare,
 415         .mode_set = radeon_legacy_primary_dac_mode_set,
 416         .commit = radeon_legacy_primary_dac_commit,
 417         .detect = radeon_legacy_primary_dac_detect,
 418         .disable = radeon_legacy_encoder_disable,
 419 };
 420
 421
 422 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 423         .destroy = radeon_enc_destroy,
 424 };
 425
 426 static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
 427                                               struct drm_display_mode *mode,
 428                                               struct drm_display_mode *adjusted_mode)
 429 {
 430         /* set the active encoder to connector routing */
 431         radeon_encoder_set_active_device(encoder);
 432         drm_mode_set_crtcinfo(adjusted_mode, 0);
 433
 434         return true;
 435 }
 436
 437 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 438 {
 439         struct drm_device *dev = encoder->dev;
 440         struct radeon_device *rdev = dev->dev_private;
 441         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
 442         DRM_DEBUG("\n");
 443
 444         switch (mode) {
 445         case DRM_MODE_DPMS_ON:
 446                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 447                 break;
 448         case DRM_MODE_DPMS_STANDBY:
 449         case DRM_MODE_DPMS_SUSPEND:
 450         case DRM_MODE_DPMS_OFF:
 451                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 452                 break;
 453         }
 454
 455         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 456
 457         if (rdev->is_atom_bios)
 458                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 459         else
 460                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 461 }
 462
 463 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 464 {
 465         struct radeon_device *rdev = encoder->dev->dev_private;
 466
 467         if (rdev->is_atom_bios)
 468                 radeon_atom_output_lock(encoder, true);
 469         else
 470                 radeon_combios_output_lock(encoder, true);
 471         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 472 }
 473
 474 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 475 {
 476         struct radeon_device *rdev = encoder->dev->dev_private;
 477
 478         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 479
 480         if (rdev->is_atom_bios)
 481                 radeon_atom_output_lock(encoder, true);
 482         else
 483                 radeon_combios_output_lock(encoder, true);
 484 }
 485
 486 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 487                                             struct drm_display_mode *mode,
 488                                             struct drm_display_mode *adjusted_mode)
 489 {
 490         struct drm_device *dev = encoder->dev;
 491         struct radeon_device *rdev = dev->dev_private;
 492         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 493         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 494         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 495         int i;
 496
 497         DRM_DEBUG("\n");
 498
 499         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
 500         tmp &= 0xfffff;
 501         if (rdev->family == CHIP_RV280) {
 502                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 503                 tmp ^= (1 << 22);
 504                 tmds_pll_cntl ^= (1 << 22);
 505         }
 506
 507         if (radeon_encoder->enc_priv) {
 508                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
 509
 510                 for (i = 0; i < 4; i++) {
 511                         if (tmds->tmds_pll[i].freq == 0)
 512                                 break;
 513                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
 514                                 tmp = tmds->tmds_pll[i].value ;
 515                                 break;
 516                         }
 517                 }
 518         }
 519
 520         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
 521                 if (tmp & 0xfff00000)
 522                         tmds_pll_cntl = tmp;
 523                 else {
 524                         tmds_pll_cntl &= 0xfff00000;
 525                         tmds_pll_cntl |= tmp;
 526                 }
 527         } else
 528                 tmds_pll_cntl = tmp;
 529
 530         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
 531                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 532
 533     if (rdev->family == CHIP_R200 ||
 534         rdev->family == CHIP_R100 ||
 535         ASIC_IS_R300(rdev))
 536             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 537     else /* RV chips got this bit reversed */
 538             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 539
 540     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
 541                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 542                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 543
 544     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 545
 546     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
 547                      RADEON_FP_DFP_SYNC_SEL |
 548                      RADEON_FP_CRT_SYNC_SEL |
 549                      RADEON_FP_CRTC_LOCK_8DOT |
 550                      RADEON_FP_USE_SHADOW_EN |
 551                      RADEON_FP_CRTC_USE_SHADOW_VEND |
 552                      RADEON_FP_CRT_SYNC_ALT);
 553
 554     if (1) /*  FIXME rgbBits == 8 */
 555             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 556     else
 557             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 558
 559     if (radeon_crtc->crtc_id == 0) {
 560             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 561                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 562                     if (radeon_encoder->rmx_type != RMX_OFF)
 563                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 564                     else
 565                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 566             } else
 567                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
 568     } else {
 569             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 570                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 571                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 572             } else
 573                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 574     }
 575
 576     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 577     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 578     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 579
 580         if (rdev->is_atom_bios)
 581                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 582         else
 583                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 584 }
 585
 586 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 587         .dpms = radeon_legacy_tmds_int_dpms,
 588         .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
 589         .prepare = radeon_legacy_tmds_int_prepare,
 590         .mode_set = radeon_legacy_tmds_int_mode_set,
 591         .commit = radeon_legacy_tmds_int_commit,
 592         .disable = radeon_legacy_encoder_disable,
 593 };
 594
 595
 596 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 597         .destroy = radeon_enc_destroy,
 598 };
 599
 600 static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
 601                                               struct drm_display_mode *mode,
 602                                               struct drm_display_mode *adjusted_mode)
 603 {
 604         /* set the active encoder to connector routing */
 605         radeon_encoder_set_active_device(encoder);
 606         drm_mode_set_crtcinfo(adjusted_mode, 0);
 607
 608         return true;
 609 }
 610
 611 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 612 {
 613         struct drm_device *dev = encoder->dev;
 614         struct radeon_device *rdev = dev->dev_private;
 615         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 616         DRM_DEBUG("\n");
 617
 618         switch (mode) {
 619         case DRM_MODE_DPMS_ON:
 620                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 621                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 622                 break;
 623         case DRM_MODE_DPMS_STANDBY:
 624         case DRM_MODE_DPMS_SUSPEND:
 625         case DRM_MODE_DPMS_OFF:
 626                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 627                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 628                 break;
 629         }
 630
 631         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 632
 633         if (rdev->is_atom_bios)
 634                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 635         else
 636                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 637 }
 638
 639 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 640 {
 641         struct radeon_device *rdev = encoder->dev->dev_private;
 642
 643         if (rdev->is_atom_bios)
 644                 radeon_atom_output_lock(encoder, true);
 645         else
 646                 radeon_combios_output_lock(encoder, true);
 647         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 648 }
 649
 650 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 651 {
 652         struct radeon_device *rdev = encoder->dev->dev_private;
 653         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 654
 655         if (rdev->is_atom_bios)
 656                 radeon_atom_output_lock(encoder, false);
 657         else
 658                 radeon_combios_output_lock(encoder, false);
 659 }
 660
 661 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 662                                             struct drm_display_mode *mode,
 663                                             struct drm_display_mode *adjusted_mode)
 664 {
 665         struct drm_device *dev = encoder->dev;
 666         struct radeon_device *rdev = dev->dev_private;
 667         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 668         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 669         uint32_t fp2_gen_cntl;
 670
 671         DRM_DEBUG("\n");
 672
 673         if (rdev->is_atom_bios) {
 674                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 675                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
 676                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 677         } else {
 678                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 679
 680                 if (1) /*  FIXME rgbBits == 8 */
 681                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 682                 else
 683                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 684
 685                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
 686                                   RADEON_FP2_DVO_EN |
 687                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 688
 689                 /* XXX: these are oem specific */
 690                 if (ASIC_IS_R300(rdev)) {
 691                         if ((dev->pdev->device == 0x4850) &&
 692                             (dev->pdev->subsystem_vendor == 0x1028) &&
 693                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 694                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 695                         else
 696                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 697
 698                         /*if (mode->clock > 165000)
 699                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 700                 }
 701                 if (!radeon_combios_external_tmds_setup(encoder))
 702                         radeon_external_tmds_setup(encoder);
 703         }
 704
 705         if (radeon_crtc->crtc_id == 0) {
 706                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 707                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 708                         if (radeon_encoder->rmx_type != RMX_OFF)
 709                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 710                         else
 711                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 712                 } else
 713                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 714         } else {
 715                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 716                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 717                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 718                 } else
 719                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 720         }
 721
 722         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 723
 724         if (rdev->is_atom_bios)
 725                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 726         else
 727                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 728 }
 729
 730 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
 731 {
 732         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 733         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
 734         if (tmds) {
 735                 if (tmds->i2c_bus)
 736                         radeon_i2c_destroy(tmds->i2c_bus);
 737         }
 738         kfree(radeon_encoder->enc_priv);
 739         drm_encoder_cleanup(encoder);
 740         kfree(radeon_encoder);
 741 }
 742
 743 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 744         .dpms = radeon_legacy_tmds_ext_dpms,
 745         .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
 746         .prepare = radeon_legacy_tmds_ext_prepare,
 747         .mode_set = radeon_legacy_tmds_ext_mode_set,
 748         .commit = radeon_legacy_tmds_ext_commit,
 749         .disable = radeon_legacy_encoder_disable,
 750 };
 751
 752
 753 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 754         .destroy = radeon_ext_tmds_enc_destroy,
 755 };
 756
 757 static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
 758                                             struct drm_display_mode *mode,
 759                                             struct drm_display_mode *adjusted_mode)
 760 {
 761         /* set the active encoder to connector routing */
 762         radeon_encoder_set_active_device(encoder);
 763         drm_mode_set_crtcinfo(adjusted_mode, 0);
 764
 765         return true;
 766 }
 767
 768 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 769 {
 770         struct drm_device *dev = encoder->dev;
 771         struct radeon_device *rdev = dev->dev_private;
 772         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 773         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
 774         uint32_t tv_master_cntl = 0;
 775         bool is_tv;
 776         DRM_DEBUG("\n");
 777
 778         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 779
 780         if (rdev->family == CHIP_R200)
 781                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 782         else {
 783                 if (is_tv)
 784                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
 785                 else
 786                         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 787                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 788         }
 789
 790         switch (mode) {
 791         case DRM_MODE_DPMS_ON:
 792                 if (rdev->family == CHIP_R200) {
 793                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 794                 } else {
 795                         if (is_tv)
 796                                 tv_master_cntl |= RADEON_TV_ON;
 797                         else
 798                                 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 799
 800                         if (rdev->family == CHIP_R420 ||
 801                             rdev->family == CHIP_R423 ||
 802                             rdev->family == CHIP_RV410)
 803                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
 804                                                  R420_TV_DAC_GDACPD |
 805                                                  R420_TV_DAC_BDACPD |
 806                                                  RADEON_TV_DAC_BGSLEEP);
 807                         else
 808                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
 809                                                  RADEON_TV_DAC_GDACPD |
 810                                                  RADEON_TV_DAC_BDACPD |
 811                                                  RADEON_TV_DAC_BGSLEEP);
 812                 }
 813                 break;
 814         case DRM_MODE_DPMS_STANDBY:
 815         case DRM_MODE_DPMS_SUSPEND:
 816         case DRM_MODE_DPMS_OFF:
 817                 if (rdev->family == CHIP_R200)
 818                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 819                 else {
 820                         if (is_tv)
 821                                 tv_master_cntl &= ~RADEON_TV_ON;
 822                         else
 823                                 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 824
 825                         if (rdev->family == CHIP_R420 ||
 826                                         rdev->family == CHIP_R423 ||
 827                                         rdev->family == CHIP_RV410)
 828                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
 829                                                 R420_TV_DAC_GDACPD |
 830                                                 R420_TV_DAC_BDACPD |
 831                                                 RADEON_TV_DAC_BGSLEEP);
 832                         else
 833                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
 834                                                 RADEON_TV_DAC_GDACPD |
 835                                                 RADEON_TV_DAC_BDACPD |
 836                                                 RADEON_TV_DAC_BGSLEEP);
 837                 }
 838                 break;
 839         }
 840
 841         if (rdev->family == CHIP_R200) {
 842                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 843         } else {
 844                 if (is_tv)
 845                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
 846                 else
 847                         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 848                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 849         }
 850
 851         if (rdev->is_atom_bios)
 852                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 853         else
 854                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 855 }
 856
 857 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
 858 {
 859         struct radeon_device *rdev = encoder->dev->dev_private;
 860
 861         if (rdev->is_atom_bios)
 862                 radeon_atom_output_lock(encoder, true);
 863         else
 864                 radeon_combios_output_lock(encoder, true);
 865         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 866 }
 867
 868 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
 869 {
 870         struct radeon_device *rdev = encoder->dev->dev_private;
 871
 872         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 873
 874         if (rdev->is_atom_bios)
 875                 radeon_atom_output_lock(encoder, true);
 876         else
 877                 radeon_combios_output_lock(encoder, true);
 878 }
 879
 880 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 881                 struct drm_display_mode *mode,
 882                 struct drm_display_mode *adjusted_mode)
 883 {
 884         struct drm_device *dev = encoder->dev;
 885         struct radeon_device *rdev = dev->dev_private;
 886         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 887         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 888         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 889         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
 890         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
 891         bool is_tv = false;
 892
 893         DRM_DEBUG("\n");
 894
 895         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 896
 897         if (rdev->family != CHIP_R200) {
 898                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 899                 if (rdev->family == CHIP_R420 ||
 900                                 rdev->family == CHIP_R423 ||
 901                                 rdev->family == CHIP_RV410) {
 902                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 903                                         RADEON_TV_DAC_BGADJ_MASK |
 904                                         R420_TV_DAC_DACADJ_MASK |
 905                                         R420_TV_DAC_RDACPD |
 906                                         R420_TV_DAC_GDACPD |
 907                                         R420_TV_DAC_BDACPD |
 908                                         R420_TV_DAC_TVENABLE);
 909                 } else {
 910                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 911                                         RADEON_TV_DAC_BGADJ_MASK |
 912                                         RADEON_TV_DAC_DACADJ_MASK |
 913                                         RADEON_TV_DAC_RDACPD |
 914                                         RADEON_TV_DAC_GDACPD |
 915                                         RADEON_TV_DAC_BDACPD);
 916                 }
 917
 918                 /*  FIXME TV */
 919                 if (tv_dac) {
 920                         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 921                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 922                                         RADEON_TV_DAC_NHOLD |
 923                                         RADEON_TV_DAC_STD_PS2 |
 924                                         tv_dac->ps2_tvdac_adj);
 925                 } else
 926                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 927                                         RADEON_TV_DAC_NHOLD |
 928                                         RADEON_TV_DAC_STD_PS2);
 929
 930                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 931         }
 932
 933         if (ASIC_IS_R300(rdev)) {
 934                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
 935                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
 936         }
 937
 938         if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
 939                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
 940         else
 941                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 942
 943         if (rdev->family == CHIP_R200)
 944                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 945
 946         if (is_tv) {
 947                 uint32_t dac_cntl;
 948
 949                 dac_cntl = RREG32(RADEON_DAC_CNTL);
 950                 dac_cntl &= ~RADEON_DAC_TVO_EN;
 951                 WREG32(RADEON_DAC_CNTL, dac_cntl);
 952
 953                 if (ASIC_IS_R300(rdev))
 954                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
 955
 956                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
 957                 if (radeon_crtc->crtc_id == 0) {
 958                         if (ASIC_IS_R300(rdev)) {
 959                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 960                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
 961                                                      RADEON_DISP_TV_SOURCE_CRTC);
 962                         }
 963                         if (rdev->family >= CHIP_R200) {
 964                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
 965                         } else {
 966                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 967                         }
 968                 } else {
 969                         if (ASIC_IS_R300(rdev)) {
 970                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 971                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
 972                         }
 973                         if (rdev->family >= CHIP_R200) {
 974                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
 975                         } else {
 976                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 977                         }
 978                 }
 979                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 980         } else {
 981
 982                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
 983
 984                 if (radeon_crtc->crtc_id == 0) {
 985                         if (ASIC_IS_R300(rdev)) {
 986                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 987                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
 988                         } else if (rdev->family == CHIP_R200) {
 989                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 990                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 991                         } else
 992                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 993                 } else {
 994                         if (ASIC_IS_R300(rdev)) {
 995                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 996                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
 997                         } else if (rdev->family == CHIP_R200) {
 998                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 999                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
1000                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1001                         } else
1002                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1003                 }
1004                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1005         }
1006
1007         if (ASIC_IS_R300(rdev)) {
1008                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1009                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1010         }
1011
1012         if (rdev->family >= CHIP_R200)
1013                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1014         else
1015                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1016
1017         if (rdev->family == CHIP_R200)
1018                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1019
1020         if (is_tv)
1021                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1022
1023         if (rdev->is_atom_bios)
1024                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1025         else
1026                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1027
1028 }
1029
1030 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1031                                   struct drm_connector *connector)
1032 {
1033         struct drm_device *dev = encoder->dev;
1034         struct radeon_device *rdev = dev->dev_private;
1035         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1036         uint32_t disp_output_cntl, gpiopad_a, tmp;
1037         bool found = false;
1038
1039         /* save regs needed */
1040         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1041         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1042         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1043         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1044         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1045         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1046
1047         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1048
1049         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1050
1051         WREG32(RADEON_CRTC2_GEN_CNTL,
1052                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1053
1054         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1055         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1056         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1057
1058         WREG32(RADEON_DAC_EXT_CNTL,
1059                RADEON_DAC2_FORCE_BLANK_OFF_EN |
1060                RADEON_DAC2_FORCE_DATA_EN |
1061                RADEON_DAC_FORCE_DATA_SEL_RGB |
1062                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1063
1064         WREG32(RADEON_TV_DAC_CNTL,
1065                RADEON_TV_DAC_STD_NTSC |
1066                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1067                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1068
1069         RREG32(RADEON_TV_DAC_CNTL);
1070         mdelay(4);
1071
1072         WREG32(RADEON_TV_DAC_CNTL,
1073                RADEON_TV_DAC_NBLANK |
1074                RADEON_TV_DAC_NHOLD |
1075                RADEON_TV_MONITOR_DETECT_EN |
1076                RADEON_TV_DAC_STD_NTSC |
1077                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1078                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1079
1080         RREG32(RADEON_TV_DAC_CNTL);
1081         mdelay(6);
1082
1083         tmp = RREG32(RADEON_TV_DAC_CNTL);
1084         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1085                 found = true;
1086                 DRM_DEBUG("S-video TV connection detected\n");
1087         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1088                 found = true;
1089                 DRM_DEBUG("Composite TV connection detected\n");
1090         }
1091
1092         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1093         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1094         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1095         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1096         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1097         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1098         return found;
1099 }
1100
1101 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1102                                     struct drm_connector *connector)
1103 {
1104         struct drm_device *dev = encoder->dev;
1105         struct radeon_device *rdev = dev->dev_private;
1106         uint32_t tv_dac_cntl, dac_cntl2;
1107         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1108         bool found = false;
1109
1110         if (ASIC_IS_R300(rdev))
1111                 return r300_legacy_tv_detect(encoder, connector);
1112
1113         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1114         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1115         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1116         config_cntl = RREG32(RADEON_CONFIG_CNTL);
1117         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1118
1119         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1120         WREG32(RADEON_DAC_CNTL2, tmp);
1121
1122         tmp = tv_master_cntl | RADEON_TV_ON;
1123         tmp &= ~(RADEON_TV_ASYNC_RST |
1124                  RADEON_RESTART_PHASE_FIX |
1125                  RADEON_CRT_FIFO_CE_EN |
1126                  RADEON_TV_FIFO_CE_EN |
1127                  RADEON_RE_SYNC_NOW_SEL_MASK);
1128         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1129         WREG32(RADEON_TV_MASTER_CNTL, tmp);
1130
1131         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1132                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1133                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1134
1135         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1136                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1137         else
1138                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1139         WREG32(RADEON_TV_DAC_CNTL, tmp);
1140
1141         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1142                 RADEON_RED_MX_FORCE_DAC_DATA |
1143                 RADEON_GRN_MX_FORCE_DAC_DATA |
1144                 RADEON_BLU_MX_FORCE_DAC_DATA |
1145                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1146         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1147
1148         mdelay(3);
1149         tmp = RREG32(RADEON_TV_DAC_CNTL);
1150         if (tmp & RADEON_TV_DAC_GDACDET) {
1151                 found = true;
1152                 DRM_DEBUG("S-video TV connection detected\n");
1153         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1154                 found = true;
1155                 DRM_DEBUG("Composite TV connection detected\n");
1156         }
1157
1158         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1159         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1160         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1161         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1162         return found;
1163 }
1164
1165 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1166                                                              struct drm_connector *connector)
1167 {
1168         struct drm_device *dev = encoder->dev;
1169         struct radeon_device *rdev = dev->dev_private;
1170         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1171         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1172         enum drm_connector_status found = connector_status_disconnected;
1173         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1174         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1175         bool color = true;
1176
1177         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1178             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1179             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1180                 bool tv_detect;
1181
1182                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1183                         return connector_status_disconnected;
1184
1185                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1186                 if (tv_detect && tv_dac)
1187                         found = connector_status_connected;
1188                 return found;
1189         }
1190
1191         /* don't probe if the encoder is being used for something else not CRT related */
1192         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1193                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1194                 return connector_status_disconnected;
1195         }
1196
1197         /* save the regs we need */
1198         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1199         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1200         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1201         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1202         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1203         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1204         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1205         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1206
1207         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1208                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1209         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1210
1211         if (ASIC_IS_R300(rdev))
1212                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1213
1214         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1215         tmp |= RADEON_CRTC2_CRT2_ON |
1216                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1217
1218         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1219
1220         if (ASIC_IS_R300(rdev)) {
1221                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1222                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1223                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1224         } else {
1225                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1226                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1227         }
1228
1229         tmp = RADEON_TV_DAC_NBLANK |
1230                 RADEON_TV_DAC_NHOLD |
1231                 RADEON_TV_MONITOR_DETECT_EN |
1232                 RADEON_TV_DAC_STD_PS2;
1233
1234         WREG32(RADEON_TV_DAC_CNTL, tmp);
1235
1236         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1237                 RADEON_DAC2_FORCE_DATA_EN;
1238
1239         if (color)
1240                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1241         else
1242                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1243
1244         if (ASIC_IS_R300(rdev))
1245                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1246         else
1247                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1248
1249         WREG32(RADEON_DAC_EXT_CNTL, tmp);
1250
1251         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1252         WREG32(RADEON_DAC_CNTL2, tmp);
1253
1254         udelay(10000);
1255
1256         if (ASIC_IS_R300(rdev)) {
1257                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1258                         found = connector_status_connected;
1259         } else {
1260                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1261                         found = connector_status_connected;
1262         }
1263
1264         /* restore regs we used */
1265         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1266         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1267         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1268         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1269
1270         if (ASIC_IS_R300(rdev)) {
1271                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1272                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1273         } else {
1274                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1275         }
1276         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1277
1278         return found;
1279
1280 }
1281
1282 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1283         .dpms = radeon_legacy_tv_dac_dpms,
1284         .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
1285         .prepare = radeon_legacy_tv_dac_prepare,
1286         .mode_set = radeon_legacy_tv_dac_mode_set,
1287         .commit = radeon_legacy_tv_dac_commit,
1288         .detect = radeon_legacy_tv_dac_detect,
1289         .disable = radeon_legacy_encoder_disable,
1290 };
1291
1292
1293 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1294         .destroy = radeon_enc_destroy,
1295 };
1296
1297
1298 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1299 {
1300         struct drm_device *dev = encoder->base.dev;
1301         struct radeon_device *rdev = dev->dev_private;
1302         struct radeon_encoder_int_tmds *tmds = NULL;
1303         bool ret;
1304
1305         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1306
1307         if (!tmds)
1308                 return NULL;
1309
1310         if (rdev->is_atom_bios)
1311                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1312         else
1313                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1314
1315         if (ret == false)
1316                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1317
1318         return tmds;
1319 }
1320
1321 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1322 {
1323         struct drm_device *dev = encoder->base.dev;
1324         struct radeon_device *rdev = dev->dev_private;
1325         struct radeon_encoder_ext_tmds *tmds = NULL;
1326         bool ret;
1327
1328         if (rdev->is_atom_bios)
1329                 return NULL;
1330
1331         tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1332
1333         if (!tmds)
1334                 return NULL;
1335
1336         ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1337
1338         if (ret == false)
1339                 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1340
1341         return tmds;
1342 }
1343
1344 void
1345 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1346 {
1347         struct radeon_device *rdev = dev->dev_private;
1348         struct drm_encoder *encoder;
1349         struct radeon_encoder *radeon_encoder;
1350
1351         /* see if we already added it */
1352         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1353                 radeon_encoder = to_radeon_encoder(encoder);
1354                 if (radeon_encoder->encoder_id == encoder_id) {
1355                         radeon_encoder->devices |= supported_device;
1356                         return;
1357                 }
1358
1359         }
1360
1361         /* add a new one */
1362         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1363         if (!radeon_encoder)
1364                 return;
1365
1366         encoder = &radeon_encoder->base;
1367         if (rdev->flags & RADEON_SINGLE_CRTC)
1368                 encoder->possible_crtcs = 0x1;
1369         else
1370                 encoder->possible_crtcs = 0x3;
1371         encoder->possible_clones = 0;
1372
1373         radeon_encoder->enc_priv = NULL;
1374
1375         radeon_encoder->encoder_id = encoder_id;
1376         radeon_encoder->devices = supported_device;
1377         radeon_encoder->rmx_type = RMX_OFF;
1378
1379         switch (radeon_encoder->encoder_id) {
1380         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1381                 encoder->possible_crtcs = 0x1;
1382                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1383                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1384                 if (rdev->is_atom_bios)
1385                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1386                 else
1387                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1388                 radeon_encoder->rmx_type = RMX_FULL;
1389                 break;
1390         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1391                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1392                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1393                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1394                 break;
1395         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1396                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1397                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1398                 if (rdev->is_atom_bios)
1399                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1400                 else
1401                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1402                 break;
1403         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1404                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1405                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1406                 if (rdev->is_atom_bios)
1407                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1408                 else
1409                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1410                 break;
1411         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1412                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1413                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1414                 if (!rdev->is_atom_bios)
1415                         radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1416                 break;
1417         }
1418 }