Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-fixes
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_mode.h
1 /*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30 #ifndef RADEON_MODE_H
31 #define RADEON_MODE_H
32
33 #include <drm_crtc.h>
34 #include <drm_mode.h>
35 #include <drm_edid.h>
36 #include <drm_dp_helper.h>
37 #include <drm_fixed.h>
38 #include <linux/i2c.h>
39 #include <linux/i2c-id.h>
40 #include <linux/i2c-algo-bit.h>
41
42 struct radeon_bo;
43 struct radeon_device;
44
45 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
50 enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55 };
56
57 enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
66 TV_STD_PAL_N,
67 };
68
69 enum radeon_hpd_id {
70 RADEON_HPD_1 = 0,
71 RADEON_HPD_2,
72 RADEON_HPD_3,
73 RADEON_HPD_4,
74 RADEON_HPD_5,
75 RADEON_HPD_6,
76 RADEON_HPD_NONE = 0xff,
77 };
78
79 /* radeon gpio-based i2c
80 * 1. "mask" reg and bits
81 * grabs the gpio pins for software use
82 * 0=not held 1=held
83 * 2. "a" reg and bits
84 * output pin value
85 * 0=low 1=high
86 * 3. "en" reg and bits
87 * sets the pin direction
88 * 0=input 1=output
89 * 4. "y" reg and bits
90 * input pin value
91 * 0=low 1=high
92 */
93 struct radeon_i2c_bus_rec {
94 bool valid;
95 /* id used by atom */
96 uint8_t i2c_id;
97 /* id used by atom */
98 enum radeon_hpd_id hpd;
99 /* can be used with hw i2c engine */
100 bool hw_capable;
101 /* uses multi-media i2c engine */
102 bool mm_i2c;
103 /* regs and bits */
104 uint32_t mask_clk_reg;
105 uint32_t mask_data_reg;
106 uint32_t a_clk_reg;
107 uint32_t a_data_reg;
108 uint32_t en_clk_reg;
109 uint32_t en_data_reg;
110 uint32_t y_clk_reg;
111 uint32_t y_data_reg;
112 uint32_t mask_clk_mask;
113 uint32_t mask_data_mask;
114 uint32_t a_clk_mask;
115 uint32_t a_data_mask;
116 uint32_t en_clk_mask;
117 uint32_t en_data_mask;
118 uint32_t y_clk_mask;
119 uint32_t y_data_mask;
120 };
121
122 struct radeon_tmds_pll {
123 uint32_t freq;
124 uint32_t value;
125 };
126
127 #define RADEON_MAX_BIOS_CONNECTOR 16
128
129 /* pll flags */
130 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
131 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
132 #define RADEON_PLL_USE_REF_DIV (1 << 2)
133 #define RADEON_PLL_LEGACY (1 << 3)
134 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
135 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
136 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
137 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
138 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
139 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
140 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
141 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
142 #define RADEON_PLL_USE_POST_DIV (1 << 12)
143 #define RADEON_PLL_IS_LCD (1 << 13)
144
145 /* pll algo */
146 enum radeon_pll_algo {
147 PLL_ALGO_LEGACY,
148 PLL_ALGO_NEW
149 };
150
151 struct radeon_pll {
152 /* reference frequency */
153 uint32_t reference_freq;
154
155 /* fixed dividers */
156 uint32_t reference_div;
157 uint32_t post_div;
158
159 /* pll in/out limits */
160 uint32_t pll_in_min;
161 uint32_t pll_in_max;
162 uint32_t pll_out_min;
163 uint32_t pll_out_max;
164 uint32_t lcd_pll_out_min;
165 uint32_t lcd_pll_out_max;
166 uint32_t best_vco;
167
168 /* divider limits */
169 uint32_t min_ref_div;
170 uint32_t max_ref_div;
171 uint32_t min_post_div;
172 uint32_t max_post_div;
173 uint32_t min_feedback_div;
174 uint32_t max_feedback_div;
175 uint32_t min_frac_feedback_div;
176 uint32_t max_frac_feedback_div;
177
178 /* flags for the current clock */
179 uint32_t flags;
180
181 /* pll id */
182 uint32_t id;
183 /* pll algo */
184 enum radeon_pll_algo algo;
185 };
186
187 struct radeon_i2c_chan {
188 struct i2c_adapter adapter;
189 struct drm_device *dev;
190 union {
191 struct i2c_algo_bit_data bit;
192 struct i2c_algo_dp_aux_data dp;
193 } algo;
194 struct radeon_i2c_bus_rec rec;
195 };
196
197 /* mostly for macs, but really any system without connector tables */
198 enum radeon_connector_table {
199 CT_NONE,
200 CT_GENERIC,
201 CT_IBOOK,
202 CT_POWERBOOK_EXTERNAL,
203 CT_POWERBOOK_INTERNAL,
204 CT_POWERBOOK_VGA,
205 CT_MINI_EXTERNAL,
206 CT_MINI_INTERNAL,
207 CT_IMAC_G5_ISIGHT,
208 CT_EMAC,
209 };
210
211 enum radeon_dvo_chip {
212 DVO_SIL164,
213 DVO_SIL1178,
214 };
215
216 struct radeon_fbdev;
217
218 struct radeon_mode_info {
219 struct atom_context *atom_context;
220 struct card_info *atom_card_info;
221 enum radeon_connector_table connector_table;
222 bool mode_config_initialized;
223 struct radeon_crtc *crtcs[6];
224 /* DVI-I properties */
225 struct drm_property *coherent_mode_property;
226 /* DAC enable load detect */
227 struct drm_property *load_detect_property;
228 /* TV standard load detect */
229 struct drm_property *tv_std_property;
230 /* legacy TMDS PLL detect */
231 struct drm_property *tmds_pll_property;
232 /* hardcoded DFP edid from BIOS */
233 struct edid *bios_hardcoded_edid;
234
235 /* pointer to fbdev info structure */
236 struct radeon_fbdev *rfbdev;
237 };
238
239 #define MAX_H_CODE_TIMING_LEN 32
240 #define MAX_V_CODE_TIMING_LEN 32
241
242 /* need to store these as reading
243 back code tables is excessive */
244 struct radeon_tv_regs {
245 uint32_t tv_uv_adr;
246 uint32_t timing_cntl;
247 uint32_t hrestart;
248 uint32_t vrestart;
249 uint32_t frestart;
250 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
251 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
252 };
253
254 struct radeon_crtc {
255 struct drm_crtc base;
256 int crtc_id;
257 u16 lut_r[256], lut_g[256], lut_b[256];
258 bool enabled;
259 bool can_tile;
260 uint32_t crtc_offset;
261 struct drm_gem_object *cursor_bo;
262 uint64_t cursor_addr;
263 int cursor_width;
264 int cursor_height;
265 uint32_t legacy_display_base_addr;
266 uint32_t legacy_cursor_offset;
267 enum radeon_rmx_type rmx_type;
268 fixed20_12 vsc;
269 fixed20_12 hsc;
270 struct drm_display_mode native_mode;
271 int pll_id;
272 };
273
274 struct radeon_encoder_primary_dac {
275 /* legacy primary dac */
276 uint32_t ps2_pdac_adj;
277 };
278
279 struct radeon_encoder_lvds {
280 /* legacy lvds */
281 uint16_t panel_vcc_delay;
282 uint8_t panel_pwr_delay;
283 uint8_t panel_digon_delay;
284 uint8_t panel_blon_delay;
285 uint16_t panel_ref_divider;
286 uint8_t panel_post_divider;
287 uint16_t panel_fb_divider;
288 bool use_bios_dividers;
289 uint32_t lvds_gen_cntl;
290 /* panel mode */
291 struct drm_display_mode native_mode;
292 };
293
294 struct radeon_encoder_tv_dac {
295 /* legacy tv dac */
296 uint32_t ps2_tvdac_adj;
297 uint32_t ntsc_tvdac_adj;
298 uint32_t pal_tvdac_adj;
299
300 int h_pos;
301 int v_pos;
302 int h_size;
303 int supported_tv_stds;
304 bool tv_on;
305 enum radeon_tv_std tv_std;
306 struct radeon_tv_regs tv;
307 };
308
309 struct radeon_encoder_int_tmds {
310 /* legacy int tmds */
311 struct radeon_tmds_pll tmds_pll[4];
312 };
313
314 struct radeon_encoder_ext_tmds {
315 /* tmds over dvo */
316 struct radeon_i2c_chan *i2c_bus;
317 uint8_t slave_addr;
318 enum radeon_dvo_chip dvo_chip;
319 };
320
321 /* spread spectrum */
322 struct radeon_atom_ss {
323 uint16_t percentage;
324 uint8_t type;
325 uint8_t step;
326 uint8_t delay;
327 uint8_t range;
328 uint8_t refdiv;
329 };
330
331 struct radeon_encoder_atom_dig {
332 /* atom dig */
333 bool coherent_mode;
334 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
335 /* atom lvds */
336 uint32_t lvds_misc;
337 uint16_t panel_pwr_delay;
338 enum radeon_pll_algo pll_algo;
339 struct radeon_atom_ss *ss;
340 /* panel mode */
341 struct drm_display_mode native_mode;
342 };
343
344 struct radeon_encoder_atom_dac {
345 enum radeon_tv_std tv_std;
346 };
347
348 struct radeon_encoder {
349 struct drm_encoder base;
350 uint32_t encoder_id;
351 uint32_t devices;
352 uint32_t active_device;
353 uint32_t flags;
354 uint32_t pixel_clock;
355 enum radeon_rmx_type rmx_type;
356 struct drm_display_mode native_mode;
357 void *enc_priv;
358 int audio_polling_active;
359 int hdmi_offset;
360 int hdmi_config_offset;
361 int hdmi_audio_workaround;
362 int hdmi_buffer_status;
363 };
364
365 struct radeon_connector_atom_dig {
366 uint32_t igp_lane_info;
367 bool linkb;
368 /* displayport */
369 struct radeon_i2c_chan *dp_i2c_bus;
370 u8 dpcd[8];
371 u8 dp_sink_type;
372 int dp_clock;
373 int dp_lane_count;
374 };
375
376 struct radeon_gpio_rec {
377 bool valid;
378 u8 id;
379 u32 reg;
380 u32 mask;
381 };
382
383 struct radeon_hpd {
384 enum radeon_hpd_id hpd;
385 u8 plugged_state;
386 struct radeon_gpio_rec gpio;
387 };
388
389 struct radeon_connector {
390 struct drm_connector base;
391 uint32_t connector_id;
392 uint32_t devices;
393 struct radeon_i2c_chan *ddc_bus;
394 /* some systems have a an hdmi and vga port with a shared ddc line */
395 bool shared_ddc;
396 bool use_digital;
397 /* we need to mind the EDID between detect
398 and get modes due to analog/digital/tvencoder */
399 struct edid *edid;
400 void *con_priv;
401 bool dac_load_detect;
402 uint16_t connector_object_id;
403 struct radeon_hpd hpd;
404 };
405
406 struct radeon_framebuffer {
407 struct drm_framebuffer base;
408 struct drm_gem_object *obj;
409 };
410
411 extern enum radeon_tv_std
412 radeon_combios_get_tv_info(struct radeon_device *rdev);
413 extern enum radeon_tv_std
414 radeon_atombios_get_tv_info(struct radeon_device *rdev);
415
416 extern void radeon_connector_hotplug(struct drm_connector *connector);
417 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
418 extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
419 struct drm_display_mode *mode);
420 extern void radeon_dp_set_link_config(struct drm_connector *connector,
421 struct drm_display_mode *mode);
422 extern void dp_link_train(struct drm_encoder *encoder,
423 struct drm_connector *connector);
424 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
425 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
426 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
427 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
428 int action, uint8_t lane_num,
429 uint8_t lane_set);
430 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
431 uint8_t write_byte, uint8_t *read_byte);
432
433 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
434 struct radeon_i2c_bus_rec *rec,
435 const char *name);
436 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
437 struct radeon_i2c_bus_rec *rec,
438 const char *name);
439 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
440 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
441 u8 slave_addr,
442 u8 addr,
443 u8 *val);
444 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
445 u8 slave_addr,
446 u8 addr,
447 u8 val);
448 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
449 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
450
451 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
452
453 extern void radeon_compute_pll(struct radeon_pll *pll,
454 uint64_t freq,
455 uint32_t *dot_clock_p,
456 uint32_t *fb_div_p,
457 uint32_t *frac_fb_div_p,
458 uint32_t *ref_div_p,
459 uint32_t *post_div_p);
460
461 extern void radeon_setup_encoder_clones(struct drm_device *dev);
462
463 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
464 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
465 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
466 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
467 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
468 extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
469 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
470 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
471 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
472
473 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
474 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
475 struct drm_framebuffer *old_fb);
476 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
477 struct drm_display_mode *mode,
478 struct drm_display_mode *adjusted_mode,
479 int x, int y,
480 struct drm_framebuffer *old_fb);
481 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
482
483 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
484 struct drm_framebuffer *old_fb);
485
486 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
487 struct drm_file *file_priv,
488 uint32_t handle,
489 uint32_t width,
490 uint32_t height);
491 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
492 int x, int y);
493
494 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
495 extern struct edid *
496 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
497 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
498 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
499 extern struct radeon_encoder_atom_dig *
500 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
501 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
502 struct radeon_encoder_int_tmds *tmds);
503 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
504 struct radeon_encoder_int_tmds *tmds);
505 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
506 struct radeon_encoder_int_tmds *tmds);
507 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
508 struct radeon_encoder_ext_tmds *tmds);
509 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
510 struct radeon_encoder_ext_tmds *tmds);
511 extern struct radeon_encoder_primary_dac *
512 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
513 extern struct radeon_encoder_tv_dac *
514 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
515 extern struct radeon_encoder_lvds *
516 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
517 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
518 extern struct radeon_encoder_tv_dac *
519 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
520 extern struct radeon_encoder_primary_dac *
521 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
522 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
523 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
524 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
525 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
526 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
527 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
528 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
529 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
530 extern void
531 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
532 extern void
533 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
534 extern void
535 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
536 extern void
537 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
538 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
539 u16 blue, int regno);
540 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
541 u16 *blue, int regno);
542 void radeon_framebuffer_init(struct drm_device *dev,
543 struct radeon_framebuffer *rfb,
544 struct drm_mode_fb_cmd *mode_cmd,
545 struct drm_gem_object *obj);
546
547 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
548 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
549 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
550 void radeon_atombios_init_crtc(struct drm_device *dev,
551 struct radeon_crtc *radeon_crtc);
552 void radeon_legacy_init_crtc(struct drm_device *dev,
553 struct radeon_crtc *radeon_crtc);
554
555 void radeon_get_clock_info(struct drm_device *dev);
556
557 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
558 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
559
560 void radeon_enc_destroy(struct drm_encoder *encoder);
561 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
562 void radeon_combios_asic_init(struct drm_device *dev);
563 extern int radeon_static_clocks_init(struct drm_device *dev);
564 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
565 struct drm_display_mode *mode,
566 struct drm_display_mode *adjusted_mode);
567 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
568 struct drm_display_mode *adjusted_mode);
569 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
570
571 /* legacy tv */
572 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
573 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
574 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
575 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
576 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
577 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
578 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
579 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
580 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
581 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
582 struct drm_display_mode *mode,
583 struct drm_display_mode *adjusted_mode);
584
585 /* fbdev layer */
586 int radeon_fbdev_init(struct radeon_device *rdev);
587 void radeon_fbdev_fini(struct radeon_device *rdev);
588 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
589 int radeon_fbdev_total_size(struct radeon_device *rdev);
590 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
591
592 void radeon_fb_output_poll_changed(struct radeon_device *rdev);
593 #endif
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