drivers/gpu/drm/radeon/rs690.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31 #include "rs690d.h"
  32
  33 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
  34 {
  35         unsigned i;
  36         uint32_t tmp;
  37
  38         for (i = 0; i < rdev->usec_timeout; i++) {
  39                 /* read MC_STATUS */
  40                 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
  41                 if (G_000090_MC_SYSTEM_IDLE(tmp))
  42                         return 0;
  43                 udelay(1);
  44         }
  45         return -1;
  46 }
  47
  48 static void rs690_gpu_init(struct radeon_device *rdev)
  49 {
  50         /* FIXME: HDP same place on rs690 ? */
  51         r100_hdp_reset(rdev);
  52         /* FIXME: is this correct ? */
  53         r420_pipes_init(rdev);
  54         if (rs690_mc_wait_for_idle(rdev)) {
  55                 printk(KERN_WARNING "Failed to wait MC idle while "
  56                        "programming pipes. Bad things might happen.\n");
  57         }
  58 }
  59
  60 void rs690_pm_info(struct radeon_device *rdev)
  61 {
  62         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  63         struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
  64         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
  65         void *ptr;
  66         uint16_t data_offset;
  67         uint8_t frev, crev;
  68         fixed20_12 tmp;
  69
  70         atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
  71                                &frev, &crev, &data_offset);
  72         ptr = rdev->mode_info.atom_context->bios + data_offset;
  73         info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
  74         info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
  75         /* Get various system informations from bios */
  76         switch (crev) {
  77         case 1:
  78                 tmp.full = rfixed_const(100);
  79                 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
  80                 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  81                 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
  82                 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
  83                 rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
  84                 break;
  85         case 2:
  86                 tmp.full = rfixed_const(100);
  87                 rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
  88                 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  89                 rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
  90                 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
  91                 rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
  92                 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
  93                 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
  94                 break;
  95         default:
  96                 tmp.full = rfixed_const(100);
  97                 /* We assume the slower possible clock ie worst case */
  98                 /* DDR 333Mhz */
  99                 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
 100                 /* FIXME: system clock ? */
 101                 rdev->pm.igp_system_mclk.full = rfixed_const(100);
 102                 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
 103                 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
 104                 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
 105                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 106                 break;
 107         }
 108         /* Compute various bandwidth */
 109         /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
 110         tmp.full = rfixed_const(4);
 111         rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
 112         /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
 113          *              = ht_clk * ht_width / 5
 114          */
 115         tmp.full = rfixed_const(5);
 116         rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
 117                                                 rdev->pm.igp_ht_link_width);
 118         rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
 119         if (tmp.full < rdev->pm.max_bandwidth.full) {
 120                 /* HT link is a limiting factor */
 121                 rdev->pm.max_bandwidth.full = tmp.full;
 122         }
 123         /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
 124          *                    = (sideport_clk * 14) / 10
 125          */
 126         tmp.full = rfixed_const(14);
 127         rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
 128         tmp.full = rfixed_const(10);
 129         rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
 130 }
 131
 132 void rs690_vram_info(struct radeon_device *rdev)
 133 {
 134         fixed20_12 a;
 135
 136         rs400_gart_adjust_size(rdev);
 137         /* DDR for all card after R300 & IGP */
 138         rdev->mc.vram_is_ddr = true;
 139         rdev->mc.vram_width = 128;
 140
 141         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 142         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 143
 144         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 145         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 146         rs690_pm_info(rdev);
 147         /* FIXME: we should enforce default clock in case GPU is not in
 148          * default setup
 149          */
 150         a.full = rfixed_const(100);
 151         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 152         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 153         a.full = rfixed_const(16);
 154         /* core_bandwidth = sclk(Mhz) * 16 */
 155         rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
 156 }
 157
 158 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 159                               struct drm_display_mode *mode1,
 160                               struct drm_display_mode *mode2)
 161 {
 162         u32 tmp;
 163
 164         /*
 165          * Line Buffer Setup
 166          * There is a single line buffer shared by both display controllers.
 167          * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 168          * the display controllers.  The paritioning can either be done
 169          * manually or via one of four preset allocations specified in bits 1:0:
 170          *  0 - line buffer is divided in half and shared between crtc
 171          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
 172          *  2 - D1 gets the whole buffer
 173          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
 174          * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
 175          * allocation mode. In manual allocation mode, D1 always starts at 0,
 176          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
 177          */
 178         tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
 179         tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
 180         /* auto */
 181         if (mode1 && mode2) {
 182                 if (mode1->hdisplay > mode2->hdisplay) {
 183                         if (mode1->hdisplay > 2560)
 184                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
 185                         else
 186                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 187                 } else if (mode2->hdisplay > mode1->hdisplay) {
 188                         if (mode2->hdisplay > 2560)
 189                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 190                         else
 191                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 192                 } else
 193                         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 194         } else if (mode1) {
 195                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
 196         } else if (mode2) {
 197                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 198         }
 199         WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
 200 }
 201
 202 struct rs690_watermark {
 203         u32        lb_request_fifo_depth;
 204         fixed20_12 num_line_pair;
 205         fixed20_12 estimated_width;
 206         fixed20_12 worst_case_latency;
 207         fixed20_12 consumption_rate;
 208         fixed20_12 active_time;
 209         fixed20_12 dbpp;
 210         fixed20_12 priority_mark_max;
 211         fixed20_12 priority_mark;
 212         fixed20_12 sclk;
 213 };
 214
 215 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 216                                   struct radeon_crtc *crtc,
 217                                   struct rs690_watermark *wm)
 218 {
 219         struct drm_display_mode *mode = &crtc->base.mode;
 220         fixed20_12 a, b, c;
 221         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 222         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 223         /* FIXME: detect IGP with sideport memory, i don't think there is any
 224          * such product available
 225          */
 226         bool sideport = false;
 227
 228         if (!crtc->base.enabled) {
 229                 /* FIXME: wouldn't it better to set priority mark to maximum */
 230                 wm->lb_request_fifo_depth = 4;
 231                 return;
 232         }
 233
 234         if (crtc->vsc.full > rfixed_const(2))
 235                 wm->num_line_pair.full = rfixed_const(2);
 236         else
 237                 wm->num_line_pair.full = rfixed_const(1);
 238
 239         b.full = rfixed_const(mode->crtc_hdisplay);
 240         c.full = rfixed_const(256);
 241         a.full = rfixed_mul(wm->num_line_pair, b);
 242         request_fifo_depth.full = rfixed_div(a, c);
 243         if (a.full < rfixed_const(4)) {
 244                 wm->lb_request_fifo_depth = 4;
 245         } else {
 246                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
 247         }
 248
 249         /* Determine consumption rate
 250          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 251          *  vtaps = number of vertical taps,
 252          *  vsc = vertical scaling ratio, defined as source/destination
 253          *  hsc = horizontal scaling ration, defined as source/destination
 254          */
 255         a.full = rfixed_const(mode->clock);
 256         b.full = rfixed_const(1000);
 257         a.full = rfixed_div(a, b);
 258         pclk.full = rfixed_div(b, a);
 259         if (crtc->rmx_type != RMX_OFF) {
 260                 b.full = rfixed_const(2);
 261                 if (crtc->vsc.full > b.full)
 262                         b.full = crtc->vsc.full;
 263                 b.full = rfixed_mul(b, crtc->hsc);
 264                 c.full = rfixed_const(2);
 265                 b.full = rfixed_div(b, c);
 266                 consumption_time.full = rfixed_div(pclk, b);
 267         } else {
 268                 consumption_time.full = pclk.full;
 269         }
 270         a.full = rfixed_const(1);
 271         wm->consumption_rate.full = rfixed_div(a, consumption_time);
 272
 273
 274         /* Determine line time
 275          *  LineTime = total time for one line of displayhtotal
 276          *  LineTime = total number of horizontal pixels
 277          *  pclk = pixel clock period(ns)
 278          */
 279         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 280         line_time.full = rfixed_mul(a, pclk);
 281
 282         /* Determine active time
 283          *  ActiveTime = time of active region of display within one line,
 284          *  hactive = total number of horizontal active pixels
 285          *  htotal = total number of horizontal pixels
 286          */
 287         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 288         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 289         wm->active_time.full = rfixed_mul(line_time, b);
 290         wm->active_time.full = rfixed_div(wm->active_time, a);
 291
 292         /* Maximun bandwidth is the minimun bandwidth of all component */
 293         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
 294         if (sideport) {
 295                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
 296                         rdev->pm.sideport_bandwidth.full)
 297                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
 298                 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
 299                 read_delay_latency.full = rfixed_div(read_delay_latency,
 300                         rdev->pm.igp_sideport_mclk);
 301         } else {
 302                 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
 303                         rdev->pm.k8_bandwidth.full)
 304                         rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
 305                 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
 306                         rdev->pm.ht_bandwidth.full)
 307                         rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
 308                 read_delay_latency.full = rfixed_const(5000);
 309         }
 310
 311         /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
 312         a.full = rfixed_const(16);
 313         rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
 314         a.full = rfixed_const(1000);
 315         rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
 316         /* Determine chunk time
 317          * ChunkTime = the time it takes the DCP to send one chunk of data
 318          * to the LB which consists of pipeline delay and inter chunk gap
 319          * sclk = system clock(ns)
 320          */
 321         a.full = rfixed_const(256 * 13);
 322         chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
 323         a.full = rfixed_const(10);
 324         chunk_time.full = rfixed_div(chunk_time, a);
 325
 326         /* Determine the worst case latency
 327          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 328          * WorstCaseLatency = worst case time from urgent to when the MC starts
 329          *                    to return data
 330          * READ_DELAY_IDLE_MAX = constant of 1us
 331          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 332          *             which consists of pipeline delay and inter chunk gap
 333          */
 334         if (rfixed_trunc(wm->num_line_pair) > 1) {
 335                 a.full = rfixed_const(3);
 336                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 337                 wm->worst_case_latency.full += read_delay_latency.full;
 338         } else {
 339                 a.full = rfixed_const(2);
 340                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 341                 wm->worst_case_latency.full += read_delay_latency.full;
 342         }
 343
 344         /* Determine the tolerable latency
 345          * TolerableLatency = Any given request has only 1 line time
 346          *                    for the data to be returned
 347          * LBRequestFifoDepth = Number of chunk requests the LB can
 348          *                      put into the request FIFO for a display
 349          *  LineTime = total time for one line of display
 350          *  ChunkTime = the time it takes the DCP to send one chunk
 351          *              of data to the LB which consists of
 352          *  pipeline delay and inter chunk gap
 353          */
 354         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
 355                 tolerable_latency.full = line_time.full;
 356         } else {
 357                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
 358                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 359                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
 360                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 361         }
 362         /* We assume worst case 32bits (4 bytes) */
 363         wm->dbpp.full = rfixed_const(4 * 8);
 364
 365         /* Determine the maximum priority mark
 366          *  width = viewport width in pixels
 367          */
 368         a.full = rfixed_const(16);
 369         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 370         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
 371
 372         /* Determine estimated width */
 373         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 374         estimated_width.full = rfixed_div(estimated_width, consumption_time);
 375         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 376                 wm->priority_mark.full = rfixed_const(10);
 377         } else {
 378                 a.full = rfixed_const(16);
 379                 wm->priority_mark.full = rfixed_div(estimated_width, a);
 380                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 381         }
 382 }
 383
 384 void rs690_bandwidth_update(struct radeon_device *rdev)
 385 {
 386         struct drm_display_mode *mode0 = NULL;
 387         struct drm_display_mode *mode1 = NULL;
 388         struct rs690_watermark wm0;
 389         struct rs690_watermark wm1;
 390         u32 tmp;
 391         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 392         fixed20_12 a, b;
 393
 394         if (rdev->mode_info.crtcs[0]->base.enabled)
 395                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 396         if (rdev->mode_info.crtcs[1]->base.enabled)
 397                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 398         /*
 399          * Set display0/1 priority up in the memory controller for
 400          * modes if the user specifies HIGH for displaypriority
 401          * option.
 402          */
 403         if (rdev->disp_priority == 2) {
 404                 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
 405                 tmp &= C_000104_MC_DISP0R_INIT_LAT;
 406                 tmp &= C_000104_MC_DISP1R_INIT_LAT;
 407                 if (mode0)
 408                         tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
 409                 if (mode1)
 410                         tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
 411                 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
 412         }
 413         rs690_line_buffer_adjust(rdev, mode0, mode1);
 414
 415         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
 416                 WREG32(R_006C9C_DCP_CONTROL, 0);
 417         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 418                 WREG32(R_006C9C_DCP_CONTROL, 2);
 419
 420         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 421         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 422
 423         tmp = (wm0.lb_request_fifo_depth - 1);
 424         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
 425         WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
 426
 427         if (mode0 && mode1) {
 428                 if (rfixed_trunc(wm0.dbpp) > 64)
 429                         a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
 430                 else
 431                         a.full = wm0.num_line_pair.full;
 432                 if (rfixed_trunc(wm1.dbpp) > 64)
 433                         b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
 434                 else
 435                         b.full = wm1.num_line_pair.full;
 436                 a.full += b.full;
 437                 fill_rate.full = rfixed_div(wm0.sclk, a);
 438                 if (wm0.consumption_rate.full > fill_rate.full) {
 439                         b.full = wm0.consumption_rate.full - fill_rate.full;
 440                         b.full = rfixed_mul(b, wm0.active_time);
 441                         a.full = rfixed_mul(wm0.worst_case_latency,
 442                                                 wm0.consumption_rate);
 443                         a.full = a.full + b.full;
 444                         b.full = rfixed_const(16 * 1000);
 445                         priority_mark02.full = rfixed_div(a, b);
 446                 } else {
 447                         a.full = rfixed_mul(wm0.worst_case_latency,
 448                                                 wm0.consumption_rate);
 449                         b.full = rfixed_const(16 * 1000);
 450                         priority_mark02.full = rfixed_div(a, b);
 451                 }
 452                 if (wm1.consumption_rate.full > fill_rate.full) {
 453                         b.full = wm1.consumption_rate.full - fill_rate.full;
 454                         b.full = rfixed_mul(b, wm1.active_time);
 455                         a.full = rfixed_mul(wm1.worst_case_latency,
 456                                                 wm1.consumption_rate);
 457                         a.full = a.full + b.full;
 458                         b.full = rfixed_const(16 * 1000);
 459                         priority_mark12.full = rfixed_div(a, b);
 460                 } else {
 461                         a.full = rfixed_mul(wm1.worst_case_latency,
 462                                                 wm1.consumption_rate);
 463                         b.full = rfixed_const(16 * 1000);
 464                         priority_mark12.full = rfixed_div(a, b);
 465                 }
 466                 if (wm0.priority_mark.full > priority_mark02.full)
 467                         priority_mark02.full = wm0.priority_mark.full;
 468                 if (rfixed_trunc(priority_mark02) < 0)
 469                         priority_mark02.full = 0;
 470                 if (wm0.priority_mark_max.full > priority_mark02.full)
 471                         priority_mark02.full = wm0.priority_mark_max.full;
 472                 if (wm1.priority_mark.full > priority_mark12.full)
 473                         priority_mark12.full = wm1.priority_mark.full;
 474                 if (rfixed_trunc(priority_mark12) < 0)
 475                         priority_mark12.full = 0;
 476                 if (wm1.priority_mark_max.full > priority_mark12.full)
 477                         priority_mark12.full = wm1.priority_mark_max.full;
 478                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 479                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 480                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 481                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 482         } else if (mode0) {
 483                 if (rfixed_trunc(wm0.dbpp) > 64)
 484                         a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
 485                 else
 486                         a.full = wm0.num_line_pair.full;
 487                 fill_rate.full = rfixed_div(wm0.sclk, a);
 488                 if (wm0.consumption_rate.full > fill_rate.full) {
 489                         b.full = wm0.consumption_rate.full - fill_rate.full;
 490                         b.full = rfixed_mul(b, wm0.active_time);
 491                         a.full = rfixed_mul(wm0.worst_case_latency,
 492                                                 wm0.consumption_rate);
 493                         a.full = a.full + b.full;
 494                         b.full = rfixed_const(16 * 1000);
 495                         priority_mark02.full = rfixed_div(a, b);
 496                 } else {
 497                         a.full = rfixed_mul(wm0.worst_case_latency,
 498                                                 wm0.consumption_rate);
 499                         b.full = rfixed_const(16 * 1000);
 500                         priority_mark02.full = rfixed_div(a, b);
 501                 }
 502                 if (wm0.priority_mark.full > priority_mark02.full)
 503                         priority_mark02.full = wm0.priority_mark.full;
 504                 if (rfixed_trunc(priority_mark02) < 0)
 505                         priority_mark02.full = 0;
 506                 if (wm0.priority_mark_max.full > priority_mark02.full)
 507                         priority_mark02.full = wm0.priority_mark_max.full;
 508                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 509                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 510                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
 511                         S_006D48_D2MODE_PRIORITY_A_OFF(1));
 512                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
 513                         S_006D4C_D2MODE_PRIORITY_B_OFF(1));
 514         } else {
 515                 if (rfixed_trunc(wm1.dbpp) > 64)
 516                         a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
 517                 else
 518                         a.full = wm1.num_line_pair.full;
 519                 fill_rate.full = rfixed_div(wm1.sclk, a);
 520                 if (wm1.consumption_rate.full > fill_rate.full) {
 521                         b.full = wm1.consumption_rate.full - fill_rate.full;
 522                         b.full = rfixed_mul(b, wm1.active_time);
 523                         a.full = rfixed_mul(wm1.worst_case_latency,
 524                                                 wm1.consumption_rate);
 525                         a.full = a.full + b.full;
 526                         b.full = rfixed_const(16 * 1000);
 527                         priority_mark12.full = rfixed_div(a, b);
 528                 } else {
 529                         a.full = rfixed_mul(wm1.worst_case_latency,
 530                                                 wm1.consumption_rate);
 531                         b.full = rfixed_const(16 * 1000);
 532                         priority_mark12.full = rfixed_div(a, b);
 533                 }
 534                 if (wm1.priority_mark.full > priority_mark12.full)
 535                         priority_mark12.full = wm1.priority_mark.full;
 536                 if (rfixed_trunc(priority_mark12) < 0)
 537                         priority_mark12.full = 0;
 538                 if (wm1.priority_mark_max.full > priority_mark12.full)
 539                         priority_mark12.full = wm1.priority_mark_max.full;
 540                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
 541                         S_006548_D1MODE_PRIORITY_A_OFF(1));
 542                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
 543                         S_00654C_D1MODE_PRIORITY_B_OFF(1));
 544                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 545                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 546         }
 547 }
 548
 549 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 550 {
 551         uint32_t r;
 552
 553         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
 554         r = RREG32(R_00007C_MC_DATA);
 555         WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
 556         return r;
 557 }
 558
 559 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 560 {
 561         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
 562                 S_000078_MC_IND_WR_EN(1));
 563         WREG32(R_00007C_MC_DATA, v);
 564         WREG32(R_000078_MC_INDEX, 0x7F);
 565 }
 566
 567 void rs690_mc_program(struct radeon_device *rdev)
 568 {
 569         struct rv515_mc_save save;
 570
 571         /* Stops all mc clients */
 572         rv515_mc_stop(rdev, &save);
 573
 574         /* Wait for mc idle */
 575         if (rs690_mc_wait_for_idle(rdev))
 576                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 577         /* Program MC, should be a 32bits limited address space */
 578         WREG32_MC(R_000100_MCCFG_FB_LOCATION,
 579                         S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
 580                         S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
 581         WREG32(R_000134_HDP_FB_LOCATION,
 582                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 583
 584         rv515_mc_resume(rdev, &save);
 585 }
 586
 587 static int rs690_startup(struct radeon_device *rdev)
 588 {
 589         int r;
 590
 591         rs690_mc_program(rdev);
 592         /* Resume clock */
 593         rv515_clock_startup(rdev);
 594         /* Initialize GPU configuration (# pipes, ...) */
 595         rs690_gpu_init(rdev);
 596         /* Initialize GART (initialize after TTM so we can allocate
 597          * memory through TTM but finalize after TTM) */
 598         r = rs400_gart_enable(rdev);
 599         if (r)
 600                 return r;
 601         /* Enable IRQ */
 602         rs600_irq_set(rdev);
 603         /* 1M ring buffer */
 604         r = r100_cp_init(rdev, 1024 * 1024);
 605         if (r) {
 606                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 607                 return r;
 608         }
 609         r = r100_wb_init(rdev);
 610         if (r)
 611                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 612         r = r100_ib_init(rdev);
 613         if (r) {
 614                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 615                 return r;
 616         }
 617         return 0;
 618 }
 619
 620 int rs690_resume(struct radeon_device *rdev)
 621 {
 622         /* Make sur GART are not working */
 623         rs400_gart_disable(rdev);
 624         /* Resume clock before doing reset */
 625         rv515_clock_startup(rdev);
 626         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 627         if (radeon_gpu_reset(rdev)) {
 628                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 629                         RREG32(R_000E40_RBBM_STATUS),
 630                         RREG32(R_0007C0_CP_STAT));
 631         }
 632         /* post */
 633         atom_asic_init(rdev->mode_info.atom_context);
 634         /* Resume clock after posting */
 635         rv515_clock_startup(rdev);
 636         return rs690_startup(rdev);
 637 }
 638
 639 int rs690_suspend(struct radeon_device *rdev)
 640 {
 641         r100_cp_disable(rdev);
 642         r100_wb_disable(rdev);
 643         rs600_irq_disable(rdev);
 644         rs400_gart_disable(rdev);
 645         return 0;
 646 }
 647
 648 void rs690_fini(struct radeon_device *rdev)
 649 {
 650         rs690_suspend(rdev);
 651         r100_cp_fini(rdev);
 652         r100_wb_fini(rdev);
 653         r100_ib_fini(rdev);
 654         radeon_gem_fini(rdev);
 655         rs400_gart_fini(rdev);
 656         radeon_irq_kms_fini(rdev);
 657         radeon_fence_driver_fini(rdev);
 658         radeon_bo_fini(rdev);
 659         radeon_atombios_fini(rdev);
 660         kfree(rdev->bios);
 661         rdev->bios = NULL;
 662 }
 663
 664 int rs690_init(struct radeon_device *rdev)
 665 {
 666         int r;
 667
 668         /* Disable VGA */
 669         rv515_vga_render_disable(rdev);
 670         /* Initialize scratch registers */
 671         radeon_scratch_init(rdev);
 672         /* Initialize surface registers */
 673         radeon_surface_init(rdev);
 674         /* TODO: disable VGA need to use VGA request */
 675         /* BIOS*/
 676         if (!radeon_get_bios(rdev)) {
 677                 if (ASIC_IS_AVIVO(rdev))
 678                         return -EINVAL;
 679         }
 680         if (rdev->is_atom_bios) {
 681                 r = radeon_atombios_init(rdev);
 682                 if (r)
 683                         return r;
 684         } else {
 685                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 686                 return -EINVAL;
 687         }
 688         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 689         if (radeon_gpu_reset(rdev)) {
 690                 dev_warn(rdev->dev,
 691                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 692                         RREG32(R_000E40_RBBM_STATUS),
 693                         RREG32(R_0007C0_CP_STAT));
 694         }
 695         /* check if cards are posted or not */
 696         if (radeon_boot_test_post_card(rdev) == false)
 697                 return -EINVAL;
 698
 699         /* Initialize clocks */
 700         radeon_get_clock_info(rdev->ddev);
 701         /* Initialize power management */
 702         radeon_pm_init(rdev);
 703         /* Get vram informations */
 704         rs690_vram_info(rdev);
 705         /* Initialize memory controller (also test AGP) */
 706         r = r420_mc_init(rdev);
 707         if (r)
 708                 return r;
 709         rv515_debugfs(rdev);
 710         /* Fence driver */
 711         r = radeon_fence_driver_init(rdev);
 712         if (r)
 713                 return r;
 714         r = radeon_irq_kms_init(rdev);
 715         if (r)
 716                 return r;
 717         /* Memory manager */
 718         r = radeon_bo_init(rdev);
 719         if (r)
 720                 return r;
 721         r = rs400_gart_init(rdev);
 722         if (r)
 723                 return r;
 724         rs600_set_safe_registers(rdev);
 725         rdev->accel_working = true;
 726         r = rs690_startup(rdev);
 727         if (r) {
 728                 /* Somethings want wront with the accel init stop accel */
 729                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 730                 rs690_suspend(rdev);
 731                 r100_cp_fini(rdev);
 732                 r100_wb_fini(rdev);
 733                 r100_ib_fini(rdev);
 734                 rs400_gart_fini(rdev);
 735                 radeon_irq_kms_fini(rdev);
 736                 rdev->accel_working = false;
 737         }
 738         return 0;
 739 }