2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/math64.h>
31 #include <linux/seq_file.h>
33 #define MC_CG_ARB_FREQ_F0 0x0a
34 #define MC_CG_ARB_FREQ_F1 0x0b
35 #define MC_CG_ARB_FREQ_F2 0x0c
36 #define MC_CG_ARB_FREQ_F3 0x0d
38 #define SMC_RAM_END 0x20000
40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
42 static const struct si_cac_config_reg cac_weights_tahiti
[] =
44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND
},
45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND
},
47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND
},
48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND
},
54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND
},
56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND
},
57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND
},
58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND
},
59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND
},
62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND
},
64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND
},
65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND
},
66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND
},
75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND
},
84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND
},
107 static const struct si_cac_config_reg lcac_tahiti
[] =
109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND
},
110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND
},
112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND
},
114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND
},
116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
199 static const struct si_cac_config_reg cac_override_tahiti
[] =
204 static const struct si_powertune_data powertune_data_tahiti
=
235 static const struct si_dte_data dte_data_tahiti
=
237 { 1159409, 0, 0, 0, 0 },
246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
253 static const struct si_dte_data dte_data_tahiti_le
=
255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
271 static const struct si_dte_data dte_data_tahiti_pro
=
273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
274 { 0x0, 0x0, 0x0, 0x0, 0x0 },
282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
289 static const struct si_dte_data dte_data_new_zealand
=
291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
307 static const struct si_dte_data dte_data_aruba_pro
=
309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
310 { 0x0, 0x0, 0x0, 0x0, 0x0 },
318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
325 static const struct si_dte_data dte_data_malta
=
327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
328 { 0x0, 0x0, 0x0, 0x0, 0x0 },
336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
343 struct si_cac_config_reg cac_weights_pitcairn
[] =
345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND
},
346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND
},
349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND
},
350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND
},
355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND
},
356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND
},
357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND
},
358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND
},
359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND
},
363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND
},
364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND
},
365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND
},
366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND
},
367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND
},
368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND
},
371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND
},
372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND
},
376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND
},
378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND
},
380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND
},
381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND
},
382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND
},
384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND
},
408 static const struct si_cac_config_reg lcac_pitcairn
[] =
410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
499 static const struct si_cac_config_reg cac_override_pitcairn
[] =
504 static const struct si_powertune_data powertune_data_pitcairn
=
535 static const struct si_dte_data dte_data_pitcairn
=
546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
553 static const struct si_dte_data dte_data_curacao_xt
=
555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
556 { 0x0, 0x0, 0x0, 0x0, 0x0 },
564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
571 static const struct si_dte_data dte_data_curacao_pro
=
573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
574 { 0x0, 0x0, 0x0, 0x0, 0x0 },
582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
589 static const struct si_dte_data dte_data_neptune_xt
=
591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
592 { 0x0, 0x0, 0x0, 0x0, 0x0 },
600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
607 static const struct si_cac_config_reg cac_weights_chelsea_pro
[] =
609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND
},
645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
672 static const struct si_cac_config_reg cac_weights_chelsea_xt
[] =
674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND
},
710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
737 static const struct si_cac_config_reg cac_weights_heathrow
[] =
739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND
},
775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
802 static const struct si_cac_config_reg cac_weights_cape_verde_pro
[] =
804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND
},
840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
867 static const struct si_cac_config_reg cac_weights_cape_verde
[] =
869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND
},
905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
932 static const struct si_cac_config_reg lcac_cape_verde
[] =
934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
991 static const struct si_cac_config_reg cac_override_cape_verde
[] =
996 static const struct si_powertune_data powertune_data_cape_verde
=
998 ((1 << 16) | 0x6993),
1027 static const struct si_dte_data dte_data_cape_verde
=
1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1045 static const struct si_dte_data dte_data_venus_xtx
=
1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1063 static const struct si_dte_data dte_data_venus_xt
=
1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1081 static const struct si_dte_data dte_data_venus_pro
=
1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1099 struct si_cac_config_reg cac_weights_oland
[] =
1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND
},
1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
1164 static const struct si_cac_config_reg cac_weights_mars_pro
[] =
1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND
},
1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND
},
1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND
},
1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND
},
1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND
},
1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND
},
1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND
},
1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND
},
1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND
},
1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND
},
1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND
},
1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND
},
1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND
},
1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND
},
1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND
},
1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND
},
1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND
},
1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND
},
1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND
},
1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND
},
1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND
},
1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND
},
1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND
},
1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND
},
1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND
},
1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND
},
1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND
},
1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND
},
1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND
},
1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND
},
1229 static const struct si_cac_config_reg cac_weights_mars_xt
[] =
1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND
},
1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND
},
1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND
},
1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND
},
1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND
},
1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND
},
1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND
},
1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND
},
1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND
},
1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND
},
1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND
},
1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND
},
1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND
},
1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND
},
1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND
},
1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND
},
1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND
},
1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND
},
1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND
},
1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND
},
1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND
},
1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND
},
1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND
},
1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND
},
1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND
},
1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND
},
1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND
},
1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND
},
1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND
},
1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND
},
1294 static const struct si_cac_config_reg cac_weights_oland_pro
[] =
1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND
},
1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND
},
1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND
},
1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND
},
1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND
},
1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND
},
1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND
},
1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND
},
1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND
},
1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND
},
1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND
},
1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND
},
1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND
},
1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND
},
1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND
},
1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND
},
1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND
},
1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND
},
1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND
},
1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND
},
1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND
},
1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND
},
1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND
},
1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND
},
1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND
},
1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND
},
1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND
},
1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND
},
1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND
},
1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND
},
1359 static const struct si_cac_config_reg cac_weights_oland_xt
[] =
1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND
},
1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND
},
1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND
},
1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND
},
1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND
},
1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND
},
1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND
},
1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND
},
1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND
},
1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND
},
1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND
},
1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND
},
1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND
},
1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND
},
1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND
},
1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND
},
1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND
},
1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND
},
1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND
},
1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND
},
1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND
},
1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND
},
1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND
},
1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND
},
1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND
},
1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND
},
1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND
},
1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND
},
1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND
},
1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND
},
1424 static const struct si_cac_config_reg lcac_oland
[] =
1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1471 static const struct si_cac_config_reg lcac_mars_pro
[] =
1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1518 static const struct si_cac_config_reg cac_override_oland
[] =
1523 static const struct si_powertune_data powertune_data_oland
=
1525 ((1 << 16) | 0x6993),
1554 static const struct si_powertune_data powertune_data_mars_pro
=
1556 ((1 << 16) | 0x6993),
1585 static const struct si_dte_data dte_data_oland
=
1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1603 static const struct si_dte_data dte_data_mars_pro
=
1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1621 static const struct si_dte_data dte_data_sun_xt
=
1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1640 static const struct si_cac_config_reg cac_weights_hainan
[] =
1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND
},
1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND
},
1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND
},
1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND
},
1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND
},
1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND
},
1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND
},
1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND
},
1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND
},
1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND
},
1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND
},
1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND
},
1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND
},
1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND
},
1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND
},
1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND
},
1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND
},
1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND
},
1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND
},
1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND
},
1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND
},
1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND
},
1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND
},
1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND
},
1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND
},
1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND
},
1705 static const struct si_powertune_data powertune_data_hainan
=
1707 ((1 << 16) | 0x6993),
1736 struct rv7xx_power_info
*rv770_get_pi(struct radeon_device
*rdev
);
1737 struct evergreen_power_info
*evergreen_get_pi(struct radeon_device
*rdev
);
1738 struct ni_power_info
*ni_get_pi(struct radeon_device
*rdev
);
1739 struct ni_ps
*ni_get_ps(struct radeon_ps
*rps
);
1741 static int si_populate_voltage_value(struct radeon_device
*rdev
,
1742 const struct atom_voltage_table
*table
,
1743 u16 value
, SISLANDS_SMC_VOLTAGE_VALUE
*voltage
);
1744 static int si_get_std_voltage_value(struct radeon_device
*rdev
,
1745 SISLANDS_SMC_VOLTAGE_VALUE
*voltage
,
1747 static int si_write_smc_soft_register(struct radeon_device
*rdev
,
1748 u16 reg_offset
, u32 value
);
1749 static int si_convert_power_level_to_smc(struct radeon_device
*rdev
,
1750 struct rv7xx_pl
*pl
,
1751 SISLANDS_SMC_HW_PERFORMANCE_LEVEL
*level
);
1752 static int si_calculate_sclk_params(struct radeon_device
*rdev
,
1754 SISLANDS_SMC_SCLK_VALUE
*sclk
);
1756 static struct si_power_info
*si_get_pi(struct radeon_device
*rdev
)
1758 struct si_power_info
*pi
= rdev
->pm
.dpm
.priv
;
1763 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients
*coeff
,
1764 u16 v
, s32 t
, u32 ileakage
, u32
*leakage
)
1766 s64 kt
, kv
, leakage_w
, i_leakage
, vddc
;
1767 s64 temperature
, t_slope
, t_intercept
, av
, bv
, t_ref
;
1770 i_leakage
= div64_s64(drm_int2fixp(ileakage
), 100);
1771 vddc
= div64_s64(drm_int2fixp(v
), 1000);
1772 temperature
= div64_s64(drm_int2fixp(t
), 1000);
1774 t_slope
= div64_s64(drm_int2fixp(coeff
->t_slope
), 100000000);
1775 t_intercept
= div64_s64(drm_int2fixp(coeff
->t_intercept
), 100000000);
1776 av
= div64_s64(drm_int2fixp(coeff
->av
), 100000000);
1777 bv
= div64_s64(drm_int2fixp(coeff
->bv
), 100000000);
1778 t_ref
= drm_int2fixp(coeff
->t_ref
);
1780 tmp
= drm_fixp_mul(t_slope
, vddc
) + t_intercept
;
1781 kt
= drm_fixp_exp(drm_fixp_mul(tmp
, temperature
));
1782 kt
= drm_fixp_div(kt
, drm_fixp_exp(drm_fixp_mul(tmp
, t_ref
)));
1783 kv
= drm_fixp_mul(av
, drm_fixp_exp(drm_fixp_mul(bv
, vddc
)));
1785 leakage_w
= drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage
, kt
), kv
), vddc
);
1787 *leakage
= drm_fixp2int(leakage_w
* 1000);
1790 static void si_calculate_leakage_for_v_and_t(struct radeon_device
*rdev
,
1791 const struct ni_leakage_coeffients
*coeff
,
1797 si_calculate_leakage_for_v_and_t_formula(coeff
, v
, t
, i_leakage
, leakage
);
1800 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients
*coeff
,
1801 const u32 fixed_kt
, u16 v
,
1802 u32 ileakage
, u32
*leakage
)
1804 s64 kt
, kv
, leakage_w
, i_leakage
, vddc
;
1806 i_leakage
= div64_s64(drm_int2fixp(ileakage
), 100);
1807 vddc
= div64_s64(drm_int2fixp(v
), 1000);
1809 kt
= div64_s64(drm_int2fixp(fixed_kt
), 100000000);
1810 kv
= drm_fixp_mul(div64_s64(drm_int2fixp(coeff
->av
), 100000000),
1811 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff
->bv
), 100000000), vddc
)));
1813 leakage_w
= drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage
, kt
), kv
), vddc
);
1815 *leakage
= drm_fixp2int(leakage_w
* 1000);
1818 static void si_calculate_leakage_for_v(struct radeon_device
*rdev
,
1819 const struct ni_leakage_coeffients
*coeff
,
1825 si_calculate_leakage_for_v_formula(coeff
, fixed_kt
, v
, i_leakage
, leakage
);
1829 static void si_update_dte_from_pl2(struct radeon_device
*rdev
,
1830 struct si_dte_data
*dte_data
)
1832 u32 p_limit1
= rdev
->pm
.dpm
.tdp_limit
;
1833 u32 p_limit2
= rdev
->pm
.dpm
.near_tdp_limit
;
1834 u32 k
= dte_data
->k
;
1835 u32 t_max
= dte_data
->max_t
;
1836 u32 t_split
[5] = { 10, 15, 20, 25, 30 };
1837 u32 t_0
= dte_data
->t0
;
1840 if (p_limit2
!= 0 && p_limit2
<= p_limit1
) {
1841 dte_data
->tdep_count
= 3;
1843 for (i
= 0; i
< k
; i
++) {
1845 (t_split
[i
] * (t_max
- t_0
/(u32
)1000) * (1 << 14)) /
1846 (p_limit2
* (u32
)100);
1849 dte_data
->tdep_r
[1] = dte_data
->r
[4] * 2;
1851 for (i
= 2; i
< SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE
; i
++) {
1852 dte_data
->tdep_r
[i
] = dte_data
->r
[4];
1855 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1859 static void si_initialize_powertune_defaults(struct radeon_device
*rdev
)
1861 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
1862 struct si_power_info
*si_pi
= si_get_pi(rdev
);
1863 bool update_dte_from_pl2
= false;
1865 if (rdev
->family
== CHIP_TAHITI
) {
1866 si_pi
->cac_weights
= cac_weights_tahiti
;
1867 si_pi
->lcac_config
= lcac_tahiti
;
1868 si_pi
->cac_override
= cac_override_tahiti
;
1869 si_pi
->powertune_data
= &powertune_data_tahiti
;
1870 si_pi
->dte_data
= dte_data_tahiti
;
1872 switch (rdev
->pdev
->device
) {
1874 si_pi
->dte_data
.enable_dte_by_default
= true;
1877 si_pi
->dte_data
= dte_data_new_zealand
;
1883 si_pi
->dte_data
= dte_data_aruba_pro
;
1884 update_dte_from_pl2
= true;
1887 si_pi
->dte_data
= dte_data_malta
;
1888 update_dte_from_pl2
= true;
1891 si_pi
->dte_data
= dte_data_tahiti_pro
;
1892 update_dte_from_pl2
= true;
1895 if (si_pi
->dte_data
.enable_dte_by_default
== true)
1896 DRM_ERROR("DTE is not enabled!\n");
1899 } else if (rdev
->family
== CHIP_PITCAIRN
) {
1900 switch (rdev
->pdev
->device
) {
1903 si_pi
->cac_weights
= cac_weights_pitcairn
;
1904 si_pi
->lcac_config
= lcac_pitcairn
;
1905 si_pi
->cac_override
= cac_override_pitcairn
;
1906 si_pi
->powertune_data
= &powertune_data_pitcairn
;
1907 si_pi
->dte_data
= dte_data_curacao_xt
;
1908 update_dte_from_pl2
= true;
1912 si_pi
->cac_weights
= cac_weights_pitcairn
;
1913 si_pi
->lcac_config
= lcac_pitcairn
;
1914 si_pi
->cac_override
= cac_override_pitcairn
;
1915 si_pi
->powertune_data
= &powertune_data_pitcairn
;
1916 si_pi
->dte_data
= dte_data_curacao_pro
;
1917 update_dte_from_pl2
= true;
1921 si_pi
->cac_weights
= cac_weights_pitcairn
;
1922 si_pi
->lcac_config
= lcac_pitcairn
;
1923 si_pi
->cac_override
= cac_override_pitcairn
;
1924 si_pi
->powertune_data
= &powertune_data_pitcairn
;
1925 si_pi
->dte_data
= dte_data_neptune_xt
;
1926 update_dte_from_pl2
= true;
1929 si_pi
->cac_weights
= cac_weights_pitcairn
;
1930 si_pi
->lcac_config
= lcac_pitcairn
;
1931 si_pi
->cac_override
= cac_override_pitcairn
;
1932 si_pi
->powertune_data
= &powertune_data_pitcairn
;
1933 si_pi
->dte_data
= dte_data_pitcairn
;
1936 } else if (rdev
->family
== CHIP_VERDE
) {
1937 si_pi
->lcac_config
= lcac_cape_verde
;
1938 si_pi
->cac_override
= cac_override_cape_verde
;
1939 si_pi
->powertune_data
= &powertune_data_cape_verde
;
1941 switch (rdev
->pdev
->device
) {
1946 si_pi
->cac_weights
= cac_weights_cape_verde_pro
;
1947 si_pi
->dte_data
= dte_data_cape_verde
;
1951 si_pi
->cac_weights
= cac_weights_heathrow
;
1952 si_pi
->dte_data
= dte_data_cape_verde
;
1956 si_pi
->cac_weights
= cac_weights_chelsea_xt
;
1957 si_pi
->dte_data
= dte_data_cape_verde
;
1960 si_pi
->cac_weights
= cac_weights_chelsea_pro
;
1961 si_pi
->dte_data
= dte_data_cape_verde
;
1964 si_pi
->cac_weights
= cac_weights_heathrow
;
1965 si_pi
->dte_data
= dte_data_venus_xtx
;
1968 si_pi
->cac_weights
= cac_weights_heathrow
;
1969 si_pi
->dte_data
= dte_data_venus_xt
;
1972 si_pi
->cac_weights
= cac_weights_chelsea_pro
;
1973 si_pi
->dte_data
= dte_data_venus_pro
;
1976 si_pi
->cac_weights
= cac_weights_chelsea_pro
;
1977 si_pi
->dte_data
= dte_data_venus_pro
;
1980 si_pi
->cac_weights
= cac_weights_cape_verde
;
1981 si_pi
->dte_data
= dte_data_cape_verde
;
1984 } else if (rdev
->family
== CHIP_OLAND
) {
1985 switch (rdev
->pdev
->device
) {
1989 si_pi
->cac_weights
= cac_weights_mars_pro
;
1990 si_pi
->lcac_config
= lcac_mars_pro
;
1991 si_pi
->cac_override
= cac_override_oland
;
1992 si_pi
->powertune_data
= &powertune_data_mars_pro
;
1993 si_pi
->dte_data
= dte_data_mars_pro
;
1994 update_dte_from_pl2
= true;
1999 si_pi
->cac_weights
= cac_weights_mars_xt
;
2000 si_pi
->lcac_config
= lcac_mars_pro
;
2001 si_pi
->cac_override
= cac_override_oland
;
2002 si_pi
->powertune_data
= &powertune_data_mars_pro
;
2003 si_pi
->dte_data
= dte_data_mars_pro
;
2004 update_dte_from_pl2
= true;
2007 si_pi
->cac_weights
= cac_weights_oland_pro
;
2008 si_pi
->lcac_config
= lcac_mars_pro
;
2009 si_pi
->cac_override
= cac_override_oland
;
2010 si_pi
->powertune_data
= &powertune_data_mars_pro
;
2011 si_pi
->dte_data
= dte_data_mars_pro
;
2012 update_dte_from_pl2
= true;
2015 si_pi
->cac_weights
= cac_weights_oland_xt
;
2016 si_pi
->lcac_config
= lcac_mars_pro
;
2017 si_pi
->cac_override
= cac_override_oland
;
2018 si_pi
->powertune_data
= &powertune_data_mars_pro
;
2019 si_pi
->dte_data
= dte_data_mars_pro
;
2020 update_dte_from_pl2
= true;
2023 si_pi
->cac_weights
= cac_weights_oland
;
2024 si_pi
->lcac_config
= lcac_oland
;
2025 si_pi
->cac_override
= cac_override_oland
;
2026 si_pi
->powertune_data
= &powertune_data_oland
;
2027 si_pi
->dte_data
= dte_data_oland
;
2030 } else if (rdev
->family
== CHIP_HAINAN
) {
2031 si_pi
->cac_weights
= cac_weights_hainan
;
2032 si_pi
->lcac_config
= lcac_oland
;
2033 si_pi
->cac_override
= cac_override_oland
;
2034 si_pi
->powertune_data
= &powertune_data_hainan
;
2035 si_pi
->dte_data
= dte_data_sun_xt
;
2036 update_dte_from_pl2
= true;
2038 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2042 ni_pi
->enable_power_containment
= false;
2043 ni_pi
->enable_cac
= false;
2044 ni_pi
->enable_sq_ramping
= false;
2045 si_pi
->enable_dte
= false;
2047 if (si_pi
->powertune_data
->enable_powertune_by_default
) {
2048 ni_pi
->enable_power_containment
= true;
2049 ni_pi
->enable_cac
= true;
2050 if (si_pi
->dte_data
.enable_dte_by_default
) {
2051 si_pi
->enable_dte
= true;
2052 if (update_dte_from_pl2
)
2053 si_update_dte_from_pl2(rdev
, &si_pi
->dte_data
);
2056 ni_pi
->enable_sq_ramping
= true;
2059 ni_pi
->driver_calculate_cac_leakage
= true;
2060 ni_pi
->cac_configuration_required
= true;
2062 if (ni_pi
->cac_configuration_required
) {
2063 ni_pi
->support_cac_long_term_average
= true;
2064 si_pi
->dyn_powertune_data
.l2_lta_window_size
=
2065 si_pi
->powertune_data
->l2_lta_window_size_default
;
2066 si_pi
->dyn_powertune_data
.lts_truncate
=
2067 si_pi
->powertune_data
->lts_truncate_default
;
2069 ni_pi
->support_cac_long_term_average
= false;
2070 si_pi
->dyn_powertune_data
.l2_lta_window_size
= 0;
2071 si_pi
->dyn_powertune_data
.lts_truncate
= 0;
2074 si_pi
->dyn_powertune_data
.disable_uvd_powertune
= false;
2077 static u32
si_get_smc_power_scaling_factor(struct radeon_device
*rdev
)
2082 static u32
si_calculate_cac_wintime(struct radeon_device
*rdev
)
2087 u32 cac_window_size
;
2089 xclk
= radeon_get_xclk(rdev
);
2094 cac_window
= RREG32(CG_CAC_CTRL
) & CAC_WINDOW_MASK
;
2095 cac_window_size
= ((cac_window
& 0xFFFF0000) >> 16) * (cac_window
& 0x0000FFFF);
2097 wintime
= (cac_window_size
* 100) / xclk
;
2102 static u32
si_scale_power_for_smc(u32 power_in_watts
, u32 scaling_factor
)
2104 return power_in_watts
;
2107 static int si_calculate_adjusted_tdp_limits(struct radeon_device
*rdev
,
2108 bool adjust_polarity
,
2111 u32
*near_tdp_limit
)
2113 u32 adjustment_delta
, max_tdp_limit
;
2115 if (tdp_adjustment
> (u32
)rdev
->pm
.dpm
.tdp_od_limit
)
2118 max_tdp_limit
= ((100 + 100) * rdev
->pm
.dpm
.tdp_limit
) / 100;
2120 if (adjust_polarity
) {
2121 *tdp_limit
= ((100 + tdp_adjustment
) * rdev
->pm
.dpm
.tdp_limit
) / 100;
2122 *near_tdp_limit
= rdev
->pm
.dpm
.near_tdp_limit_adjusted
+ (*tdp_limit
- rdev
->pm
.dpm
.tdp_limit
);
2124 *tdp_limit
= ((100 - tdp_adjustment
) * rdev
->pm
.dpm
.tdp_limit
) / 100;
2125 adjustment_delta
= rdev
->pm
.dpm
.tdp_limit
- *tdp_limit
;
2126 if (adjustment_delta
< rdev
->pm
.dpm
.near_tdp_limit_adjusted
)
2127 *near_tdp_limit
= rdev
->pm
.dpm
.near_tdp_limit_adjusted
- adjustment_delta
;
2129 *near_tdp_limit
= 0;
2132 if ((*tdp_limit
<= 0) || (*tdp_limit
> max_tdp_limit
))
2134 if ((*near_tdp_limit
<= 0) || (*near_tdp_limit
> *tdp_limit
))
2140 static int si_populate_smc_tdp_limits(struct radeon_device
*rdev
,
2141 struct radeon_ps
*radeon_state
)
2143 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2144 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2146 if (ni_pi
->enable_power_containment
) {
2147 SISLANDS_SMC_STATETABLE
*smc_table
= &si_pi
->smc_statetable
;
2148 PP_SIslands_PAPMParameters
*papm_parm
;
2149 struct radeon_ppm_table
*ppm
= rdev
->pm
.dpm
.dyn_state
.ppm_table
;
2150 u32 scaling_factor
= si_get_smc_power_scaling_factor(rdev
);
2155 if (scaling_factor
== 0)
2158 memset(smc_table
, 0, sizeof(SISLANDS_SMC_STATETABLE
));
2160 ret
= si_calculate_adjusted_tdp_limits(rdev
,
2162 rdev
->pm
.dpm
.tdp_adjustment
,
2168 smc_table
->dpm2Params
.TDPLimit
=
2169 cpu_to_be32(si_scale_power_for_smc(tdp_limit
, scaling_factor
) * 1000);
2170 smc_table
->dpm2Params
.NearTDPLimit
=
2171 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit
, scaling_factor
) * 1000);
2172 smc_table
->dpm2Params
.SafePowerLimit
=
2173 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit
* SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT
) / 100, scaling_factor
) * 1000);
2175 ret
= si_copy_bytes_to_smc(rdev
,
2176 (si_pi
->state_table_start
+ offsetof(SISLANDS_SMC_STATETABLE
, dpm2Params
) +
2177 offsetof(PP_SIslands_DPM2Parameters
, TDPLimit
)),
2178 (u8
*)(&(smc_table
->dpm2Params
.TDPLimit
)),
2184 if (si_pi
->enable_ppm
) {
2185 papm_parm
= &si_pi
->papm_parm
;
2186 memset(papm_parm
, 0, sizeof(PP_SIslands_PAPMParameters
));
2187 papm_parm
->NearTDPLimitTherm
= cpu_to_be32(ppm
->dgpu_tdp
);
2188 papm_parm
->dGPU_T_Limit
= cpu_to_be32(ppm
->tj_max
);
2189 papm_parm
->dGPU_T_Warning
= cpu_to_be32(95);
2190 papm_parm
->dGPU_T_Hysteresis
= cpu_to_be32(5);
2191 papm_parm
->PlatformPowerLimit
= 0xffffffff;
2192 papm_parm
->NearTDPLimitPAPM
= 0xffffffff;
2194 ret
= si_copy_bytes_to_smc(rdev
, si_pi
->papm_cfg_table_start
,
2196 sizeof(PP_SIslands_PAPMParameters
),
2205 static int si_populate_smc_tdp_limits_2(struct radeon_device
*rdev
,
2206 struct radeon_ps
*radeon_state
)
2208 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2209 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2211 if (ni_pi
->enable_power_containment
) {
2212 SISLANDS_SMC_STATETABLE
*smc_table
= &si_pi
->smc_statetable
;
2213 u32 scaling_factor
= si_get_smc_power_scaling_factor(rdev
);
2216 memset(smc_table
, 0, sizeof(SISLANDS_SMC_STATETABLE
));
2218 smc_table
->dpm2Params
.NearTDPLimit
=
2219 cpu_to_be32(si_scale_power_for_smc(rdev
->pm
.dpm
.near_tdp_limit_adjusted
, scaling_factor
) * 1000);
2220 smc_table
->dpm2Params
.SafePowerLimit
=
2221 cpu_to_be32(si_scale_power_for_smc((rdev
->pm
.dpm
.near_tdp_limit_adjusted
* SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT
) / 100, scaling_factor
) * 1000);
2223 ret
= si_copy_bytes_to_smc(rdev
,
2224 (si_pi
->state_table_start
+
2225 offsetof(SISLANDS_SMC_STATETABLE
, dpm2Params
) +
2226 offsetof(PP_SIslands_DPM2Parameters
, NearTDPLimit
)),
2227 (u8
*)(&(smc_table
->dpm2Params
.NearTDPLimit
)),
2237 static u16
si_calculate_power_efficiency_ratio(struct radeon_device
*rdev
,
2238 const u16 prev_std_vddc
,
2239 const u16 curr_std_vddc
)
2241 u64 margin
= (u64
)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN
;
2242 u64 prev_vddc
= (u64
)prev_std_vddc
;
2243 u64 curr_vddc
= (u64
)curr_std_vddc
;
2244 u64 pwr_efficiency_ratio
, n
, d
;
2246 if ((prev_vddc
== 0) || (curr_vddc
== 0))
2249 n
= div64_u64((u64
)1024 * curr_vddc
* curr_vddc
* ((u64
)1000 + margin
), (u64
)1000);
2250 d
= prev_vddc
* prev_vddc
;
2251 pwr_efficiency_ratio
= div64_u64(n
, d
);
2253 if (pwr_efficiency_ratio
> (u64
)0xFFFF)
2256 return (u16
)pwr_efficiency_ratio
;
2259 static bool si_should_disable_uvd_powertune(struct radeon_device
*rdev
,
2260 struct radeon_ps
*radeon_state
)
2262 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2264 if (si_pi
->dyn_powertune_data
.disable_uvd_powertune
&&
2265 radeon_state
->vclk
&& radeon_state
->dclk
)
2271 static int si_populate_power_containment_values(struct radeon_device
*rdev
,
2272 struct radeon_ps
*radeon_state
,
2273 SISLANDS_SMC_SWSTATE
*smc_state
)
2275 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
2276 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2277 struct ni_ps
*state
= ni_get_ps(radeon_state
);
2278 SISLANDS_SMC_VOLTAGE_VALUE vddc
;
2285 u16 pwr_efficiency_ratio
;
2287 bool disable_uvd_power_tune
;
2290 if (ni_pi
->enable_power_containment
== false)
2293 if (state
->performance_level_count
== 0)
2296 if (smc_state
->levelCount
!= state
->performance_level_count
)
2299 disable_uvd_power_tune
= si_should_disable_uvd_powertune(rdev
, radeon_state
);
2301 smc_state
->levels
[0].dpm2
.MaxPS
= 0;
2302 smc_state
->levels
[0].dpm2
.NearTDPDec
= 0;
2303 smc_state
->levels
[0].dpm2
.AboveSafeInc
= 0;
2304 smc_state
->levels
[0].dpm2
.BelowSafeInc
= 0;
2305 smc_state
->levels
[0].dpm2
.PwrEfficiencyRatio
= 0;
2307 for (i
= 1; i
< state
->performance_level_count
; i
++) {
2308 prev_sclk
= state
->performance_levels
[i
-1].sclk
;
2309 max_sclk
= state
->performance_levels
[i
].sclk
;
2311 max_ps_percent
= SISLANDS_DPM2_MAXPS_PERCENT_M
;
2313 max_ps_percent
= SISLANDS_DPM2_MAXPS_PERCENT_H
;
2315 if (prev_sclk
> max_sclk
)
2318 if ((max_ps_percent
== 0) ||
2319 (prev_sclk
== max_sclk
) ||
2320 disable_uvd_power_tune
) {
2321 min_sclk
= max_sclk
;
2322 } else if (i
== 1) {
2323 min_sclk
= prev_sclk
;
2325 min_sclk
= (prev_sclk
* (u32
)max_ps_percent
) / 100;
2328 if (min_sclk
< state
->performance_levels
[0].sclk
)
2329 min_sclk
= state
->performance_levels
[0].sclk
;
2334 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
2335 state
->performance_levels
[i
-1].vddc
, &vddc
);
2339 ret
= si_get_std_voltage_value(rdev
, &vddc
, &prev_std_vddc
);
2343 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
2344 state
->performance_levels
[i
].vddc
, &vddc
);
2348 ret
= si_get_std_voltage_value(rdev
, &vddc
, &curr_std_vddc
);
2352 pwr_efficiency_ratio
= si_calculate_power_efficiency_ratio(rdev
,
2353 prev_std_vddc
, curr_std_vddc
);
2355 smc_state
->levels
[i
].dpm2
.MaxPS
= (u8
)((SISLANDS_DPM2_MAX_PULSE_SKIP
* (max_sclk
- min_sclk
)) / max_sclk
);
2356 smc_state
->levels
[i
].dpm2
.NearTDPDec
= SISLANDS_DPM2_NEAR_TDP_DEC
;
2357 smc_state
->levels
[i
].dpm2
.AboveSafeInc
= SISLANDS_DPM2_ABOVE_SAFE_INC
;
2358 smc_state
->levels
[i
].dpm2
.BelowSafeInc
= SISLANDS_DPM2_BELOW_SAFE_INC
;
2359 smc_state
->levels
[i
].dpm2
.PwrEfficiencyRatio
= cpu_to_be16(pwr_efficiency_ratio
);
2365 static int si_populate_sq_ramping_values(struct radeon_device
*rdev
,
2366 struct radeon_ps
*radeon_state
,
2367 SISLANDS_SMC_SWSTATE
*smc_state
)
2369 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2370 struct ni_ps
*state
= ni_get_ps(radeon_state
);
2371 u32 sq_power_throttle
, sq_power_throttle2
;
2372 bool enable_sq_ramping
= ni_pi
->enable_sq_ramping
;
2375 if (state
->performance_level_count
== 0)
2378 if (smc_state
->levelCount
!= state
->performance_level_count
)
2381 if (rdev
->pm
.dpm
.sq_ramping_threshold
== 0)
2384 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER
> (MAX_POWER_MASK
>> MAX_POWER_SHIFT
))
2385 enable_sq_ramping
= false;
2387 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER
> (MIN_POWER_MASK
>> MIN_POWER_SHIFT
))
2388 enable_sq_ramping
= false;
2390 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA
> (MAX_POWER_DELTA_MASK
>> MAX_POWER_DELTA_SHIFT
))
2391 enable_sq_ramping
= false;
2393 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE
> (STI_SIZE_MASK
>> STI_SIZE_SHIFT
))
2394 enable_sq_ramping
= false;
2396 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO
<= (LTI_RATIO_MASK
>> LTI_RATIO_SHIFT
))
2397 enable_sq_ramping
= false;
2399 for (i
= 0; i
< state
->performance_level_count
; i
++) {
2400 sq_power_throttle
= 0;
2401 sq_power_throttle2
= 0;
2403 if ((state
->performance_levels
[i
].sclk
>= rdev
->pm
.dpm
.sq_ramping_threshold
) &&
2404 enable_sq_ramping
) {
2405 sq_power_throttle
|= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER
);
2406 sq_power_throttle
|= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER
);
2407 sq_power_throttle2
|= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA
);
2408 sq_power_throttle2
|= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE
);
2409 sq_power_throttle2
|= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO
);
2411 sq_power_throttle
|= MAX_POWER_MASK
| MIN_POWER_MASK
;
2412 sq_power_throttle2
|= MAX_POWER_DELTA_MASK
| STI_SIZE_MASK
| LTI_RATIO_MASK
;
2415 smc_state
->levels
[i
].SQPowerThrottle
= cpu_to_be32(sq_power_throttle
);
2416 smc_state
->levels
[i
].SQPowerThrottle_2
= cpu_to_be32(sq_power_throttle2
);
2422 static int si_enable_power_containment(struct radeon_device
*rdev
,
2423 struct radeon_ps
*radeon_new_state
,
2426 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2427 PPSMC_Result smc_result
;
2430 if (ni_pi
->enable_power_containment
) {
2432 if (!si_should_disable_uvd_powertune(rdev
, radeon_new_state
)) {
2433 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_TDPClampingActive
);
2434 if (smc_result
!= PPSMC_Result_OK
) {
2436 ni_pi
->pc_enabled
= false;
2438 ni_pi
->pc_enabled
= true;
2442 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_TDPClampingInactive
);
2443 if (smc_result
!= PPSMC_Result_OK
)
2445 ni_pi
->pc_enabled
= false;
2452 static int si_initialize_smc_dte_tables(struct radeon_device
*rdev
)
2454 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2456 struct si_dte_data
*dte_data
= &si_pi
->dte_data
;
2457 Smc_SIslands_DTE_Configuration
*dte_tables
= NULL
;
2462 if (dte_data
== NULL
)
2463 si_pi
->enable_dte
= false;
2465 if (si_pi
->enable_dte
== false)
2468 if (dte_data
->k
<= 0)
2471 dte_tables
= kzalloc(sizeof(Smc_SIslands_DTE_Configuration
), GFP_KERNEL
);
2472 if (dte_tables
== NULL
) {
2473 si_pi
->enable_dte
= false;
2477 table_size
= dte_data
->k
;
2479 if (table_size
> SMC_SISLANDS_DTE_MAX_FILTER_STAGES
)
2480 table_size
= SMC_SISLANDS_DTE_MAX_FILTER_STAGES
;
2482 tdep_count
= dte_data
->tdep_count
;
2483 if (tdep_count
> SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE
)
2484 tdep_count
= SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE
;
2486 dte_tables
->K
= cpu_to_be32(table_size
);
2487 dte_tables
->T0
= cpu_to_be32(dte_data
->t0
);
2488 dte_tables
->MaxT
= cpu_to_be32(dte_data
->max_t
);
2489 dte_tables
->WindowSize
= dte_data
->window_size
;
2490 dte_tables
->temp_select
= dte_data
->temp_select
;
2491 dte_tables
->DTE_mode
= dte_data
->dte_mode
;
2492 dte_tables
->Tthreshold
= cpu_to_be32(dte_data
->t_threshold
);
2497 for (i
= 0; i
< table_size
; i
++) {
2498 dte_tables
->tau
[i
] = cpu_to_be32(dte_data
->tau
[i
]);
2499 dte_tables
->R
[i
] = cpu_to_be32(dte_data
->r
[i
]);
2502 dte_tables
->Tdep_count
= tdep_count
;
2504 for (i
= 0; i
< (u32
)tdep_count
; i
++) {
2505 dte_tables
->T_limits
[i
] = dte_data
->t_limits
[i
];
2506 dte_tables
->Tdep_tau
[i
] = cpu_to_be32(dte_data
->tdep_tau
[i
]);
2507 dte_tables
->Tdep_R
[i
] = cpu_to_be32(dte_data
->tdep_r
[i
]);
2510 ret
= si_copy_bytes_to_smc(rdev
, si_pi
->dte_table_start
, (u8
*)dte_tables
,
2511 sizeof(Smc_SIslands_DTE_Configuration
), si_pi
->sram_end
);
2517 static int si_get_cac_std_voltage_max_min(struct radeon_device
*rdev
,
2520 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2521 struct radeon_cac_leakage_table
*table
=
2522 &rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
;
2533 for (i
= 0; i
< table
->count
; i
++) {
2534 if (table
->entries
[i
].vddc
> *max
)
2535 *max
= table
->entries
[i
].vddc
;
2536 if (table
->entries
[i
].vddc
< *min
)
2537 *min
= table
->entries
[i
].vddc
;
2540 if (si_pi
->powertune_data
->lkge_lut_v0_percent
> 100)
2543 v0_loadline
= (*min
) * (100 - si_pi
->powertune_data
->lkge_lut_v0_percent
) / 100;
2545 if (v0_loadline
> 0xFFFFUL
)
2548 *min
= (u16
)v0_loadline
;
2550 if ((*min
> *max
) || (*max
== 0) || (*min
== 0))
2556 static u16
si_get_cac_std_voltage_step(u16 max
, u16 min
)
2558 return ((max
- min
) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
- 1)) /
2559 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
;
2562 static int si_init_dte_leakage_table(struct radeon_device
*rdev
,
2563 PP_SIslands_CacConfig
*cac_tables
,
2564 u16 vddc_max
, u16 vddc_min
, u16 vddc_step
,
2567 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2575 scaling_factor
= si_get_smc_power_scaling_factor(rdev
);
2577 for (i
= 0; i
< SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES
; i
++) {
2578 t
= (1000 * (i
* t_step
+ t0
));
2580 for (j
= 0; j
< SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
; j
++) {
2581 voltage
= vddc_max
- (vddc_step
* j
);
2583 si_calculate_leakage_for_v_and_t(rdev
,
2584 &si_pi
->powertune_data
->leakage_coefficients
,
2587 si_pi
->dyn_powertune_data
.cac_leakage
,
2590 smc_leakage
= si_scale_power_for_smc(leakage
, scaling_factor
) / 4;
2592 if (smc_leakage
> 0xFFFF)
2593 smc_leakage
= 0xFFFF;
2595 cac_tables
->cac_lkge_lut
[i
][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
-1-j
] =
2596 cpu_to_be16((u16
)smc_leakage
);
2602 static int si_init_simplified_leakage_table(struct radeon_device
*rdev
,
2603 PP_SIslands_CacConfig
*cac_tables
,
2604 u16 vddc_max
, u16 vddc_min
, u16 vddc_step
)
2606 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2613 scaling_factor
= si_get_smc_power_scaling_factor(rdev
);
2615 for (j
= 0; j
< SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
; j
++) {
2616 voltage
= vddc_max
- (vddc_step
* j
);
2618 si_calculate_leakage_for_v(rdev
,
2619 &si_pi
->powertune_data
->leakage_coefficients
,
2620 si_pi
->powertune_data
->fixed_kt
,
2622 si_pi
->dyn_powertune_data
.cac_leakage
,
2625 smc_leakage
= si_scale_power_for_smc(leakage
, scaling_factor
) / 4;
2627 if (smc_leakage
> 0xFFFF)
2628 smc_leakage
= 0xFFFF;
2630 for (i
= 0; i
< SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES
; i
++)
2631 cac_tables
->cac_lkge_lut
[i
][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
-1-j
] =
2632 cpu_to_be16((u16
)smc_leakage
);
2637 static int si_initialize_smc_cac_tables(struct radeon_device
*rdev
)
2639 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2640 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2641 PP_SIslands_CacConfig
*cac_tables
= NULL
;
2642 u16 vddc_max
, vddc_min
, vddc_step
;
2644 u32 load_line_slope
, reg
;
2646 u32 ticks_per_us
= radeon_get_xclk(rdev
) / 100;
2648 if (ni_pi
->enable_cac
== false)
2651 cac_tables
= kzalloc(sizeof(PP_SIslands_CacConfig
), GFP_KERNEL
);
2655 reg
= RREG32(CG_CAC_CTRL
) & ~CAC_WINDOW_MASK
;
2656 reg
|= CAC_WINDOW(si_pi
->powertune_data
->cac_window
);
2657 WREG32(CG_CAC_CTRL
, reg
);
2659 si_pi
->dyn_powertune_data
.cac_leakage
= rdev
->pm
.dpm
.cac_leakage
;
2660 si_pi
->dyn_powertune_data
.dc_pwr_value
=
2661 si_pi
->powertune_data
->dc_cac
[NISLANDS_DCCAC_LEVEL_0
];
2662 si_pi
->dyn_powertune_data
.wintime
= si_calculate_cac_wintime(rdev
);
2663 si_pi
->dyn_powertune_data
.shift_n
= si_pi
->powertune_data
->shift_n_default
;
2665 si_pi
->dyn_powertune_data
.leakage_minimum_temperature
= 80 * 1000;
2667 ret
= si_get_cac_std_voltage_max_min(rdev
, &vddc_max
, &vddc_min
);
2671 vddc_step
= si_get_cac_std_voltage_step(vddc_max
, vddc_min
);
2672 vddc_min
= vddc_max
- (vddc_step
* (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
- 1));
2676 if (si_pi
->enable_dte
|| ni_pi
->driver_calculate_cac_leakage
)
2677 ret
= si_init_dte_leakage_table(rdev
, cac_tables
,
2678 vddc_max
, vddc_min
, vddc_step
,
2681 ret
= si_init_simplified_leakage_table(rdev
, cac_tables
,
2682 vddc_max
, vddc_min
, vddc_step
);
2686 load_line_slope
= ((u32
)rdev
->pm
.dpm
.load_line_slope
<< SMC_SISLANDS_SCALE_R
) / 100;
2688 cac_tables
->l2numWin_TDP
= cpu_to_be32(si_pi
->dyn_powertune_data
.l2_lta_window_size
);
2689 cac_tables
->lts_truncate_n
= si_pi
->dyn_powertune_data
.lts_truncate
;
2690 cac_tables
->SHIFT_N
= si_pi
->dyn_powertune_data
.shift_n
;
2691 cac_tables
->lkge_lut_V0
= cpu_to_be32((u32
)vddc_min
);
2692 cac_tables
->lkge_lut_Vstep
= cpu_to_be32((u32
)vddc_step
);
2693 cac_tables
->R_LL
= cpu_to_be32(load_line_slope
);
2694 cac_tables
->WinTime
= cpu_to_be32(si_pi
->dyn_powertune_data
.wintime
);
2695 cac_tables
->calculation_repeats
= cpu_to_be32(2);
2696 cac_tables
->dc_cac
= cpu_to_be32(0);
2697 cac_tables
->log2_PG_LKG_SCALE
= 12;
2698 cac_tables
->cac_temp
= si_pi
->powertune_data
->operating_temp
;
2699 cac_tables
->lkge_lut_T0
= cpu_to_be32((u32
)t0
);
2700 cac_tables
->lkge_lut_Tstep
= cpu_to_be32((u32
)t_step
);
2702 ret
= si_copy_bytes_to_smc(rdev
, si_pi
->cac_table_start
, (u8
*)cac_tables
,
2703 sizeof(PP_SIslands_CacConfig
), si_pi
->sram_end
);
2708 ret
= si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_ticks_per_us
, ticks_per_us
);
2712 ni_pi
->enable_cac
= false;
2713 ni_pi
->enable_power_containment
= false;
2721 static int si_program_cac_config_registers(struct radeon_device
*rdev
,
2722 const struct si_cac_config_reg
*cac_config_regs
)
2724 const struct si_cac_config_reg
*config_regs
= cac_config_regs
;
2725 u32 data
= 0, offset
;
2730 while (config_regs
->offset
!= 0xFFFFFFFF) {
2731 switch (config_regs
->type
) {
2732 case SISLANDS_CACCONFIG_CGIND
:
2733 offset
= SMC_CG_IND_START
+ config_regs
->offset
;
2734 if (offset
< SMC_CG_IND_END
)
2735 data
= RREG32_SMC(offset
);
2738 data
= RREG32(config_regs
->offset
<< 2);
2742 data
&= ~config_regs
->mask
;
2743 data
|= ((config_regs
->value
<< config_regs
->shift
) & config_regs
->mask
);
2745 switch (config_regs
->type
) {
2746 case SISLANDS_CACCONFIG_CGIND
:
2747 offset
= SMC_CG_IND_START
+ config_regs
->offset
;
2748 if (offset
< SMC_CG_IND_END
)
2749 WREG32_SMC(offset
, data
);
2752 WREG32(config_regs
->offset
<< 2, data
);
2760 static int si_initialize_hardware_cac_manager(struct radeon_device
*rdev
)
2762 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2763 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2766 if ((ni_pi
->enable_cac
== false) ||
2767 (ni_pi
->cac_configuration_required
== false))
2770 ret
= si_program_cac_config_registers(rdev
, si_pi
->lcac_config
);
2773 ret
= si_program_cac_config_registers(rdev
, si_pi
->cac_override
);
2776 ret
= si_program_cac_config_registers(rdev
, si_pi
->cac_weights
);
2783 static int si_enable_smc_cac(struct radeon_device
*rdev
,
2784 struct radeon_ps
*radeon_new_state
,
2787 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2788 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2789 PPSMC_Result smc_result
;
2792 if (ni_pi
->enable_cac
) {
2794 if (!si_should_disable_uvd_powertune(rdev
, radeon_new_state
)) {
2795 if (ni_pi
->support_cac_long_term_average
) {
2796 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_CACLongTermAvgEnable
);
2797 if (smc_result
!= PPSMC_Result_OK
)
2798 ni_pi
->support_cac_long_term_average
= false;
2801 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableCac
);
2802 if (smc_result
!= PPSMC_Result_OK
) {
2804 ni_pi
->cac_enabled
= false;
2806 ni_pi
->cac_enabled
= true;
2809 if (si_pi
->enable_dte
) {
2810 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableDTE
);
2811 if (smc_result
!= PPSMC_Result_OK
)
2815 } else if (ni_pi
->cac_enabled
) {
2816 if (si_pi
->enable_dte
)
2817 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_DisableDTE
);
2819 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_DisableCac
);
2821 ni_pi
->cac_enabled
= false;
2823 if (ni_pi
->support_cac_long_term_average
)
2824 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_CACLongTermAvgDisable
);
2830 static int si_init_smc_spll_table(struct radeon_device
*rdev
)
2832 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2833 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2834 SMC_SISLANDS_SPLL_DIV_TABLE
*spll_table
;
2835 SISLANDS_SMC_SCLK_VALUE sclk_params
;
2843 if (si_pi
->spll_table_start
== 0)
2846 spll_table
= kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE
), GFP_KERNEL
);
2847 if (spll_table
== NULL
)
2850 for (i
= 0; i
< 256; i
++) {
2851 ret
= si_calculate_sclk_params(rdev
, sclk
, &sclk_params
);
2855 p_div
= (sclk_params
.vCG_SPLL_FUNC_CNTL
& SPLL_PDIV_A_MASK
) >> SPLL_PDIV_A_SHIFT
;
2856 fb_div
= (sclk_params
.vCG_SPLL_FUNC_CNTL_3
& SPLL_FB_DIV_MASK
) >> SPLL_FB_DIV_SHIFT
;
2857 clk_s
= (sclk_params
.vCG_SPLL_SPREAD_SPECTRUM
& CLK_S_MASK
) >> CLK_S_SHIFT
;
2858 clk_v
= (sclk_params
.vCG_SPLL_SPREAD_SPECTRUM_2
& CLK_V_MASK
) >> CLK_V_SHIFT
;
2860 fb_div
&= ~0x00001FFF;
2864 if (p_div
& ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK
>> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT
))
2866 if (fb_div
& ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK
>> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT
))
2868 if (clk_s
& ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK
>> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT
))
2870 if (clk_v
& ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK
>> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT
))
2876 tmp
= ((fb_div
<< SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT
) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK
) |
2877 ((p_div
<< SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT
) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK
);
2878 spll_table
->freq
[i
] = cpu_to_be32(tmp
);
2880 tmp
= ((clk_v
<< SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT
) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK
) |
2881 ((clk_s
<< SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT
) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK
);
2882 spll_table
->ss
[i
] = cpu_to_be32(tmp
);
2889 ret
= si_copy_bytes_to_smc(rdev
, si_pi
->spll_table_start
,
2890 (u8
*)spll_table
, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE
),
2894 ni_pi
->enable_power_containment
= false;
2901 static void si_apply_state_adjust_rules(struct radeon_device
*rdev
,
2902 struct radeon_ps
*rps
)
2904 struct ni_ps
*ps
= ni_get_ps(rps
);
2905 struct radeon_clock_and_voltage_limits
*max_limits
;
2906 bool disable_mclk_switching
= false;
2907 bool disable_sclk_switching
= false;
2912 if ((rdev
->pm
.dpm
.new_active_crtc_count
> 1) ||
2913 ni_dpm_vblank_too_short(rdev
))
2914 disable_mclk_switching
= true;
2916 if (rps
->vclk
|| rps
->dclk
) {
2917 disable_mclk_switching
= true;
2918 disable_sclk_switching
= true;
2921 if (rdev
->pm
.dpm
.ac_power
)
2922 max_limits
= &rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
2924 max_limits
= &rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
;
2926 for (i
= ps
->performance_level_count
- 2; i
>= 0; i
--) {
2927 if (ps
->performance_levels
[i
].vddc
> ps
->performance_levels
[i
+1].vddc
)
2928 ps
->performance_levels
[i
].vddc
= ps
->performance_levels
[i
+1].vddc
;
2930 if (rdev
->pm
.dpm
.ac_power
== false) {
2931 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
2932 if (ps
->performance_levels
[i
].mclk
> max_limits
->mclk
)
2933 ps
->performance_levels
[i
].mclk
= max_limits
->mclk
;
2934 if (ps
->performance_levels
[i
].sclk
> max_limits
->sclk
)
2935 ps
->performance_levels
[i
].sclk
= max_limits
->sclk
;
2936 if (ps
->performance_levels
[i
].vddc
> max_limits
->vddc
)
2937 ps
->performance_levels
[i
].vddc
= max_limits
->vddc
;
2938 if (ps
->performance_levels
[i
].vddci
> max_limits
->vddci
)
2939 ps
->performance_levels
[i
].vddci
= max_limits
->vddci
;
2943 /* XXX validate the min clocks required for display */
2945 if (disable_mclk_switching
) {
2946 mclk
= ps
->performance_levels
[ps
->performance_level_count
- 1].mclk
;
2947 vddci
= ps
->performance_levels
[ps
->performance_level_count
- 1].vddci
;
2949 mclk
= ps
->performance_levels
[0].mclk
;
2950 vddci
= ps
->performance_levels
[0].vddci
;
2953 if (disable_sclk_switching
) {
2954 sclk
= ps
->performance_levels
[ps
->performance_level_count
- 1].sclk
;
2955 vddc
= ps
->performance_levels
[ps
->performance_level_count
- 1].vddc
;
2957 sclk
= ps
->performance_levels
[0].sclk
;
2958 vddc
= ps
->performance_levels
[0].vddc
;
2961 /* adjusted low state */
2962 ps
->performance_levels
[0].sclk
= sclk
;
2963 ps
->performance_levels
[0].mclk
= mclk
;
2964 ps
->performance_levels
[0].vddc
= vddc
;
2965 ps
->performance_levels
[0].vddci
= vddci
;
2967 if (disable_sclk_switching
) {
2968 sclk
= ps
->performance_levels
[0].sclk
;
2969 for (i
= 1; i
< ps
->performance_level_count
; i
++) {
2970 if (sclk
< ps
->performance_levels
[i
].sclk
)
2971 sclk
= ps
->performance_levels
[i
].sclk
;
2973 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
2974 ps
->performance_levels
[i
].sclk
= sclk
;
2975 ps
->performance_levels
[i
].vddc
= vddc
;
2978 for (i
= 1; i
< ps
->performance_level_count
; i
++) {
2979 if (ps
->performance_levels
[i
].sclk
< ps
->performance_levels
[i
- 1].sclk
)
2980 ps
->performance_levels
[i
].sclk
= ps
->performance_levels
[i
- 1].sclk
;
2981 if (ps
->performance_levels
[i
].vddc
< ps
->performance_levels
[i
- 1].vddc
)
2982 ps
->performance_levels
[i
].vddc
= ps
->performance_levels
[i
- 1].vddc
;
2986 if (disable_mclk_switching
) {
2987 mclk
= ps
->performance_levels
[0].mclk
;
2988 for (i
= 1; i
< ps
->performance_level_count
; i
++) {
2989 if (mclk
< ps
->performance_levels
[i
].mclk
)
2990 mclk
= ps
->performance_levels
[i
].mclk
;
2992 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
2993 ps
->performance_levels
[i
].mclk
= mclk
;
2994 ps
->performance_levels
[i
].vddci
= vddci
;
2997 for (i
= 1; i
< ps
->performance_level_count
; i
++) {
2998 if (ps
->performance_levels
[i
].mclk
< ps
->performance_levels
[i
- 1].mclk
)
2999 ps
->performance_levels
[i
].mclk
= ps
->performance_levels
[i
- 1].mclk
;
3000 if (ps
->performance_levels
[i
].vddci
< ps
->performance_levels
[i
- 1].vddci
)
3001 ps
->performance_levels
[i
].vddci
= ps
->performance_levels
[i
- 1].vddci
;
3005 for (i
= 0; i
< ps
->performance_level_count
; i
++)
3006 btc_adjust_clock_combinations(rdev
, max_limits
,
3007 &ps
->performance_levels
[i
]);
3009 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3010 btc_apply_voltage_dependency_rules(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
,
3011 ps
->performance_levels
[i
].sclk
,
3012 max_limits
->vddc
, &ps
->performance_levels
[i
].vddc
);
3013 btc_apply_voltage_dependency_rules(&rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
,
3014 ps
->performance_levels
[i
].mclk
,
3015 max_limits
->vddci
, &ps
->performance_levels
[i
].vddci
);
3016 btc_apply_voltage_dependency_rules(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
,
3017 ps
->performance_levels
[i
].mclk
,
3018 max_limits
->vddc
, &ps
->performance_levels
[i
].vddc
);
3019 btc_apply_voltage_dependency_rules(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
,
3020 rdev
->clock
.current_dispclk
,
3021 max_limits
->vddc
, &ps
->performance_levels
[i
].vddc
);
3024 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3025 btc_apply_voltage_delta_rules(rdev
,
3026 max_limits
->vddc
, max_limits
->vddci
,
3027 &ps
->performance_levels
[i
].vddc
,
3028 &ps
->performance_levels
[i
].vddci
);
3031 ps
->dc_compatible
= true;
3032 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3033 if (ps
->performance_levels
[i
].vddc
> rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.vddc
)
3034 ps
->dc_compatible
= false;
3040 static int si_read_smc_soft_register(struct radeon_device
*rdev
,
3041 u16 reg_offset
, u32
*value
)
3043 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3045 return si_read_smc_sram_dword(rdev
,
3046 si_pi
->soft_regs_start
+ reg_offset
, value
,
3051 static int si_write_smc_soft_register(struct radeon_device
*rdev
,
3052 u16 reg_offset
, u32 value
)
3054 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3056 return si_write_smc_sram_dword(rdev
,
3057 si_pi
->soft_regs_start
+ reg_offset
,
3058 value
, si_pi
->sram_end
);
3061 static bool si_is_special_1gb_platform(struct radeon_device
*rdev
)
3064 u32 tmp
, width
, row
, column
, bank
, density
;
3065 bool is_memory_gddr5
, is_special
;
3067 tmp
= RREG32(MC_SEQ_MISC0
);
3068 is_memory_gddr5
= (MC_SEQ_MISC0_GDDR5_VALUE
== ((tmp
& MC_SEQ_MISC0_GDDR5_MASK
) >> MC_SEQ_MISC0_GDDR5_SHIFT
));
3069 is_special
= (MC_SEQ_MISC0_REV_ID_VALUE
== ((tmp
& MC_SEQ_MISC0_REV_ID_MASK
) >> MC_SEQ_MISC0_REV_ID_SHIFT
))
3070 & (MC_SEQ_MISC0_VEN_ID_VALUE
== ((tmp
& MC_SEQ_MISC0_VEN_ID_MASK
) >> MC_SEQ_MISC0_VEN_ID_SHIFT
));
3072 WREG32(MC_SEQ_IO_DEBUG_INDEX
, 0xb);
3073 width
= ((RREG32(MC_SEQ_IO_DEBUG_DATA
) >> 1) & 1) ? 16 : 32;
3075 tmp
= RREG32(MC_ARB_RAMCFG
);
3076 row
= ((tmp
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
) + 10;
3077 column
= ((tmp
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
) + 8;
3078 bank
= ((tmp
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
) + 2;
3080 density
= (1 << (row
+ column
- 20 + bank
)) * width
;
3082 if ((rdev
->pdev
->device
== 0x6819) &&
3083 is_memory_gddr5
&& is_special
&& (density
== 0x400))
3089 static void si_get_leakage_vddc(struct radeon_device
*rdev
)
3091 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3092 u16 vddc
, count
= 0;
3095 for (i
= 0; i
< SISLANDS_MAX_LEAKAGE_COUNT
; i
++) {
3096 ret
= radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev
, &vddc
, SISLANDS_LEAKAGE_INDEX0
+ i
);
3098 if (!ret
&& (vddc
> 0) && (vddc
!= (SISLANDS_LEAKAGE_INDEX0
+ i
))) {
3099 si_pi
->leakage_voltage
.entries
[count
].voltage
= vddc
;
3100 si_pi
->leakage_voltage
.entries
[count
].leakage_index
=
3101 SISLANDS_LEAKAGE_INDEX0
+ i
;
3105 si_pi
->leakage_voltage
.count
= count
;
3108 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device
*rdev
,
3109 u32 index
, u16
*leakage_voltage
)
3111 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3114 if (leakage_voltage
== NULL
)
3117 if ((index
& 0xff00) != 0xff00)
3120 if ((index
& 0xff) > SISLANDS_MAX_LEAKAGE_COUNT
+ 1)
3123 if (index
< SISLANDS_LEAKAGE_INDEX0
)
3126 for (i
= 0; i
< si_pi
->leakage_voltage
.count
; i
++) {
3127 if (si_pi
->leakage_voltage
.entries
[i
].leakage_index
== index
) {
3128 *leakage_voltage
= si_pi
->leakage_voltage
.entries
[i
].voltage
;
3135 static void si_set_dpm_event_sources(struct radeon_device
*rdev
, u32 sources
)
3137 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3138 bool want_thermal_protection
;
3139 enum radeon_dpm_event_src dpm_event_src
;
3144 want_thermal_protection
= false;
3146 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
):
3147 want_thermal_protection
= true;
3148 dpm_event_src
= RADEON_DPM_EVENT_SRC_DIGITAL
;
3150 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
):
3151 want_thermal_protection
= true;
3152 dpm_event_src
= RADEON_DPM_EVENT_SRC_EXTERNAL
;
3154 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
) |
3155 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
)):
3156 want_thermal_protection
= true;
3157 dpm_event_src
= RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
;
3161 if (want_thermal_protection
) {
3162 WREG32_P(CG_THERMAL_CTRL
, DPM_EVENT_SRC(dpm_event_src
), ~DPM_EVENT_SRC_MASK
);
3163 if (pi
->thermal_protection
)
3164 WREG32_P(GENERAL_PWRMGT
, 0, ~THERMAL_PROTECTION_DIS
);
3166 WREG32_P(GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, ~THERMAL_PROTECTION_DIS
);
3170 static void si_enable_auto_throttle_source(struct radeon_device
*rdev
,
3171 enum radeon_dpm_auto_throttle_src source
,
3174 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3177 if (!(pi
->active_auto_throttle_sources
& (1 << source
))) {
3178 pi
->active_auto_throttle_sources
|= 1 << source
;
3179 si_set_dpm_event_sources(rdev
, pi
->active_auto_throttle_sources
);
3182 if (pi
->active_auto_throttle_sources
& (1 << source
)) {
3183 pi
->active_auto_throttle_sources
&= ~(1 << source
);
3184 si_set_dpm_event_sources(rdev
, pi
->active_auto_throttle_sources
);
3189 static void si_start_dpm(struct radeon_device
*rdev
)
3191 WREG32_P(GENERAL_PWRMGT
, GLOBAL_PWRMGT_EN
, ~GLOBAL_PWRMGT_EN
);
3194 static void si_stop_dpm(struct radeon_device
*rdev
)
3196 WREG32_P(GENERAL_PWRMGT
, 0, ~GLOBAL_PWRMGT_EN
);
3199 static void si_enable_sclk_control(struct radeon_device
*rdev
, bool enable
)
3202 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~SCLK_PWRMGT_OFF
);
3204 WREG32_P(SCLK_PWRMGT_CNTL
, SCLK_PWRMGT_OFF
, ~SCLK_PWRMGT_OFF
);
3209 static int si_notify_hardware_of_thermal_state(struct radeon_device
*rdev
,
3214 if (thermal_level
== 0) {
3215 ret
= si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableThermalInterrupt
);
3216 if (ret
== PPSMC_Result_OK
)
3224 static void si_notify_hardware_vpu_recovery_event(struct radeon_device
*rdev
)
3226 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen
, true);
3231 static int si_notify_hw_of_powersource(struct radeon_device
*rdev
, bool ac_power
)
3234 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_RunningOnAC
) == PPSMC_Result_OK
) ?
3241 static PPSMC_Result
si_send_msg_to_smc_with_parameter(struct radeon_device
*rdev
,
3242 PPSMC_Msg msg
, u32 parameter
)
3244 WREG32(SMC_SCRATCH0
, parameter
);
3245 return si_send_msg_to_smc(rdev
, msg
);
3248 static int si_restrict_performance_levels_before_switch(struct radeon_device
*rdev
)
3250 if (si_send_msg_to_smc(rdev
, PPSMC_MSG_NoForcedLevel
) != PPSMC_Result_OK
)
3253 return (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetEnabledLevels
, 1) == PPSMC_Result_OK
) ?
3257 int si_dpm_force_performance_level(struct radeon_device
*rdev
,
3258 enum radeon_dpm_forced_level level
)
3260 struct radeon_ps
*rps
= rdev
->pm
.dpm
.current_ps
;
3261 struct ni_ps
*ps
= ni_get_ps(rps
);
3262 u32 levels
= ps
->performance_level_count
;
3264 if (level
== RADEON_DPM_FORCED_LEVEL_HIGH
) {
3265 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetEnabledLevels
, levels
) != PPSMC_Result_OK
)
3268 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetForcedLevels
, 1) != PPSMC_Result_OK
)
3270 } else if (level
== RADEON_DPM_FORCED_LEVEL_LOW
) {
3271 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetForcedLevels
, 0) != PPSMC_Result_OK
)
3274 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetEnabledLevels
, 1) != PPSMC_Result_OK
)
3276 } else if (level
== RADEON_DPM_FORCED_LEVEL_AUTO
) {
3277 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetForcedLevels
, 0) != PPSMC_Result_OK
)
3280 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetEnabledLevels
, levels
) != PPSMC_Result_OK
)
3284 rdev
->pm
.dpm
.forced_level
= level
;
3289 static int si_set_boot_state(struct radeon_device
*rdev
)
3291 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_SwitchToInitialState
) == PPSMC_Result_OK
) ?
3295 static int si_set_sw_state(struct radeon_device
*rdev
)
3297 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_SwitchToSwState
) == PPSMC_Result_OK
) ?
3301 static int si_halt_smc(struct radeon_device
*rdev
)
3303 if (si_send_msg_to_smc(rdev
, PPSMC_MSG_Halt
) != PPSMC_Result_OK
)
3306 return (si_wait_for_smc_inactive(rdev
) == PPSMC_Result_OK
) ?
3310 static int si_resume_smc(struct radeon_device
*rdev
)
3312 if (si_send_msg_to_smc(rdev
, PPSMC_FlushDataCache
) != PPSMC_Result_OK
)
3315 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_Resume
) == PPSMC_Result_OK
) ?
3319 static void si_dpm_start_smc(struct radeon_device
*rdev
)
3321 si_program_jump_on_start(rdev
);
3323 si_start_smc_clock(rdev
);
3326 static void si_dpm_stop_smc(struct radeon_device
*rdev
)
3329 si_stop_smc_clock(rdev
);
3332 static int si_process_firmware_header(struct radeon_device
*rdev
)
3334 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3338 ret
= si_read_smc_sram_dword(rdev
,
3339 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3340 SISLANDS_SMC_FIRMWARE_HEADER_stateTable
,
3341 &tmp
, si_pi
->sram_end
);
3345 si_pi
->state_table_start
= tmp
;
3347 ret
= si_read_smc_sram_dword(rdev
,
3348 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3349 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters
,
3350 &tmp
, si_pi
->sram_end
);
3354 si_pi
->soft_regs_start
= tmp
;
3356 ret
= si_read_smc_sram_dword(rdev
,
3357 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3358 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable
,
3359 &tmp
, si_pi
->sram_end
);
3363 si_pi
->mc_reg_table_start
= tmp
;
3365 ret
= si_read_smc_sram_dword(rdev
,
3366 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3367 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable
,
3368 &tmp
, si_pi
->sram_end
);
3372 si_pi
->arb_table_start
= tmp
;
3374 ret
= si_read_smc_sram_dword(rdev
,
3375 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3376 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable
,
3377 &tmp
, si_pi
->sram_end
);
3381 si_pi
->cac_table_start
= tmp
;
3383 ret
= si_read_smc_sram_dword(rdev
,
3384 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3385 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration
,
3386 &tmp
, si_pi
->sram_end
);
3390 si_pi
->dte_table_start
= tmp
;
3392 ret
= si_read_smc_sram_dword(rdev
,
3393 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3394 SISLANDS_SMC_FIRMWARE_HEADER_spllTable
,
3395 &tmp
, si_pi
->sram_end
);
3399 si_pi
->spll_table_start
= tmp
;
3401 ret
= si_read_smc_sram_dword(rdev
,
3402 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3403 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters
,
3404 &tmp
, si_pi
->sram_end
);
3408 si_pi
->papm_cfg_table_start
= tmp
;
3413 static void si_read_clock_registers(struct radeon_device
*rdev
)
3415 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3417 si_pi
->clock_registers
.cg_spll_func_cntl
= RREG32(CG_SPLL_FUNC_CNTL
);
3418 si_pi
->clock_registers
.cg_spll_func_cntl_2
= RREG32(CG_SPLL_FUNC_CNTL_2
);
3419 si_pi
->clock_registers
.cg_spll_func_cntl_3
= RREG32(CG_SPLL_FUNC_CNTL_3
);
3420 si_pi
->clock_registers
.cg_spll_func_cntl_4
= RREG32(CG_SPLL_FUNC_CNTL_4
);
3421 si_pi
->clock_registers
.cg_spll_spread_spectrum
= RREG32(CG_SPLL_SPREAD_SPECTRUM
);
3422 si_pi
->clock_registers
.cg_spll_spread_spectrum_2
= RREG32(CG_SPLL_SPREAD_SPECTRUM_2
);
3423 si_pi
->clock_registers
.dll_cntl
= RREG32(DLL_CNTL
);
3424 si_pi
->clock_registers
.mclk_pwrmgt_cntl
= RREG32(MCLK_PWRMGT_CNTL
);
3425 si_pi
->clock_registers
.mpll_ad_func_cntl
= RREG32(MPLL_AD_FUNC_CNTL
);
3426 si_pi
->clock_registers
.mpll_dq_func_cntl
= RREG32(MPLL_DQ_FUNC_CNTL
);
3427 si_pi
->clock_registers
.mpll_func_cntl
= RREG32(MPLL_FUNC_CNTL
);
3428 si_pi
->clock_registers
.mpll_func_cntl_1
= RREG32(MPLL_FUNC_CNTL_1
);
3429 si_pi
->clock_registers
.mpll_func_cntl_2
= RREG32(MPLL_FUNC_CNTL_2
);
3430 si_pi
->clock_registers
.mpll_ss1
= RREG32(MPLL_SS1
);
3431 si_pi
->clock_registers
.mpll_ss2
= RREG32(MPLL_SS2
);
3434 static void si_enable_thermal_protection(struct radeon_device
*rdev
,
3438 WREG32_P(GENERAL_PWRMGT
, 0, ~THERMAL_PROTECTION_DIS
);
3440 WREG32_P(GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, ~THERMAL_PROTECTION_DIS
);
3443 static void si_enable_acpi_power_management(struct radeon_device
*rdev
)
3445 WREG32_P(GENERAL_PWRMGT
, STATIC_PM_EN
, ~STATIC_PM_EN
);
3449 static int si_enter_ulp_state(struct radeon_device
*rdev
)
3451 WREG32(SMC_MESSAGE_0
, PPSMC_MSG_SwitchToMinimumPower
);
3458 static int si_exit_ulp_state(struct radeon_device
*rdev
)
3462 WREG32(SMC_MESSAGE_0
, PPSMC_MSG_ResumeFromMinimumPower
);
3466 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3467 if (RREG32(SMC_RESP_0
) == 1)
3476 static int si_notify_smc_display_change(struct radeon_device
*rdev
,
3479 PPSMC_Msg msg
= has_display
?
3480 PPSMC_MSG_HasDisplay
: PPSMC_MSG_NoDisplay
;
3482 return (si_send_msg_to_smc(rdev
, msg
) == PPSMC_Result_OK
) ?
3486 static void si_program_response_times(struct radeon_device
*rdev
)
3488 u32 voltage_response_time
, backbias_response_time
, acpi_delay_time
, vbi_time_out
;
3489 u32 vddc_dly
, acpi_dly
, vbi_dly
;
3490 u32 reference_clock
;
3492 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_mvdd_chg_time
, 1);
3494 voltage_response_time
= (u32
)rdev
->pm
.dpm
.voltage_response_time
;
3495 backbias_response_time
= (u32
)rdev
->pm
.dpm
.backbias_response_time
;
3497 if (voltage_response_time
== 0)
3498 voltage_response_time
= 1000;
3500 acpi_delay_time
= 15000;
3501 vbi_time_out
= 100000;
3503 reference_clock
= radeon_get_xclk(rdev
);
3505 vddc_dly
= (voltage_response_time
* reference_clock
) / 100;
3506 acpi_dly
= (acpi_delay_time
* reference_clock
) / 100;
3507 vbi_dly
= (vbi_time_out
* reference_clock
) / 100;
3509 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_delay_vreg
, vddc_dly
);
3510 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_delay_acpi
, acpi_dly
);
3511 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_mclk_chg_timeout
, vbi_dly
);
3512 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_mc_block_delay
, 0xAA);
3515 static void si_program_ds_registers(struct radeon_device
*rdev
)
3517 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
3518 u32 tmp
= 1; /* XXX: 0x10 on tahiti A0 */
3520 if (eg_pi
->sclk_deep_sleep
) {
3521 WREG32_P(MISC_CLK_CNTL
, DEEP_SLEEP_CLK_SEL(tmp
), ~DEEP_SLEEP_CLK_SEL_MASK
);
3522 WREG32_P(CG_SPLL_AUTOSCALE_CNTL
, AUTOSCALE_ON_SS_CLEAR
,
3523 ~AUTOSCALE_ON_SS_CLEAR
);
3527 static void si_program_display_gap(struct radeon_device
*rdev
)
3532 tmp
= RREG32(CG_DISPLAY_GAP_CNTL
) & ~(DISP1_GAP_MASK
| DISP2_GAP_MASK
);
3533 if (rdev
->pm
.dpm
.new_active_crtc_count
> 0)
3534 tmp
|= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM
);
3536 tmp
|= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE
);
3538 if (rdev
->pm
.dpm
.new_active_crtc_count
> 1)
3539 tmp
|= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM
);
3541 tmp
|= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE
);
3543 WREG32(CG_DISPLAY_GAP_CNTL
, tmp
);
3545 tmp
= RREG32(DCCG_DISP_SLOW_SELECT_REG
);
3546 pipe
= (tmp
& DCCG_DISP1_SLOW_SELECT_MASK
) >> DCCG_DISP1_SLOW_SELECT_SHIFT
;
3548 if ((rdev
->pm
.dpm
.new_active_crtc_count
> 0) &&
3549 (!(rdev
->pm
.dpm
.new_active_crtcs
& (1 << pipe
)))) {
3550 /* find the first active crtc */
3551 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
3552 if (rdev
->pm
.dpm
.new_active_crtcs
& (1 << i
))
3555 if (i
== rdev
->num_crtc
)
3560 tmp
&= ~DCCG_DISP1_SLOW_SELECT_MASK
;
3561 tmp
|= DCCG_DISP1_SLOW_SELECT(pipe
);
3562 WREG32(DCCG_DISP_SLOW_SELECT_REG
, tmp
);
3565 si_notify_smc_display_change(rdev
, rdev
->pm
.dpm
.new_active_crtc_count
> 0);
3568 static void si_enable_spread_spectrum(struct radeon_device
*rdev
, bool enable
)
3570 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3574 WREG32_P(GENERAL_PWRMGT
, DYN_SPREAD_SPECTRUM_EN
, ~DYN_SPREAD_SPECTRUM_EN
);
3576 WREG32_P(CG_SPLL_SPREAD_SPECTRUM
, 0, ~SSEN
);
3577 WREG32_P(GENERAL_PWRMGT
, 0, ~DYN_SPREAD_SPECTRUM_EN
);
3581 static void si_setup_bsp(struct radeon_device
*rdev
)
3583 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3584 u32 xclk
= radeon_get_xclk(rdev
);
3586 r600_calculate_u_and_p(pi
->asi
,
3592 r600_calculate_u_and_p(pi
->pasi
,
3599 pi
->dsp
= BSP(pi
->bsp
) | BSU(pi
->bsu
);
3600 pi
->psp
= BSP(pi
->pbsp
) | BSU(pi
->pbsu
);
3602 WREG32(CG_BSP
, pi
->dsp
);
3605 static void si_program_git(struct radeon_device
*rdev
)
3607 WREG32_P(CG_GIT
, CG_GICST(R600_GICST_DFLT
), ~CG_GICST_MASK
);
3610 static void si_program_tp(struct radeon_device
*rdev
)
3613 enum r600_td td
= R600_TD_DFLT
;
3615 for (i
= 0; i
< R600_PM_NUMBER_OF_TC
; i
++)
3616 WREG32(CG_FFCT_0
+ (i
* 4), (UTC_0(r600_utc
[i
]) | DTC_0(r600_dtc
[i
])));
3618 if (td
== R600_TD_AUTO
)
3619 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_FORCE_TREND_SEL
);
3621 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_FORCE_TREND_SEL
, ~FIR_FORCE_TREND_SEL
);
3623 if (td
== R600_TD_UP
)
3624 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_TREND_MODE
);
3626 if (td
== R600_TD_DOWN
)
3627 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_TREND_MODE
, ~FIR_TREND_MODE
);
3630 static void si_program_tpp(struct radeon_device
*rdev
)
3632 WREG32(CG_TPC
, R600_TPC_DFLT
);
3635 static void si_program_sstp(struct radeon_device
*rdev
)
3637 WREG32(CG_SSP
, (SSTU(R600_SSTU_DFLT
) | SST(R600_SST_DFLT
)));
3640 static void si_enable_display_gap(struct radeon_device
*rdev
)
3642 u32 tmp
= RREG32(CG_DISPLAY_GAP_CNTL
);
3644 tmp
&= ~(DISP1_GAP_MASK
| DISP2_GAP_MASK
);
3645 tmp
|= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE
) |
3646 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE
));
3648 tmp
&= ~(DISP1_GAP_MCHG_MASK
| DISP2_GAP_MCHG_MASK
);
3649 tmp
|= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK
) |
3650 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE
));
3651 WREG32(CG_DISPLAY_GAP_CNTL
, tmp
);
3654 static void si_program_vc(struct radeon_device
*rdev
)
3656 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3658 WREG32(CG_FTV
, pi
->vrc
);
3661 static void si_clear_vc(struct radeon_device
*rdev
)
3666 static u8
si_get_ddr3_mclk_frequency_ratio(u32 memory_clock
)
3670 if (memory_clock
< 10000)
3672 else if (memory_clock
>= 80000)
3673 mc_para_index
= 0x0f;
3675 mc_para_index
= (u8
)((memory_clock
- 10000) / 5000 + 1);
3676 return mc_para_index
;
3679 static u8
si_get_mclk_frequency_ratio(u32 memory_clock
, bool strobe_mode
)
3684 if (memory_clock
< 12500)
3685 mc_para_index
= 0x00;
3686 else if (memory_clock
> 47500)
3687 mc_para_index
= 0x0f;
3689 mc_para_index
= (u8
)((memory_clock
- 10000) / 2500);
3691 if (memory_clock
< 65000)
3692 mc_para_index
= 0x00;
3693 else if (memory_clock
> 135000)
3694 mc_para_index
= 0x0f;
3696 mc_para_index
= (u8
)((memory_clock
- 60000) / 5000);
3698 return mc_para_index
;
3701 static u8
si_get_strobe_mode_settings(struct radeon_device
*rdev
, u32 mclk
)
3703 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3704 bool strobe_mode
= false;
3707 if (mclk
<= pi
->mclk_strobe_mode_threshold
)
3711 result
= si_get_mclk_frequency_ratio(mclk
, strobe_mode
);
3713 result
= si_get_ddr3_mclk_frequency_ratio(mclk
);
3716 result
|= SISLANDS_SMC_STROBE_ENABLE
;
3721 static int si_upload_firmware(struct radeon_device
*rdev
)
3723 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3727 si_stop_smc_clock(rdev
);
3729 ret
= si_load_smc_ucode(rdev
, si_pi
->sram_end
);
3734 static bool si_validate_phase_shedding_tables(struct radeon_device
*rdev
,
3735 const struct atom_voltage_table
*table
,
3736 const struct radeon_phase_shedding_limits_table
*limits
)
3738 u32 data
, num_bits
, num_levels
;
3740 if ((table
== NULL
) || (limits
== NULL
))
3743 data
= table
->mask_low
;
3745 num_bits
= hweight32(data
);
3750 num_levels
= (1 << num_bits
);
3752 if (table
->count
!= num_levels
)
3755 if (limits
->count
!= (num_levels
- 1))
3761 static void si_trim_voltage_table_to_fit_state_table(struct radeon_device
*rdev
,
3762 struct atom_voltage_table
*voltage_table
)
3764 unsigned int i
, diff
;
3766 if (voltage_table
->count
<= SISLANDS_MAX_NO_VREG_STEPS
)
3769 diff
= voltage_table
->count
- SISLANDS_MAX_NO_VREG_STEPS
;
3771 for (i
= 0; i
< SISLANDS_MAX_NO_VREG_STEPS
; i
++)
3772 voltage_table
->entries
[i
] = voltage_table
->entries
[i
+ diff
];
3774 voltage_table
->count
= SISLANDS_MAX_NO_VREG_STEPS
;
3777 static int si_construct_voltage_tables(struct radeon_device
*rdev
)
3779 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3780 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
3781 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3784 ret
= radeon_atom_get_voltage_table(rdev
, VOLTAGE_TYPE_VDDC
,
3785 VOLTAGE_OBJ_GPIO_LUT
, &eg_pi
->vddc_voltage_table
);
3789 if (eg_pi
->vddc_voltage_table
.count
> SISLANDS_MAX_NO_VREG_STEPS
)
3790 si_trim_voltage_table_to_fit_state_table(rdev
, &eg_pi
->vddc_voltage_table
);
3792 if (eg_pi
->vddci_control
) {
3793 ret
= radeon_atom_get_voltage_table(rdev
, VOLTAGE_TYPE_VDDCI
,
3794 VOLTAGE_OBJ_GPIO_LUT
, &eg_pi
->vddci_voltage_table
);
3798 if (eg_pi
->vddci_voltage_table
.count
> SISLANDS_MAX_NO_VREG_STEPS
)
3799 si_trim_voltage_table_to_fit_state_table(rdev
, &eg_pi
->vddci_voltage_table
);
3802 if (pi
->mvdd_control
) {
3803 ret
= radeon_atom_get_voltage_table(rdev
, VOLTAGE_TYPE_MVDDC
,
3804 VOLTAGE_OBJ_GPIO_LUT
, &si_pi
->mvdd_voltage_table
);
3807 pi
->mvdd_control
= false;
3811 if (si_pi
->mvdd_voltage_table
.count
== 0) {
3812 pi
->mvdd_control
= false;
3816 if (si_pi
->mvdd_voltage_table
.count
> SISLANDS_MAX_NO_VREG_STEPS
)
3817 si_trim_voltage_table_to_fit_state_table(rdev
, &si_pi
->mvdd_voltage_table
);
3820 if (si_pi
->vddc_phase_shed_control
) {
3821 ret
= radeon_atom_get_voltage_table(rdev
, VOLTAGE_TYPE_VDDC
,
3822 VOLTAGE_OBJ_PHASE_LUT
, &si_pi
->vddc_phase_shed_table
);
3824 si_pi
->vddc_phase_shed_control
= false;
3826 if ((si_pi
->vddc_phase_shed_table
.count
== 0) ||
3827 (si_pi
->vddc_phase_shed_table
.count
> SISLANDS_MAX_NO_VREG_STEPS
))
3828 si_pi
->vddc_phase_shed_control
= false;
3834 static void si_populate_smc_voltage_table(struct radeon_device
*rdev
,
3835 const struct atom_voltage_table
*voltage_table
,
3836 SISLANDS_SMC_STATETABLE
*table
)
3840 for (i
= 0; i
< voltage_table
->count
; i
++)
3841 table
->lowSMIO
[i
] |= cpu_to_be32(voltage_table
->entries
[i
].smio_low
);
3844 static int si_populate_smc_voltage_tables(struct radeon_device
*rdev
,
3845 SISLANDS_SMC_STATETABLE
*table
)
3847 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3848 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
3849 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3852 if (eg_pi
->vddc_voltage_table
.count
) {
3853 si_populate_smc_voltage_table(rdev
, &eg_pi
->vddc_voltage_table
, table
);
3854 table
->voltageMaskTable
.lowMask
[SISLANDS_SMC_VOLTAGEMASK_VDDC
] =
3855 cpu_to_be32(eg_pi
->vddc_voltage_table
.mask_low
);
3857 for (i
= 0; i
< eg_pi
->vddc_voltage_table
.count
; i
++) {
3858 if (pi
->max_vddc_in_table
<= eg_pi
->vddc_voltage_table
.entries
[i
].value
) {
3859 table
->maxVDDCIndexInPPTable
= i
;
3865 if (eg_pi
->vddci_voltage_table
.count
) {
3866 si_populate_smc_voltage_table(rdev
, &eg_pi
->vddci_voltage_table
, table
);
3868 table
->voltageMaskTable
.lowMask
[SISLANDS_SMC_VOLTAGEMASK_VDDCI
] =
3869 cpu_to_be32(eg_pi
->vddci_voltage_table
.mask_low
);
3873 if (si_pi
->mvdd_voltage_table
.count
) {
3874 si_populate_smc_voltage_table(rdev
, &si_pi
->mvdd_voltage_table
, table
);
3876 table
->voltageMaskTable
.lowMask
[SISLANDS_SMC_VOLTAGEMASK_MVDD
] =
3877 cpu_to_be32(si_pi
->mvdd_voltage_table
.mask_low
);
3880 if (si_pi
->vddc_phase_shed_control
) {
3881 if (si_validate_phase_shedding_tables(rdev
, &si_pi
->vddc_phase_shed_table
,
3882 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
)) {
3883 si_populate_smc_voltage_table(rdev
, &si_pi
->vddc_phase_shed_table
, table
);
3885 table
->phaseMaskTable
.lowMask
[SISLANDS_SMC_VOLTAGEMASK_VDDC
] =
3886 cpu_to_be32(si_pi
->vddc_phase_shed_table
.mask_low
);
3888 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_phase_shedding_delay
,
3889 (u32
)si_pi
->vddc_phase_shed_table
.phase_delay
);
3891 si_pi
->vddc_phase_shed_control
= false;
3898 static int si_populate_voltage_value(struct radeon_device
*rdev
,
3899 const struct atom_voltage_table
*table
,
3900 u16 value
, SISLANDS_SMC_VOLTAGE_VALUE
*voltage
)
3904 for (i
= 0; i
< table
->count
; i
++) {
3905 if (value
<= table
->entries
[i
].value
) {
3906 voltage
->index
= (u8
)i
;
3907 voltage
->value
= cpu_to_be16(table
->entries
[i
].value
);
3912 if (i
>= table
->count
)
3918 static int si_populate_mvdd_value(struct radeon_device
*rdev
, u32 mclk
,
3919 SISLANDS_SMC_VOLTAGE_VALUE
*voltage
)
3921 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3922 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3924 if (pi
->mvdd_control
) {
3925 if (mclk
<= pi
->mvdd_split_frequency
)
3928 voltage
->index
= (u8
)(si_pi
->mvdd_voltage_table
.count
) - 1;
3930 voltage
->value
= cpu_to_be16(si_pi
->mvdd_voltage_table
.entries
[voltage
->index
].value
);
3935 static int si_get_std_voltage_value(struct radeon_device
*rdev
,
3936 SISLANDS_SMC_VOLTAGE_VALUE
*voltage
,
3940 bool voltage_found
= false;
3941 *std_voltage
= be16_to_cpu(voltage
->value
);
3943 if (rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
) {
3944 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE
) {
3945 if (rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
== NULL
)
3948 for (v_index
= 0; (u32
)v_index
< rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
; v_index
++) {
3949 if (be16_to_cpu(voltage
->value
) ==
3950 (u16
)rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[v_index
].v
) {
3951 voltage_found
= true;
3952 if ((u32
)v_index
< rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
)
3954 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[v_index
].vddc
;
3957 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
-1].vddc
;
3962 if (!voltage_found
) {
3963 for (v_index
= 0; (u32
)v_index
< rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
; v_index
++) {
3964 if (be16_to_cpu(voltage
->value
) <=
3965 (u16
)rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[v_index
].v
) {
3966 voltage_found
= true;
3967 if ((u32
)v_index
< rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
)
3969 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[v_index
].vddc
;
3972 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
-1].vddc
;
3978 if ((u32
)voltage
->index
< rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
)
3979 *std_voltage
= rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[voltage
->index
].vddc
;
3986 static int si_populate_std_voltage_value(struct radeon_device
*rdev
,
3987 u16 value
, u8 index
,
3988 SISLANDS_SMC_VOLTAGE_VALUE
*voltage
)
3990 voltage
->index
= index
;
3991 voltage
->value
= cpu_to_be16(value
);
3996 static int si_populate_phase_shedding_value(struct radeon_device
*rdev
,
3997 const struct radeon_phase_shedding_limits_table
*limits
,
3998 u16 voltage
, u32 sclk
, u32 mclk
,
3999 SISLANDS_SMC_VOLTAGE_VALUE
*smc_voltage
)
4003 for (i
= 0; i
< limits
->count
; i
++) {
4004 if ((voltage
<= limits
->entries
[i
].voltage
) &&
4005 (sclk
<= limits
->entries
[i
].sclk
) &&
4006 (mclk
<= limits
->entries
[i
].mclk
))
4010 smc_voltage
->phase_settings
= (u8
)i
;
4015 static int si_init_arb_table_index(struct radeon_device
*rdev
)
4017 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4021 ret
= si_read_smc_sram_dword(rdev
, si_pi
->arb_table_start
, &tmp
, si_pi
->sram_end
);
4026 tmp
|= MC_CG_ARB_FREQ_F1
<< 24;
4028 return si_write_smc_sram_dword(rdev
, si_pi
->arb_table_start
, tmp
, si_pi
->sram_end
);
4031 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device
*rdev
)
4033 return ni_copy_and_switch_arb_sets(rdev
, MC_CG_ARB_FREQ_F0
, MC_CG_ARB_FREQ_F1
);
4036 static int si_reset_to_default(struct radeon_device
*rdev
)
4038 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_ResetToDefaults
) == PPSMC_Result_OK
) ?
4042 static int si_force_switch_to_arb_f0(struct radeon_device
*rdev
)
4044 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4048 ret
= si_read_smc_sram_dword(rdev
, si_pi
->arb_table_start
,
4049 &tmp
, si_pi
->sram_end
);
4053 tmp
= (tmp
>> 24) & 0xff;
4055 if (tmp
== MC_CG_ARB_FREQ_F0
)
4058 return ni_copy_and_switch_arb_sets(rdev
, tmp
, MC_CG_ARB_FREQ_F0
);
4061 static u32
si_calculate_memory_refresh_rate(struct radeon_device
*rdev
,
4065 u32 dram_refresh_rate
;
4066 u32 mc_arb_rfsh_rate
;
4067 u32 tmp
= (RREG32(MC_ARB_RAMCFG
) & NOOFROWS_MASK
) >> NOOFROWS_SHIFT
;
4072 dram_rows
= 1 << (tmp
+ 10);
4074 dram_refresh_rate
= 1 << ((RREG32(MC_SEQ_MISC0
) & 0x3) + 3);
4075 mc_arb_rfsh_rate
= ((engine_clock
* 10) * dram_refresh_rate
/ dram_rows
- 32) / 64;
4077 return mc_arb_rfsh_rate
;
4080 static int si_populate_memory_timing_parameters(struct radeon_device
*rdev
,
4081 struct rv7xx_pl
*pl
,
4082 SMC_SIslands_MCArbDramTimingRegisterSet
*arb_regs
)
4088 arb_regs
->mc_arb_rfsh_rate
=
4089 (u8
)si_calculate_memory_refresh_rate(rdev
, pl
->sclk
);
4091 radeon_atom_set_engine_dram_timings(rdev
,
4095 dram_timing
= RREG32(MC_ARB_DRAM_TIMING
);
4096 dram_timing2
= RREG32(MC_ARB_DRAM_TIMING2
);
4097 burst_time
= RREG32(MC_ARB_BURST_TIME
) & STATE0_MASK
;
4099 arb_regs
->mc_arb_dram_timing
= cpu_to_be32(dram_timing
);
4100 arb_regs
->mc_arb_dram_timing2
= cpu_to_be32(dram_timing2
);
4101 arb_regs
->mc_arb_burst_time
= (u8
)burst_time
;
4106 static int si_do_program_memory_timing_parameters(struct radeon_device
*rdev
,
4107 struct radeon_ps
*radeon_state
,
4108 unsigned int first_arb_set
)
4110 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4111 struct ni_ps
*state
= ni_get_ps(radeon_state
);
4112 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs
= { 0 };
4115 for (i
= 0; i
< state
->performance_level_count
; i
++) {
4116 ret
= si_populate_memory_timing_parameters(rdev
, &state
->performance_levels
[i
], &arb_regs
);
4119 ret
= si_copy_bytes_to_smc(rdev
,
4120 si_pi
->arb_table_start
+
4121 offsetof(SMC_SIslands_MCArbDramTimingRegisters
, data
) +
4122 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet
) * (first_arb_set
+ i
),
4124 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet
),
4133 static int si_program_memory_timing_parameters(struct radeon_device
*rdev
,
4134 struct radeon_ps
*radeon_new_state
)
4136 return si_do_program_memory_timing_parameters(rdev
, radeon_new_state
,
4137 SISLANDS_DRIVER_STATE_ARB_INDEX
);
4140 static int si_populate_initial_mvdd_value(struct radeon_device
*rdev
,
4141 struct SISLANDS_SMC_VOLTAGE_VALUE
*voltage
)
4143 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4144 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4146 if (pi
->mvdd_control
)
4147 return si_populate_voltage_value(rdev
, &si_pi
->mvdd_voltage_table
,
4148 si_pi
->mvdd_bootup_value
, voltage
);
4153 static int si_populate_smc_initial_state(struct radeon_device
*rdev
,
4154 struct radeon_ps
*radeon_initial_state
,
4155 SISLANDS_SMC_STATETABLE
*table
)
4157 struct ni_ps
*initial_state
= ni_get_ps(radeon_initial_state
);
4158 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4159 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
4160 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4164 table
->initialState
.levels
[0].mclk
.vDLL_CNTL
=
4165 cpu_to_be32(si_pi
->clock_registers
.dll_cntl
);
4166 table
->initialState
.levels
[0].mclk
.vMCLK_PWRMGT_CNTL
=
4167 cpu_to_be32(si_pi
->clock_registers
.mclk_pwrmgt_cntl
);
4168 table
->initialState
.levels
[0].mclk
.vMPLL_AD_FUNC_CNTL
=
4169 cpu_to_be32(si_pi
->clock_registers
.mpll_ad_func_cntl
);
4170 table
->initialState
.levels
[0].mclk
.vMPLL_DQ_FUNC_CNTL
=
4171 cpu_to_be32(si_pi
->clock_registers
.mpll_dq_func_cntl
);
4172 table
->initialState
.levels
[0].mclk
.vMPLL_FUNC_CNTL
=
4173 cpu_to_be32(si_pi
->clock_registers
.mpll_func_cntl
);
4174 table
->initialState
.levels
[0].mclk
.vMPLL_FUNC_CNTL_1
=
4175 cpu_to_be32(si_pi
->clock_registers
.mpll_func_cntl_1
);
4176 table
->initialState
.levels
[0].mclk
.vMPLL_FUNC_CNTL_2
=
4177 cpu_to_be32(si_pi
->clock_registers
.mpll_func_cntl_2
);
4178 table
->initialState
.levels
[0].mclk
.vMPLL_SS
=
4179 cpu_to_be32(si_pi
->clock_registers
.mpll_ss1
);
4180 table
->initialState
.levels
[0].mclk
.vMPLL_SS2
=
4181 cpu_to_be32(si_pi
->clock_registers
.mpll_ss2
);
4183 table
->initialState
.levels
[0].mclk
.mclk_value
=
4184 cpu_to_be32(initial_state
->performance_levels
[0].mclk
);
4186 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL
=
4187 cpu_to_be32(si_pi
->clock_registers
.cg_spll_func_cntl
);
4188 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_2
=
4189 cpu_to_be32(si_pi
->clock_registers
.cg_spll_func_cntl_2
);
4190 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_3
=
4191 cpu_to_be32(si_pi
->clock_registers
.cg_spll_func_cntl_3
);
4192 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_4
=
4193 cpu_to_be32(si_pi
->clock_registers
.cg_spll_func_cntl_4
);
4194 table
->initialState
.levels
[0].sclk
.vCG_SPLL_SPREAD_SPECTRUM
=
4195 cpu_to_be32(si_pi
->clock_registers
.cg_spll_spread_spectrum
);
4196 table
->initialState
.levels
[0].sclk
.vCG_SPLL_SPREAD_SPECTRUM_2
=
4197 cpu_to_be32(si_pi
->clock_registers
.cg_spll_spread_spectrum_2
);
4199 table
->initialState
.levels
[0].sclk
.sclk_value
=
4200 cpu_to_be32(initial_state
->performance_levels
[0].sclk
);
4202 table
->initialState
.levels
[0].arbRefreshState
=
4203 SISLANDS_INITIAL_STATE_ARB_INDEX
;
4205 table
->initialState
.levels
[0].ACIndex
= 0;
4207 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
4208 initial_state
->performance_levels
[0].vddc
,
4209 &table
->initialState
.levels
[0].vddc
);
4214 ret
= si_get_std_voltage_value(rdev
,
4215 &table
->initialState
.levels
[0].vddc
,
4218 si_populate_std_voltage_value(rdev
, std_vddc
,
4219 table
->initialState
.levels
[0].vddc
.index
,
4220 &table
->initialState
.levels
[0].std_vddc
);
4223 if (eg_pi
->vddci_control
)
4224 si_populate_voltage_value(rdev
,
4225 &eg_pi
->vddci_voltage_table
,
4226 initial_state
->performance_levels
[0].vddci
,
4227 &table
->initialState
.levels
[0].vddci
);
4229 if (si_pi
->vddc_phase_shed_control
)
4230 si_populate_phase_shedding_value(rdev
,
4231 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
4232 initial_state
->performance_levels
[0].vddc
,
4233 initial_state
->performance_levels
[0].sclk
,
4234 initial_state
->performance_levels
[0].mclk
,
4235 &table
->initialState
.levels
[0].vddc
);
4237 si_populate_initial_mvdd_value(rdev
, &table
->initialState
.levels
[0].mvdd
);
4239 reg
= CG_R(0xffff) | CG_L(0);
4240 table
->initialState
.levels
[0].aT
= cpu_to_be32(reg
);
4242 table
->initialState
.levels
[0].bSP
= cpu_to_be32(pi
->dsp
);
4244 table
->initialState
.levels
[0].gen2PCIE
= (u8
)si_pi
->boot_pcie_gen
;
4246 if (pi
->mem_gddr5
) {
4247 table
->initialState
.levels
[0].strobeMode
=
4248 si_get_strobe_mode_settings(rdev
,
4249 initial_state
->performance_levels
[0].mclk
);
4251 if (initial_state
->performance_levels
[0].mclk
> pi
->mclk_edc_enable_threshold
)
4252 table
->initialState
.levels
[0].mcFlags
= SISLANDS_SMC_MC_EDC_RD_FLAG
| SISLANDS_SMC_MC_EDC_WR_FLAG
;
4254 table
->initialState
.levels
[0].mcFlags
= 0;
4257 table
->initialState
.levelCount
= 1;
4259 table
->initialState
.flags
|= PPSMC_SWSTATE_FLAG_DC
;
4261 table
->initialState
.levels
[0].dpm2
.MaxPS
= 0;
4262 table
->initialState
.levels
[0].dpm2
.NearTDPDec
= 0;
4263 table
->initialState
.levels
[0].dpm2
.AboveSafeInc
= 0;
4264 table
->initialState
.levels
[0].dpm2
.BelowSafeInc
= 0;
4265 table
->initialState
.levels
[0].dpm2
.PwrEfficiencyRatio
= 0;
4267 reg
= MIN_POWER_MASK
| MAX_POWER_MASK
;
4268 table
->initialState
.levels
[0].SQPowerThrottle
= cpu_to_be32(reg
);
4270 reg
= MAX_POWER_DELTA_MASK
| STI_SIZE_MASK
| LTI_RATIO_MASK
;
4271 table
->initialState
.levels
[0].SQPowerThrottle_2
= cpu_to_be32(reg
);
4276 static int si_populate_smc_acpi_state(struct radeon_device
*rdev
,
4277 SISLANDS_SMC_STATETABLE
*table
)
4279 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4280 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
4281 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4282 u32 spll_func_cntl
= si_pi
->clock_registers
.cg_spll_func_cntl
;
4283 u32 spll_func_cntl_2
= si_pi
->clock_registers
.cg_spll_func_cntl_2
;
4284 u32 spll_func_cntl_3
= si_pi
->clock_registers
.cg_spll_func_cntl_3
;
4285 u32 spll_func_cntl_4
= si_pi
->clock_registers
.cg_spll_func_cntl_4
;
4286 u32 dll_cntl
= si_pi
->clock_registers
.dll_cntl
;
4287 u32 mclk_pwrmgt_cntl
= si_pi
->clock_registers
.mclk_pwrmgt_cntl
;
4288 u32 mpll_ad_func_cntl
= si_pi
->clock_registers
.mpll_ad_func_cntl
;
4289 u32 mpll_dq_func_cntl
= si_pi
->clock_registers
.mpll_dq_func_cntl
;
4290 u32 mpll_func_cntl
= si_pi
->clock_registers
.mpll_func_cntl
;
4291 u32 mpll_func_cntl_1
= si_pi
->clock_registers
.mpll_func_cntl_1
;
4292 u32 mpll_func_cntl_2
= si_pi
->clock_registers
.mpll_func_cntl_2
;
4296 table
->ACPIState
= table
->initialState
;
4298 table
->ACPIState
.flags
&= ~PPSMC_SWSTATE_FLAG_DC
;
4300 if (pi
->acpi_vddc
) {
4301 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
4302 pi
->acpi_vddc
, &table
->ACPIState
.levels
[0].vddc
);
4306 ret
= si_get_std_voltage_value(rdev
,
4307 &table
->ACPIState
.levels
[0].vddc
, &std_vddc
);
4309 si_populate_std_voltage_value(rdev
, std_vddc
,
4310 table
->ACPIState
.levels
[0].vddc
.index
,
4311 &table
->ACPIState
.levels
[0].std_vddc
);
4313 table
->ACPIState
.levels
[0].gen2PCIE
= si_pi
->acpi_pcie_gen
;
4315 if (si_pi
->vddc_phase_shed_control
) {
4316 si_populate_phase_shedding_value(rdev
,
4317 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
4321 &table
->ACPIState
.levels
[0].vddc
);
4324 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
4325 pi
->min_vddc_in_table
, &table
->ACPIState
.levels
[0].vddc
);
4329 ret
= si_get_std_voltage_value(rdev
,
4330 &table
->ACPIState
.levels
[0].vddc
, &std_vddc
);
4333 si_populate_std_voltage_value(rdev
, std_vddc
,
4334 table
->ACPIState
.levels
[0].vddc
.index
,
4335 &table
->ACPIState
.levels
[0].std_vddc
);
4337 table
->ACPIState
.levels
[0].gen2PCIE
= (u8
)r600_get_pcie_gen_support(rdev
,
4338 si_pi
->sys_pcie_mask
,
4339 si_pi
->boot_pcie_gen
,
4342 if (si_pi
->vddc_phase_shed_control
)
4343 si_populate_phase_shedding_value(rdev
,
4344 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
4345 pi
->min_vddc_in_table
,
4348 &table
->ACPIState
.levels
[0].vddc
);
4351 if (pi
->acpi_vddc
) {
4352 if (eg_pi
->acpi_vddci
)
4353 si_populate_voltage_value(rdev
, &eg_pi
->vddci_voltage_table
,
4355 &table
->ACPIState
.levels
[0].vddci
);
4358 mclk_pwrmgt_cntl
|= MRDCK0_RESET
| MRDCK1_RESET
;
4359 mclk_pwrmgt_cntl
&= ~(MRDCK0_PDNB
| MRDCK1_PDNB
);
4361 dll_cntl
&= ~(MRDCK0_BYPASS
| MRDCK1_BYPASS
);
4363 spll_func_cntl_2
&= ~SCLK_MUX_SEL_MASK
;
4364 spll_func_cntl_2
|= SCLK_MUX_SEL(4);
4366 table
->ACPIState
.levels
[0].mclk
.vDLL_CNTL
=
4367 cpu_to_be32(dll_cntl
);
4368 table
->ACPIState
.levels
[0].mclk
.vMCLK_PWRMGT_CNTL
=
4369 cpu_to_be32(mclk_pwrmgt_cntl
);
4370 table
->ACPIState
.levels
[0].mclk
.vMPLL_AD_FUNC_CNTL
=
4371 cpu_to_be32(mpll_ad_func_cntl
);
4372 table
->ACPIState
.levels
[0].mclk
.vMPLL_DQ_FUNC_CNTL
=
4373 cpu_to_be32(mpll_dq_func_cntl
);
4374 table
->ACPIState
.levels
[0].mclk
.vMPLL_FUNC_CNTL
=
4375 cpu_to_be32(mpll_func_cntl
);
4376 table
->ACPIState
.levels
[0].mclk
.vMPLL_FUNC_CNTL_1
=
4377 cpu_to_be32(mpll_func_cntl_1
);
4378 table
->ACPIState
.levels
[0].mclk
.vMPLL_FUNC_CNTL_2
=
4379 cpu_to_be32(mpll_func_cntl_2
);
4380 table
->ACPIState
.levels
[0].mclk
.vMPLL_SS
=
4381 cpu_to_be32(si_pi
->clock_registers
.mpll_ss1
);
4382 table
->ACPIState
.levels
[0].mclk
.vMPLL_SS2
=
4383 cpu_to_be32(si_pi
->clock_registers
.mpll_ss2
);
4385 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL
=
4386 cpu_to_be32(spll_func_cntl
);
4387 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_2
=
4388 cpu_to_be32(spll_func_cntl_2
);
4389 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_3
=
4390 cpu_to_be32(spll_func_cntl_3
);
4391 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_4
=
4392 cpu_to_be32(spll_func_cntl_4
);
4394 table
->ACPIState
.levels
[0].mclk
.mclk_value
= 0;
4395 table
->ACPIState
.levels
[0].sclk
.sclk_value
= 0;
4397 si_populate_mvdd_value(rdev
, 0, &table
->ACPIState
.levels
[0].mvdd
);
4399 if (eg_pi
->dynamic_ac_timing
)
4400 table
->ACPIState
.levels
[0].ACIndex
= 0;
4402 table
->ACPIState
.levels
[0].dpm2
.MaxPS
= 0;
4403 table
->ACPIState
.levels
[0].dpm2
.NearTDPDec
= 0;
4404 table
->ACPIState
.levels
[0].dpm2
.AboveSafeInc
= 0;
4405 table
->ACPIState
.levels
[0].dpm2
.BelowSafeInc
= 0;
4406 table
->ACPIState
.levels
[0].dpm2
.PwrEfficiencyRatio
= 0;
4408 reg
= MIN_POWER_MASK
| MAX_POWER_MASK
;
4409 table
->ACPIState
.levels
[0].SQPowerThrottle
= cpu_to_be32(reg
);
4411 reg
= MAX_POWER_DELTA_MASK
| STI_SIZE_MASK
| LTI_RATIO_MASK
;
4412 table
->ACPIState
.levels
[0].SQPowerThrottle_2
= cpu_to_be32(reg
);
4417 static int si_populate_ulv_state(struct radeon_device
*rdev
,
4418 SISLANDS_SMC_SWSTATE
*state
)
4420 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
4421 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4422 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
4423 u32 sclk_in_sr
= 1350; /* ??? */
4426 ret
= si_convert_power_level_to_smc(rdev
, &ulv
->pl
,
4429 if (eg_pi
->sclk_deep_sleep
) {
4430 if (sclk_in_sr
<= SCLK_MIN_DEEPSLEEP_FREQ
)
4431 state
->levels
[0].stateFlags
|= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS
;
4433 state
->levels
[0].stateFlags
|= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE
;
4435 if (ulv
->one_pcie_lane_in_ulv
)
4436 state
->flags
|= PPSMC_SWSTATE_FLAG_PCIE_X1
;
4437 state
->levels
[0].arbRefreshState
= (u8
)(SISLANDS_ULV_STATE_ARB_INDEX
);
4438 state
->levels
[0].ACIndex
= 1;
4439 state
->levels
[0].std_vddc
= state
->levels
[0].vddc
;
4440 state
->levelCount
= 1;
4442 state
->flags
|= PPSMC_SWSTATE_FLAG_DC
;
4448 static int si_program_ulv_memory_timing_parameters(struct radeon_device
*rdev
)
4450 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4451 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
4452 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs
= { 0 };
4455 ret
= si_populate_memory_timing_parameters(rdev
, &ulv
->pl
,
4460 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay
,
4461 ulv
->volt_change_delay
);
4463 ret
= si_copy_bytes_to_smc(rdev
,
4464 si_pi
->arb_table_start
+
4465 offsetof(SMC_SIslands_MCArbDramTimingRegisters
, data
) +
4466 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet
) * SISLANDS_ULV_STATE_ARB_INDEX
,
4468 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet
),
4474 static void si_get_mvdd_configuration(struct radeon_device
*rdev
)
4476 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4478 pi
->mvdd_split_frequency
= 30000;
4481 static int si_init_smc_table(struct radeon_device
*rdev
)
4483 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4484 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4485 struct radeon_ps
*radeon_boot_state
= rdev
->pm
.dpm
.boot_ps
;
4486 const struct si_ulv_param
*ulv
= &si_pi
->ulv
;
4487 SISLANDS_SMC_STATETABLE
*table
= &si_pi
->smc_statetable
;
4492 si_populate_smc_voltage_tables(rdev
, table
);
4494 switch (rdev
->pm
.int_thermal_type
) {
4495 case THERMAL_TYPE_SI
:
4496 case THERMAL_TYPE_EMC2103_WITH_INTERNAL
:
4497 table
->thermalProtectType
= PPSMC_THERMAL_PROTECT_TYPE_INTERNAL
;
4499 case THERMAL_TYPE_NONE
:
4500 table
->thermalProtectType
= PPSMC_THERMAL_PROTECT_TYPE_NONE
;
4503 table
->thermalProtectType
= PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL
;
4507 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_HARDWAREDC
)
4508 table
->systemFlags
|= PPSMC_SYSTEMFLAG_GPIO_DC
;
4510 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_REGULATOR_HOT
) {
4511 if ((rdev
->pdev
->device
!= 0x6818) && (rdev
->pdev
->device
!= 0x6819))
4512 table
->systemFlags
|= PPSMC_SYSTEMFLAG_REGULATOR_HOT
;
4515 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_STEPVDDC
)
4516 table
->systemFlags
|= PPSMC_SYSTEMFLAG_STEPVDDC
;
4519 table
->systemFlags
|= PPSMC_SYSTEMFLAG_GDDR5
;
4521 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY
)
4522 table
->systemFlags
|= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH
;
4524 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE
) {
4525 table
->systemFlags
|= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO
;
4526 vr_hot_gpio
= rdev
->pm
.dpm
.backbias_response_time
;
4527 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_vr_hot_gpio
,
4531 ret
= si_populate_smc_initial_state(rdev
, radeon_boot_state
, table
);
4535 ret
= si_populate_smc_acpi_state(rdev
, table
);
4539 table
->driverState
= table
->initialState
;
4541 ret
= si_do_program_memory_timing_parameters(rdev
, radeon_boot_state
,
4542 SISLANDS_INITIAL_STATE_ARB_INDEX
);
4546 if (ulv
->supported
&& ulv
->pl
.vddc
) {
4547 ret
= si_populate_ulv_state(rdev
, &table
->ULVState
);
4551 ret
= si_program_ulv_memory_timing_parameters(rdev
);
4555 WREG32(CG_ULV_CONTROL
, ulv
->cg_ulv_control
);
4556 WREG32(CG_ULV_PARAMETER
, ulv
->cg_ulv_parameter
);
4558 lane_width
= radeon_get_pcie_lanes(rdev
);
4559 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width
, lane_width
);
4561 table
->ULVState
= table
->initialState
;
4564 return si_copy_bytes_to_smc(rdev
, si_pi
->state_table_start
,
4565 (u8
*)table
, sizeof(SISLANDS_SMC_STATETABLE
),
4569 static int si_calculate_sclk_params(struct radeon_device
*rdev
,
4571 SISLANDS_SMC_SCLK_VALUE
*sclk
)
4573 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4574 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4575 struct atom_clock_dividers dividers
;
4576 u32 spll_func_cntl
= si_pi
->clock_registers
.cg_spll_func_cntl
;
4577 u32 spll_func_cntl_2
= si_pi
->clock_registers
.cg_spll_func_cntl_2
;
4578 u32 spll_func_cntl_3
= si_pi
->clock_registers
.cg_spll_func_cntl_3
;
4579 u32 spll_func_cntl_4
= si_pi
->clock_registers
.cg_spll_func_cntl_4
;
4580 u32 cg_spll_spread_spectrum
= si_pi
->clock_registers
.cg_spll_spread_spectrum
;
4581 u32 cg_spll_spread_spectrum_2
= si_pi
->clock_registers
.cg_spll_spread_spectrum_2
;
4583 u32 reference_clock
= rdev
->clock
.spll
.reference_freq
;
4584 u32 reference_divider
;
4588 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
4589 engine_clock
, false, ÷rs
);
4593 reference_divider
= 1 + dividers
.ref_div
;
4595 tmp
= (u64
) engine_clock
* reference_divider
* dividers
.post_div
* 16384;
4596 do_div(tmp
, reference_clock
);
4599 spll_func_cntl
&= ~(SPLL_PDIV_A_MASK
| SPLL_REF_DIV_MASK
);
4600 spll_func_cntl
|= SPLL_REF_DIV(dividers
.ref_div
);
4601 spll_func_cntl
|= SPLL_PDIV_A(dividers
.post_div
);
4603 spll_func_cntl_2
&= ~SCLK_MUX_SEL_MASK
;
4604 spll_func_cntl_2
|= SCLK_MUX_SEL(2);
4606 spll_func_cntl_3
&= ~SPLL_FB_DIV_MASK
;
4607 spll_func_cntl_3
|= SPLL_FB_DIV(fbdiv
);
4608 spll_func_cntl_3
|= SPLL_DITHEN
;
4611 struct radeon_atom_ss ss
;
4612 u32 vco_freq
= engine_clock
* dividers
.post_div
;
4614 if (radeon_atombios_get_asic_ss_info(rdev
, &ss
,
4615 ASIC_INTERNAL_ENGINE_SS
, vco_freq
)) {
4616 u32 clk_s
= reference_clock
* 5 / (reference_divider
* ss
.rate
);
4617 u32 clk_v
= 4 * ss
.percentage
* fbdiv
/ (clk_s
* 10000);
4619 cg_spll_spread_spectrum
&= ~CLK_S_MASK
;
4620 cg_spll_spread_spectrum
|= CLK_S(clk_s
);
4621 cg_spll_spread_spectrum
|= SSEN
;
4623 cg_spll_spread_spectrum_2
&= ~CLK_V_MASK
;
4624 cg_spll_spread_spectrum_2
|= CLK_V(clk_v
);
4628 sclk
->sclk_value
= engine_clock
;
4629 sclk
->vCG_SPLL_FUNC_CNTL
= spll_func_cntl
;
4630 sclk
->vCG_SPLL_FUNC_CNTL_2
= spll_func_cntl_2
;
4631 sclk
->vCG_SPLL_FUNC_CNTL_3
= spll_func_cntl_3
;
4632 sclk
->vCG_SPLL_FUNC_CNTL_4
= spll_func_cntl_4
;
4633 sclk
->vCG_SPLL_SPREAD_SPECTRUM
= cg_spll_spread_spectrum
;
4634 sclk
->vCG_SPLL_SPREAD_SPECTRUM_2
= cg_spll_spread_spectrum_2
;
4639 static int si_populate_sclk_value(struct radeon_device
*rdev
,
4641 SISLANDS_SMC_SCLK_VALUE
*sclk
)
4643 SISLANDS_SMC_SCLK_VALUE sclk_tmp
;
4646 ret
= si_calculate_sclk_params(rdev
, engine_clock
, &sclk_tmp
);
4648 sclk
->sclk_value
= cpu_to_be32(sclk_tmp
.sclk_value
);
4649 sclk
->vCG_SPLL_FUNC_CNTL
= cpu_to_be32(sclk_tmp
.vCG_SPLL_FUNC_CNTL
);
4650 sclk
->vCG_SPLL_FUNC_CNTL_2
= cpu_to_be32(sclk_tmp
.vCG_SPLL_FUNC_CNTL_2
);
4651 sclk
->vCG_SPLL_FUNC_CNTL_3
= cpu_to_be32(sclk_tmp
.vCG_SPLL_FUNC_CNTL_3
);
4652 sclk
->vCG_SPLL_FUNC_CNTL_4
= cpu_to_be32(sclk_tmp
.vCG_SPLL_FUNC_CNTL_4
);
4653 sclk
->vCG_SPLL_SPREAD_SPECTRUM
= cpu_to_be32(sclk_tmp
.vCG_SPLL_SPREAD_SPECTRUM
);
4654 sclk
->vCG_SPLL_SPREAD_SPECTRUM_2
= cpu_to_be32(sclk_tmp
.vCG_SPLL_SPREAD_SPECTRUM_2
);
4660 static int si_populate_mclk_value(struct radeon_device
*rdev
,
4663 SISLANDS_SMC_MCLK_VALUE
*mclk
,
4667 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4668 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4669 u32 dll_cntl
= si_pi
->clock_registers
.dll_cntl
;
4670 u32 mclk_pwrmgt_cntl
= si_pi
->clock_registers
.mclk_pwrmgt_cntl
;
4671 u32 mpll_ad_func_cntl
= si_pi
->clock_registers
.mpll_ad_func_cntl
;
4672 u32 mpll_dq_func_cntl
= si_pi
->clock_registers
.mpll_dq_func_cntl
;
4673 u32 mpll_func_cntl
= si_pi
->clock_registers
.mpll_func_cntl
;
4674 u32 mpll_func_cntl_1
= si_pi
->clock_registers
.mpll_func_cntl_1
;
4675 u32 mpll_func_cntl_2
= si_pi
->clock_registers
.mpll_func_cntl_2
;
4676 u32 mpll_ss1
= si_pi
->clock_registers
.mpll_ss1
;
4677 u32 mpll_ss2
= si_pi
->clock_registers
.mpll_ss2
;
4678 struct atom_mpll_param mpll_param
;
4681 ret
= radeon_atom_get_memory_pll_dividers(rdev
, memory_clock
, strobe_mode
, &mpll_param
);
4685 mpll_func_cntl
&= ~BWCTRL_MASK
;
4686 mpll_func_cntl
|= BWCTRL(mpll_param
.bwcntl
);
4688 mpll_func_cntl_1
&= ~(CLKF_MASK
| CLKFRAC_MASK
| VCO_MODE_MASK
);
4689 mpll_func_cntl_1
|= CLKF(mpll_param
.clkf
) |
4690 CLKFRAC(mpll_param
.clkfrac
) | VCO_MODE(mpll_param
.vco_mode
);
4692 mpll_ad_func_cntl
&= ~YCLK_POST_DIV_MASK
;
4693 mpll_ad_func_cntl
|= YCLK_POST_DIV(mpll_param
.post_div
);
4695 if (pi
->mem_gddr5
) {
4696 mpll_dq_func_cntl
&= ~(YCLK_SEL_MASK
| YCLK_POST_DIV_MASK
);
4697 mpll_dq_func_cntl
|= YCLK_SEL(mpll_param
.yclk_sel
) |
4698 YCLK_POST_DIV(mpll_param
.post_div
);
4702 struct radeon_atom_ss ss
;
4705 u32 reference_clock
= rdev
->clock
.mpll
.reference_freq
;
4708 freq_nom
= memory_clock
* 4;
4710 freq_nom
= memory_clock
* 2;
4712 tmp
= freq_nom
/ reference_clock
;
4714 if (radeon_atombios_get_asic_ss_info(rdev
, &ss
,
4715 ASIC_INTERNAL_MEMORY_SS
, freq_nom
)) {
4716 u32 clks
= reference_clock
* 5 / ss
.rate
;
4717 u32 clkv
= (u32
)((((131 * ss
.percentage
* ss
.rate
) / 100) * tmp
) / freq_nom
);
4719 mpll_ss1
&= ~CLKV_MASK
;
4720 mpll_ss1
|= CLKV(clkv
);
4722 mpll_ss2
&= ~CLKS_MASK
;
4723 mpll_ss2
|= CLKS(clks
);
4727 mclk_pwrmgt_cntl
&= ~DLL_SPEED_MASK
;
4728 mclk_pwrmgt_cntl
|= DLL_SPEED(mpll_param
.dll_speed
);
4731 mclk_pwrmgt_cntl
|= MRDCK0_PDNB
| MRDCK1_PDNB
;
4733 mclk_pwrmgt_cntl
&= ~(MRDCK0_PDNB
| MRDCK1_PDNB
);
4735 mclk
->mclk_value
= cpu_to_be32(memory_clock
);
4736 mclk
->vMPLL_FUNC_CNTL
= cpu_to_be32(mpll_func_cntl
);
4737 mclk
->vMPLL_FUNC_CNTL_1
= cpu_to_be32(mpll_func_cntl_1
);
4738 mclk
->vMPLL_FUNC_CNTL_2
= cpu_to_be32(mpll_func_cntl_2
);
4739 mclk
->vMPLL_AD_FUNC_CNTL
= cpu_to_be32(mpll_ad_func_cntl
);
4740 mclk
->vMPLL_DQ_FUNC_CNTL
= cpu_to_be32(mpll_dq_func_cntl
);
4741 mclk
->vMCLK_PWRMGT_CNTL
= cpu_to_be32(mclk_pwrmgt_cntl
);
4742 mclk
->vDLL_CNTL
= cpu_to_be32(dll_cntl
);
4743 mclk
->vMPLL_SS
= cpu_to_be32(mpll_ss1
);
4744 mclk
->vMPLL_SS2
= cpu_to_be32(mpll_ss2
);
4749 static void si_populate_smc_sp(struct radeon_device
*rdev
,
4750 struct radeon_ps
*radeon_state
,
4751 SISLANDS_SMC_SWSTATE
*smc_state
)
4753 struct ni_ps
*ps
= ni_get_ps(radeon_state
);
4754 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4757 for (i
= 0; i
< ps
->performance_level_count
- 1; i
++)
4758 smc_state
->levels
[i
].bSP
= cpu_to_be32(pi
->dsp
);
4760 smc_state
->levels
[ps
->performance_level_count
- 1].bSP
=
4761 cpu_to_be32(pi
->psp
);
4764 static int si_convert_power_level_to_smc(struct radeon_device
*rdev
,
4765 struct rv7xx_pl
*pl
,
4766 SISLANDS_SMC_HW_PERFORMANCE_LEVEL
*level
)
4768 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4769 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
4770 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4774 bool gmc_pg
= false;
4776 if (eg_pi
->pcie_performance_request
&&
4777 (si_pi
->force_pcie_gen
!= RADEON_PCIE_GEN_INVALID
))
4778 level
->gen2PCIE
= (u8
)si_pi
->force_pcie_gen
;
4780 level
->gen2PCIE
= (u8
)pl
->pcie_gen
;
4782 ret
= si_populate_sclk_value(rdev
, pl
->sclk
, &level
->sclk
);
4788 if (pi
->mclk_stutter_mode_threshold
&&
4789 (pl
->mclk
<= pi
->mclk_stutter_mode_threshold
) &&
4790 !eg_pi
->uvd_enabled
&&
4791 (RREG32(DPG_PIPE_STUTTER_CONTROL
) & STUTTER_ENABLE
) &&
4792 (rdev
->pm
.dpm
.new_active_crtc_count
<= 2)) {
4793 level
->mcFlags
|= SISLANDS_SMC_MC_STUTTER_EN
;
4796 level
->mcFlags
|= SISLANDS_SMC_MC_PG_EN
;
4799 if (pi
->mem_gddr5
) {
4800 if (pl
->mclk
> pi
->mclk_edc_enable_threshold
)
4801 level
->mcFlags
|= SISLANDS_SMC_MC_EDC_RD_FLAG
;
4803 if (pl
->mclk
> eg_pi
->mclk_edc_wr_enable_threshold
)
4804 level
->mcFlags
|= SISLANDS_SMC_MC_EDC_WR_FLAG
;
4806 level
->strobeMode
= si_get_strobe_mode_settings(rdev
, pl
->mclk
);
4808 if (level
->strobeMode
& SISLANDS_SMC_STROBE_ENABLE
) {
4809 if (si_get_mclk_frequency_ratio(pl
->mclk
, true) >=
4810 ((RREG32(MC_SEQ_MISC7
) >> 16) & 0xf))
4811 dll_state_on
= ((RREG32(MC_SEQ_MISC5
) >> 1) & 0x1) ? true : false;
4813 dll_state_on
= ((RREG32(MC_SEQ_MISC6
) >> 1) & 0x1) ? true : false;
4815 dll_state_on
= false;
4818 level
->strobeMode
= si_get_strobe_mode_settings(rdev
,
4821 dll_state_on
= ((RREG32(MC_SEQ_MISC5
) >> 1) & 0x1) ? true : false;
4824 ret
= si_populate_mclk_value(rdev
,
4828 (level
->strobeMode
& SISLANDS_SMC_STROBE_ENABLE
) != 0, dll_state_on
);
4832 ret
= si_populate_voltage_value(rdev
,
4833 &eg_pi
->vddc_voltage_table
,
4834 pl
->vddc
, &level
->vddc
);
4839 ret
= si_get_std_voltage_value(rdev
, &level
->vddc
, &std_vddc
);
4843 ret
= si_populate_std_voltage_value(rdev
, std_vddc
,
4844 level
->vddc
.index
, &level
->std_vddc
);
4848 if (eg_pi
->vddci_control
) {
4849 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddci_voltage_table
,
4850 pl
->vddci
, &level
->vddci
);
4855 if (si_pi
->vddc_phase_shed_control
) {
4856 ret
= si_populate_phase_shedding_value(rdev
,
4857 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
4866 level
->MaxPoweredUpCU
= si_pi
->max_cu
;
4868 ret
= si_populate_mvdd_value(rdev
, pl
->mclk
, &level
->mvdd
);
4873 static int si_populate_smc_t(struct radeon_device
*rdev
,
4874 struct radeon_ps
*radeon_state
,
4875 SISLANDS_SMC_SWSTATE
*smc_state
)
4877 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4878 struct ni_ps
*state
= ni_get_ps(radeon_state
);
4884 if (state
->performance_level_count
>= 9)
4887 if (state
->performance_level_count
< 2) {
4888 a_t
= CG_R(0xffff) | CG_L(0);
4889 smc_state
->levels
[0].aT
= cpu_to_be32(a_t
);
4893 smc_state
->levels
[0].aT
= cpu_to_be32(0);
4895 for (i
= 0; i
<= state
->performance_level_count
- 2; i
++) {
4896 ret
= r600_calculate_at(
4897 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS
) * 100 * (i
+ 1),
4899 state
->performance_levels
[i
+ 1].sclk
,
4900 state
->performance_levels
[i
].sclk
,
4905 t_h
= (i
+ 1) * 1000 - 50 * R600_AH_DFLT
;
4906 t_l
= (i
+ 1) * 1000 + 50 * R600_AH_DFLT
;
4909 a_t
= be32_to_cpu(smc_state
->levels
[i
].aT
) & ~CG_R_MASK
;
4910 a_t
|= CG_R(t_l
* pi
->bsp
/ 20000);
4911 smc_state
->levels
[i
].aT
= cpu_to_be32(a_t
);
4913 high_bsp
= (i
== state
->performance_level_count
- 2) ?
4915 a_t
= CG_R(0xffff) | CG_L(t_h
* high_bsp
/ 20000);
4916 smc_state
->levels
[i
+ 1].aT
= cpu_to_be32(a_t
);
4922 static int si_disable_ulv(struct radeon_device
*rdev
)
4924 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4925 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
4928 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_DisableULV
) == PPSMC_Result_OK
) ?
4934 static bool si_is_state_ulv_compatible(struct radeon_device
*rdev
,
4935 struct radeon_ps
*radeon_state
)
4937 const struct si_power_info
*si_pi
= si_get_pi(rdev
);
4938 const struct si_ulv_param
*ulv
= &si_pi
->ulv
;
4939 const struct ni_ps
*state
= ni_get_ps(radeon_state
);
4942 if (state
->performance_levels
[0].mclk
!= ulv
->pl
.mclk
)
4945 /* XXX validate against display requirements! */
4947 for (i
= 0; i
< rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.count
; i
++) {
4948 if (rdev
->clock
.current_dispclk
<=
4949 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[i
].clk
) {
4951 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[i
].v
)
4956 if ((radeon_state
->vclk
!= 0) || (radeon_state
->dclk
!= 0))
4962 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device
*rdev
,
4963 struct radeon_ps
*radeon_new_state
)
4965 const struct si_power_info
*si_pi
= si_get_pi(rdev
);
4966 const struct si_ulv_param
*ulv
= &si_pi
->ulv
;
4968 if (ulv
->supported
) {
4969 if (si_is_state_ulv_compatible(rdev
, radeon_new_state
))
4970 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableULV
) == PPSMC_Result_OK
) ?
4976 static int si_convert_power_state_to_smc(struct radeon_device
*rdev
,
4977 struct radeon_ps
*radeon_state
,
4978 SISLANDS_SMC_SWSTATE
*smc_state
)
4980 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
4981 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
4982 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4983 struct ni_ps
*state
= ni_get_ps(radeon_state
);
4986 u32 sclk_in_sr
= 1350; /* ??? */
4988 if (state
->performance_level_count
> SISLANDS_MAX_HARDWARE_POWERLEVELS
)
4991 threshold
= state
->performance_levels
[state
->performance_level_count
-1].sclk
* 100 / 100;
4993 if (radeon_state
->vclk
&& radeon_state
->dclk
) {
4994 eg_pi
->uvd_enabled
= true;
4995 if (eg_pi
->smu_uvd_hs
)
4996 smc_state
->flags
|= PPSMC_SWSTATE_FLAG_UVD
;
4998 eg_pi
->uvd_enabled
= false;
5001 if (state
->dc_compatible
)
5002 smc_state
->flags
|= PPSMC_SWSTATE_FLAG_DC
;
5004 smc_state
->levelCount
= 0;
5005 for (i
= 0; i
< state
->performance_level_count
; i
++) {
5006 if (eg_pi
->sclk_deep_sleep
) {
5007 if ((i
== 0) || si_pi
->sclk_deep_sleep_above_low
) {
5008 if (sclk_in_sr
<= SCLK_MIN_DEEPSLEEP_FREQ
)
5009 smc_state
->levels
[i
].stateFlags
|= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS
;
5011 smc_state
->levels
[i
].stateFlags
|= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE
;
5015 ret
= si_convert_power_level_to_smc(rdev
, &state
->performance_levels
[i
],
5016 &smc_state
->levels
[i
]);
5017 smc_state
->levels
[i
].arbRefreshState
=
5018 (u8
)(SISLANDS_DRIVER_STATE_ARB_INDEX
+ i
);
5023 if (ni_pi
->enable_power_containment
)
5024 smc_state
->levels
[i
].displayWatermark
=
5025 (state
->performance_levels
[i
].sclk
< threshold
) ?
5026 PPSMC_DISPLAY_WATERMARK_LOW
: PPSMC_DISPLAY_WATERMARK_HIGH
;
5028 smc_state
->levels
[i
].displayWatermark
= (i
< 2) ?
5029 PPSMC_DISPLAY_WATERMARK_LOW
: PPSMC_DISPLAY_WATERMARK_HIGH
;
5031 if (eg_pi
->dynamic_ac_timing
)
5032 smc_state
->levels
[i
].ACIndex
= SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT
+ i
;
5034 smc_state
->levels
[i
].ACIndex
= 0;
5036 smc_state
->levelCount
++;
5039 si_write_smc_soft_register(rdev
,
5040 SI_SMC_SOFT_REGISTER_watermark_threshold
,
5043 si_populate_smc_sp(rdev
, radeon_state
, smc_state
);
5045 ret
= si_populate_power_containment_values(rdev
, radeon_state
, smc_state
);
5047 ni_pi
->enable_power_containment
= false;
5049 ret
= si_populate_sq_ramping_values(rdev
, radeon_state
, smc_state
);
5051 ni_pi
->enable_sq_ramping
= false;
5053 return si_populate_smc_t(rdev
, radeon_state
, smc_state
);
5056 static int si_upload_sw_state(struct radeon_device
*rdev
,
5057 struct radeon_ps
*radeon_new_state
)
5059 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5060 struct ni_ps
*new_state
= ni_get_ps(radeon_new_state
);
5062 u32 address
= si_pi
->state_table_start
+
5063 offsetof(SISLANDS_SMC_STATETABLE
, driverState
);
5064 u32 state_size
= sizeof(SISLANDS_SMC_SWSTATE
) +
5065 ((new_state
->performance_level_count
- 1) *
5066 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL
));
5067 SISLANDS_SMC_SWSTATE
*smc_state
= &si_pi
->smc_statetable
.driverState
;
5069 memset(smc_state
, 0, state_size
);
5071 ret
= si_convert_power_state_to_smc(rdev
, radeon_new_state
, smc_state
);
5075 ret
= si_copy_bytes_to_smc(rdev
, address
, (u8
*)smc_state
,
5076 state_size
, si_pi
->sram_end
);
5081 static int si_upload_ulv_state(struct radeon_device
*rdev
)
5083 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5084 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
5087 if (ulv
->supported
&& ulv
->pl
.vddc
) {
5088 u32 address
= si_pi
->state_table_start
+
5089 offsetof(SISLANDS_SMC_STATETABLE
, ULVState
);
5090 SISLANDS_SMC_SWSTATE
*smc_state
= &si_pi
->smc_statetable
.ULVState
;
5091 u32 state_size
= sizeof(SISLANDS_SMC_SWSTATE
);
5093 memset(smc_state
, 0, state_size
);
5095 ret
= si_populate_ulv_state(rdev
, smc_state
);
5097 ret
= si_copy_bytes_to_smc(rdev
, address
, (u8
*)smc_state
,
5098 state_size
, si_pi
->sram_end
);
5104 static int si_upload_smc_data(struct radeon_device
*rdev
)
5106 struct radeon_crtc
*radeon_crtc
= NULL
;
5109 if (rdev
->pm
.dpm
.new_active_crtc_count
== 0)
5112 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
5113 if (rdev
->pm
.dpm
.new_active_crtcs
& (1 << i
)) {
5114 radeon_crtc
= rdev
->mode_info
.crtcs
[i
];
5119 if (radeon_crtc
== NULL
)
5122 if (radeon_crtc
->line_time
<= 0)
5125 if (si_write_smc_soft_register(rdev
,
5126 SI_SMC_SOFT_REGISTER_crtc_index
,
5127 radeon_crtc
->crtc_id
) != PPSMC_Result_OK
)
5130 if (si_write_smc_soft_register(rdev
,
5131 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min
,
5132 radeon_crtc
->wm_high
/ radeon_crtc
->line_time
) != PPSMC_Result_OK
)
5135 if (si_write_smc_soft_register(rdev
,
5136 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max
,
5137 radeon_crtc
->wm_low
/ radeon_crtc
->line_time
) != PPSMC_Result_OK
)
5143 static int si_set_mc_special_registers(struct radeon_device
*rdev
,
5144 struct si_mc_reg_table
*table
)
5146 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
5150 for (i
= 0, j
= table
->last
; i
< table
->last
; i
++) {
5151 if (j
>= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5153 switch (table
->mc_reg_address
[i
].s1
<< 2) {
5155 temp_reg
= RREG32(MC_PMG_CMD_EMRS
);
5156 table
->mc_reg_address
[j
].s1
= MC_PMG_CMD_EMRS
>> 2;
5157 table
->mc_reg_address
[j
].s0
= MC_SEQ_PMG_CMD_EMRS_LP
>> 2;
5158 for (k
= 0; k
< table
->num_entries
; k
++)
5159 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
5160 ((temp_reg
& 0xffff0000)) |
5161 ((table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16);
5163 if (j
>= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5166 temp_reg
= RREG32(MC_PMG_CMD_MRS
);
5167 table
->mc_reg_address
[j
].s1
= MC_PMG_CMD_MRS
>> 2;
5168 table
->mc_reg_address
[j
].s0
= MC_SEQ_PMG_CMD_MRS_LP
>> 2;
5169 for (k
= 0; k
< table
->num_entries
; k
++) {
5170 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
5171 (temp_reg
& 0xffff0000) |
5172 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
5174 table
->mc_reg_table_entry
[k
].mc_data
[j
] |= 0x100;
5177 if (j
> SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5180 if (!pi
->mem_gddr5
) {
5181 table
->mc_reg_address
[j
].s1
= MC_PMG_AUTO_CMD
>> 2;
5182 table
->mc_reg_address
[j
].s0
= MC_PMG_AUTO_CMD
>> 2;
5183 for (k
= 0; k
< table
->num_entries
; k
++)
5184 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
5185 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16;
5187 if (j
> SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5191 case MC_SEQ_RESERVE_M
:
5192 temp_reg
= RREG32(MC_PMG_CMD_MRS1
);
5193 table
->mc_reg_address
[j
].s1
= MC_PMG_CMD_MRS1
>> 2;
5194 table
->mc_reg_address
[j
].s0
= MC_SEQ_PMG_CMD_MRS1_LP
>> 2;
5195 for(k
= 0; k
< table
->num_entries
; k
++)
5196 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
5197 (temp_reg
& 0xffff0000) |
5198 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
5200 if (j
> SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5213 static bool si_check_s0_mc_reg_index(u16 in_reg
, u16
*out_reg
)
5218 case MC_SEQ_RAS_TIMING
>> 2:
5219 *out_reg
= MC_SEQ_RAS_TIMING_LP
>> 2;
5221 case MC_SEQ_CAS_TIMING
>> 2:
5222 *out_reg
= MC_SEQ_CAS_TIMING_LP
>> 2;
5224 case MC_SEQ_MISC_TIMING
>> 2:
5225 *out_reg
= MC_SEQ_MISC_TIMING_LP
>> 2;
5227 case MC_SEQ_MISC_TIMING2
>> 2:
5228 *out_reg
= MC_SEQ_MISC_TIMING2_LP
>> 2;
5230 case MC_SEQ_RD_CTL_D0
>> 2:
5231 *out_reg
= MC_SEQ_RD_CTL_D0_LP
>> 2;
5233 case MC_SEQ_RD_CTL_D1
>> 2:
5234 *out_reg
= MC_SEQ_RD_CTL_D1_LP
>> 2;
5236 case MC_SEQ_WR_CTL_D0
>> 2:
5237 *out_reg
= MC_SEQ_WR_CTL_D0_LP
>> 2;
5239 case MC_SEQ_WR_CTL_D1
>> 2:
5240 *out_reg
= MC_SEQ_WR_CTL_D1_LP
>> 2;
5242 case MC_PMG_CMD_EMRS
>> 2:
5243 *out_reg
= MC_SEQ_PMG_CMD_EMRS_LP
>> 2;
5245 case MC_PMG_CMD_MRS
>> 2:
5246 *out_reg
= MC_SEQ_PMG_CMD_MRS_LP
>> 2;
5248 case MC_PMG_CMD_MRS1
>> 2:
5249 *out_reg
= MC_SEQ_PMG_CMD_MRS1_LP
>> 2;
5251 case MC_SEQ_PMG_TIMING
>> 2:
5252 *out_reg
= MC_SEQ_PMG_TIMING_LP
>> 2;
5254 case MC_PMG_CMD_MRS2
>> 2:
5255 *out_reg
= MC_SEQ_PMG_CMD_MRS2_LP
>> 2;
5257 case MC_SEQ_WR_CTL_2
>> 2:
5258 *out_reg
= MC_SEQ_WR_CTL_2_LP
>> 2;
5268 static void si_set_valid_flag(struct si_mc_reg_table
*table
)
5272 for (i
= 0; i
< table
->last
; i
++) {
5273 for (j
= 1; j
< table
->num_entries
; j
++) {
5274 if (table
->mc_reg_table_entry
[j
-1].mc_data
[i
] != table
->mc_reg_table_entry
[j
].mc_data
[i
]) {
5275 table
->valid_flag
|= 1 << i
;
5282 static void si_set_s0_mc_reg_index(struct si_mc_reg_table
*table
)
5287 for (i
= 0; i
< table
->last
; i
++)
5288 table
->mc_reg_address
[i
].s0
= si_check_s0_mc_reg_index(table
->mc_reg_address
[i
].s1
, &address
) ?
5289 address
: table
->mc_reg_address
[i
].s1
;
5293 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table
*table
,
5294 struct si_mc_reg_table
*si_table
)
5298 if (table
->last
> SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5300 if (table
->num_entries
> MAX_AC_TIMING_ENTRIES
)
5303 for (i
= 0; i
< table
->last
; i
++)
5304 si_table
->mc_reg_address
[i
].s1
= table
->mc_reg_address
[i
].s1
;
5305 si_table
->last
= table
->last
;
5307 for (i
= 0; i
< table
->num_entries
; i
++) {
5308 si_table
->mc_reg_table_entry
[i
].mclk_max
=
5309 table
->mc_reg_table_entry
[i
].mclk_max
;
5310 for (j
= 0; j
< table
->last
; j
++) {
5311 si_table
->mc_reg_table_entry
[i
].mc_data
[j
] =
5312 table
->mc_reg_table_entry
[i
].mc_data
[j
];
5315 si_table
->num_entries
= table
->num_entries
;
5320 static int si_initialize_mc_reg_table(struct radeon_device
*rdev
)
5322 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5323 struct atom_mc_reg_table
*table
;
5324 struct si_mc_reg_table
*si_table
= &si_pi
->mc_reg_table
;
5325 u8 module_index
= rv770_get_memory_module_index(rdev
);
5328 table
= kzalloc(sizeof(struct atom_mc_reg_table
), GFP_KERNEL
);
5332 WREG32(MC_SEQ_RAS_TIMING_LP
, RREG32(MC_SEQ_RAS_TIMING
));
5333 WREG32(MC_SEQ_CAS_TIMING_LP
, RREG32(MC_SEQ_CAS_TIMING
));
5334 WREG32(MC_SEQ_MISC_TIMING_LP
, RREG32(MC_SEQ_MISC_TIMING
));
5335 WREG32(MC_SEQ_MISC_TIMING2_LP
, RREG32(MC_SEQ_MISC_TIMING2
));
5336 WREG32(MC_SEQ_PMG_CMD_EMRS_LP
, RREG32(MC_PMG_CMD_EMRS
));
5337 WREG32(MC_SEQ_PMG_CMD_MRS_LP
, RREG32(MC_PMG_CMD_MRS
));
5338 WREG32(MC_SEQ_PMG_CMD_MRS1_LP
, RREG32(MC_PMG_CMD_MRS1
));
5339 WREG32(MC_SEQ_WR_CTL_D0_LP
, RREG32(MC_SEQ_WR_CTL_D0
));
5340 WREG32(MC_SEQ_WR_CTL_D1_LP
, RREG32(MC_SEQ_WR_CTL_D1
));
5341 WREG32(MC_SEQ_RD_CTL_D0_LP
, RREG32(MC_SEQ_RD_CTL_D0
));
5342 WREG32(MC_SEQ_RD_CTL_D1_LP
, RREG32(MC_SEQ_RD_CTL_D1
));
5343 WREG32(MC_SEQ_PMG_TIMING_LP
, RREG32(MC_SEQ_PMG_TIMING
));
5344 WREG32(MC_SEQ_PMG_CMD_MRS2_LP
, RREG32(MC_PMG_CMD_MRS2
));
5345 WREG32(MC_SEQ_WR_CTL_2_LP
, RREG32(MC_SEQ_WR_CTL_2
));
5347 ret
= radeon_atom_init_mc_reg_table(rdev
, module_index
, table
);
5351 ret
= si_copy_vbios_mc_reg_table(table
, si_table
);
5355 si_set_s0_mc_reg_index(si_table
);
5357 ret
= si_set_mc_special_registers(rdev
, si_table
);
5361 si_set_valid_flag(si_table
);
5370 static void si_populate_mc_reg_addresses(struct radeon_device
*rdev
,
5371 SMC_SIslands_MCRegisters
*mc_reg_table
)
5373 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5376 for (i
= 0, j
= 0; j
< si_pi
->mc_reg_table
.last
; j
++) {
5377 if (si_pi
->mc_reg_table
.valid_flag
& (1 << j
)) {
5378 if (i
>= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE
)
5380 mc_reg_table
->address
[i
].s0
=
5381 cpu_to_be16(si_pi
->mc_reg_table
.mc_reg_address
[j
].s0
);
5382 mc_reg_table
->address
[i
].s1
=
5383 cpu_to_be16(si_pi
->mc_reg_table
.mc_reg_address
[j
].s1
);
5387 mc_reg_table
->last
= (u8
)i
;
5390 static void si_convert_mc_registers(const struct si_mc_reg_entry
*entry
,
5391 SMC_SIslands_MCRegisterSet
*data
,
5392 u32 num_entries
, u32 valid_flag
)
5396 for(i
= 0, j
= 0; j
< num_entries
; j
++) {
5397 if (valid_flag
& (1 << j
)) {
5398 data
->value
[i
] = cpu_to_be32(entry
->mc_data
[j
]);
5404 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device
*rdev
,
5405 struct rv7xx_pl
*pl
,
5406 SMC_SIslands_MCRegisterSet
*mc_reg_table_data
)
5408 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5411 for (i
= 0; i
< si_pi
->mc_reg_table
.num_entries
; i
++) {
5412 if (pl
->mclk
<= si_pi
->mc_reg_table
.mc_reg_table_entry
[i
].mclk_max
)
5416 if ((i
== si_pi
->mc_reg_table
.num_entries
) && (i
> 0))
5419 si_convert_mc_registers(&si_pi
->mc_reg_table
.mc_reg_table_entry
[i
],
5420 mc_reg_table_data
, si_pi
->mc_reg_table
.last
,
5421 si_pi
->mc_reg_table
.valid_flag
);
5424 static void si_convert_mc_reg_table_to_smc(struct radeon_device
*rdev
,
5425 struct radeon_ps
*radeon_state
,
5426 SMC_SIslands_MCRegisters
*mc_reg_table
)
5428 struct ni_ps
*state
= ni_get_ps(radeon_state
);
5431 for (i
= 0; i
< state
->performance_level_count
; i
++) {
5432 si_convert_mc_reg_table_entry_to_smc(rdev
,
5433 &state
->performance_levels
[i
],
5434 &mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT
+ i
]);
5438 static int si_populate_mc_reg_table(struct radeon_device
*rdev
,
5439 struct radeon_ps
*radeon_boot_state
)
5441 struct ni_ps
*boot_state
= ni_get_ps(radeon_boot_state
);
5442 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5443 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
5444 SMC_SIslands_MCRegisters
*smc_mc_reg_table
= &si_pi
->smc_mc_reg_table
;
5446 memset(smc_mc_reg_table
, 0, sizeof(SMC_SIslands_MCRegisters
));
5448 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_seq_index
, 1);
5450 si_populate_mc_reg_addresses(rdev
, smc_mc_reg_table
);
5452 si_convert_mc_reg_table_entry_to_smc(rdev
, &boot_state
->performance_levels
[0],
5453 &smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT
]);
5455 si_convert_mc_registers(&si_pi
->mc_reg_table
.mc_reg_table_entry
[0],
5456 &smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_ACPI_SLOT
],
5457 si_pi
->mc_reg_table
.last
,
5458 si_pi
->mc_reg_table
.valid_flag
);
5460 if (ulv
->supported
&& ulv
->pl
.vddc
!= 0)
5461 si_convert_mc_reg_table_entry_to_smc(rdev
, &ulv
->pl
,
5462 &smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_ULV_SLOT
]);
5464 si_convert_mc_registers(&si_pi
->mc_reg_table
.mc_reg_table_entry
[0],
5465 &smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_ULV_SLOT
],
5466 si_pi
->mc_reg_table
.last
,
5467 si_pi
->mc_reg_table
.valid_flag
);
5469 si_convert_mc_reg_table_to_smc(rdev
, radeon_boot_state
, smc_mc_reg_table
);
5471 return si_copy_bytes_to_smc(rdev
, si_pi
->mc_reg_table_start
,
5472 (u8
*)smc_mc_reg_table
,
5473 sizeof(SMC_SIslands_MCRegisters
), si_pi
->sram_end
);
5476 static int si_upload_mc_reg_table(struct radeon_device
*rdev
,
5477 struct radeon_ps
*radeon_new_state
)
5479 struct ni_ps
*new_state
= ni_get_ps(radeon_new_state
);
5480 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5481 u32 address
= si_pi
->mc_reg_table_start
+
5482 offsetof(SMC_SIslands_MCRegisters
,
5483 data
[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT
]);
5484 SMC_SIslands_MCRegisters
*smc_mc_reg_table
= &si_pi
->smc_mc_reg_table
;
5486 memset(smc_mc_reg_table
, 0, sizeof(SMC_SIslands_MCRegisters
));
5488 si_convert_mc_reg_table_to_smc(rdev
, radeon_new_state
, smc_mc_reg_table
);
5491 return si_copy_bytes_to_smc(rdev
, address
,
5492 (u8
*)&smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT
],
5493 sizeof(SMC_SIslands_MCRegisterSet
) * new_state
->performance_level_count
,
5498 static void si_enable_voltage_control(struct radeon_device
*rdev
, bool enable
)
5501 WREG32_P(GENERAL_PWRMGT
, VOLT_PWRMGT_EN
, ~VOLT_PWRMGT_EN
);
5503 WREG32_P(GENERAL_PWRMGT
, 0, ~VOLT_PWRMGT_EN
);
5506 static enum radeon_pcie_gen
si_get_maximum_link_speed(struct radeon_device
*rdev
,
5507 struct radeon_ps
*radeon_state
)
5509 struct ni_ps
*state
= ni_get_ps(radeon_state
);
5511 u16 pcie_speed
, max_speed
= 0;
5513 for (i
= 0; i
< state
->performance_level_count
; i
++) {
5514 pcie_speed
= state
->performance_levels
[i
].pcie_gen
;
5515 if (max_speed
< pcie_speed
)
5516 max_speed
= pcie_speed
;
5521 static u16
si_get_current_pcie_speed(struct radeon_device
*rdev
)
5525 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
) & LC_CURRENT_DATA_RATE_MASK
;
5526 speed_cntl
>>= LC_CURRENT_DATA_RATE_SHIFT
;
5528 return (u16
)speed_cntl
;
5531 static void si_request_link_speed_change_before_state_change(struct radeon_device
*rdev
,
5532 struct radeon_ps
*radeon_new_state
,
5533 struct radeon_ps
*radeon_current_state
)
5535 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5536 enum radeon_pcie_gen target_link_speed
= si_get_maximum_link_speed(rdev
, radeon_new_state
);
5537 enum radeon_pcie_gen current_link_speed
;
5539 if (si_pi
->force_pcie_gen
== RADEON_PCIE_GEN_INVALID
)
5540 current_link_speed
= si_get_maximum_link_speed(rdev
, radeon_current_state
);
5542 current_link_speed
= si_pi
->force_pcie_gen
;
5544 si_pi
->force_pcie_gen
= RADEON_PCIE_GEN_INVALID
;
5545 si_pi
->pspp_notify_required
= false;
5546 if (target_link_speed
> current_link_speed
) {
5547 switch (target_link_speed
) {
5548 #if defined(CONFIG_ACPI)
5549 case RADEON_PCIE_GEN3
:
5550 if (radeon_acpi_pcie_performance_request(rdev
, PCIE_PERF_REQ_PECI_GEN3
, false) == 0)
5552 si_pi
->force_pcie_gen
= RADEON_PCIE_GEN2
;
5553 if (current_link_speed
== RADEON_PCIE_GEN2
)
5555 case RADEON_PCIE_GEN2
:
5556 if (radeon_acpi_pcie_performance_request(rdev
, PCIE_PERF_REQ_PECI_GEN2
, false) == 0)
5560 si_pi
->force_pcie_gen
= si_get_current_pcie_speed(rdev
);
5564 if (target_link_speed
< current_link_speed
)
5565 si_pi
->pspp_notify_required
= true;
5569 static void si_notify_link_speed_change_after_state_change(struct radeon_device
*rdev
,
5570 struct radeon_ps
*radeon_new_state
,
5571 struct radeon_ps
*radeon_current_state
)
5573 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5574 enum radeon_pcie_gen target_link_speed
= si_get_maximum_link_speed(rdev
, radeon_new_state
);
5577 if (si_pi
->pspp_notify_required
) {
5578 if (target_link_speed
== RADEON_PCIE_GEN3
)
5579 request
= PCIE_PERF_REQ_PECI_GEN3
;
5580 else if (target_link_speed
== RADEON_PCIE_GEN2
)
5581 request
= PCIE_PERF_REQ_PECI_GEN2
;
5583 request
= PCIE_PERF_REQ_PECI_GEN1
;
5585 if ((request
== PCIE_PERF_REQ_PECI_GEN1
) &&
5586 (si_get_current_pcie_speed(rdev
) > 0))
5589 #if defined(CONFIG_ACPI)
5590 radeon_acpi_pcie_performance_request(rdev
, request
, false);
5596 static int si_ds_request(struct radeon_device
*rdev
,
5597 bool ds_status_on
, u32 count_write
)
5599 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
5601 if (eg_pi
->sclk_deep_sleep
) {
5603 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_CancelThrottleOVRDSCLKDS
) ==
5607 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_ThrottleOVRDSCLKDS
) ==
5608 PPSMC_Result_OK
) ? 0 : -EINVAL
;
5614 static void si_set_max_cu_value(struct radeon_device
*rdev
)
5616 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5618 if (rdev
->family
== CHIP_VERDE
) {
5619 switch (rdev
->pdev
->device
) {
5655 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device
*rdev
,
5656 struct radeon_clock_voltage_dependency_table
*table
)
5660 u16 leakage_voltage
;
5663 for (i
= 0; i
< table
->count
; i
++) {
5664 switch (si_get_leakage_voltage_from_leakage_index(rdev
,
5665 table
->entries
[i
].v
,
5666 &leakage_voltage
)) {
5668 table
->entries
[i
].v
= leakage_voltage
;
5678 for (j
= (table
->count
- 2); j
>= 0; j
--) {
5679 table
->entries
[j
].v
= (table
->entries
[j
].v
<= table
->entries
[j
+ 1].v
) ?
5680 table
->entries
[j
].v
: table
->entries
[j
+ 1].v
;
5686 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device
*rdev
)
5690 ret
= si_patch_single_dependency_table_based_on_leakage(rdev
,
5691 &rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
);
5692 ret
= si_patch_single_dependency_table_based_on_leakage(rdev
,
5693 &rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
);
5694 ret
= si_patch_single_dependency_table_based_on_leakage(rdev
,
5695 &rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
);
5699 static void si_set_pcie_lane_width_in_smc(struct radeon_device
*rdev
,
5700 struct radeon_ps
*radeon_new_state
,
5701 struct radeon_ps
*radeon_current_state
)
5704 u32 new_lane_width
=
5705 (radeon_new_state
->caps
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
;
5706 u32 current_lane_width
=
5707 (radeon_current_state
->caps
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
;
5709 if (new_lane_width
!= current_lane_width
) {
5710 radeon_set_pcie_lanes(rdev
, new_lane_width
);
5711 lane_width
= radeon_get_pcie_lanes(rdev
);
5712 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width
, lane_width
);
5716 void si_dpm_setup_asic(struct radeon_device
*rdev
)
5718 rv770_get_memory_type(rdev
);
5719 si_read_clock_registers(rdev
);
5720 si_enable_acpi_power_management(rdev
);
5723 static int si_set_thermal_temperature_range(struct radeon_device
*rdev
,
5724 int min_temp
, int max_temp
)
5726 int low_temp
= 0 * 1000;
5727 int high_temp
= 255 * 1000;
5729 if (low_temp
< min_temp
)
5730 low_temp
= min_temp
;
5731 if (high_temp
> max_temp
)
5732 high_temp
= max_temp
;
5733 if (high_temp
< low_temp
) {
5734 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp
, high_temp
);
5738 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTH(high_temp
/ 1000), ~DIG_THERM_INTH_MASK
);
5739 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTL(low_temp
/ 1000), ~DIG_THERM_INTL_MASK
);
5740 WREG32_P(CG_THERMAL_CTRL
, DIG_THERM_DPM(high_temp
/ 1000), ~DIG_THERM_DPM_MASK
);
5742 rdev
->pm
.dpm
.thermal
.min_temp
= low_temp
;
5743 rdev
->pm
.dpm
.thermal
.max_temp
= high_temp
;
5748 int si_dpm_enable(struct radeon_device
*rdev
)
5750 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
5751 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
5752 struct radeon_ps
*boot_ps
= rdev
->pm
.dpm
.boot_ps
;
5755 if (si_is_smc_running(rdev
))
5757 if (pi
->voltage_control
)
5758 si_enable_voltage_control(rdev
, true);
5759 if (pi
->mvdd_control
)
5760 si_get_mvdd_configuration(rdev
);
5761 if (pi
->voltage_control
) {
5762 ret
= si_construct_voltage_tables(rdev
);
5764 DRM_ERROR("si_construct_voltage_tables failed\n");
5768 if (eg_pi
->dynamic_ac_timing
) {
5769 ret
= si_initialize_mc_reg_table(rdev
);
5771 eg_pi
->dynamic_ac_timing
= false;
5774 si_enable_spread_spectrum(rdev
, true);
5775 if (pi
->thermal_protection
)
5776 si_enable_thermal_protection(rdev
, true);
5778 si_program_git(rdev
);
5779 si_program_tp(rdev
);
5780 si_program_tpp(rdev
);
5781 si_program_sstp(rdev
);
5782 si_enable_display_gap(rdev
);
5783 si_program_vc(rdev
);
5784 ret
= si_upload_firmware(rdev
);
5786 DRM_ERROR("si_upload_firmware failed\n");
5789 ret
= si_process_firmware_header(rdev
);
5791 DRM_ERROR("si_process_firmware_header failed\n");
5794 ret
= si_initial_switch_from_arb_f0_to_f1(rdev
);
5796 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5799 ret
= si_init_smc_table(rdev
);
5801 DRM_ERROR("si_init_smc_table failed\n");
5804 ret
= si_init_smc_spll_table(rdev
);
5806 DRM_ERROR("si_init_smc_spll_table failed\n");
5809 ret
= si_init_arb_table_index(rdev
);
5811 DRM_ERROR("si_init_arb_table_index failed\n");
5814 if (eg_pi
->dynamic_ac_timing
) {
5815 ret
= si_populate_mc_reg_table(rdev
, boot_ps
);
5817 DRM_ERROR("si_populate_mc_reg_table failed\n");
5821 ret
= si_initialize_smc_cac_tables(rdev
);
5823 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5826 ret
= si_initialize_hardware_cac_manager(rdev
);
5828 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5831 ret
= si_initialize_smc_dte_tables(rdev
);
5833 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5836 ret
= si_populate_smc_tdp_limits(rdev
, boot_ps
);
5838 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5841 ret
= si_populate_smc_tdp_limits_2(rdev
, boot_ps
);
5843 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5846 si_program_response_times(rdev
);
5847 si_program_ds_registers(rdev
);
5848 si_dpm_start_smc(rdev
);
5849 ret
= si_notify_smc_display_change(rdev
, false);
5851 DRM_ERROR("si_notify_smc_display_change failed\n");
5854 si_enable_sclk_control(rdev
, true);
5857 if (rdev
->irq
.installed
&&
5858 r600_is_internal_thermal_sensor(rdev
->pm
.int_thermal_type
)) {
5859 PPSMC_Result result
;
5861 ret
= si_set_thermal_temperature_range(rdev
, R600_TEMP_RANGE_MIN
, R600_TEMP_RANGE_MAX
);
5864 rdev
->irq
.dpm_thermal
= true;
5865 radeon_irq_set(rdev
);
5866 result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableThermalInterrupt
);
5868 if (result
!= PPSMC_Result_OK
)
5869 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5872 si_enable_auto_throttle_source(rdev
, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
, true);
5874 ni_update_current_ps(rdev
, boot_ps
);
5879 void si_dpm_disable(struct radeon_device
*rdev
)
5881 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
5882 struct radeon_ps
*boot_ps
= rdev
->pm
.dpm
.boot_ps
;
5884 if (!si_is_smc_running(rdev
))
5886 si_disable_ulv(rdev
);
5888 if (pi
->thermal_protection
)
5889 si_enable_thermal_protection(rdev
, false);
5890 si_enable_power_containment(rdev
, boot_ps
, false);
5891 si_enable_smc_cac(rdev
, boot_ps
, false);
5892 si_enable_spread_spectrum(rdev
, false);
5893 si_enable_auto_throttle_source(rdev
, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
, false);
5895 si_reset_to_default(rdev
);
5896 si_dpm_stop_smc(rdev
);
5897 si_force_switch_to_arb_f0(rdev
);
5899 ni_update_current_ps(rdev
, boot_ps
);
5902 int si_dpm_pre_set_power_state(struct radeon_device
*rdev
)
5904 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
5905 struct radeon_ps requested_ps
= *rdev
->pm
.dpm
.requested_ps
;
5906 struct radeon_ps
*new_ps
= &requested_ps
;
5908 ni_update_requested_ps(rdev
, new_ps
);
5910 si_apply_state_adjust_rules(rdev
, &eg_pi
->requested_rps
);
5915 static int si_power_control_set_level(struct radeon_device
*rdev
)
5917 struct radeon_ps
*new_ps
= rdev
->pm
.dpm
.requested_ps
;
5920 ret
= si_restrict_performance_levels_before_switch(rdev
);
5923 ret
= si_halt_smc(rdev
);
5926 ret
= si_populate_smc_tdp_limits(rdev
, new_ps
);
5929 ret
= si_populate_smc_tdp_limits_2(rdev
, new_ps
);
5932 ret
= si_resume_smc(rdev
);
5935 ret
= si_set_sw_state(rdev
);
5941 int si_dpm_set_power_state(struct radeon_device
*rdev
)
5943 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
5944 struct radeon_ps
*new_ps
= &eg_pi
->requested_rps
;
5945 struct radeon_ps
*old_ps
= &eg_pi
->current_rps
;
5948 ret
= si_disable_ulv(rdev
);
5950 DRM_ERROR("si_disable_ulv failed\n");
5953 ret
= si_restrict_performance_levels_before_switch(rdev
);
5955 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
5958 if (eg_pi
->pcie_performance_request
)
5959 si_request_link_speed_change_before_state_change(rdev
, new_ps
, old_ps
);
5960 ni_set_uvd_clock_before_set_eng_clock(rdev
, new_ps
, old_ps
);
5961 ret
= si_enable_power_containment(rdev
, new_ps
, false);
5963 DRM_ERROR("si_enable_power_containment failed\n");
5966 ret
= si_enable_smc_cac(rdev
, new_ps
, false);
5968 DRM_ERROR("si_enable_smc_cac failed\n");
5971 ret
= si_halt_smc(rdev
);
5973 DRM_ERROR("si_halt_smc failed\n");
5976 ret
= si_upload_sw_state(rdev
, new_ps
);
5978 DRM_ERROR("si_upload_sw_state failed\n");
5981 ret
= si_upload_smc_data(rdev
);
5983 DRM_ERROR("si_upload_smc_data failed\n");
5986 ret
= si_upload_ulv_state(rdev
);
5988 DRM_ERROR("si_upload_ulv_state failed\n");
5991 if (eg_pi
->dynamic_ac_timing
) {
5992 ret
= si_upload_mc_reg_table(rdev
, new_ps
);
5994 DRM_ERROR("si_upload_mc_reg_table failed\n");
5998 ret
= si_program_memory_timing_parameters(rdev
, new_ps
);
6000 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6003 si_set_pcie_lane_width_in_smc(rdev
, new_ps
, old_ps
);
6005 ret
= si_resume_smc(rdev
);
6007 DRM_ERROR("si_resume_smc failed\n");
6010 ret
= si_set_sw_state(rdev
);
6012 DRM_ERROR("si_set_sw_state failed\n");
6015 ni_set_uvd_clock_after_set_eng_clock(rdev
, new_ps
, old_ps
);
6016 if (eg_pi
->pcie_performance_request
)
6017 si_notify_link_speed_change_after_state_change(rdev
, new_ps
, old_ps
);
6018 ret
= si_set_power_state_conditionally_enable_ulv(rdev
, new_ps
);
6020 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6023 ret
= si_enable_smc_cac(rdev
, new_ps
, true);
6025 DRM_ERROR("si_enable_smc_cac failed\n");
6028 ret
= si_enable_power_containment(rdev
, new_ps
, true);
6030 DRM_ERROR("si_enable_power_containment failed\n");
6034 ret
= si_power_control_set_level(rdev
);
6036 DRM_ERROR("si_power_control_set_level failed\n");
6040 ret
= si_dpm_force_performance_level(rdev
, RADEON_DPM_FORCED_LEVEL_AUTO
);
6042 DRM_ERROR("si_dpm_force_performance_level failed\n");
6049 void si_dpm_post_set_power_state(struct radeon_device
*rdev
)
6051 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
6052 struct radeon_ps
*new_ps
= &eg_pi
->requested_rps
;
6054 ni_update_current_ps(rdev
, new_ps
);
6058 void si_dpm_reset_asic(struct radeon_device
*rdev
)
6060 si_restrict_performance_levels_before_switch(rdev
);
6061 si_disable_ulv(rdev
);
6062 si_set_boot_state(rdev
);
6065 void si_dpm_display_configuration_changed(struct radeon_device
*rdev
)
6067 si_program_display_gap(rdev
);
6071 struct _ATOM_POWERPLAY_INFO info
;
6072 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
6073 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
6074 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
6075 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
6076 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
6079 union pplib_clock_info
{
6080 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
6081 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
6082 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
6083 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
6084 struct _ATOM_PPLIB_SI_CLOCK_INFO si
;
6087 union pplib_power_state
{
6088 struct _ATOM_PPLIB_STATE v1
;
6089 struct _ATOM_PPLIB_STATE_V2 v2
;
6092 static void si_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
6093 struct radeon_ps
*rps
,
6094 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
,
6097 rps
->caps
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
6098 rps
->class = le16_to_cpu(non_clock_info
->usClassification
);
6099 rps
->class2
= le16_to_cpu(non_clock_info
->usClassification2
);
6101 if (ATOM_PPLIB_NONCLOCKINFO_VER1
< table_rev
) {
6102 rps
->vclk
= le32_to_cpu(non_clock_info
->ulVCLK
);
6103 rps
->dclk
= le32_to_cpu(non_clock_info
->ulDCLK
);
6104 } else if (r600_is_uvd_state(rps
->class, rps
->class2
)) {
6105 rps
->vclk
= RV770_DEFAULT_VCLK_FREQ
;
6106 rps
->dclk
= RV770_DEFAULT_DCLK_FREQ
;
6112 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
)
6113 rdev
->pm
.dpm
.boot_ps
= rps
;
6114 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
)
6115 rdev
->pm
.dpm
.uvd_ps
= rps
;
6118 static void si_parse_pplib_clock_info(struct radeon_device
*rdev
,
6119 struct radeon_ps
*rps
, int index
,
6120 union pplib_clock_info
*clock_info
)
6122 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
6123 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
6124 struct si_power_info
*si_pi
= si_get_pi(rdev
);
6125 struct ni_ps
*ps
= ni_get_ps(rps
);
6126 u16 leakage_voltage
;
6127 struct rv7xx_pl
*pl
= &ps
->performance_levels
[index
];
6130 ps
->performance_level_count
= index
+ 1;
6132 pl
->sclk
= le16_to_cpu(clock_info
->si
.usEngineClockLow
);
6133 pl
->sclk
|= clock_info
->si
.ucEngineClockHigh
<< 16;
6134 pl
->mclk
= le16_to_cpu(clock_info
->si
.usMemoryClockLow
);
6135 pl
->mclk
|= clock_info
->si
.ucMemoryClockHigh
<< 16;
6137 pl
->vddc
= le16_to_cpu(clock_info
->si
.usVDDC
);
6138 pl
->vddci
= le16_to_cpu(clock_info
->si
.usVDDCI
);
6139 pl
->flags
= le32_to_cpu(clock_info
->si
.ulFlags
);
6140 pl
->pcie_gen
= r600_get_pcie_gen_support(rdev
,
6141 si_pi
->sys_pcie_mask
,
6142 si_pi
->boot_pcie_gen
,
6143 clock_info
->si
.ucPCIEGen
);
6145 /* patch up vddc if necessary */
6146 ret
= si_get_leakage_voltage_from_leakage_index(rdev
, pl
->vddc
,
6149 pl
->vddc
= leakage_voltage
;
6151 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
) {
6152 pi
->acpi_vddc
= pl
->vddc
;
6153 eg_pi
->acpi_vddci
= pl
->vddci
;
6154 si_pi
->acpi_pcie_gen
= pl
->pcie_gen
;
6157 if ((rps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
) &&
6159 /* XXX disable for A0 tahiti */
6160 si_pi
->ulv
.supported
= true;
6161 si_pi
->ulv
.pl
= *pl
;
6162 si_pi
->ulv
.one_pcie_lane_in_ulv
= false;
6163 si_pi
->ulv
.volt_change_delay
= SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT
;
6164 si_pi
->ulv
.cg_ulv_parameter
= SISLANDS_CGULVPARAMETER_DFLT
;
6165 si_pi
->ulv
.cg_ulv_control
= SISLANDS_CGULVCONTROL_DFLT
;
6168 if (pi
->min_vddc_in_table
> pl
->vddc
)
6169 pi
->min_vddc_in_table
= pl
->vddc
;
6171 if (pi
->max_vddc_in_table
< pl
->vddc
)
6172 pi
->max_vddc_in_table
= pl
->vddc
;
6174 /* patch up boot state */
6175 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
) {
6176 u16 vddc
, vddci
, mvdd
;
6177 radeon_atombios_get_default_voltages(rdev
, &vddc
, &vddci
, &mvdd
);
6178 pl
->mclk
= rdev
->clock
.default_mclk
;
6179 pl
->sclk
= rdev
->clock
.default_sclk
;
6182 si_pi
->mvdd_bootup_value
= mvdd
;
6185 if ((rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
) ==
6186 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
6187 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.sclk
= pl
->sclk
;
6188 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.mclk
= pl
->mclk
;
6189 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.vddc
= pl
->vddc
;
6190 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.vddci
= pl
->vddci
;
6194 static int si_parse_power_table(struct radeon_device
*rdev
)
6196 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
6197 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
6198 union pplib_power_state
*power_state
;
6199 int i
, j
, k
, non_clock_array_index
, clock_array_index
;
6200 union pplib_clock_info
*clock_info
;
6201 struct _StateArray
*state_array
;
6202 struct _ClockInfoArray
*clock_info_array
;
6203 struct _NonClockInfoArray
*non_clock_info_array
;
6204 union power_info
*power_info
;
6205 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
6208 u8
*power_state_offset
;
6211 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
6212 &frev
, &crev
, &data_offset
))
6214 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
6216 state_array
= (struct _StateArray
*)
6217 (mode_info
->atom_context
->bios
+ data_offset
+
6218 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
));
6219 clock_info_array
= (struct _ClockInfoArray
*)
6220 (mode_info
->atom_context
->bios
+ data_offset
+
6221 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
));
6222 non_clock_info_array
= (struct _NonClockInfoArray
*)
6223 (mode_info
->atom_context
->bios
+ data_offset
+
6224 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
));
6226 rdev
->pm
.dpm
.ps
= kzalloc(sizeof(struct radeon_ps
) *
6227 state_array
->ucNumEntries
, GFP_KERNEL
);
6228 if (!rdev
->pm
.dpm
.ps
)
6230 power_state_offset
= (u8
*)state_array
->states
;
6231 rdev
->pm
.dpm
.platform_caps
= le32_to_cpu(power_info
->pplib
.ulPlatformCaps
);
6232 rdev
->pm
.dpm
.backbias_response_time
= le16_to_cpu(power_info
->pplib
.usBackbiasTime
);
6233 rdev
->pm
.dpm
.voltage_response_time
= le16_to_cpu(power_info
->pplib
.usVoltageTime
);
6234 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
6235 power_state
= (union pplib_power_state
*)power_state_offset
;
6236 non_clock_array_index
= power_state
->v2
.nonClockInfoIndex
;
6237 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
6238 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
6239 if (!rdev
->pm
.power_state
[i
].clock_info
)
6241 ps
= kzalloc(sizeof(struct ni_ps
), GFP_KERNEL
);
6243 kfree(rdev
->pm
.dpm
.ps
);
6246 rdev
->pm
.dpm
.ps
[i
].ps_priv
= ps
;
6247 si_parse_pplib_non_clock_info(rdev
, &rdev
->pm
.dpm
.ps
[i
],
6249 non_clock_info_array
->ucEntrySize
);
6251 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
6252 clock_array_index
= power_state
->v2
.clockInfoIndex
[j
];
6253 if (clock_array_index
>= clock_info_array
->ucNumEntries
)
6255 if (k
>= SISLANDS_MAX_HARDWARE_POWERLEVELS
)
6257 clock_info
= (union pplib_clock_info
*)
6258 &clock_info_array
->clockInfo
[clock_array_index
* clock_info_array
->ucEntrySize
];
6259 si_parse_pplib_clock_info(rdev
,
6260 &rdev
->pm
.dpm
.ps
[i
], k
,
6264 power_state_offset
+= 2 + power_state
->v2
.ucNumDPMLevels
;
6266 rdev
->pm
.dpm
.num_ps
= state_array
->ucNumEntries
;
6270 int si_dpm_init(struct radeon_device
*rdev
)
6272 struct rv7xx_power_info
*pi
;
6273 struct evergreen_power_info
*eg_pi
;
6274 struct ni_power_info
*ni_pi
;
6275 struct si_power_info
*si_pi
;
6276 struct atom_clock_dividers dividers
;
6280 si_pi
= kzalloc(sizeof(struct si_power_info
), GFP_KERNEL
);
6283 rdev
->pm
.dpm
.priv
= si_pi
;
6288 ret
= drm_pcie_get_speed_cap_mask(rdev
->ddev
, &mask
);
6290 si_pi
->sys_pcie_mask
= 0;
6292 si_pi
->sys_pcie_mask
= mask
;
6293 si_pi
->force_pcie_gen
= RADEON_PCIE_GEN_INVALID
;
6294 si_pi
->boot_pcie_gen
= si_get_current_pcie_speed(rdev
);
6296 si_set_max_cu_value(rdev
);
6298 rv770_get_max_vddc(rdev
);
6299 si_get_leakage_vddc(rdev
);
6300 si_patch_dependency_tables_based_on_leakage(rdev
);
6303 eg_pi
->acpi_vddci
= 0;
6304 pi
->min_vddc_in_table
= 0;
6305 pi
->max_vddc_in_table
= 0;
6307 ret
= si_parse_power_table(rdev
);
6310 ret
= r600_parse_extended_power_table(rdev
);
6314 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
=
6315 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry
), GFP_KERNEL
);
6316 if (!rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
) {
6317 r600_free_extended_power_table(rdev
);
6320 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.count
= 4;
6321 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[0].clk
= 0;
6322 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[0].v
= 0;
6323 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[1].clk
= 36000;
6324 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[1].v
= 720;
6325 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[2].clk
= 54000;
6326 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[2].v
= 810;
6327 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[3].clk
= 72000;
6328 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[3].v
= 900;
6330 if (rdev
->pm
.dpm
.voltage_response_time
== 0)
6331 rdev
->pm
.dpm
.voltage_response_time
= R600_VOLTAGERESPONSETIME_DFLT
;
6332 if (rdev
->pm
.dpm
.backbias_response_time
== 0)
6333 rdev
->pm
.dpm
.backbias_response_time
= R600_BACKBIASRESPONSETIME_DFLT
;
6335 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
6336 0, false, ÷rs
);
6338 pi
->ref_div
= dividers
.ref_div
+ 1;
6340 pi
->ref_div
= R600_REFERENCEDIVIDER_DFLT
;
6342 eg_pi
->smu_uvd_hs
= false;
6344 pi
->mclk_strobe_mode_threshold
= 40000;
6345 if (si_is_special_1gb_platform(rdev
))
6346 pi
->mclk_stutter_mode_threshold
= 0;
6348 pi
->mclk_stutter_mode_threshold
= pi
->mclk_strobe_mode_threshold
;
6349 pi
->mclk_edc_enable_threshold
= 40000;
6350 eg_pi
->mclk_edc_wr_enable_threshold
= 40000;
6352 ni_pi
->mclk_rtt_mode_threshold
= eg_pi
->mclk_edc_wr_enable_threshold
;
6354 pi
->voltage_control
=
6355 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
, VOLTAGE_OBJ_GPIO_LUT
);
6358 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
);
6360 eg_pi
->vddci_control
=
6361 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
);
6363 si_pi
->vddc_phase_shed_control
=
6364 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
, VOLTAGE_OBJ_PHASE_LUT
);
6366 rv770_get_engine_memory_ss(rdev
);
6368 pi
->asi
= RV770_ASI_DFLT
;
6369 pi
->pasi
= CYPRESS_HASI_DFLT
;
6370 pi
->vrc
= SISLANDS_VRC_DFLT
;
6372 pi
->gfx_clock_gating
= true;
6374 eg_pi
->sclk_deep_sleep
= true;
6375 si_pi
->sclk_deep_sleep_above_low
= false;
6377 if (rdev
->pm
.int_thermal_type
!= THERMAL_TYPE_NONE
)
6378 pi
->thermal_protection
= true;
6380 pi
->thermal_protection
= false;
6382 eg_pi
->dynamic_ac_timing
= true;
6384 eg_pi
->light_sleep
= true;
6385 #if defined(CONFIG_ACPI)
6386 eg_pi
->pcie_performance_request
=
6387 radeon_acpi_is_pcie_performance_request_supported(rdev
);
6389 eg_pi
->pcie_performance_request
= false;
6392 si_pi
->sram_end
= SMC_RAM_END
;
6394 rdev
->pm
.dpm
.dyn_state
.mclk_sclk_ratio
= 4;
6395 rdev
->pm
.dpm
.dyn_state
.sclk_mclk_delta
= 15000;
6396 rdev
->pm
.dpm
.dyn_state
.vddc_vddci_delta
= 200;
6397 rdev
->pm
.dpm
.dyn_state
.valid_sclk_values
.count
= 0;
6398 rdev
->pm
.dpm
.dyn_state
.valid_sclk_values
.values
= NULL
;
6399 rdev
->pm
.dpm
.dyn_state
.valid_mclk_values
.count
= 0;
6400 rdev
->pm
.dpm
.dyn_state
.valid_mclk_values
.values
= NULL
;
6402 si_initialize_powertune_defaults(rdev
);
6407 void si_dpm_fini(struct radeon_device
*rdev
)
6411 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
6412 kfree(rdev
->pm
.dpm
.ps
[i
].ps_priv
);
6414 kfree(rdev
->pm
.dpm
.ps
);
6415 kfree(rdev
->pm
.dpm
.priv
);
6416 kfree(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
);
6417 r600_free_extended_power_table(rdev
);
6420 void si_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
6423 struct radeon_ps
*rps
= rdev
->pm
.dpm
.current_ps
;
6424 struct ni_ps
*ps
= ni_get_ps(rps
);
6425 struct rv7xx_pl
*pl
;
6427 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX
) & CURRENT_STATE_INDEX_MASK
) >>
6428 CURRENT_STATE_INDEX_SHIFT
;
6430 if (current_index
>= ps
->performance_level_count
) {
6431 seq_printf(m
, "invalid dpm profile %d\n", current_index
);
6433 pl
= &ps
->performance_levels
[current_index
];
6434 seq_printf(m
, "uvd vclk: %d dclk: %d\n", rps
->vclk
, rps
->dclk
);
6435 seq_printf(m
, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6436 current_index
, pl
->sclk
, pl
->mclk
, pl
->vddc
, pl
->vddci
, pl
->pcie_gen
+ 1);