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Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6
[deliverable/linux.git] / drivers / gpu / drm / radeon / si_dpm.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "radeon.h"
26 #include "sid.h"
27 #include "r600_dpm.h"
28 #include "si_dpm.h"
29 #include "atom.h"
30 #include <linux/math64.h>
31 #include <linux/seq_file.h>
32
33 #define MC_CG_ARB_FREQ_F0 0x0a
34 #define MC_CG_ARB_FREQ_F1 0x0b
35 #define MC_CG_ARB_FREQ_F2 0x0c
36 #define MC_CG_ARB_FREQ_F3 0x0d
37
38 #define SMC_RAM_END 0x20000
39
40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
41
42 static const struct si_cac_config_reg cac_weights_tahiti[] =
43 {
44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
104 { 0xFFFFFFFF }
105 };
106
107 static const struct si_cac_config_reg lcac_tahiti[] =
108 {
109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
195 { 0xFFFFFFFF }
196
197 };
198
199 static const struct si_cac_config_reg cac_override_tahiti[] =
200 {
201 { 0xFFFFFFFF }
202 };
203
204 static const struct si_powertune_data powertune_data_tahiti =
205 {
206 ((1 << 16) | 27027),
207 6,
208 0,
209 4,
210 95,
211 {
212 0UL,
213 0UL,
214 4521550UL,
215 309631529UL,
216 -1270850L,
217 4513710L,
218 40
219 },
220 595000000UL,
221 12,
222 {
223 0,
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0
231 },
232 true
233 };
234
235 static const struct si_dte_data dte_data_tahiti =
236 {
237 { 1159409, 0, 0, 0, 0 },
238 { 777, 0, 0, 0, 0 },
239 2,
240 54000,
241 127000,
242 25,
243 2,
244 10,
245 13,
246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
249 85,
250 false
251 };
252
253 static const struct si_dte_data dte_data_tahiti_le =
254 {
255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
257 0x5,
258 0xAFC8,
259 0x64,
260 0x32,
261 1,
262 0,
263 0x10,
264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
267 85,
268 true
269 };
270
271 static const struct si_dte_data dte_data_tahiti_pro =
272 {
273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
274 { 0x0, 0x0, 0x0, 0x0, 0x0 },
275 5,
276 45000,
277 100,
278 0xA,
279 1,
280 0,
281 0x10,
282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
285 90,
286 true
287 };
288
289 static const struct si_dte_data dte_data_new_zealand =
290 {
291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
293 0x5,
294 0xAFC8,
295 0x69,
296 0x32,
297 1,
298 0,
299 0x10,
300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
303 85,
304 true
305 };
306
307 static const struct si_dte_data dte_data_aruba_pro =
308 {
309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
310 { 0x0, 0x0, 0x0, 0x0, 0x0 },
311 5,
312 45000,
313 100,
314 0xA,
315 1,
316 0,
317 0x10,
318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
321 90,
322 true
323 };
324
325 static const struct si_dte_data dte_data_malta =
326 {
327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
328 { 0x0, 0x0, 0x0, 0x0, 0x0 },
329 5,
330 45000,
331 100,
332 0xA,
333 1,
334 0,
335 0x10,
336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
339 90,
340 true
341 };
342
343 struct si_cac_config_reg cac_weights_pitcairn[] =
344 {
345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
405 { 0xFFFFFFFF }
406 };
407
408 static const struct si_cac_config_reg lcac_pitcairn[] =
409 {
410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
496 { 0xFFFFFFFF }
497 };
498
499 static const struct si_cac_config_reg cac_override_pitcairn[] =
500 {
501 { 0xFFFFFFFF }
502 };
503
504 static const struct si_powertune_data powertune_data_pitcairn =
505 {
506 ((1 << 16) | 27027),
507 5,
508 0,
509 6,
510 100,
511 {
512 51600000UL,
513 1800000UL,
514 7194395UL,
515 309631529UL,
516 -1270850L,
517 4513710L,
518 100
519 },
520 117830498UL,
521 12,
522 {
523 0,
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0
531 },
532 true
533 };
534
535 static const struct si_dte_data dte_data_pitcairn =
536 {
537 { 0, 0, 0, 0, 0 },
538 { 0, 0, 0, 0, 0 },
539 0,
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 0,
550 false
551 };
552
553 static const struct si_dte_data dte_data_curacao_xt =
554 {
555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
556 { 0x0, 0x0, 0x0, 0x0, 0x0 },
557 5,
558 45000,
559 100,
560 0xA,
561 1,
562 0,
563 0x10,
564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
567 90,
568 true
569 };
570
571 static const struct si_dte_data dte_data_curacao_pro =
572 {
573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
574 { 0x0, 0x0, 0x0, 0x0, 0x0 },
575 5,
576 45000,
577 100,
578 0xA,
579 1,
580 0,
581 0x10,
582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
585 90,
586 true
587 };
588
589 static const struct si_dte_data dte_data_neptune_xt =
590 {
591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
592 { 0x0, 0x0, 0x0, 0x0, 0x0 },
593 5,
594 45000,
595 100,
596 0xA,
597 1,
598 0,
599 0x10,
600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
603 90,
604 true
605 };
606
607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
608 {
609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
669 { 0xFFFFFFFF }
670 };
671
672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
673 {
674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
734 { 0xFFFFFFFF }
735 };
736
737 static const struct si_cac_config_reg cac_weights_heathrow[] =
738 {
739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
799 { 0xFFFFFFFF }
800 };
801
802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
803 {
804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
864 { 0xFFFFFFFF }
865 };
866
867 static const struct si_cac_config_reg cac_weights_cape_verde[] =
868 {
869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
929 { 0xFFFFFFFF }
930 };
931
932 static const struct si_cac_config_reg lcac_cape_verde[] =
933 {
934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0xFFFFFFFF }
989 };
990
991 static const struct si_cac_config_reg cac_override_cape_verde[] =
992 {
993 { 0xFFFFFFFF }
994 };
995
996 static const struct si_powertune_data powertune_data_cape_verde =
997 {
998 ((1 << 16) | 0x6993),
999 5,
1000 0,
1001 7,
1002 105,
1003 {
1004 0UL,
1005 0UL,
1006 7194395UL,
1007 309631529UL,
1008 -1270850L,
1009 4513710L,
1010 100
1011 },
1012 117830498UL,
1013 12,
1014 {
1015 0,
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0
1023 },
1024 true
1025 };
1026
1027 static const struct si_dte_data dte_data_cape_verde =
1028 {
1029 { 0, 0, 0, 0, 0 },
1030 { 0, 0, 0, 0, 0 },
1031 0,
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 0,
1042 false
1043 };
1044
1045 static const struct si_dte_data dte_data_venus_xtx =
1046 {
1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1049 5,
1050 55000,
1051 0x69,
1052 0xA,
1053 1,
1054 0,
1055 0x3,
1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 90,
1060 true
1061 };
1062
1063 static const struct si_dte_data dte_data_venus_xt =
1064 {
1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1067 5,
1068 55000,
1069 0x69,
1070 0xA,
1071 1,
1072 0,
1073 0x3,
1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 90,
1078 true
1079 };
1080
1081 static const struct si_dte_data dte_data_venus_pro =
1082 {
1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1085 5,
1086 55000,
1087 0x69,
1088 0xA,
1089 1,
1090 0,
1091 0x3,
1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 90,
1096 true
1097 };
1098
1099 struct si_cac_config_reg cac_weights_oland[] =
1100 {
1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1161 { 0xFFFFFFFF }
1162 };
1163
1164 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1165 {
1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1226 { 0xFFFFFFFF }
1227 };
1228
1229 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1230 {
1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1291 { 0xFFFFFFFF }
1292 };
1293
1294 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1295 {
1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1356 { 0xFFFFFFFF }
1357 };
1358
1359 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1360 {
1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1421 { 0xFFFFFFFF }
1422 };
1423
1424 static const struct si_cac_config_reg lcac_oland[] =
1425 {
1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0xFFFFFFFF }
1469 };
1470
1471 static const struct si_cac_config_reg lcac_mars_pro[] =
1472 {
1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0xFFFFFFFF }
1516 };
1517
1518 static const struct si_cac_config_reg cac_override_oland[] =
1519 {
1520 { 0xFFFFFFFF }
1521 };
1522
1523 static const struct si_powertune_data powertune_data_oland =
1524 {
1525 ((1 << 16) | 0x6993),
1526 5,
1527 0,
1528 7,
1529 105,
1530 {
1531 0UL,
1532 0UL,
1533 7194395UL,
1534 309631529UL,
1535 -1270850L,
1536 4513710L,
1537 100
1538 },
1539 117830498UL,
1540 12,
1541 {
1542 0,
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0
1550 },
1551 true
1552 };
1553
1554 static const struct si_powertune_data powertune_data_mars_pro =
1555 {
1556 ((1 << 16) | 0x6993),
1557 5,
1558 0,
1559 7,
1560 105,
1561 {
1562 0UL,
1563 0UL,
1564 7194395UL,
1565 309631529UL,
1566 -1270850L,
1567 4513710L,
1568 100
1569 },
1570 117830498UL,
1571 12,
1572 {
1573 0,
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0
1581 },
1582 true
1583 };
1584
1585 static const struct si_dte_data dte_data_oland =
1586 {
1587 { 0, 0, 0, 0, 0 },
1588 { 0, 0, 0, 0, 0 },
1589 0,
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 0,
1600 false
1601 };
1602
1603 static const struct si_dte_data dte_data_mars_pro =
1604 {
1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1607 5,
1608 55000,
1609 105,
1610 0xA,
1611 1,
1612 0,
1613 0x10,
1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1617 90,
1618 true
1619 };
1620
1621 static const struct si_dte_data dte_data_sun_xt =
1622 {
1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1625 5,
1626 55000,
1627 105,
1628 0xA,
1629 1,
1630 0,
1631 0x10,
1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1635 90,
1636 true
1637 };
1638
1639
1640 static const struct si_cac_config_reg cac_weights_hainan[] =
1641 {
1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1702 { 0xFFFFFFFF }
1703 };
1704
1705 static const struct si_powertune_data powertune_data_hainan =
1706 {
1707 ((1 << 16) | 0x6993),
1708 5,
1709 0,
1710 9,
1711 105,
1712 {
1713 0UL,
1714 0UL,
1715 7194395UL,
1716 309631529UL,
1717 -1270850L,
1718 4513710L,
1719 100
1720 },
1721 117830498UL,
1722 12,
1723 {
1724 0,
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0
1732 },
1733 true
1734 };
1735
1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1740
1741 static int si_populate_voltage_value(struct radeon_device *rdev,
1742 const struct atom_voltage_table *table,
1743 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1744 static int si_get_std_voltage_value(struct radeon_device *rdev,
1745 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1746 u16 *std_voltage);
1747 static int si_write_smc_soft_register(struct radeon_device *rdev,
1748 u16 reg_offset, u32 value);
1749 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1750 struct rv7xx_pl *pl,
1751 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1752 static int si_calculate_sclk_params(struct radeon_device *rdev,
1753 u32 engine_clock,
1754 SISLANDS_SMC_SCLK_VALUE *sclk);
1755
1756 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1757 {
1758 struct si_power_info *pi = rdev->pm.dpm.priv;
1759
1760 return pi;
1761 }
1762
1763 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1764 u16 v, s32 t, u32 ileakage, u32 *leakage)
1765 {
1766 s64 kt, kv, leakage_w, i_leakage, vddc;
1767 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1768
1769 i_leakage = drm_int2fixp(ileakage / 100);
1770 vddc = div64_s64(drm_int2fixp(v), 1000);
1771 temperature = div64_s64(drm_int2fixp(t), 1000);
1772
1773 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1774 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1775 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1776 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1777 t_ref = drm_int2fixp(coeff->t_ref);
1778
1779 kt = drm_fixp_div(drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, temperature)),
1780 drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, t_ref)));
1781 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1782
1783 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1784
1785 *leakage = drm_fixp2int(leakage_w * 1000);
1786 }
1787
1788 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1789 const struct ni_leakage_coeffients *coeff,
1790 u16 v,
1791 s32 t,
1792 u32 i_leakage,
1793 u32 *leakage)
1794 {
1795 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1796 }
1797
1798 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1799 const u32 fixed_kt, u16 v,
1800 u32 ileakage, u32 *leakage)
1801 {
1802 s64 kt, kv, leakage_w, i_leakage, vddc;
1803
1804 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1805 vddc = div64_s64(drm_int2fixp(v), 1000);
1806
1807 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1808 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1809 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1810
1811 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1812
1813 *leakage = drm_fixp2int(leakage_w * 1000);
1814 }
1815
1816 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1817 const struct ni_leakage_coeffients *coeff,
1818 const u32 fixed_kt,
1819 u16 v,
1820 u32 i_leakage,
1821 u32 *leakage)
1822 {
1823 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1824 }
1825
1826
1827 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1828 struct si_dte_data *dte_data)
1829 {
1830 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1831 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1832 u32 k = dte_data->k;
1833 u32 t_max = dte_data->max_t;
1834 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1835 u32 t_0 = dte_data->t0;
1836 u32 i;
1837
1838 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1839 dte_data->tdep_count = 3;
1840
1841 for (i = 0; i < k; i++) {
1842 dte_data->r[i] =
1843 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1844 (p_limit2 * (u32)100);
1845 }
1846
1847 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1848
1849 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1850 dte_data->tdep_r[i] = dte_data->r[4];
1851 }
1852 } else {
1853 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1854 }
1855 }
1856
1857 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1858 {
1859 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1860 struct si_power_info *si_pi = si_get_pi(rdev);
1861 bool update_dte_from_pl2 = false;
1862
1863 if (rdev->family == CHIP_TAHITI) {
1864 si_pi->cac_weights = cac_weights_tahiti;
1865 si_pi->lcac_config = lcac_tahiti;
1866 si_pi->cac_override = cac_override_tahiti;
1867 si_pi->powertune_data = &powertune_data_tahiti;
1868 si_pi->dte_data = dte_data_tahiti;
1869
1870 switch (rdev->pdev->device) {
1871 case 0x6798:
1872 si_pi->dte_data.enable_dte_by_default = true;
1873 break;
1874 case 0x6799:
1875 si_pi->dte_data = dte_data_new_zealand;
1876 break;
1877 case 0x6790:
1878 case 0x6791:
1879 case 0x6792:
1880 case 0x679E:
1881 si_pi->dte_data = dte_data_aruba_pro;
1882 update_dte_from_pl2 = true;
1883 break;
1884 case 0x679B:
1885 si_pi->dte_data = dte_data_malta;
1886 update_dte_from_pl2 = true;
1887 break;
1888 case 0x679A:
1889 si_pi->dte_data = dte_data_tahiti_pro;
1890 update_dte_from_pl2 = true;
1891 break;
1892 default:
1893 if (si_pi->dte_data.enable_dte_by_default == true)
1894 DRM_ERROR("DTE is not enabled!\n");
1895 break;
1896 }
1897 } else if (rdev->family == CHIP_PITCAIRN) {
1898 switch (rdev->pdev->device) {
1899 case 0x6810:
1900 case 0x6818:
1901 si_pi->cac_weights = cac_weights_pitcairn;
1902 si_pi->lcac_config = lcac_pitcairn;
1903 si_pi->cac_override = cac_override_pitcairn;
1904 si_pi->powertune_data = &powertune_data_pitcairn;
1905 si_pi->dte_data = dte_data_curacao_xt;
1906 update_dte_from_pl2 = true;
1907 break;
1908 case 0x6819:
1909 case 0x6811:
1910 si_pi->cac_weights = cac_weights_pitcairn;
1911 si_pi->lcac_config = lcac_pitcairn;
1912 si_pi->cac_override = cac_override_pitcairn;
1913 si_pi->powertune_data = &powertune_data_pitcairn;
1914 si_pi->dte_data = dte_data_curacao_pro;
1915 update_dte_from_pl2 = true;
1916 break;
1917 case 0x6800:
1918 case 0x6806:
1919 si_pi->cac_weights = cac_weights_pitcairn;
1920 si_pi->lcac_config = lcac_pitcairn;
1921 si_pi->cac_override = cac_override_pitcairn;
1922 si_pi->powertune_data = &powertune_data_pitcairn;
1923 si_pi->dte_data = dte_data_neptune_xt;
1924 update_dte_from_pl2 = true;
1925 break;
1926 default:
1927 si_pi->cac_weights = cac_weights_pitcairn;
1928 si_pi->lcac_config = lcac_pitcairn;
1929 si_pi->cac_override = cac_override_pitcairn;
1930 si_pi->powertune_data = &powertune_data_pitcairn;
1931 si_pi->dte_data = dte_data_pitcairn;
1932 break;
1933 }
1934 } else if (rdev->family == CHIP_VERDE) {
1935 si_pi->lcac_config = lcac_cape_verde;
1936 si_pi->cac_override = cac_override_cape_verde;
1937 si_pi->powertune_data = &powertune_data_cape_verde;
1938
1939 switch (rdev->pdev->device) {
1940 case 0x683B:
1941 case 0x683F:
1942 case 0x6829:
1943 case 0x6835:
1944 si_pi->cac_weights = cac_weights_cape_verde_pro;
1945 si_pi->dte_data = dte_data_cape_verde;
1946 break;
1947 case 0x6825:
1948 case 0x6827:
1949 si_pi->cac_weights = cac_weights_heathrow;
1950 si_pi->dte_data = dte_data_cape_verde;
1951 break;
1952 case 0x6824:
1953 case 0x682D:
1954 si_pi->cac_weights = cac_weights_chelsea_xt;
1955 si_pi->dte_data = dte_data_cape_verde;
1956 break;
1957 case 0x682F:
1958 si_pi->cac_weights = cac_weights_chelsea_pro;
1959 si_pi->dte_data = dte_data_cape_verde;
1960 break;
1961 case 0x6820:
1962 si_pi->cac_weights = cac_weights_heathrow;
1963 si_pi->dte_data = dte_data_venus_xtx;
1964 break;
1965 case 0x6821:
1966 si_pi->cac_weights = cac_weights_heathrow;
1967 si_pi->dte_data = dte_data_venus_xt;
1968 break;
1969 case 0x6823:
1970 si_pi->cac_weights = cac_weights_chelsea_pro;
1971 si_pi->dte_data = dte_data_venus_pro;
1972 break;
1973 case 0x682B:
1974 si_pi->cac_weights = cac_weights_chelsea_pro;
1975 si_pi->dte_data = dte_data_venus_pro;
1976 break;
1977 default:
1978 si_pi->cac_weights = cac_weights_cape_verde;
1979 si_pi->dte_data = dte_data_cape_verde;
1980 break;
1981 }
1982 } else if (rdev->family == CHIP_OLAND) {
1983 switch (rdev->pdev->device) {
1984 case 0x6601:
1985 case 0x6621:
1986 case 0x6603:
1987 si_pi->cac_weights = cac_weights_mars_pro;
1988 si_pi->lcac_config = lcac_mars_pro;
1989 si_pi->cac_override = cac_override_oland;
1990 si_pi->powertune_data = &powertune_data_mars_pro;
1991 si_pi->dte_data = dte_data_mars_pro;
1992 update_dte_from_pl2 = true;
1993 break;
1994 case 0x6600:
1995 case 0x6606:
1996 case 0x6620:
1997 si_pi->cac_weights = cac_weights_mars_xt;
1998 si_pi->lcac_config = lcac_mars_pro;
1999 si_pi->cac_override = cac_override_oland;
2000 si_pi->powertune_data = &powertune_data_mars_pro;
2001 si_pi->dte_data = dte_data_mars_pro;
2002 update_dte_from_pl2 = true;
2003 break;
2004 case 0x6611:
2005 si_pi->cac_weights = cac_weights_oland_pro;
2006 si_pi->lcac_config = lcac_mars_pro;
2007 si_pi->cac_override = cac_override_oland;
2008 si_pi->powertune_data = &powertune_data_mars_pro;
2009 si_pi->dte_data = dte_data_mars_pro;
2010 update_dte_from_pl2 = true;
2011 break;
2012 case 0x6610:
2013 si_pi->cac_weights = cac_weights_oland_xt;
2014 si_pi->lcac_config = lcac_mars_pro;
2015 si_pi->cac_override = cac_override_oland;
2016 si_pi->powertune_data = &powertune_data_mars_pro;
2017 si_pi->dte_data = dte_data_mars_pro;
2018 update_dte_from_pl2 = true;
2019 break;
2020 default:
2021 si_pi->cac_weights = cac_weights_oland;
2022 si_pi->lcac_config = lcac_oland;
2023 si_pi->cac_override = cac_override_oland;
2024 si_pi->powertune_data = &powertune_data_oland;
2025 si_pi->dte_data = dte_data_oland;
2026 break;
2027 }
2028 } else if (rdev->family == CHIP_HAINAN) {
2029 si_pi->cac_weights = cac_weights_hainan;
2030 si_pi->lcac_config = lcac_oland;
2031 si_pi->cac_override = cac_override_oland;
2032 si_pi->powertune_data = &powertune_data_hainan;
2033 si_pi->dte_data = dte_data_sun_xt;
2034 update_dte_from_pl2 = true;
2035 } else {
2036 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2037 return;
2038 }
2039
2040 ni_pi->enable_power_containment = false;
2041 ni_pi->enable_cac = false;
2042 ni_pi->enable_sq_ramping = false;
2043 si_pi->enable_dte = false;
2044
2045 /* XXX: fix me */
2046 if (0/*si_pi->powertune_data->enable_powertune_by_default*/) {
2047 ni_pi->enable_power_containment= true;
2048 ni_pi->enable_cac = true;
2049 if (si_pi->dte_data.enable_dte_by_default) {
2050 si_pi->enable_dte = true;
2051 if (update_dte_from_pl2)
2052 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2053
2054 }
2055 ni_pi->enable_sq_ramping = true;
2056 }
2057
2058 ni_pi->driver_calculate_cac_leakage = true;
2059 ni_pi->cac_configuration_required = true;
2060
2061 if (ni_pi->cac_configuration_required) {
2062 ni_pi->support_cac_long_term_average = true;
2063 si_pi->dyn_powertune_data.l2_lta_window_size =
2064 si_pi->powertune_data->l2_lta_window_size_default;
2065 si_pi->dyn_powertune_data.lts_truncate =
2066 si_pi->powertune_data->lts_truncate_default;
2067 } else {
2068 ni_pi->support_cac_long_term_average = false;
2069 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2070 si_pi->dyn_powertune_data.lts_truncate = 0;
2071 }
2072
2073 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2074 }
2075
2076 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2077 {
2078 return 1;
2079 }
2080
2081 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2082 {
2083 u32 xclk;
2084 u32 wintime;
2085 u32 cac_window;
2086 u32 cac_window_size;
2087
2088 xclk = radeon_get_xclk(rdev);
2089
2090 if (xclk == 0)
2091 return 0;
2092
2093 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2094 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2095
2096 wintime = (cac_window_size * 100) / xclk;
2097
2098 return wintime;
2099 }
2100
2101 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2102 {
2103 return power_in_watts;
2104 }
2105
2106 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2107 bool adjust_polarity,
2108 u32 tdp_adjustment,
2109 u32 *tdp_limit,
2110 u32 *near_tdp_limit)
2111 {
2112 u32 adjustment_delta, max_tdp_limit;
2113
2114 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2115 return -EINVAL;
2116
2117 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2118
2119 if (adjust_polarity) {
2120 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2121 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2122 } else {
2123 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2124 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2125 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2126 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2127 else
2128 *near_tdp_limit = 0;
2129 }
2130
2131 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2132 return -EINVAL;
2133 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2134 return -EINVAL;
2135
2136 return 0;
2137 }
2138
2139 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2140 struct radeon_ps *radeon_state)
2141 {
2142 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2143 struct si_power_info *si_pi = si_get_pi(rdev);
2144
2145 if (ni_pi->enable_power_containment) {
2146 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2147 PP_SIslands_PAPMParameters *papm_parm;
2148 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2149 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2150 u32 tdp_limit;
2151 u32 near_tdp_limit;
2152 int ret;
2153
2154 if (scaling_factor == 0)
2155 return -EINVAL;
2156
2157 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2158
2159 ret = si_calculate_adjusted_tdp_limits(rdev,
2160 false, /* ??? */
2161 rdev->pm.dpm.tdp_adjustment,
2162 &tdp_limit,
2163 &near_tdp_limit);
2164 if (ret)
2165 return ret;
2166
2167 smc_table->dpm2Params.TDPLimit =
2168 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2169 smc_table->dpm2Params.NearTDPLimit =
2170 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2171 smc_table->dpm2Params.SafePowerLimit =
2172 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2173
2174 ret = si_copy_bytes_to_smc(rdev,
2175 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2176 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2177 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2178 sizeof(u32) * 3,
2179 si_pi->sram_end);
2180 if (ret)
2181 return ret;
2182
2183 if (si_pi->enable_ppm) {
2184 papm_parm = &si_pi->papm_parm;
2185 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2186 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2187 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2188 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2189 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2190 papm_parm->PlatformPowerLimit = 0xffffffff;
2191 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2192
2193 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2194 (u8 *)papm_parm,
2195 sizeof(PP_SIslands_PAPMParameters),
2196 si_pi->sram_end);
2197 if (ret)
2198 return ret;
2199 }
2200 }
2201 return 0;
2202 }
2203
2204 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2205 struct radeon_ps *radeon_state)
2206 {
2207 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2208 struct si_power_info *si_pi = si_get_pi(rdev);
2209
2210 if (ni_pi->enable_power_containment) {
2211 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2212 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2213 int ret;
2214
2215 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2216
2217 smc_table->dpm2Params.NearTDPLimit =
2218 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2219 smc_table->dpm2Params.SafePowerLimit =
2220 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2221
2222 ret = si_copy_bytes_to_smc(rdev,
2223 (si_pi->state_table_start +
2224 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2225 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2226 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2227 sizeof(u32) * 2,
2228 si_pi->sram_end);
2229 if (ret)
2230 return ret;
2231 }
2232
2233 return 0;
2234 }
2235
2236 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2237 const u16 prev_std_vddc,
2238 const u16 curr_std_vddc)
2239 {
2240 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2241 u64 prev_vddc = (u64)prev_std_vddc;
2242 u64 curr_vddc = (u64)curr_std_vddc;
2243 u64 pwr_efficiency_ratio, n, d;
2244
2245 if ((prev_vddc == 0) || (curr_vddc == 0))
2246 return 0;
2247
2248 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2249 d = prev_vddc * prev_vddc;
2250 pwr_efficiency_ratio = div64_u64(n, d);
2251
2252 if (pwr_efficiency_ratio > (u64)0xFFFF)
2253 return 0;
2254
2255 return (u16)pwr_efficiency_ratio;
2256 }
2257
2258 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2259 struct radeon_ps *radeon_state)
2260 {
2261 struct si_power_info *si_pi = si_get_pi(rdev);
2262
2263 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2264 radeon_state->vclk && radeon_state->dclk)
2265 return true;
2266
2267 return false;
2268 }
2269
2270 static int si_populate_power_containment_values(struct radeon_device *rdev,
2271 struct radeon_ps *radeon_state,
2272 SISLANDS_SMC_SWSTATE *smc_state)
2273 {
2274 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2275 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2276 struct ni_ps *state = ni_get_ps(radeon_state);
2277 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2278 u32 prev_sclk;
2279 u32 max_sclk;
2280 u32 min_sclk;
2281 u16 prev_std_vddc;
2282 u16 curr_std_vddc;
2283 int i;
2284 u16 pwr_efficiency_ratio;
2285 u8 max_ps_percent;
2286 bool disable_uvd_power_tune;
2287 int ret;
2288
2289 if (ni_pi->enable_power_containment == false)
2290 return 0;
2291
2292 if (state->performance_level_count == 0)
2293 return -EINVAL;
2294
2295 if (smc_state->levelCount != state->performance_level_count)
2296 return -EINVAL;
2297
2298 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2299
2300 smc_state->levels[0].dpm2.MaxPS = 0;
2301 smc_state->levels[0].dpm2.NearTDPDec = 0;
2302 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2303 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2304 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2305
2306 for (i = 1; i < state->performance_level_count; i++) {
2307 prev_sclk = state->performance_levels[i-1].sclk;
2308 max_sclk = state->performance_levels[i].sclk;
2309 if (i == 1)
2310 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2311 else
2312 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2313
2314 if (prev_sclk > max_sclk)
2315 return -EINVAL;
2316
2317 if ((max_ps_percent == 0) ||
2318 (prev_sclk == max_sclk) ||
2319 disable_uvd_power_tune) {
2320 min_sclk = max_sclk;
2321 } else if (i == 1) {
2322 min_sclk = prev_sclk;
2323 } else {
2324 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2325 }
2326
2327 if (min_sclk < state->performance_levels[0].sclk)
2328 min_sclk = state->performance_levels[0].sclk;
2329
2330 if (min_sclk == 0)
2331 return -EINVAL;
2332
2333 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2334 state->performance_levels[i-1].vddc, &vddc);
2335 if (ret)
2336 return ret;
2337
2338 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2339 if (ret)
2340 return ret;
2341
2342 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2343 state->performance_levels[i].vddc, &vddc);
2344 if (ret)
2345 return ret;
2346
2347 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2348 if (ret)
2349 return ret;
2350
2351 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2352 prev_std_vddc, curr_std_vddc);
2353
2354 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2355 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2356 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2357 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2358 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2359 }
2360
2361 return 0;
2362 }
2363
2364 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2365 struct radeon_ps *radeon_state,
2366 SISLANDS_SMC_SWSTATE *smc_state)
2367 {
2368 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2369 struct ni_ps *state = ni_get_ps(radeon_state);
2370 u32 sq_power_throttle, sq_power_throttle2;
2371 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2372 int i;
2373
2374 if (state->performance_level_count == 0)
2375 return -EINVAL;
2376
2377 if (smc_state->levelCount != state->performance_level_count)
2378 return -EINVAL;
2379
2380 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2381 return -EINVAL;
2382
2383 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2384 enable_sq_ramping = false;
2385
2386 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2387 enable_sq_ramping = false;
2388
2389 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2390 enable_sq_ramping = false;
2391
2392 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2393 enable_sq_ramping = false;
2394
2395 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2396 enable_sq_ramping = false;
2397
2398 for (i = 0; i < state->performance_level_count; i++) {
2399 sq_power_throttle = 0;
2400 sq_power_throttle2 = 0;
2401
2402 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2403 enable_sq_ramping) {
2404 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2405 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2406 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2407 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2408 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2409 } else {
2410 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2411 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2412 }
2413
2414 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2415 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2416 }
2417
2418 return 0;
2419 }
2420
2421 static int si_enable_power_containment(struct radeon_device *rdev,
2422 struct radeon_ps *radeon_new_state,
2423 bool enable)
2424 {
2425 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2426 PPSMC_Result smc_result;
2427 int ret = 0;
2428
2429 if (ni_pi->enable_power_containment) {
2430 if (enable) {
2431 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2432 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2433 if (smc_result != PPSMC_Result_OK) {
2434 ret = -EINVAL;
2435 ni_pi->pc_enabled = false;
2436 } else {
2437 ni_pi->pc_enabled = true;
2438 }
2439 }
2440 } else {
2441 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2442 if (smc_result != PPSMC_Result_OK)
2443 ret = -EINVAL;
2444 ni_pi->pc_enabled = false;
2445 }
2446 }
2447
2448 return ret;
2449 }
2450
2451 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2452 {
2453 struct si_power_info *si_pi = si_get_pi(rdev);
2454 int ret = 0;
2455 struct si_dte_data *dte_data = &si_pi->dte_data;
2456 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2457 u32 table_size;
2458 u8 tdep_count;
2459 u32 i;
2460
2461 if (dte_data == NULL)
2462 si_pi->enable_dte = false;
2463
2464 if (si_pi->enable_dte == false)
2465 return 0;
2466
2467 if (dte_data->k <= 0)
2468 return -EINVAL;
2469
2470 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2471 if (dte_tables == NULL) {
2472 si_pi->enable_dte = false;
2473 return -ENOMEM;
2474 }
2475
2476 table_size = dte_data->k;
2477
2478 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2479 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2480
2481 tdep_count = dte_data->tdep_count;
2482 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2483 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2484
2485 dte_tables->K = cpu_to_be32(table_size);
2486 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2487 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2488 dte_tables->WindowSize = dte_data->window_size;
2489 dte_tables->temp_select = dte_data->temp_select;
2490 dte_tables->DTE_mode = dte_data->dte_mode;
2491 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2492
2493 if (tdep_count > 0)
2494 table_size--;
2495
2496 for (i = 0; i < table_size; i++) {
2497 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2498 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2499 }
2500
2501 dte_tables->Tdep_count = tdep_count;
2502
2503 for (i = 0; i < (u32)tdep_count; i++) {
2504 dte_tables->T_limits[i] = dte_data->t_limits[i];
2505 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2506 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2507 }
2508
2509 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2510 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2511 kfree(dte_tables);
2512
2513 return ret;
2514 }
2515
2516 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2517 u16 *max, u16 *min)
2518 {
2519 struct si_power_info *si_pi = si_get_pi(rdev);
2520 struct radeon_cac_leakage_table *table =
2521 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2522 u32 i;
2523 u32 v0_loadline;
2524
2525
2526 if (table == NULL)
2527 return -EINVAL;
2528
2529 *max = 0;
2530 *min = 0xFFFF;
2531
2532 for (i = 0; i < table->count; i++) {
2533 if (table->entries[i].vddc > *max)
2534 *max = table->entries[i].vddc;
2535 if (table->entries[i].vddc < *min)
2536 *min = table->entries[i].vddc;
2537 }
2538
2539 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2540 return -EINVAL;
2541
2542 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2543
2544 if (v0_loadline > 0xFFFFUL)
2545 return -EINVAL;
2546
2547 *min = (u16)v0_loadline;
2548
2549 if ((*min > *max) || (*max == 0) || (*min == 0))
2550 return -EINVAL;
2551
2552 return 0;
2553 }
2554
2555 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2556 {
2557 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2558 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2559 }
2560
2561 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2562 PP_SIslands_CacConfig *cac_tables,
2563 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2564 u16 t0, u16 t_step)
2565 {
2566 struct si_power_info *si_pi = si_get_pi(rdev);
2567 u32 leakage;
2568 unsigned int i, j;
2569 s32 t;
2570 u32 smc_leakage;
2571 u32 scaling_factor;
2572 u16 voltage;
2573
2574 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2575
2576 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2577 t = (1000 * (i * t_step + t0));
2578
2579 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2580 voltage = vddc_max - (vddc_step * j);
2581
2582 si_calculate_leakage_for_v_and_t(rdev,
2583 &si_pi->powertune_data->leakage_coefficients,
2584 voltage,
2585 t,
2586 si_pi->dyn_powertune_data.cac_leakage,
2587 &leakage);
2588
2589 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2590
2591 if (smc_leakage > 0xFFFF)
2592 smc_leakage = 0xFFFF;
2593
2594 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2595 cpu_to_be16((u16)smc_leakage);
2596 }
2597 }
2598 return 0;
2599 }
2600
2601 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2602 PP_SIslands_CacConfig *cac_tables,
2603 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2604 {
2605 struct si_power_info *si_pi = si_get_pi(rdev);
2606 u32 leakage;
2607 unsigned int i, j;
2608 u32 smc_leakage;
2609 u32 scaling_factor;
2610 u16 voltage;
2611
2612 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2613
2614 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2615 voltage = vddc_max - (vddc_step * j);
2616
2617 si_calculate_leakage_for_v(rdev,
2618 &si_pi->powertune_data->leakage_coefficients,
2619 si_pi->powertune_data->fixed_kt,
2620 voltage,
2621 si_pi->dyn_powertune_data.cac_leakage,
2622 &leakage);
2623
2624 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2625
2626 if (smc_leakage > 0xFFFF)
2627 smc_leakage = 0xFFFF;
2628
2629 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2630 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2631 cpu_to_be16((u16)smc_leakage);
2632 }
2633 return 0;
2634 }
2635
2636 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2637 {
2638 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2639 struct si_power_info *si_pi = si_get_pi(rdev);
2640 PP_SIslands_CacConfig *cac_tables = NULL;
2641 u16 vddc_max, vddc_min, vddc_step;
2642 u16 t0, t_step;
2643 u32 load_line_slope, reg;
2644 int ret = 0;
2645 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2646
2647 if (ni_pi->enable_cac == false)
2648 return 0;
2649
2650 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2651 if (!cac_tables)
2652 return -ENOMEM;
2653
2654 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2655 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2656 WREG32(CG_CAC_CTRL, reg);
2657
2658 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2659 si_pi->dyn_powertune_data.dc_pwr_value =
2660 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2661 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2662 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2663
2664 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2665
2666 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2667 if (ret)
2668 goto done_free;
2669
2670 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2671 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2672 t_step = 4;
2673 t0 = 60;
2674
2675 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2676 ret = si_init_dte_leakage_table(rdev, cac_tables,
2677 vddc_max, vddc_min, vddc_step,
2678 t0, t_step);
2679 else
2680 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2681 vddc_max, vddc_min, vddc_step);
2682 if (ret)
2683 goto done_free;
2684
2685 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2686
2687 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2688 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2689 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2690 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2691 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2692 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2693 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2694 cac_tables->calculation_repeats = cpu_to_be32(2);
2695 cac_tables->dc_cac = cpu_to_be32(0);
2696 cac_tables->log2_PG_LKG_SCALE = 12;
2697 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2698 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2699 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2700
2701 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2702 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2703
2704 if (ret)
2705 goto done_free;
2706
2707 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2708
2709 done_free:
2710 if (ret) {
2711 ni_pi->enable_cac = false;
2712 ni_pi->enable_power_containment = false;
2713 }
2714
2715 kfree(cac_tables);
2716
2717 return 0;
2718 }
2719
2720 static int si_program_cac_config_registers(struct radeon_device *rdev,
2721 const struct si_cac_config_reg *cac_config_regs)
2722 {
2723 const struct si_cac_config_reg *config_regs = cac_config_regs;
2724 u32 data = 0, offset;
2725
2726 if (!config_regs)
2727 return -EINVAL;
2728
2729 while (config_regs->offset != 0xFFFFFFFF) {
2730 switch (config_regs->type) {
2731 case SISLANDS_CACCONFIG_CGIND:
2732 offset = SMC_CG_IND_START + config_regs->offset;
2733 if (offset < SMC_CG_IND_END)
2734 data = RREG32_SMC(offset);
2735 break;
2736 default:
2737 data = RREG32(config_regs->offset << 2);
2738 break;
2739 }
2740
2741 data &= ~config_regs->mask;
2742 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2743
2744 switch (config_regs->type) {
2745 case SISLANDS_CACCONFIG_CGIND:
2746 offset = SMC_CG_IND_START + config_regs->offset;
2747 if (offset < SMC_CG_IND_END)
2748 WREG32_SMC(offset, data);
2749 break;
2750 default:
2751 WREG32(config_regs->offset << 2, data);
2752 break;
2753 }
2754 config_regs++;
2755 }
2756 return 0;
2757 }
2758
2759 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2760 {
2761 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2762 struct si_power_info *si_pi = si_get_pi(rdev);
2763 int ret;
2764
2765 if ((ni_pi->enable_cac == false) ||
2766 (ni_pi->cac_configuration_required == false))
2767 return 0;
2768
2769 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2770 if (ret)
2771 return ret;
2772 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2773 if (ret)
2774 return ret;
2775 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2776 if (ret)
2777 return ret;
2778
2779 return 0;
2780 }
2781
2782 static int si_enable_smc_cac(struct radeon_device *rdev,
2783 struct radeon_ps *radeon_new_state,
2784 bool enable)
2785 {
2786 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2787 struct si_power_info *si_pi = si_get_pi(rdev);
2788 PPSMC_Result smc_result;
2789 int ret = 0;
2790
2791 if (ni_pi->enable_cac) {
2792 if (enable) {
2793 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2794 if (ni_pi->support_cac_long_term_average) {
2795 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2796 if (smc_result != PPSMC_Result_OK)
2797 ni_pi->support_cac_long_term_average = false;
2798 }
2799
2800 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2801 if (smc_result != PPSMC_Result_OK) {
2802 ret = -EINVAL;
2803 ni_pi->cac_enabled = false;
2804 } else {
2805 ni_pi->cac_enabled = true;
2806 }
2807
2808 if (si_pi->enable_dte) {
2809 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2810 if (smc_result != PPSMC_Result_OK)
2811 ret = -EINVAL;
2812 }
2813 }
2814 } else if (ni_pi->cac_enabled) {
2815 if (si_pi->enable_dte)
2816 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2817
2818 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2819
2820 ni_pi->cac_enabled = false;
2821
2822 if (ni_pi->support_cac_long_term_average)
2823 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2824 }
2825 }
2826 return ret;
2827 }
2828
2829 static int si_init_smc_spll_table(struct radeon_device *rdev)
2830 {
2831 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2832 struct si_power_info *si_pi = si_get_pi(rdev);
2833 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2834 SISLANDS_SMC_SCLK_VALUE sclk_params;
2835 u32 fb_div, p_div;
2836 u32 clk_s, clk_v;
2837 u32 sclk = 0;
2838 int ret = 0;
2839 u32 tmp;
2840 int i;
2841
2842 if (si_pi->spll_table_start == 0)
2843 return -EINVAL;
2844
2845 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2846 if (spll_table == NULL)
2847 return -ENOMEM;
2848
2849 for (i = 0; i < 256; i++) {
2850 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2851 if (ret)
2852 break;
2853
2854 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2855 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2856 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2857 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2858
2859 fb_div &= ~0x00001FFF;
2860 fb_div >>= 1;
2861 clk_v >>= 6;
2862
2863 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2864 ret = -EINVAL;
2865 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2866 ret = -EINVAL;
2867 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2868 ret = -EINVAL;
2869 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2870 ret = -EINVAL;
2871
2872 if (ret)
2873 break;
2874
2875 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2876 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2877 spll_table->freq[i] = cpu_to_be32(tmp);
2878
2879 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2880 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2881 spll_table->ss[i] = cpu_to_be32(tmp);
2882
2883 sclk += 512;
2884 }
2885
2886
2887 if (!ret)
2888 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2889 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2890 si_pi->sram_end);
2891
2892 if (ret)
2893 ni_pi->enable_power_containment = false;
2894
2895 kfree(spll_table);
2896
2897 return ret;
2898 }
2899
2900 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2901 struct radeon_ps *rps)
2902 {
2903 struct ni_ps *ps = ni_get_ps(rps);
2904 struct radeon_clock_and_voltage_limits *max_limits;
2905 bool disable_mclk_switching;
2906 u32 mclk, sclk;
2907 u16 vddc, vddci;
2908 int i;
2909
2910 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2911 ni_dpm_vblank_too_short(rdev))
2912 disable_mclk_switching = true;
2913 else
2914 disable_mclk_switching = false;
2915
2916 if (rdev->pm.dpm.ac_power)
2917 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2918 else
2919 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2920
2921 for (i = ps->performance_level_count - 2; i >= 0; i--) {
2922 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2923 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2924 }
2925 if (rdev->pm.dpm.ac_power == false) {
2926 for (i = 0; i < ps->performance_level_count; i++) {
2927 if (ps->performance_levels[i].mclk > max_limits->mclk)
2928 ps->performance_levels[i].mclk = max_limits->mclk;
2929 if (ps->performance_levels[i].sclk > max_limits->sclk)
2930 ps->performance_levels[i].sclk = max_limits->sclk;
2931 if (ps->performance_levels[i].vddc > max_limits->vddc)
2932 ps->performance_levels[i].vddc = max_limits->vddc;
2933 if (ps->performance_levels[i].vddci > max_limits->vddci)
2934 ps->performance_levels[i].vddci = max_limits->vddci;
2935 }
2936 }
2937
2938 /* XXX validate the min clocks required for display */
2939
2940 if (disable_mclk_switching) {
2941 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
2942 sclk = ps->performance_levels[0].sclk;
2943 vddc = ps->performance_levels[0].vddc;
2944 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
2945 } else {
2946 sclk = ps->performance_levels[0].sclk;
2947 mclk = ps->performance_levels[0].mclk;
2948 vddc = ps->performance_levels[0].vddc;
2949 vddci = ps->performance_levels[0].vddci;
2950 }
2951
2952 /* adjusted low state */
2953 ps->performance_levels[0].sclk = sclk;
2954 ps->performance_levels[0].mclk = mclk;
2955 ps->performance_levels[0].vddc = vddc;
2956 ps->performance_levels[0].vddci = vddci;
2957
2958 for (i = 1; i < ps->performance_level_count; i++) {
2959 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
2960 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
2961 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
2962 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
2963 }
2964
2965 if (disable_mclk_switching) {
2966 mclk = ps->performance_levels[0].mclk;
2967 for (i = 1; i < ps->performance_level_count; i++) {
2968 if (mclk < ps->performance_levels[i].mclk)
2969 mclk = ps->performance_levels[i].mclk;
2970 }
2971 for (i = 0; i < ps->performance_level_count; i++) {
2972 ps->performance_levels[i].mclk = mclk;
2973 ps->performance_levels[i].vddci = vddci;
2974 }
2975 } else {
2976 for (i = 1; i < ps->performance_level_count; i++) {
2977 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
2978 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
2979 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
2980 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
2981 }
2982 }
2983
2984 for (i = 0; i < ps->performance_level_count; i++)
2985 btc_adjust_clock_combinations(rdev, max_limits,
2986 &ps->performance_levels[i]);
2987
2988 for (i = 0; i < ps->performance_level_count; i++) {
2989 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2990 ps->performance_levels[i].sclk,
2991 max_limits->vddc, &ps->performance_levels[i].vddc);
2992 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2993 ps->performance_levels[i].mclk,
2994 max_limits->vddci, &ps->performance_levels[i].vddci);
2995 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2996 ps->performance_levels[i].mclk,
2997 max_limits->vddc, &ps->performance_levels[i].vddc);
2998 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2999 rdev->clock.current_dispclk,
3000 max_limits->vddc, &ps->performance_levels[i].vddc);
3001 }
3002
3003 for (i = 0; i < ps->performance_level_count; i++) {
3004 btc_apply_voltage_delta_rules(rdev,
3005 max_limits->vddc, max_limits->vddci,
3006 &ps->performance_levels[i].vddc,
3007 &ps->performance_levels[i].vddci);
3008 }
3009
3010 ps->dc_compatible = true;
3011 for (i = 0; i < ps->performance_level_count; i++) {
3012 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3013 ps->dc_compatible = false;
3014 }
3015
3016 }
3017
3018 #if 0
3019 static int si_read_smc_soft_register(struct radeon_device *rdev,
3020 u16 reg_offset, u32 *value)
3021 {
3022 struct si_power_info *si_pi = si_get_pi(rdev);
3023
3024 return si_read_smc_sram_dword(rdev,
3025 si_pi->soft_regs_start + reg_offset, value,
3026 si_pi->sram_end);
3027 }
3028 #endif
3029
3030 static int si_write_smc_soft_register(struct radeon_device *rdev,
3031 u16 reg_offset, u32 value)
3032 {
3033 struct si_power_info *si_pi = si_get_pi(rdev);
3034
3035 return si_write_smc_sram_dword(rdev,
3036 si_pi->soft_regs_start + reg_offset,
3037 value, si_pi->sram_end);
3038 }
3039
3040 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3041 {
3042 bool ret = false;
3043 u32 tmp, width, row, column, bank, density;
3044 bool is_memory_gddr5, is_special;
3045
3046 tmp = RREG32(MC_SEQ_MISC0);
3047 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3048 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3049 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3050
3051 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3052 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3053
3054 tmp = RREG32(MC_ARB_RAMCFG);
3055 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3056 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3057 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3058
3059 density = (1 << (row + column - 20 + bank)) * width;
3060
3061 if ((rdev->pdev->device == 0x6819) &&
3062 is_memory_gddr5 && is_special && (density == 0x400))
3063 ret = true;
3064
3065 return ret;
3066 }
3067
3068 static void si_get_leakage_vddc(struct radeon_device *rdev)
3069 {
3070 struct si_power_info *si_pi = si_get_pi(rdev);
3071 u16 vddc, count = 0;
3072 int i, ret;
3073
3074 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3075 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3076
3077 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3078 si_pi->leakage_voltage.entries[count].voltage = vddc;
3079 si_pi->leakage_voltage.entries[count].leakage_index =
3080 SISLANDS_LEAKAGE_INDEX0 + i;
3081 count++;
3082 }
3083 }
3084 si_pi->leakage_voltage.count = count;
3085 }
3086
3087 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3088 u32 index, u16 *leakage_voltage)
3089 {
3090 struct si_power_info *si_pi = si_get_pi(rdev);
3091 int i;
3092
3093 if (leakage_voltage == NULL)
3094 return -EINVAL;
3095
3096 if ((index & 0xff00) != 0xff00)
3097 return -EINVAL;
3098
3099 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3100 return -EINVAL;
3101
3102 if (index < SISLANDS_LEAKAGE_INDEX0)
3103 return -EINVAL;
3104
3105 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3106 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3107 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3108 return 0;
3109 }
3110 }
3111 return -EAGAIN;
3112 }
3113
3114 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3115 {
3116 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3117 bool want_thermal_protection;
3118 enum radeon_dpm_event_src dpm_event_src;
3119
3120 switch (sources) {
3121 case 0:
3122 default:
3123 want_thermal_protection = false;
3124 break;
3125 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3126 want_thermal_protection = true;
3127 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3128 break;
3129 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3130 want_thermal_protection = true;
3131 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3132 break;
3133 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3134 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3135 want_thermal_protection = true;
3136 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3137 break;
3138 }
3139
3140 if (want_thermal_protection) {
3141 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3142 if (pi->thermal_protection)
3143 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3144 } else {
3145 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3146 }
3147 }
3148
3149 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3150 enum radeon_dpm_auto_throttle_src source,
3151 bool enable)
3152 {
3153 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3154
3155 if (enable) {
3156 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3157 pi->active_auto_throttle_sources |= 1 << source;
3158 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3159 }
3160 } else {
3161 if (pi->active_auto_throttle_sources & (1 << source)) {
3162 pi->active_auto_throttle_sources &= ~(1 << source);
3163 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3164 }
3165 }
3166 }
3167
3168 static void si_start_dpm(struct radeon_device *rdev)
3169 {
3170 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3171 }
3172
3173 static void si_stop_dpm(struct radeon_device *rdev)
3174 {
3175 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3176 }
3177
3178 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3179 {
3180 if (enable)
3181 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3182 else
3183 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3184
3185 }
3186
3187 #if 0
3188 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3189 u32 thermal_level)
3190 {
3191 PPSMC_Result ret;
3192
3193 if (thermal_level == 0) {
3194 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3195 if (ret == PPSMC_Result_OK)
3196 return 0;
3197 else
3198 return -EINVAL;
3199 }
3200 return 0;
3201 }
3202
3203 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3204 {
3205 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3206 }
3207 #endif
3208
3209 #if 0
3210 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3211 {
3212 if (ac_power)
3213 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3214 0 : -EINVAL;
3215
3216 return 0;
3217 }
3218 #endif
3219
3220 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3221 PPSMC_Msg msg, u32 parameter)
3222 {
3223 WREG32(SMC_SCRATCH0, parameter);
3224 return si_send_msg_to_smc(rdev, msg);
3225 }
3226
3227 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3228 {
3229 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3230 return -EINVAL;
3231
3232 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3233 0 : -EINVAL;
3234 }
3235
3236 int si_dpm_force_performance_level(struct radeon_device *rdev,
3237 enum radeon_dpm_forced_level level)
3238 {
3239 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3240 struct ni_ps *ps = ni_get_ps(rps);
3241 u32 levels = ps->performance_level_count;
3242
3243 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3244 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3245 return -EINVAL;
3246
3247 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3248 return -EINVAL;
3249 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3250 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3251 return -EINVAL;
3252
3253 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3254 return -EINVAL;
3255 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3256 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3257 return -EINVAL;
3258
3259 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3260 return -EINVAL;
3261 }
3262
3263 rdev->pm.dpm.forced_level = level;
3264
3265 return 0;
3266 }
3267
3268 static int si_set_boot_state(struct radeon_device *rdev)
3269 {
3270 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3271 0 : -EINVAL;
3272 }
3273
3274 static int si_set_sw_state(struct radeon_device *rdev)
3275 {
3276 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3277 0 : -EINVAL;
3278 }
3279
3280 static int si_halt_smc(struct radeon_device *rdev)
3281 {
3282 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3283 return -EINVAL;
3284
3285 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3286 0 : -EINVAL;
3287 }
3288
3289 static int si_resume_smc(struct radeon_device *rdev)
3290 {
3291 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3292 return -EINVAL;
3293
3294 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3295 0 : -EINVAL;
3296 }
3297
3298 static void si_dpm_start_smc(struct radeon_device *rdev)
3299 {
3300 si_program_jump_on_start(rdev);
3301 si_start_smc(rdev);
3302 si_start_smc_clock(rdev);
3303 }
3304
3305 static void si_dpm_stop_smc(struct radeon_device *rdev)
3306 {
3307 si_reset_smc(rdev);
3308 si_stop_smc_clock(rdev);
3309 }
3310
3311 static int si_process_firmware_header(struct radeon_device *rdev)
3312 {
3313 struct si_power_info *si_pi = si_get_pi(rdev);
3314 u32 tmp;
3315 int ret;
3316
3317 ret = si_read_smc_sram_dword(rdev,
3318 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3319 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3320 &tmp, si_pi->sram_end);
3321 if (ret)
3322 return ret;
3323
3324 si_pi->state_table_start = tmp;
3325
3326 ret = si_read_smc_sram_dword(rdev,
3327 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3328 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3329 &tmp, si_pi->sram_end);
3330 if (ret)
3331 return ret;
3332
3333 si_pi->soft_regs_start = tmp;
3334
3335 ret = si_read_smc_sram_dword(rdev,
3336 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3337 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3338 &tmp, si_pi->sram_end);
3339 if (ret)
3340 return ret;
3341
3342 si_pi->mc_reg_table_start = tmp;
3343
3344 ret = si_read_smc_sram_dword(rdev,
3345 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3346 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3347 &tmp, si_pi->sram_end);
3348 if (ret)
3349 return ret;
3350
3351 si_pi->arb_table_start = tmp;
3352
3353 ret = si_read_smc_sram_dword(rdev,
3354 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3355 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3356 &tmp, si_pi->sram_end);
3357 if (ret)
3358 return ret;
3359
3360 si_pi->cac_table_start = tmp;
3361
3362 ret = si_read_smc_sram_dword(rdev,
3363 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3364 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3365 &tmp, si_pi->sram_end);
3366 if (ret)
3367 return ret;
3368
3369 si_pi->dte_table_start = tmp;
3370
3371 ret = si_read_smc_sram_dword(rdev,
3372 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3373 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3374 &tmp, si_pi->sram_end);
3375 if (ret)
3376 return ret;
3377
3378 si_pi->spll_table_start = tmp;
3379
3380 ret = si_read_smc_sram_dword(rdev,
3381 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3382 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3383 &tmp, si_pi->sram_end);
3384 if (ret)
3385 return ret;
3386
3387 si_pi->papm_cfg_table_start = tmp;
3388
3389 return ret;
3390 }
3391
3392 static void si_read_clock_registers(struct radeon_device *rdev)
3393 {
3394 struct si_power_info *si_pi = si_get_pi(rdev);
3395
3396 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3397 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3398 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3399 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3400 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3401 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3402 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3403 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3404 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3405 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3406 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3407 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3408 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3409 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3410 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3411 }
3412
3413 static void si_enable_thermal_protection(struct radeon_device *rdev,
3414 bool enable)
3415 {
3416 if (enable)
3417 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3418 else
3419 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3420 }
3421
3422 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3423 {
3424 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3425 }
3426
3427 #if 0
3428 static int si_enter_ulp_state(struct radeon_device *rdev)
3429 {
3430 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3431
3432 udelay(25000);
3433
3434 return 0;
3435 }
3436
3437 static int si_exit_ulp_state(struct radeon_device *rdev)
3438 {
3439 int i;
3440
3441 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3442
3443 udelay(7000);
3444
3445 for (i = 0; i < rdev->usec_timeout; i++) {
3446 if (RREG32(SMC_RESP_0) == 1)
3447 break;
3448 udelay(1000);
3449 }
3450
3451 return 0;
3452 }
3453 #endif
3454
3455 static int si_notify_smc_display_change(struct radeon_device *rdev,
3456 bool has_display)
3457 {
3458 PPSMC_Msg msg = has_display ?
3459 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3460
3461 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3462 0 : -EINVAL;
3463 }
3464
3465 static void si_program_response_times(struct radeon_device *rdev)
3466 {
3467 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3468 u32 vddc_dly, acpi_dly, vbi_dly;
3469 u32 reference_clock;
3470
3471 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3472
3473 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3474 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3475
3476 if (voltage_response_time == 0)
3477 voltage_response_time = 1000;
3478
3479 acpi_delay_time = 15000;
3480 vbi_time_out = 100000;
3481
3482 reference_clock = radeon_get_xclk(rdev);
3483
3484 vddc_dly = (voltage_response_time * reference_clock) / 100;
3485 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3486 vbi_dly = (vbi_time_out * reference_clock) / 100;
3487
3488 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3489 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3490 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3491 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3492 }
3493
3494 static void si_program_ds_registers(struct radeon_device *rdev)
3495 {
3496 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3497 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3498
3499 if (eg_pi->sclk_deep_sleep) {
3500 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3501 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3502 ~AUTOSCALE_ON_SS_CLEAR);
3503 }
3504 }
3505
3506 static void si_program_display_gap(struct radeon_device *rdev)
3507 {
3508 u32 tmp, pipe;
3509 int i;
3510
3511 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3512 if (rdev->pm.dpm.new_active_crtc_count > 0)
3513 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3514 else
3515 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3516
3517 if (rdev->pm.dpm.new_active_crtc_count > 1)
3518 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3519 else
3520 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3521
3522 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3523
3524 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3525 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3526
3527 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3528 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3529 /* find the first active crtc */
3530 for (i = 0; i < rdev->num_crtc; i++) {
3531 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3532 break;
3533 }
3534 if (i == rdev->num_crtc)
3535 pipe = 0;
3536 else
3537 pipe = i;
3538
3539 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3540 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3541 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3542 }
3543
3544 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3545 }
3546
3547 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3548 {
3549 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3550
3551 if (enable) {
3552 if (pi->sclk_ss)
3553 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3554 } else {
3555 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3556 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3557 }
3558 }
3559
3560 static void si_setup_bsp(struct radeon_device *rdev)
3561 {
3562 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3563 u32 xclk = radeon_get_xclk(rdev);
3564
3565 r600_calculate_u_and_p(pi->asi,
3566 xclk,
3567 16,
3568 &pi->bsp,
3569 &pi->bsu);
3570
3571 r600_calculate_u_and_p(pi->pasi,
3572 xclk,
3573 16,
3574 &pi->pbsp,
3575 &pi->pbsu);
3576
3577
3578 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3579 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3580
3581 WREG32(CG_BSP, pi->dsp);
3582 }
3583
3584 static void si_program_git(struct radeon_device *rdev)
3585 {
3586 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3587 }
3588
3589 static void si_program_tp(struct radeon_device *rdev)
3590 {
3591 int i;
3592 enum r600_td td = R600_TD_DFLT;
3593
3594 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3595 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3596
3597 if (td == R600_TD_AUTO)
3598 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3599 else
3600 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3601
3602 if (td == R600_TD_UP)
3603 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3604
3605 if (td == R600_TD_DOWN)
3606 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3607 }
3608
3609 static void si_program_tpp(struct radeon_device *rdev)
3610 {
3611 WREG32(CG_TPC, R600_TPC_DFLT);
3612 }
3613
3614 static void si_program_sstp(struct radeon_device *rdev)
3615 {
3616 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3617 }
3618
3619 static void si_enable_display_gap(struct radeon_device *rdev)
3620 {
3621 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3622
3623 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3624 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3625 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3626
3627 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3628 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3629 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3630 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3631 }
3632
3633 static void si_program_vc(struct radeon_device *rdev)
3634 {
3635 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3636
3637 WREG32(CG_FTV, pi->vrc);
3638 }
3639
3640 static void si_clear_vc(struct radeon_device *rdev)
3641 {
3642 WREG32(CG_FTV, 0);
3643 }
3644
3645 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3646 {
3647 u8 mc_para_index;
3648
3649 if (memory_clock < 10000)
3650 mc_para_index = 0;
3651 else if (memory_clock >= 80000)
3652 mc_para_index = 0x0f;
3653 else
3654 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3655 return mc_para_index;
3656 }
3657
3658 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3659 {
3660 u8 mc_para_index;
3661
3662 if (strobe_mode) {
3663 if (memory_clock < 12500)
3664 mc_para_index = 0x00;
3665 else if (memory_clock > 47500)
3666 mc_para_index = 0x0f;
3667 else
3668 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3669 } else {
3670 if (memory_clock < 65000)
3671 mc_para_index = 0x00;
3672 else if (memory_clock > 135000)
3673 mc_para_index = 0x0f;
3674 else
3675 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3676 }
3677 return mc_para_index;
3678 }
3679
3680 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3681 {
3682 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3683 bool strobe_mode = false;
3684 u8 result = 0;
3685
3686 if (mclk <= pi->mclk_strobe_mode_threshold)
3687 strobe_mode = true;
3688
3689 if (pi->mem_gddr5)
3690 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3691 else
3692 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3693
3694 if (strobe_mode)
3695 result |= SISLANDS_SMC_STROBE_ENABLE;
3696
3697 return result;
3698 }
3699
3700 static int si_upload_firmware(struct radeon_device *rdev)
3701 {
3702 struct si_power_info *si_pi = si_get_pi(rdev);
3703 int ret;
3704
3705 si_reset_smc(rdev);
3706 si_stop_smc_clock(rdev);
3707
3708 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3709
3710 return ret;
3711 }
3712
3713 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3714 const struct atom_voltage_table *table,
3715 const struct radeon_phase_shedding_limits_table *limits)
3716 {
3717 u32 data, num_bits, num_levels;
3718
3719 if ((table == NULL) || (limits == NULL))
3720 return false;
3721
3722 data = table->mask_low;
3723
3724 num_bits = hweight32(data);
3725
3726 if (num_bits == 0)
3727 return false;
3728
3729 num_levels = (1 << num_bits);
3730
3731 if (table->count != num_levels)
3732 return false;
3733
3734 if (limits->count != (num_levels - 1))
3735 return false;
3736
3737 return true;
3738 }
3739
3740 static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3741 struct atom_voltage_table *voltage_table)
3742 {
3743 unsigned int i, diff;
3744
3745 if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS)
3746 return;
3747
3748 diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS;
3749
3750 for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++)
3751 voltage_table->entries[i] = voltage_table->entries[i + diff];
3752
3753 voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS;
3754 }
3755
3756 static int si_construct_voltage_tables(struct radeon_device *rdev)
3757 {
3758 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3759 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3760 struct si_power_info *si_pi = si_get_pi(rdev);
3761 int ret;
3762
3763 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3764 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3765 if (ret)
3766 return ret;
3767
3768 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3769 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table);
3770
3771 if (eg_pi->vddci_control) {
3772 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3773 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3774 if (ret)
3775 return ret;
3776
3777 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3778 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table);
3779 }
3780
3781 if (pi->mvdd_control) {
3782 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3783 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3784
3785 if (ret) {
3786 pi->mvdd_control = false;
3787 return ret;
3788 }
3789
3790 if (si_pi->mvdd_voltage_table.count == 0) {
3791 pi->mvdd_control = false;
3792 return -EINVAL;
3793 }
3794
3795 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3796 si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table);
3797 }
3798
3799 if (si_pi->vddc_phase_shed_control) {
3800 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3801 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3802 if (ret)
3803 si_pi->vddc_phase_shed_control = false;
3804
3805 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3806 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3807 si_pi->vddc_phase_shed_control = false;
3808 }
3809
3810 return 0;
3811 }
3812
3813 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3814 const struct atom_voltage_table *voltage_table,
3815 SISLANDS_SMC_STATETABLE *table)
3816 {
3817 unsigned int i;
3818
3819 for (i = 0; i < voltage_table->count; i++)
3820 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3821 }
3822
3823 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3824 SISLANDS_SMC_STATETABLE *table)
3825 {
3826 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3827 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3828 struct si_power_info *si_pi = si_get_pi(rdev);
3829 u8 i;
3830
3831 if (eg_pi->vddc_voltage_table.count) {
3832 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3833 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3834 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3835
3836 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3837 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3838 table->maxVDDCIndexInPPTable = i;
3839 break;
3840 }
3841 }
3842 }
3843
3844 if (eg_pi->vddci_voltage_table.count) {
3845 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3846
3847 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3848 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3849 }
3850
3851
3852 if (si_pi->mvdd_voltage_table.count) {
3853 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3854
3855 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3856 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3857 }
3858
3859 if (si_pi->vddc_phase_shed_control) {
3860 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3861 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3862 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3863
3864 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3865 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3866
3867 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3868 (u32)si_pi->vddc_phase_shed_table.phase_delay);
3869 } else {
3870 si_pi->vddc_phase_shed_control = false;
3871 }
3872 }
3873
3874 return 0;
3875 }
3876
3877 static int si_populate_voltage_value(struct radeon_device *rdev,
3878 const struct atom_voltage_table *table,
3879 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3880 {
3881 unsigned int i;
3882
3883 for (i = 0; i < table->count; i++) {
3884 if (value <= table->entries[i].value) {
3885 voltage->index = (u8)i;
3886 voltage->value = cpu_to_be16(table->entries[i].value);
3887 break;
3888 }
3889 }
3890
3891 if (i >= table->count)
3892 return -EINVAL;
3893
3894 return 0;
3895 }
3896
3897 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
3898 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3899 {
3900 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3901 struct si_power_info *si_pi = si_get_pi(rdev);
3902
3903 if (pi->mvdd_control) {
3904 if (mclk <= pi->mvdd_split_frequency)
3905 voltage->index = 0;
3906 else
3907 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
3908
3909 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
3910 }
3911 return 0;
3912 }
3913
3914 static int si_get_std_voltage_value(struct radeon_device *rdev,
3915 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
3916 u16 *std_voltage)
3917 {
3918 u16 v_index;
3919 bool voltage_found = false;
3920 *std_voltage = be16_to_cpu(voltage->value);
3921
3922 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
3923 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
3924 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
3925 return -EINVAL;
3926
3927 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3928 if (be16_to_cpu(voltage->value) ==
3929 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3930 voltage_found = true;
3931 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3932 *std_voltage =
3933 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3934 else
3935 *std_voltage =
3936 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3937 break;
3938 }
3939 }
3940
3941 if (!voltage_found) {
3942 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3943 if (be16_to_cpu(voltage->value) <=
3944 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3945 voltage_found = true;
3946 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3947 *std_voltage =
3948 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3949 else
3950 *std_voltage =
3951 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3952 break;
3953 }
3954 }
3955 }
3956 } else {
3957 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3958 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
3959 }
3960 }
3961
3962 return 0;
3963 }
3964
3965 static int si_populate_std_voltage_value(struct radeon_device *rdev,
3966 u16 value, u8 index,
3967 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3968 {
3969 voltage->index = index;
3970 voltage->value = cpu_to_be16(value);
3971
3972 return 0;
3973 }
3974
3975 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
3976 const struct radeon_phase_shedding_limits_table *limits,
3977 u16 voltage, u32 sclk, u32 mclk,
3978 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
3979 {
3980 unsigned int i;
3981
3982 for (i = 0; i < limits->count; i++) {
3983 if ((voltage <= limits->entries[i].voltage) &&
3984 (sclk <= limits->entries[i].sclk) &&
3985 (mclk <= limits->entries[i].mclk))
3986 break;
3987 }
3988
3989 smc_voltage->phase_settings = (u8)i;
3990
3991 return 0;
3992 }
3993
3994 static int si_init_arb_table_index(struct radeon_device *rdev)
3995 {
3996 struct si_power_info *si_pi = si_get_pi(rdev);
3997 u32 tmp;
3998 int ret;
3999
4000 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4001 if (ret)
4002 return ret;
4003
4004 tmp &= 0x00FFFFFF;
4005 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4006
4007 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4008 }
4009
4010 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4011 {
4012 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4013 }
4014
4015 static int si_reset_to_default(struct radeon_device *rdev)
4016 {
4017 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4018 0 : -EINVAL;
4019 }
4020
4021 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4022 {
4023 struct si_power_info *si_pi = si_get_pi(rdev);
4024 u32 tmp;
4025 int ret;
4026
4027 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4028 &tmp, si_pi->sram_end);
4029 if (ret)
4030 return ret;
4031
4032 tmp = (tmp >> 24) & 0xff;
4033
4034 if (tmp == MC_CG_ARB_FREQ_F0)
4035 return 0;
4036
4037 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4038 }
4039
4040 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4041 u32 engine_clock)
4042 {
4043 u32 dram_rows;
4044 u32 dram_refresh_rate;
4045 u32 mc_arb_rfsh_rate;
4046 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4047
4048 if (tmp >= 4)
4049 dram_rows = 16384;
4050 else
4051 dram_rows = 1 << (tmp + 10);
4052
4053 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4054 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4055
4056 return mc_arb_rfsh_rate;
4057 }
4058
4059 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4060 struct rv7xx_pl *pl,
4061 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4062 {
4063 u32 dram_timing;
4064 u32 dram_timing2;
4065 u32 burst_time;
4066
4067 arb_regs->mc_arb_rfsh_rate =
4068 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4069
4070 radeon_atom_set_engine_dram_timings(rdev,
4071 pl->sclk,
4072 pl->mclk);
4073
4074 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4075 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4076 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4077
4078 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4079 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4080 arb_regs->mc_arb_burst_time = (u8)burst_time;
4081
4082 return 0;
4083 }
4084
4085 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4086 struct radeon_ps *radeon_state,
4087 unsigned int first_arb_set)
4088 {
4089 struct si_power_info *si_pi = si_get_pi(rdev);
4090 struct ni_ps *state = ni_get_ps(radeon_state);
4091 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4092 int i, ret = 0;
4093
4094 for (i = 0; i < state->performance_level_count; i++) {
4095 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4096 if (ret)
4097 break;
4098 ret = si_copy_bytes_to_smc(rdev,
4099 si_pi->arb_table_start +
4100 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4101 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4102 (u8 *)&arb_regs,
4103 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4104 si_pi->sram_end);
4105 if (ret)
4106 break;
4107 }
4108
4109 return ret;
4110 }
4111
4112 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4113 struct radeon_ps *radeon_new_state)
4114 {
4115 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4116 SISLANDS_DRIVER_STATE_ARB_INDEX);
4117 }
4118
4119 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4120 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4121 {
4122 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4123 struct si_power_info *si_pi = si_get_pi(rdev);
4124
4125 if (pi->mvdd_control)
4126 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4127 si_pi->mvdd_bootup_value, voltage);
4128
4129 return 0;
4130 }
4131
4132 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4133 struct radeon_ps *radeon_initial_state,
4134 SISLANDS_SMC_STATETABLE *table)
4135 {
4136 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4137 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4138 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4139 struct si_power_info *si_pi = si_get_pi(rdev);
4140 u32 reg;
4141 int ret;
4142
4143 table->initialState.levels[0].mclk.vDLL_CNTL =
4144 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4145 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4146 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4147 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4148 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4149 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4150 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4151 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4152 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4153 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4154 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4155 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4156 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4157 table->initialState.levels[0].mclk.vMPLL_SS =
4158 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4159 table->initialState.levels[0].mclk.vMPLL_SS2 =
4160 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4161
4162 table->initialState.levels[0].mclk.mclk_value =
4163 cpu_to_be32(initial_state->performance_levels[0].mclk);
4164
4165 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4166 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4167 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4168 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4169 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4170 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4171 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4172 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4173 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4174 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4175 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4176 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4177
4178 table->initialState.levels[0].sclk.sclk_value =
4179 cpu_to_be32(initial_state->performance_levels[0].sclk);
4180
4181 table->initialState.levels[0].arbRefreshState =
4182 SISLANDS_INITIAL_STATE_ARB_INDEX;
4183
4184 table->initialState.levels[0].ACIndex = 0;
4185
4186 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4187 initial_state->performance_levels[0].vddc,
4188 &table->initialState.levels[0].vddc);
4189
4190 if (!ret) {
4191 u16 std_vddc;
4192
4193 ret = si_get_std_voltage_value(rdev,
4194 &table->initialState.levels[0].vddc,
4195 &std_vddc);
4196 if (!ret)
4197 si_populate_std_voltage_value(rdev, std_vddc,
4198 table->initialState.levels[0].vddc.index,
4199 &table->initialState.levels[0].std_vddc);
4200 }
4201
4202 if (eg_pi->vddci_control)
4203 si_populate_voltage_value(rdev,
4204 &eg_pi->vddci_voltage_table,
4205 initial_state->performance_levels[0].vddci,
4206 &table->initialState.levels[0].vddci);
4207
4208 if (si_pi->vddc_phase_shed_control)
4209 si_populate_phase_shedding_value(rdev,
4210 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4211 initial_state->performance_levels[0].vddc,
4212 initial_state->performance_levels[0].sclk,
4213 initial_state->performance_levels[0].mclk,
4214 &table->initialState.levels[0].vddc);
4215
4216 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4217
4218 reg = CG_R(0xffff) | CG_L(0);
4219 table->initialState.levels[0].aT = cpu_to_be32(reg);
4220
4221 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4222
4223 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4224
4225 if (pi->mem_gddr5) {
4226 table->initialState.levels[0].strobeMode =
4227 si_get_strobe_mode_settings(rdev,
4228 initial_state->performance_levels[0].mclk);
4229
4230 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4231 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4232 else
4233 table->initialState.levels[0].mcFlags = 0;
4234 }
4235
4236 table->initialState.levelCount = 1;
4237
4238 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4239
4240 table->initialState.levels[0].dpm2.MaxPS = 0;
4241 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4242 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4243 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4244 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4245
4246 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4247 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4248
4249 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4250 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4251
4252 return 0;
4253 }
4254
4255 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4256 SISLANDS_SMC_STATETABLE *table)
4257 {
4258 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4259 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4260 struct si_power_info *si_pi = si_get_pi(rdev);
4261 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4262 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4263 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4264 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4265 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4266 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4267 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4268 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4269 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4270 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4271 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4272 u32 reg;
4273 int ret;
4274
4275 table->ACPIState = table->initialState;
4276
4277 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4278
4279 if (pi->acpi_vddc) {
4280 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4281 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4282 if (!ret) {
4283 u16 std_vddc;
4284
4285 ret = si_get_std_voltage_value(rdev,
4286 &table->ACPIState.levels[0].vddc, &std_vddc);
4287 if (!ret)
4288 si_populate_std_voltage_value(rdev, std_vddc,
4289 table->ACPIState.levels[0].vddc.index,
4290 &table->ACPIState.levels[0].std_vddc);
4291 }
4292 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4293
4294 if (si_pi->vddc_phase_shed_control) {
4295 si_populate_phase_shedding_value(rdev,
4296 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4297 pi->acpi_vddc,
4298 0,
4299 0,
4300 &table->ACPIState.levels[0].vddc);
4301 }
4302 } else {
4303 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4304 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4305 if (!ret) {
4306 u16 std_vddc;
4307
4308 ret = si_get_std_voltage_value(rdev,
4309 &table->ACPIState.levels[0].vddc, &std_vddc);
4310
4311 if (!ret)
4312 si_populate_std_voltage_value(rdev, std_vddc,
4313 table->ACPIState.levels[0].vddc.index,
4314 &table->ACPIState.levels[0].std_vddc);
4315 }
4316 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4317 si_pi->sys_pcie_mask,
4318 si_pi->boot_pcie_gen,
4319 RADEON_PCIE_GEN1);
4320
4321 if (si_pi->vddc_phase_shed_control)
4322 si_populate_phase_shedding_value(rdev,
4323 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4324 pi->min_vddc_in_table,
4325 0,
4326 0,
4327 &table->ACPIState.levels[0].vddc);
4328 }
4329
4330 if (pi->acpi_vddc) {
4331 if (eg_pi->acpi_vddci)
4332 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4333 eg_pi->acpi_vddci,
4334 &table->ACPIState.levels[0].vddci);
4335 }
4336
4337 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4338 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4339
4340 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4341
4342 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4343 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4344
4345 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4346 cpu_to_be32(dll_cntl);
4347 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4348 cpu_to_be32(mclk_pwrmgt_cntl);
4349 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4350 cpu_to_be32(mpll_ad_func_cntl);
4351 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4352 cpu_to_be32(mpll_dq_func_cntl);
4353 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4354 cpu_to_be32(mpll_func_cntl);
4355 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4356 cpu_to_be32(mpll_func_cntl_1);
4357 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4358 cpu_to_be32(mpll_func_cntl_2);
4359 table->ACPIState.levels[0].mclk.vMPLL_SS =
4360 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4361 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4362 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4363
4364 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4365 cpu_to_be32(spll_func_cntl);
4366 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4367 cpu_to_be32(spll_func_cntl_2);
4368 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4369 cpu_to_be32(spll_func_cntl_3);
4370 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4371 cpu_to_be32(spll_func_cntl_4);
4372
4373 table->ACPIState.levels[0].mclk.mclk_value = 0;
4374 table->ACPIState.levels[0].sclk.sclk_value = 0;
4375
4376 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4377
4378 if (eg_pi->dynamic_ac_timing)
4379 table->ACPIState.levels[0].ACIndex = 0;
4380
4381 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4382 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4383 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4384 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4385 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4386
4387 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4388 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4389
4390 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4391 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4392
4393 return 0;
4394 }
4395
4396 static int si_populate_ulv_state(struct radeon_device *rdev,
4397 SISLANDS_SMC_SWSTATE *state)
4398 {
4399 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4400 struct si_power_info *si_pi = si_get_pi(rdev);
4401 struct si_ulv_param *ulv = &si_pi->ulv;
4402 u32 sclk_in_sr = 1350; /* ??? */
4403 int ret;
4404
4405 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4406 &state->levels[0]);
4407 if (!ret) {
4408 if (eg_pi->sclk_deep_sleep) {
4409 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4410 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4411 else
4412 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4413 }
4414 if (ulv->one_pcie_lane_in_ulv)
4415 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4416 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4417 state->levels[0].ACIndex = 1;
4418 state->levels[0].std_vddc = state->levels[0].vddc;
4419 state->levelCount = 1;
4420
4421 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4422 }
4423
4424 return ret;
4425 }
4426
4427 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4428 {
4429 struct si_power_info *si_pi = si_get_pi(rdev);
4430 struct si_ulv_param *ulv = &si_pi->ulv;
4431 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4432 int ret;
4433
4434 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4435 &arb_regs);
4436 if (ret)
4437 return ret;
4438
4439 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4440 ulv->volt_change_delay);
4441
4442 ret = si_copy_bytes_to_smc(rdev,
4443 si_pi->arb_table_start +
4444 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4445 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4446 (u8 *)&arb_regs,
4447 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4448 si_pi->sram_end);
4449
4450 return ret;
4451 }
4452
4453 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4454 {
4455 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4456
4457 pi->mvdd_split_frequency = 30000;
4458 }
4459
4460 static int si_init_smc_table(struct radeon_device *rdev)
4461 {
4462 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4463 struct si_power_info *si_pi = si_get_pi(rdev);
4464 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4465 const struct si_ulv_param *ulv = &si_pi->ulv;
4466 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4467 int ret;
4468 u32 lane_width;
4469 u32 vr_hot_gpio;
4470
4471 si_populate_smc_voltage_tables(rdev, table);
4472
4473 switch (rdev->pm.int_thermal_type) {
4474 case THERMAL_TYPE_SI:
4475 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4476 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4477 break;
4478 case THERMAL_TYPE_NONE:
4479 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4480 break;
4481 default:
4482 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4483 break;
4484 }
4485
4486 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4487 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4488
4489 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4490 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4491 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4492 }
4493
4494 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4495 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4496
4497 if (pi->mem_gddr5)
4498 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4499
4500 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4501 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4502
4503 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4504 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4505 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4506 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4507 vr_hot_gpio);
4508 }
4509
4510 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4511 if (ret)
4512 return ret;
4513
4514 ret = si_populate_smc_acpi_state(rdev, table);
4515 if (ret)
4516 return ret;
4517
4518 table->driverState = table->initialState;
4519
4520 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4521 SISLANDS_INITIAL_STATE_ARB_INDEX);
4522 if (ret)
4523 return ret;
4524
4525 if (ulv->supported && ulv->pl.vddc) {
4526 ret = si_populate_ulv_state(rdev, &table->ULVState);
4527 if (ret)
4528 return ret;
4529
4530 ret = si_program_ulv_memory_timing_parameters(rdev);
4531 if (ret)
4532 return ret;
4533
4534 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4535 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4536
4537 lane_width = radeon_get_pcie_lanes(rdev);
4538 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4539 } else {
4540 table->ULVState = table->initialState;
4541 }
4542
4543 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4544 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4545 si_pi->sram_end);
4546 }
4547
4548 static int si_calculate_sclk_params(struct radeon_device *rdev,
4549 u32 engine_clock,
4550 SISLANDS_SMC_SCLK_VALUE *sclk)
4551 {
4552 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4553 struct si_power_info *si_pi = si_get_pi(rdev);
4554 struct atom_clock_dividers dividers;
4555 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4556 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4557 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4558 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4559 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4560 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4561 u64 tmp;
4562 u32 reference_clock = rdev->clock.spll.reference_freq;
4563 u32 reference_divider;
4564 u32 fbdiv;
4565 int ret;
4566
4567 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4568 engine_clock, false, &dividers);
4569 if (ret)
4570 return ret;
4571
4572 reference_divider = 1 + dividers.ref_div;
4573
4574 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4575 do_div(tmp, reference_clock);
4576 fbdiv = (u32) tmp;
4577
4578 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4579 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4580 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4581
4582 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4583 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4584
4585 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4586 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4587 spll_func_cntl_3 |= SPLL_DITHEN;
4588
4589 if (pi->sclk_ss) {
4590 struct radeon_atom_ss ss;
4591 u32 vco_freq = engine_clock * dividers.post_div;
4592
4593 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4594 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4595 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4596 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4597
4598 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4599 cg_spll_spread_spectrum |= CLK_S(clk_s);
4600 cg_spll_spread_spectrum |= SSEN;
4601
4602 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4603 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4604 }
4605 }
4606
4607 sclk->sclk_value = engine_clock;
4608 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4609 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4610 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4611 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4612 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4613 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4614
4615 return 0;
4616 }
4617
4618 static int si_populate_sclk_value(struct radeon_device *rdev,
4619 u32 engine_clock,
4620 SISLANDS_SMC_SCLK_VALUE *sclk)
4621 {
4622 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4623 int ret;
4624
4625 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4626 if (!ret) {
4627 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4628 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4629 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4630 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4631 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4632 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4633 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4634 }
4635
4636 return ret;
4637 }
4638
4639 static int si_populate_mclk_value(struct radeon_device *rdev,
4640 u32 engine_clock,
4641 u32 memory_clock,
4642 SISLANDS_SMC_MCLK_VALUE *mclk,
4643 bool strobe_mode,
4644 bool dll_state_on)
4645 {
4646 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4647 struct si_power_info *si_pi = si_get_pi(rdev);
4648 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4649 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4650 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4651 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4652 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4653 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4654 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4655 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4656 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4657 struct atom_mpll_param mpll_param;
4658 int ret;
4659
4660 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4661 if (ret)
4662 return ret;
4663
4664 mpll_func_cntl &= ~BWCTRL_MASK;
4665 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4666
4667 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4668 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4669 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4670
4671 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4672 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4673
4674 if (pi->mem_gddr5) {
4675 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4676 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4677 YCLK_POST_DIV(mpll_param.post_div);
4678 }
4679
4680 if (pi->mclk_ss) {
4681 struct radeon_atom_ss ss;
4682 u32 freq_nom;
4683 u32 tmp;
4684 u32 reference_clock = rdev->clock.mpll.reference_freq;
4685
4686 if (pi->mem_gddr5)
4687 freq_nom = memory_clock * 4;
4688 else
4689 freq_nom = memory_clock * 2;
4690
4691 tmp = freq_nom / reference_clock;
4692 tmp = tmp * tmp;
4693 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4694 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4695 u32 clks = reference_clock * 5 / ss.rate;
4696 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4697
4698 mpll_ss1 &= ~CLKV_MASK;
4699 mpll_ss1 |= CLKV(clkv);
4700
4701 mpll_ss2 &= ~CLKS_MASK;
4702 mpll_ss2 |= CLKS(clks);
4703 }
4704 }
4705
4706 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4707 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4708
4709 if (dll_state_on)
4710 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4711 else
4712 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4713
4714 mclk->mclk_value = cpu_to_be32(memory_clock);
4715 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4716 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4717 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4718 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4719 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4720 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4721 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4722 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4723 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4724
4725 return 0;
4726 }
4727
4728 static void si_populate_smc_sp(struct radeon_device *rdev,
4729 struct radeon_ps *radeon_state,
4730 SISLANDS_SMC_SWSTATE *smc_state)
4731 {
4732 struct ni_ps *ps = ni_get_ps(radeon_state);
4733 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4734 int i;
4735
4736 for (i = 0; i < ps->performance_level_count - 1; i++)
4737 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4738
4739 smc_state->levels[ps->performance_level_count - 1].bSP =
4740 cpu_to_be32(pi->psp);
4741 }
4742
4743 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4744 struct rv7xx_pl *pl,
4745 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4746 {
4747 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4748 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4749 struct si_power_info *si_pi = si_get_pi(rdev);
4750 int ret;
4751 bool dll_state_on;
4752 u16 std_vddc;
4753 bool gmc_pg = false;
4754
4755 if (eg_pi->pcie_performance_request &&
4756 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4757 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4758 else
4759 level->gen2PCIE = (u8)pl->pcie_gen;
4760
4761 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4762 if (ret)
4763 return ret;
4764
4765 level->mcFlags = 0;
4766
4767 if (pi->mclk_stutter_mode_threshold &&
4768 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4769 !eg_pi->uvd_enabled &&
4770 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4771 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4772 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4773
4774 if (gmc_pg)
4775 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4776 }
4777
4778 if (pi->mem_gddr5) {
4779 if (pl->mclk > pi->mclk_edc_enable_threshold)
4780 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4781
4782 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4783 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4784
4785 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4786
4787 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4788 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4789 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4790 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4791 else
4792 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4793 } else {
4794 dll_state_on = false;
4795 }
4796 } else {
4797 level->strobeMode = si_get_strobe_mode_settings(rdev,
4798 pl->mclk);
4799
4800 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4801 }
4802
4803 ret = si_populate_mclk_value(rdev,
4804 pl->sclk,
4805 pl->mclk,
4806 &level->mclk,
4807 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4808 if (ret)
4809 return ret;
4810
4811 ret = si_populate_voltage_value(rdev,
4812 &eg_pi->vddc_voltage_table,
4813 pl->vddc, &level->vddc);
4814 if (ret)
4815 return ret;
4816
4817
4818 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4819 if (ret)
4820 return ret;
4821
4822 ret = si_populate_std_voltage_value(rdev, std_vddc,
4823 level->vddc.index, &level->std_vddc);
4824 if (ret)
4825 return ret;
4826
4827 if (eg_pi->vddci_control) {
4828 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4829 pl->vddci, &level->vddci);
4830 if (ret)
4831 return ret;
4832 }
4833
4834 if (si_pi->vddc_phase_shed_control) {
4835 ret = si_populate_phase_shedding_value(rdev,
4836 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4837 pl->vddc,
4838 pl->sclk,
4839 pl->mclk,
4840 &level->vddc);
4841 if (ret)
4842 return ret;
4843 }
4844
4845 level->MaxPoweredUpCU = si_pi->max_cu;
4846
4847 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4848
4849 return ret;
4850 }
4851
4852 static int si_populate_smc_t(struct radeon_device *rdev,
4853 struct radeon_ps *radeon_state,
4854 SISLANDS_SMC_SWSTATE *smc_state)
4855 {
4856 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4857 struct ni_ps *state = ni_get_ps(radeon_state);
4858 u32 a_t;
4859 u32 t_l, t_h;
4860 u32 high_bsp;
4861 int i, ret;
4862
4863 if (state->performance_level_count >= 9)
4864 return -EINVAL;
4865
4866 if (state->performance_level_count < 2) {
4867 a_t = CG_R(0xffff) | CG_L(0);
4868 smc_state->levels[0].aT = cpu_to_be32(a_t);
4869 return 0;
4870 }
4871
4872 smc_state->levels[0].aT = cpu_to_be32(0);
4873
4874 for (i = 0; i <= state->performance_level_count - 2; i++) {
4875 ret = r600_calculate_at(
4876 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4877 100 * R600_AH_DFLT,
4878 state->performance_levels[i + 1].sclk,
4879 state->performance_levels[i].sclk,
4880 &t_l,
4881 &t_h);
4882
4883 if (ret) {
4884 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4885 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
4886 }
4887
4888 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
4889 a_t |= CG_R(t_l * pi->bsp / 20000);
4890 smc_state->levels[i].aT = cpu_to_be32(a_t);
4891
4892 high_bsp = (i == state->performance_level_count - 2) ?
4893 pi->pbsp : pi->bsp;
4894 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
4895 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
4896 }
4897
4898 return 0;
4899 }
4900
4901 static int si_disable_ulv(struct radeon_device *rdev)
4902 {
4903 struct si_power_info *si_pi = si_get_pi(rdev);
4904 struct si_ulv_param *ulv = &si_pi->ulv;
4905
4906 if (ulv->supported)
4907 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
4908 0 : -EINVAL;
4909
4910 return 0;
4911 }
4912
4913 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
4914 struct radeon_ps *radeon_state)
4915 {
4916 const struct si_power_info *si_pi = si_get_pi(rdev);
4917 const struct si_ulv_param *ulv = &si_pi->ulv;
4918 const struct ni_ps *state = ni_get_ps(radeon_state);
4919 int i;
4920
4921 if (state->performance_levels[0].mclk != ulv->pl.mclk)
4922 return false;
4923
4924 /* XXX validate against display requirements! */
4925
4926 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
4927 if (rdev->clock.current_dispclk <=
4928 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
4929 if (ulv->pl.vddc <
4930 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
4931 return false;
4932 }
4933 }
4934
4935 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
4936 return false;
4937
4938 return true;
4939 }
4940
4941 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
4942 struct radeon_ps *radeon_new_state)
4943 {
4944 const struct si_power_info *si_pi = si_get_pi(rdev);
4945 const struct si_ulv_param *ulv = &si_pi->ulv;
4946
4947 if (ulv->supported) {
4948 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
4949 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
4950 0 : -EINVAL;
4951 }
4952 return 0;
4953 }
4954
4955 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
4956 struct radeon_ps *radeon_state,
4957 SISLANDS_SMC_SWSTATE *smc_state)
4958 {
4959 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4960 struct ni_power_info *ni_pi = ni_get_pi(rdev);
4961 struct si_power_info *si_pi = si_get_pi(rdev);
4962 struct ni_ps *state = ni_get_ps(radeon_state);
4963 int i, ret;
4964 u32 threshold;
4965 u32 sclk_in_sr = 1350; /* ??? */
4966
4967 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
4968 return -EINVAL;
4969
4970 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
4971
4972 if (radeon_state->vclk && radeon_state->dclk) {
4973 eg_pi->uvd_enabled = true;
4974 if (eg_pi->smu_uvd_hs)
4975 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
4976 } else {
4977 eg_pi->uvd_enabled = false;
4978 }
4979
4980 if (state->dc_compatible)
4981 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
4982
4983 smc_state->levelCount = 0;
4984 for (i = 0; i < state->performance_level_count; i++) {
4985 if (eg_pi->sclk_deep_sleep) {
4986 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
4987 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4988 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4989 else
4990 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4991 }
4992 }
4993
4994 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
4995 &smc_state->levels[i]);
4996 smc_state->levels[i].arbRefreshState =
4997 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
4998
4999 if (ret)
5000 return ret;
5001
5002 if (ni_pi->enable_power_containment)
5003 smc_state->levels[i].displayWatermark =
5004 (state->performance_levels[i].sclk < threshold) ?
5005 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5006 else
5007 smc_state->levels[i].displayWatermark = (i < 2) ?
5008 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5009
5010 if (eg_pi->dynamic_ac_timing)
5011 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5012 else
5013 smc_state->levels[i].ACIndex = 0;
5014
5015 smc_state->levelCount++;
5016 }
5017
5018 si_write_smc_soft_register(rdev,
5019 SI_SMC_SOFT_REGISTER_watermark_threshold,
5020 threshold / 512);
5021
5022 si_populate_smc_sp(rdev, radeon_state, smc_state);
5023
5024 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5025 if (ret)
5026 ni_pi->enable_power_containment = false;
5027
5028 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5029 if (ret)
5030 ni_pi->enable_sq_ramping = false;
5031
5032 return si_populate_smc_t(rdev, radeon_state, smc_state);
5033 }
5034
5035 static int si_upload_sw_state(struct radeon_device *rdev,
5036 struct radeon_ps *radeon_new_state)
5037 {
5038 struct si_power_info *si_pi = si_get_pi(rdev);
5039 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5040 int ret;
5041 u32 address = si_pi->state_table_start +
5042 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5043 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5044 ((new_state->performance_level_count - 1) *
5045 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5046 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5047
5048 memset(smc_state, 0, state_size);
5049
5050 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5051 if (ret)
5052 return ret;
5053
5054 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5055 state_size, si_pi->sram_end);
5056
5057 return ret;
5058 }
5059
5060 static int si_upload_ulv_state(struct radeon_device *rdev)
5061 {
5062 struct si_power_info *si_pi = si_get_pi(rdev);
5063 struct si_ulv_param *ulv = &si_pi->ulv;
5064 int ret = 0;
5065
5066 if (ulv->supported && ulv->pl.vddc) {
5067 u32 address = si_pi->state_table_start +
5068 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5069 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5070 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5071
5072 memset(smc_state, 0, state_size);
5073
5074 ret = si_populate_ulv_state(rdev, smc_state);
5075 if (!ret)
5076 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5077 state_size, si_pi->sram_end);
5078 }
5079
5080 return ret;
5081 }
5082
5083 static int si_upload_smc_data(struct radeon_device *rdev)
5084 {
5085 struct radeon_crtc *radeon_crtc = NULL;
5086 int i;
5087
5088 if (rdev->pm.dpm.new_active_crtc_count == 0)
5089 return 0;
5090
5091 for (i = 0; i < rdev->num_crtc; i++) {
5092 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5093 radeon_crtc = rdev->mode_info.crtcs[i];
5094 break;
5095 }
5096 }
5097
5098 if (radeon_crtc == NULL)
5099 return 0;
5100
5101 if (radeon_crtc->line_time <= 0)
5102 return 0;
5103
5104 if (si_write_smc_soft_register(rdev,
5105 SI_SMC_SOFT_REGISTER_crtc_index,
5106 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5107 return 0;
5108
5109 if (si_write_smc_soft_register(rdev,
5110 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5111 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5112 return 0;
5113
5114 if (si_write_smc_soft_register(rdev,
5115 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5116 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5117 return 0;
5118
5119 return 0;
5120 }
5121
5122 static int si_set_mc_special_registers(struct radeon_device *rdev,
5123 struct si_mc_reg_table *table)
5124 {
5125 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5126 u8 i, j, k;
5127 u32 temp_reg;
5128
5129 for (i = 0, j = table->last; i < table->last; i++) {
5130 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5131 return -EINVAL;
5132 switch (table->mc_reg_address[i].s1 << 2) {
5133 case MC_SEQ_MISC1:
5134 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5135 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5136 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5137 for (k = 0; k < table->num_entries; k++)
5138 table->mc_reg_table_entry[k].mc_data[j] =
5139 ((temp_reg & 0xffff0000)) |
5140 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5141 j++;
5142 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5143 return -EINVAL;
5144
5145 temp_reg = RREG32(MC_PMG_CMD_MRS);
5146 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5147 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5148 for (k = 0; k < table->num_entries; k++) {
5149 table->mc_reg_table_entry[k].mc_data[j] =
5150 (temp_reg & 0xffff0000) |
5151 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5152 if (!pi->mem_gddr5)
5153 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5154 }
5155 j++;
5156 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5157 return -EINVAL;
5158
5159 if (!pi->mem_gddr5) {
5160 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5161 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5162 for (k = 0; k < table->num_entries; k++)
5163 table->mc_reg_table_entry[k].mc_data[j] =
5164 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5165 j++;
5166 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5167 return -EINVAL;
5168 }
5169 break;
5170 case MC_SEQ_RESERVE_M:
5171 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5172 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5173 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5174 for(k = 0; k < table->num_entries; k++)
5175 table->mc_reg_table_entry[k].mc_data[j] =
5176 (temp_reg & 0xffff0000) |
5177 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5178 j++;
5179 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5180 return -EINVAL;
5181 break;
5182 default:
5183 break;
5184 }
5185 }
5186
5187 table->last = j;
5188
5189 return 0;
5190 }
5191
5192 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5193 {
5194 bool result = true;
5195
5196 switch (in_reg) {
5197 case MC_SEQ_RAS_TIMING >> 2:
5198 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5199 break;
5200 case MC_SEQ_CAS_TIMING >> 2:
5201 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5202 break;
5203 case MC_SEQ_MISC_TIMING >> 2:
5204 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5205 break;
5206 case MC_SEQ_MISC_TIMING2 >> 2:
5207 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5208 break;
5209 case MC_SEQ_RD_CTL_D0 >> 2:
5210 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5211 break;
5212 case MC_SEQ_RD_CTL_D1 >> 2:
5213 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5214 break;
5215 case MC_SEQ_WR_CTL_D0 >> 2:
5216 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5217 break;
5218 case MC_SEQ_WR_CTL_D1 >> 2:
5219 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5220 break;
5221 case MC_PMG_CMD_EMRS >> 2:
5222 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5223 break;
5224 case MC_PMG_CMD_MRS >> 2:
5225 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5226 break;
5227 case MC_PMG_CMD_MRS1 >> 2:
5228 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5229 break;
5230 case MC_SEQ_PMG_TIMING >> 2:
5231 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5232 break;
5233 case MC_PMG_CMD_MRS2 >> 2:
5234 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5235 break;
5236 case MC_SEQ_WR_CTL_2 >> 2:
5237 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5238 break;
5239 default:
5240 result = false;
5241 break;
5242 }
5243
5244 return result;
5245 }
5246
5247 static void si_set_valid_flag(struct si_mc_reg_table *table)
5248 {
5249 u8 i, j;
5250
5251 for (i = 0; i < table->last; i++) {
5252 for (j = 1; j < table->num_entries; j++) {
5253 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5254 table->valid_flag |= 1 << i;
5255 break;
5256 }
5257 }
5258 }
5259 }
5260
5261 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5262 {
5263 u32 i;
5264 u16 address;
5265
5266 for (i = 0; i < table->last; i++)
5267 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5268 address : table->mc_reg_address[i].s1;
5269
5270 }
5271
5272 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5273 struct si_mc_reg_table *si_table)
5274 {
5275 u8 i, j;
5276
5277 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5278 return -EINVAL;
5279 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5280 return -EINVAL;
5281
5282 for (i = 0; i < table->last; i++)
5283 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5284 si_table->last = table->last;
5285
5286 for (i = 0; i < table->num_entries; i++) {
5287 si_table->mc_reg_table_entry[i].mclk_max =
5288 table->mc_reg_table_entry[i].mclk_max;
5289 for (j = 0; j < table->last; j++) {
5290 si_table->mc_reg_table_entry[i].mc_data[j] =
5291 table->mc_reg_table_entry[i].mc_data[j];
5292 }
5293 }
5294 si_table->num_entries = table->num_entries;
5295
5296 return 0;
5297 }
5298
5299 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5300 {
5301 struct si_power_info *si_pi = si_get_pi(rdev);
5302 struct atom_mc_reg_table *table;
5303 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5304 u8 module_index = rv770_get_memory_module_index(rdev);
5305 int ret;
5306
5307 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5308 if (!table)
5309 return -ENOMEM;
5310
5311 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5312 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5313 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5314 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5315 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5316 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5317 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5318 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5319 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5320 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5321 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5322 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5323 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5324 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5325
5326 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5327 if (ret)
5328 goto init_mc_done;
5329
5330 ret = si_copy_vbios_mc_reg_table(table, si_table);
5331 if (ret)
5332 goto init_mc_done;
5333
5334 si_set_s0_mc_reg_index(si_table);
5335
5336 ret = si_set_mc_special_registers(rdev, si_table);
5337 if (ret)
5338 goto init_mc_done;
5339
5340 si_set_valid_flag(si_table);
5341
5342 init_mc_done:
5343 kfree(table);
5344
5345 return ret;
5346
5347 }
5348
5349 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5350 SMC_SIslands_MCRegisters *mc_reg_table)
5351 {
5352 struct si_power_info *si_pi = si_get_pi(rdev);
5353 u32 i, j;
5354
5355 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5356 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5357 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
5358 break;
5359 mc_reg_table->address[i].s0 =
5360 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5361 mc_reg_table->address[i].s1 =
5362 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5363 i++;
5364 }
5365 }
5366 mc_reg_table->last = (u8)i;
5367 }
5368
5369 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5370 SMC_SIslands_MCRegisterSet *data,
5371 u32 num_entries, u32 valid_flag)
5372 {
5373 u32 i, j;
5374
5375 for(i = 0, j = 0; j < num_entries; j++) {
5376 if (valid_flag & (1 << j)) {
5377 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5378 i++;
5379 }
5380 }
5381 }
5382
5383 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5384 struct rv7xx_pl *pl,
5385 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5386 {
5387 struct si_power_info *si_pi = si_get_pi(rdev);
5388 u32 i = 0;
5389
5390 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5391 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5392 break;
5393 }
5394
5395 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5396 --i;
5397
5398 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5399 mc_reg_table_data, si_pi->mc_reg_table.last,
5400 si_pi->mc_reg_table.valid_flag);
5401 }
5402
5403 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5404 struct radeon_ps *radeon_state,
5405 SMC_SIslands_MCRegisters *mc_reg_table)
5406 {
5407 struct ni_ps *state = ni_get_ps(radeon_state);
5408 int i;
5409
5410 for (i = 0; i < state->performance_level_count; i++) {
5411 si_convert_mc_reg_table_entry_to_smc(rdev,
5412 &state->performance_levels[i],
5413 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5414 }
5415 }
5416
5417 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5418 struct radeon_ps *radeon_boot_state)
5419 {
5420 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5421 struct si_power_info *si_pi = si_get_pi(rdev);
5422 struct si_ulv_param *ulv = &si_pi->ulv;
5423 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5424
5425 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5426
5427 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5428
5429 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5430
5431 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5432 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5433
5434 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5435 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5436 si_pi->mc_reg_table.last,
5437 si_pi->mc_reg_table.valid_flag);
5438
5439 if (ulv->supported && ulv->pl.vddc != 0)
5440 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5441 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5442 else
5443 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5444 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5445 si_pi->mc_reg_table.last,
5446 si_pi->mc_reg_table.valid_flag);
5447
5448 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5449
5450 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5451 (u8 *)smc_mc_reg_table,
5452 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5453 }
5454
5455 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5456 struct radeon_ps *radeon_new_state)
5457 {
5458 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5459 struct si_power_info *si_pi = si_get_pi(rdev);
5460 u32 address = si_pi->mc_reg_table_start +
5461 offsetof(SMC_SIslands_MCRegisters,
5462 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5463 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5464
5465 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5466
5467 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5468
5469
5470 return si_copy_bytes_to_smc(rdev, address,
5471 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5472 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5473 si_pi->sram_end);
5474
5475 }
5476
5477 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5478 {
5479 if (enable)
5480 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5481 else
5482 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5483 }
5484
5485 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5486 struct radeon_ps *radeon_state)
5487 {
5488 struct ni_ps *state = ni_get_ps(radeon_state);
5489 int i;
5490 u16 pcie_speed, max_speed = 0;
5491
5492 for (i = 0; i < state->performance_level_count; i++) {
5493 pcie_speed = state->performance_levels[i].pcie_gen;
5494 if (max_speed < pcie_speed)
5495 max_speed = pcie_speed;
5496 }
5497 return max_speed;
5498 }
5499
5500 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5501 {
5502 u32 speed_cntl;
5503
5504 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5505 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5506
5507 return (u16)speed_cntl;
5508 }
5509
5510 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5511 struct radeon_ps *radeon_new_state,
5512 struct radeon_ps *radeon_current_state)
5513 {
5514 struct si_power_info *si_pi = si_get_pi(rdev);
5515 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5516 enum radeon_pcie_gen current_link_speed;
5517
5518 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5519 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5520 else
5521 current_link_speed = si_pi->force_pcie_gen;
5522
5523 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5524 si_pi->pspp_notify_required = false;
5525 if (target_link_speed > current_link_speed) {
5526 switch (target_link_speed) {
5527 #if defined(CONFIG_ACPI)
5528 case RADEON_PCIE_GEN3:
5529 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5530 break;
5531 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5532 if (current_link_speed == RADEON_PCIE_GEN2)
5533 break;
5534 case RADEON_PCIE_GEN2:
5535 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5536 break;
5537 #endif
5538 default:
5539 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5540 break;
5541 }
5542 } else {
5543 if (target_link_speed < current_link_speed)
5544 si_pi->pspp_notify_required = true;
5545 }
5546 }
5547
5548 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5549 struct radeon_ps *radeon_new_state,
5550 struct radeon_ps *radeon_current_state)
5551 {
5552 struct si_power_info *si_pi = si_get_pi(rdev);
5553 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5554 u8 request;
5555
5556 if (si_pi->pspp_notify_required) {
5557 if (target_link_speed == RADEON_PCIE_GEN3)
5558 request = PCIE_PERF_REQ_PECI_GEN3;
5559 else if (target_link_speed == RADEON_PCIE_GEN2)
5560 request = PCIE_PERF_REQ_PECI_GEN2;
5561 else
5562 request = PCIE_PERF_REQ_PECI_GEN1;
5563
5564 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5565 (si_get_current_pcie_speed(rdev) > 0))
5566 return;
5567
5568 #if defined(CONFIG_ACPI)
5569 radeon_acpi_pcie_performance_request(rdev, request, false);
5570 #endif
5571 }
5572 }
5573
5574 #if 0
5575 static int si_ds_request(struct radeon_device *rdev,
5576 bool ds_status_on, u32 count_write)
5577 {
5578 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5579
5580 if (eg_pi->sclk_deep_sleep) {
5581 if (ds_status_on)
5582 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5583 PPSMC_Result_OK) ?
5584 0 : -EINVAL;
5585 else
5586 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5587 PPSMC_Result_OK) ? 0 : -EINVAL;
5588 }
5589 return 0;
5590 }
5591 #endif
5592
5593 static void si_set_max_cu_value(struct radeon_device *rdev)
5594 {
5595 struct si_power_info *si_pi = si_get_pi(rdev);
5596
5597 if (rdev->family == CHIP_VERDE) {
5598 switch (rdev->pdev->device) {
5599 case 0x6820:
5600 case 0x6825:
5601 case 0x6821:
5602 case 0x6823:
5603 case 0x6827:
5604 si_pi->max_cu = 10;
5605 break;
5606 case 0x682D:
5607 case 0x6824:
5608 case 0x682F:
5609 case 0x6826:
5610 si_pi->max_cu = 8;
5611 break;
5612 case 0x6828:
5613 case 0x6830:
5614 case 0x6831:
5615 case 0x6838:
5616 case 0x6839:
5617 case 0x683D:
5618 si_pi->max_cu = 10;
5619 break;
5620 case 0x683B:
5621 case 0x683F:
5622 case 0x6829:
5623 si_pi->max_cu = 8;
5624 break;
5625 default:
5626 si_pi->max_cu = 0;
5627 break;
5628 }
5629 } else {
5630 si_pi->max_cu = 0;
5631 }
5632 }
5633
5634 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5635 struct radeon_clock_voltage_dependency_table *table)
5636 {
5637 u32 i;
5638 int j;
5639 u16 leakage_voltage;
5640
5641 if (table) {
5642 for (i = 0; i < table->count; i++) {
5643 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5644 table->entries[i].v,
5645 &leakage_voltage)) {
5646 case 0:
5647 table->entries[i].v = leakage_voltage;
5648 break;
5649 case -EAGAIN:
5650 return -EINVAL;
5651 case -EINVAL:
5652 default:
5653 break;
5654 }
5655 }
5656
5657 for (j = (table->count - 2); j >= 0; j--) {
5658 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5659 table->entries[j].v : table->entries[j + 1].v;
5660 }
5661 }
5662 return 0;
5663 }
5664
5665 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5666 {
5667 int ret = 0;
5668
5669 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5670 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5671 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5672 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5673 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5674 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5675 return ret;
5676 }
5677
5678 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5679 struct radeon_ps *radeon_new_state,
5680 struct radeon_ps *radeon_current_state)
5681 {
5682 u32 lane_width;
5683 u32 new_lane_width =
5684 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5685 u32 current_lane_width =
5686 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5687
5688 if (new_lane_width != current_lane_width) {
5689 radeon_set_pcie_lanes(rdev, new_lane_width);
5690 lane_width = radeon_get_pcie_lanes(rdev);
5691 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5692 }
5693 }
5694
5695 void si_dpm_setup_asic(struct radeon_device *rdev)
5696 {
5697 rv770_get_memory_type(rdev);
5698 si_read_clock_registers(rdev);
5699 si_enable_acpi_power_management(rdev);
5700 }
5701
5702 static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5703 int min_temp, int max_temp)
5704 {
5705 int low_temp = 0 * 1000;
5706 int high_temp = 255 * 1000;
5707
5708 if (low_temp < min_temp)
5709 low_temp = min_temp;
5710 if (high_temp > max_temp)
5711 high_temp = max_temp;
5712 if (high_temp < low_temp) {
5713 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5714 return -EINVAL;
5715 }
5716
5717 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5718 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5719 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5720
5721 rdev->pm.dpm.thermal.min_temp = low_temp;
5722 rdev->pm.dpm.thermal.max_temp = high_temp;
5723
5724 return 0;
5725 }
5726
5727 int si_dpm_enable(struct radeon_device *rdev)
5728 {
5729 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5730 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5731 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5732 int ret;
5733
5734 if (si_is_smc_running(rdev))
5735 return -EINVAL;
5736 if (pi->voltage_control)
5737 si_enable_voltage_control(rdev, true);
5738 if (pi->mvdd_control)
5739 si_get_mvdd_configuration(rdev);
5740 if (pi->voltage_control) {
5741 ret = si_construct_voltage_tables(rdev);
5742 if (ret) {
5743 DRM_ERROR("si_construct_voltage_tables failed\n");
5744 return ret;
5745 }
5746 }
5747 if (eg_pi->dynamic_ac_timing) {
5748 ret = si_initialize_mc_reg_table(rdev);
5749 if (ret)
5750 eg_pi->dynamic_ac_timing = false;
5751 }
5752 if (pi->dynamic_ss)
5753 si_enable_spread_spectrum(rdev, true);
5754 if (pi->thermal_protection)
5755 si_enable_thermal_protection(rdev, true);
5756 si_setup_bsp(rdev);
5757 si_program_git(rdev);
5758 si_program_tp(rdev);
5759 si_program_tpp(rdev);
5760 si_program_sstp(rdev);
5761 si_enable_display_gap(rdev);
5762 si_program_vc(rdev);
5763 ret = si_upload_firmware(rdev);
5764 if (ret) {
5765 DRM_ERROR("si_upload_firmware failed\n");
5766 return ret;
5767 }
5768 ret = si_process_firmware_header(rdev);
5769 if (ret) {
5770 DRM_ERROR("si_process_firmware_header failed\n");
5771 return ret;
5772 }
5773 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5774 if (ret) {
5775 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5776 return ret;
5777 }
5778 ret = si_init_smc_table(rdev);
5779 if (ret) {
5780 DRM_ERROR("si_init_smc_table failed\n");
5781 return ret;
5782 }
5783 ret = si_init_smc_spll_table(rdev);
5784 if (ret) {
5785 DRM_ERROR("si_init_smc_spll_table failed\n");
5786 return ret;
5787 }
5788 ret = si_init_arb_table_index(rdev);
5789 if (ret) {
5790 DRM_ERROR("si_init_arb_table_index failed\n");
5791 return ret;
5792 }
5793 if (eg_pi->dynamic_ac_timing) {
5794 ret = si_populate_mc_reg_table(rdev, boot_ps);
5795 if (ret) {
5796 DRM_ERROR("si_populate_mc_reg_table failed\n");
5797 return ret;
5798 }
5799 }
5800 ret = si_initialize_smc_cac_tables(rdev);
5801 if (ret) {
5802 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5803 return ret;
5804 }
5805 ret = si_initialize_hardware_cac_manager(rdev);
5806 if (ret) {
5807 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5808 return ret;
5809 }
5810 ret = si_initialize_smc_dte_tables(rdev);
5811 if (ret) {
5812 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5813 return ret;
5814 }
5815 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5816 if (ret) {
5817 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5818 return ret;
5819 }
5820 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5821 if (ret) {
5822 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5823 return ret;
5824 }
5825 si_program_response_times(rdev);
5826 si_program_ds_registers(rdev);
5827 si_dpm_start_smc(rdev);
5828 ret = si_notify_smc_display_change(rdev, false);
5829 if (ret) {
5830 DRM_ERROR("si_notify_smc_display_change failed\n");
5831 return ret;
5832 }
5833 si_enable_sclk_control(rdev, true);
5834 si_start_dpm(rdev);
5835
5836 if (rdev->irq.installed &&
5837 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5838 PPSMC_Result result;
5839
5840 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5841 if (ret)
5842 return ret;
5843 rdev->irq.dpm_thermal = true;
5844 radeon_irq_set(rdev);
5845 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5846
5847 if (result != PPSMC_Result_OK)
5848 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5849 }
5850
5851 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5852
5853 ni_update_current_ps(rdev, boot_ps);
5854
5855 return 0;
5856 }
5857
5858 void si_dpm_disable(struct radeon_device *rdev)
5859 {
5860 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5861 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5862
5863 if (!si_is_smc_running(rdev))
5864 return;
5865 si_disable_ulv(rdev);
5866 si_clear_vc(rdev);
5867 if (pi->thermal_protection)
5868 si_enable_thermal_protection(rdev, false);
5869 si_enable_power_containment(rdev, boot_ps, false);
5870 si_enable_smc_cac(rdev, boot_ps, false);
5871 si_enable_spread_spectrum(rdev, false);
5872 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5873 si_stop_dpm(rdev);
5874 si_reset_to_default(rdev);
5875 si_dpm_stop_smc(rdev);
5876 si_force_switch_to_arb_f0(rdev);
5877
5878 ni_update_current_ps(rdev, boot_ps);
5879 }
5880
5881 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
5882 {
5883 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5884 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5885 struct radeon_ps *new_ps = &requested_ps;
5886
5887 ni_update_requested_ps(rdev, new_ps);
5888
5889 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
5890
5891 return 0;
5892 }
5893
5894 static int si_power_control_set_level(struct radeon_device *rdev)
5895 {
5896 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
5897 int ret;
5898
5899 ret = si_restrict_performance_levels_before_switch(rdev);
5900 if (ret)
5901 return ret;
5902 ret = si_halt_smc(rdev);
5903 if (ret)
5904 return ret;
5905 ret = si_populate_smc_tdp_limits(rdev, new_ps);
5906 if (ret)
5907 return ret;
5908 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
5909 if (ret)
5910 return ret;
5911 ret = si_resume_smc(rdev);
5912 if (ret)
5913 return ret;
5914 ret = si_set_sw_state(rdev);
5915 if (ret)
5916 return ret;
5917 return 0;
5918 }
5919
5920 int si_dpm_set_power_state(struct radeon_device *rdev)
5921 {
5922 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5923 struct radeon_ps *new_ps = &eg_pi->requested_rps;
5924 struct radeon_ps *old_ps = &eg_pi->current_rps;
5925 int ret;
5926
5927 ret = si_disable_ulv(rdev);
5928 if (ret) {
5929 DRM_ERROR("si_disable_ulv failed\n");
5930 return ret;
5931 }
5932 ret = si_restrict_performance_levels_before_switch(rdev);
5933 if (ret) {
5934 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
5935 return ret;
5936 }
5937 if (eg_pi->pcie_performance_request)
5938 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5939 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
5940 ret = si_enable_power_containment(rdev, new_ps, false);
5941 if (ret) {
5942 DRM_ERROR("si_enable_power_containment failed\n");
5943 return ret;
5944 }
5945 ret = si_enable_smc_cac(rdev, new_ps, false);
5946 if (ret) {
5947 DRM_ERROR("si_enable_smc_cac failed\n");
5948 return ret;
5949 }
5950 ret = si_halt_smc(rdev);
5951 if (ret) {
5952 DRM_ERROR("si_halt_smc failed\n");
5953 return ret;
5954 }
5955 ret = si_upload_sw_state(rdev, new_ps);
5956 if (ret) {
5957 DRM_ERROR("si_upload_sw_state failed\n");
5958 return ret;
5959 }
5960 ret = si_upload_smc_data(rdev);
5961 if (ret) {
5962 DRM_ERROR("si_upload_smc_data failed\n");
5963 return ret;
5964 }
5965 ret = si_upload_ulv_state(rdev);
5966 if (ret) {
5967 DRM_ERROR("si_upload_ulv_state failed\n");
5968 return ret;
5969 }
5970 if (eg_pi->dynamic_ac_timing) {
5971 ret = si_upload_mc_reg_table(rdev, new_ps);
5972 if (ret) {
5973 DRM_ERROR("si_upload_mc_reg_table failed\n");
5974 return ret;
5975 }
5976 }
5977 ret = si_program_memory_timing_parameters(rdev, new_ps);
5978 if (ret) {
5979 DRM_ERROR("si_program_memory_timing_parameters failed\n");
5980 return ret;
5981 }
5982 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
5983
5984 ret = si_resume_smc(rdev);
5985 if (ret) {
5986 DRM_ERROR("si_resume_smc failed\n");
5987 return ret;
5988 }
5989 ret = si_set_sw_state(rdev);
5990 if (ret) {
5991 DRM_ERROR("si_set_sw_state failed\n");
5992 return ret;
5993 }
5994 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
5995 if (eg_pi->pcie_performance_request)
5996 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5997 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
5998 if (ret) {
5999 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6000 return ret;
6001 }
6002 ret = si_enable_smc_cac(rdev, new_ps, true);
6003 if (ret) {
6004 DRM_ERROR("si_enable_smc_cac failed\n");
6005 return ret;
6006 }
6007 ret = si_enable_power_containment(rdev, new_ps, true);
6008 if (ret) {
6009 DRM_ERROR("si_enable_power_containment failed\n");
6010 return ret;
6011 }
6012
6013 ret = si_power_control_set_level(rdev);
6014 if (ret) {
6015 DRM_ERROR("si_power_control_set_level failed\n");
6016 return ret;
6017 }
6018
6019 ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
6020 if (ret) {
6021 DRM_ERROR("si_dpm_force_performance_level failed\n");
6022 return ret;
6023 }
6024
6025 return 0;
6026 }
6027
6028 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6029 {
6030 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6031 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6032
6033 ni_update_current_ps(rdev, new_ps);
6034 }
6035
6036
6037 void si_dpm_reset_asic(struct radeon_device *rdev)
6038 {
6039 si_restrict_performance_levels_before_switch(rdev);
6040 si_disable_ulv(rdev);
6041 si_set_boot_state(rdev);
6042 }
6043
6044 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6045 {
6046 si_program_display_gap(rdev);
6047 }
6048
6049 union power_info {
6050 struct _ATOM_POWERPLAY_INFO info;
6051 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6052 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6053 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6054 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6055 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6056 };
6057
6058 union pplib_clock_info {
6059 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6060 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6061 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6062 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6063 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6064 };
6065
6066 union pplib_power_state {
6067 struct _ATOM_PPLIB_STATE v1;
6068 struct _ATOM_PPLIB_STATE_V2 v2;
6069 };
6070
6071 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6072 struct radeon_ps *rps,
6073 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6074 u8 table_rev)
6075 {
6076 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6077 rps->class = le16_to_cpu(non_clock_info->usClassification);
6078 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6079
6080 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6081 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6082 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6083 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6084 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6085 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6086 } else {
6087 rps->vclk = 0;
6088 rps->dclk = 0;
6089 }
6090
6091 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6092 rdev->pm.dpm.boot_ps = rps;
6093 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6094 rdev->pm.dpm.uvd_ps = rps;
6095 }
6096
6097 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6098 struct radeon_ps *rps, int index,
6099 union pplib_clock_info *clock_info)
6100 {
6101 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6102 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6103 struct si_power_info *si_pi = si_get_pi(rdev);
6104 struct ni_ps *ps = ni_get_ps(rps);
6105 u16 leakage_voltage;
6106 struct rv7xx_pl *pl = &ps->performance_levels[index];
6107 int ret;
6108
6109 ps->performance_level_count = index + 1;
6110
6111 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6112 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6113 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6114 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6115
6116 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6117 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6118 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6119 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6120 si_pi->sys_pcie_mask,
6121 si_pi->boot_pcie_gen,
6122 clock_info->si.ucPCIEGen);
6123
6124 /* patch up vddc if necessary */
6125 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6126 &leakage_voltage);
6127 if (ret == 0)
6128 pl->vddc = leakage_voltage;
6129
6130 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6131 pi->acpi_vddc = pl->vddc;
6132 eg_pi->acpi_vddci = pl->vddci;
6133 si_pi->acpi_pcie_gen = pl->pcie_gen;
6134 }
6135
6136 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6137 index == 0) {
6138 /* XXX disable for A0 tahiti */
6139 si_pi->ulv.supported = true;
6140 si_pi->ulv.pl = *pl;
6141 si_pi->ulv.one_pcie_lane_in_ulv = false;
6142 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6143 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6144 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6145 }
6146
6147 if (pi->min_vddc_in_table > pl->vddc)
6148 pi->min_vddc_in_table = pl->vddc;
6149
6150 if (pi->max_vddc_in_table < pl->vddc)
6151 pi->max_vddc_in_table = pl->vddc;
6152
6153 /* patch up boot state */
6154 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6155 u16 vddc, vddci, mvdd;
6156 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6157 pl->mclk = rdev->clock.default_mclk;
6158 pl->sclk = rdev->clock.default_sclk;
6159 pl->vddc = vddc;
6160 pl->vddci = vddci;
6161 si_pi->mvdd_bootup_value = mvdd;
6162 }
6163
6164 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6165 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6166 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6167 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6168 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6169 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6170 }
6171 }
6172
6173 static int si_parse_power_table(struct radeon_device *rdev)
6174 {
6175 struct radeon_mode_info *mode_info = &rdev->mode_info;
6176 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6177 union pplib_power_state *power_state;
6178 int i, j, k, non_clock_array_index, clock_array_index;
6179 union pplib_clock_info *clock_info;
6180 struct _StateArray *state_array;
6181 struct _ClockInfoArray *clock_info_array;
6182 struct _NonClockInfoArray *non_clock_info_array;
6183 union power_info *power_info;
6184 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6185 u16 data_offset;
6186 u8 frev, crev;
6187 u8 *power_state_offset;
6188 struct ni_ps *ps;
6189
6190 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6191 &frev, &crev, &data_offset))
6192 return -EINVAL;
6193 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6194
6195 state_array = (struct _StateArray *)
6196 (mode_info->atom_context->bios + data_offset +
6197 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6198 clock_info_array = (struct _ClockInfoArray *)
6199 (mode_info->atom_context->bios + data_offset +
6200 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6201 non_clock_info_array = (struct _NonClockInfoArray *)
6202 (mode_info->atom_context->bios + data_offset +
6203 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6204
6205 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6206 state_array->ucNumEntries, GFP_KERNEL);
6207 if (!rdev->pm.dpm.ps)
6208 return -ENOMEM;
6209 power_state_offset = (u8 *)state_array->states;
6210 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
6211 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
6212 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
6213 for (i = 0; i < state_array->ucNumEntries; i++) {
6214 power_state = (union pplib_power_state *)power_state_offset;
6215 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6216 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6217 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6218 if (!rdev->pm.power_state[i].clock_info)
6219 return -EINVAL;
6220 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6221 if (ps == NULL) {
6222 kfree(rdev->pm.dpm.ps);
6223 return -ENOMEM;
6224 }
6225 rdev->pm.dpm.ps[i].ps_priv = ps;
6226 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6227 non_clock_info,
6228 non_clock_info_array->ucEntrySize);
6229 k = 0;
6230 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6231 clock_array_index = power_state->v2.clockInfoIndex[j];
6232 if (clock_array_index >= clock_info_array->ucNumEntries)
6233 continue;
6234 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6235 break;
6236 clock_info = (union pplib_clock_info *)
6237 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6238 si_parse_pplib_clock_info(rdev,
6239 &rdev->pm.dpm.ps[i], k,
6240 clock_info);
6241 k++;
6242 }
6243 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6244 }
6245 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6246 return 0;
6247 }
6248
6249 int si_dpm_init(struct radeon_device *rdev)
6250 {
6251 struct rv7xx_power_info *pi;
6252 struct evergreen_power_info *eg_pi;
6253 struct ni_power_info *ni_pi;
6254 struct si_power_info *si_pi;
6255 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
6256 u16 data_offset, size;
6257 u8 frev, crev;
6258 struct atom_clock_dividers dividers;
6259 int ret;
6260 u32 mask;
6261
6262 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6263 if (si_pi == NULL)
6264 return -ENOMEM;
6265 rdev->pm.dpm.priv = si_pi;
6266 ni_pi = &si_pi->ni;
6267 eg_pi = &ni_pi->eg;
6268 pi = &eg_pi->rv7xx;
6269
6270 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6271 if (ret)
6272 si_pi->sys_pcie_mask = 0;
6273 else
6274 si_pi->sys_pcie_mask = mask;
6275 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6276 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6277
6278 si_set_max_cu_value(rdev);
6279
6280 rv770_get_max_vddc(rdev);
6281 si_get_leakage_vddc(rdev);
6282 si_patch_dependency_tables_based_on_leakage(rdev);
6283
6284 pi->acpi_vddc = 0;
6285 eg_pi->acpi_vddci = 0;
6286 pi->min_vddc_in_table = 0;
6287 pi->max_vddc_in_table = 0;
6288
6289 ret = si_parse_power_table(rdev);
6290 if (ret)
6291 return ret;
6292 ret = r600_parse_extended_power_table(rdev);
6293 if (ret)
6294 return ret;
6295
6296 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6297 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6298 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6299 r600_free_extended_power_table(rdev);
6300 return -ENOMEM;
6301 }
6302 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6303 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6304 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6305 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6306 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6307 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6308 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6309 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6310 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6311
6312 if (rdev->pm.dpm.voltage_response_time == 0)
6313 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6314 if (rdev->pm.dpm.backbias_response_time == 0)
6315 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6316
6317 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6318 0, false, &dividers);
6319 if (ret)
6320 pi->ref_div = dividers.ref_div + 1;
6321 else
6322 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6323
6324 eg_pi->smu_uvd_hs = false;
6325
6326 pi->mclk_strobe_mode_threshold = 40000;
6327 if (si_is_special_1gb_platform(rdev))
6328 pi->mclk_stutter_mode_threshold = 0;
6329 else
6330 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6331 pi->mclk_edc_enable_threshold = 40000;
6332 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6333
6334 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6335
6336 pi->voltage_control =
6337 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6338
6339 pi->mvdd_control =
6340 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6341
6342 eg_pi->vddci_control =
6343 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6344
6345 si_pi->vddc_phase_shed_control =
6346 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6347
6348 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
6349 &frev, &crev, &data_offset)) {
6350 pi->sclk_ss = true;
6351 pi->mclk_ss = true;
6352 pi->dynamic_ss = true;
6353 } else {
6354 pi->sclk_ss = false;
6355 pi->mclk_ss = false;
6356 pi->dynamic_ss = true;
6357 }
6358
6359 pi->asi = RV770_ASI_DFLT;
6360 pi->pasi = CYPRESS_HASI_DFLT;
6361 pi->vrc = SISLANDS_VRC_DFLT;
6362
6363 pi->gfx_clock_gating = true;
6364
6365 eg_pi->sclk_deep_sleep = true;
6366 si_pi->sclk_deep_sleep_above_low = false;
6367
6368 if (pi->gfx_clock_gating &&
6369 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
6370 pi->thermal_protection = true;
6371 else
6372 pi->thermal_protection = false;
6373
6374 eg_pi->dynamic_ac_timing = true;
6375
6376 eg_pi->light_sleep = true;
6377 #if defined(CONFIG_ACPI)
6378 eg_pi->pcie_performance_request =
6379 radeon_acpi_is_pcie_performance_request_supported(rdev);
6380 #else
6381 eg_pi->pcie_performance_request = false;
6382 #endif
6383
6384 si_pi->sram_end = SMC_RAM_END;
6385
6386 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6387 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6388 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6389 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6390 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6391 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6392 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6393
6394 si_initialize_powertune_defaults(rdev);
6395
6396 return 0;
6397 }
6398
6399 void si_dpm_fini(struct radeon_device *rdev)
6400 {
6401 int i;
6402
6403 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6404 kfree(rdev->pm.dpm.ps[i].ps_priv);
6405 }
6406 kfree(rdev->pm.dpm.ps);
6407 kfree(rdev->pm.dpm.priv);
6408 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6409 r600_free_extended_power_table(rdev);
6410 }
6411
6412 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6413 struct seq_file *m)
6414 {
6415 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
6416 struct ni_ps *ps = ni_get_ps(rps);
6417 struct rv7xx_pl *pl;
6418 u32 current_index =
6419 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6420 CURRENT_STATE_INDEX_SHIFT;
6421
6422 if (current_index >= ps->performance_level_count) {
6423 seq_printf(m, "invalid dpm profile %d\n", current_index);
6424 } else {
6425 pl = &ps->performance_levels[current_index];
6426 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6427 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6428 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6429 }
6430 }
Linux kernel - Deliverables
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