2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
25 #include <linux/firmware.h>
30 #include "radeon_ucode.h"
31 #include "sislands_smc.h"
33 static int si_set_smc_sram_address(struct radeon_device
*rdev
,
34 u32 smc_address
, u32 limit
)
38 if ((smc_address
+ 3) > limit
)
41 WREG32(SMC_IND_INDEX_0
, smc_address
);
42 WREG32_P(SMC_IND_ACCESS_CNTL
, 0, ~AUTO_INCREMENT_IND_0
);
47 int si_copy_bytes_to_smc(struct radeon_device
*rdev
,
48 u32 smc_start_address
,
49 const u8
*src
, u32 byte_count
, u32 limit
)
53 u32 data
, original_data
, addr
, extra_shift
;
55 if (smc_start_address
& 3)
57 if ((smc_start_address
+ byte_count
) > limit
)
60 addr
= smc_start_address
;
62 spin_lock_irqsave(&rdev
->smc_idx_lock
, flags
);
63 while (byte_count
>= 4) {
64 /* SMC address space is BE */
65 data
= (src
[0] << 24) | (src
[1] << 16) | (src
[2] << 8) | src
[3];
67 ret
= si_set_smc_sram_address(rdev
, addr
, limit
);
71 WREG32(SMC_IND_DATA_0
, data
);
78 /* RMW for the final bytes */
82 ret
= si_set_smc_sram_address(rdev
, addr
, limit
);
86 original_data
= RREG32(SMC_IND_DATA_0
);
88 extra_shift
= 8 * (4 - byte_count
);
90 while (byte_count
> 0) {
91 /* SMC address space is BE */
92 data
= (data
<< 8) + *src
++;
98 data
|= (original_data
& ~((~0UL) << extra_shift
));
100 ret
= si_set_smc_sram_address(rdev
, addr
, limit
);
104 WREG32(SMC_IND_DATA_0
, data
);
108 spin_unlock_irqrestore(&rdev
->smc_idx_lock
, flags
);
113 void si_start_smc(struct radeon_device
*rdev
)
115 u32 tmp
= RREG32_SMC(SMC_SYSCON_RESET_CNTL
);
119 WREG32_SMC(SMC_SYSCON_RESET_CNTL
, tmp
);
122 void si_reset_smc(struct radeon_device
*rdev
)
126 RREG32(CB_CGTT_SCLK_CTRL
);
127 RREG32(CB_CGTT_SCLK_CTRL
);
128 RREG32(CB_CGTT_SCLK_CTRL
);
129 RREG32(CB_CGTT_SCLK_CTRL
);
131 tmp
= RREG32_SMC(SMC_SYSCON_RESET_CNTL
);
133 WREG32_SMC(SMC_SYSCON_RESET_CNTL
, tmp
);
136 int si_program_jump_on_start(struct radeon_device
*rdev
)
138 static const u8 data
[] = { 0x0E, 0x00, 0x40, 0x40 };
140 return si_copy_bytes_to_smc(rdev
, 0x0, data
, 4, sizeof(data
)+1);
143 void si_stop_smc_clock(struct radeon_device
*rdev
)
145 u32 tmp
= RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
);
149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
, tmp
);
152 void si_start_smc_clock(struct radeon_device
*rdev
)
154 u32 tmp
= RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
);
158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
, tmp
);
161 bool si_is_smc_running(struct radeon_device
*rdev
)
163 u32 rst
= RREG32_SMC(SMC_SYSCON_RESET_CNTL
);
164 u32 clk
= RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
);
166 if (!(rst
& RST_REG
) && !(clk
& CK_DISABLE
))
172 PPSMC_Result
si_send_msg_to_smc(struct radeon_device
*rdev
, PPSMC_Msg msg
)
177 if (!si_is_smc_running(rdev
))
178 return PPSMC_Result_Failed
;
180 WREG32(SMC_MESSAGE_0
, msg
);
182 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
183 tmp
= RREG32(SMC_RESP_0
);
188 tmp
= RREG32(SMC_RESP_0
);
190 return (PPSMC_Result
)tmp
;
193 PPSMC_Result
si_wait_for_smc_inactive(struct radeon_device
*rdev
)
198 if (!si_is_smc_running(rdev
))
199 return PPSMC_Result_OK
;
201 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
202 tmp
= RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0
);
203 if ((tmp
& CKEN
) == 0)
208 return PPSMC_Result_OK
;
211 int si_load_smc_ucode(struct radeon_device
*rdev
, u32 limit
)
214 u32 ucode_start_address
;
223 const struct smc_firmware_header_v1_0
*hdr
=
224 (const struct smc_firmware_header_v1_0
*)rdev
->smc_fw
->data
;
226 radeon_ucode_print_smc_hdr(&hdr
->header
);
228 ucode_start_address
= le32_to_cpu(hdr
->ucode_start_addr
);
229 ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
);
231 (rdev
->smc_fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
233 switch (rdev
->family
) {
235 ucode_start_address
= TAHITI_SMC_UCODE_START
;
236 ucode_size
= TAHITI_SMC_UCODE_SIZE
;
239 ucode_start_address
= PITCAIRN_SMC_UCODE_START
;
240 ucode_size
= PITCAIRN_SMC_UCODE_SIZE
;
243 ucode_start_address
= VERDE_SMC_UCODE_START
;
244 ucode_size
= VERDE_SMC_UCODE_SIZE
;
247 ucode_start_address
= OLAND_SMC_UCODE_START
;
248 ucode_size
= OLAND_SMC_UCODE_SIZE
;
251 ucode_start_address
= HAINAN_SMC_UCODE_START
;
252 ucode_size
= HAINAN_SMC_UCODE_SIZE
;
255 DRM_ERROR("unknown asic in smc ucode loader\n");
258 src
= (const u8
*)rdev
->smc_fw
->data
;
264 spin_lock_irqsave(&rdev
->smc_idx_lock
, flags
);
265 WREG32(SMC_IND_INDEX_0
, ucode_start_address
);
266 WREG32_P(SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, ~AUTO_INCREMENT_IND_0
);
267 while (ucode_size
>= 4) {
268 /* SMC address space is BE */
269 data
= (src
[0] << 24) | (src
[1] << 16) | (src
[2] << 8) | src
[3];
271 WREG32(SMC_IND_DATA_0
, data
);
276 WREG32_P(SMC_IND_ACCESS_CNTL
, 0, ~AUTO_INCREMENT_IND_0
);
277 spin_unlock_irqrestore(&rdev
->smc_idx_lock
, flags
);
282 int si_read_smc_sram_dword(struct radeon_device
*rdev
, u32 smc_address
,
283 u32
*value
, u32 limit
)
288 spin_lock_irqsave(&rdev
->smc_idx_lock
, flags
);
289 ret
= si_set_smc_sram_address(rdev
, smc_address
, limit
);
291 *value
= RREG32(SMC_IND_DATA_0
);
292 spin_unlock_irqrestore(&rdev
->smc_idx_lock
, flags
);
297 int si_write_smc_sram_dword(struct radeon_device
*rdev
, u32 smc_address
,
298 u32 value
, u32 limit
)
303 spin_lock_irqsave(&rdev
->smc_idx_lock
, flags
);
304 ret
= si_set_smc_sram_address(rdev
, smc_address
, limit
);
306 WREG32(SMC_IND_DATA_0
, value
);
307 spin_unlock_irqrestore(&rdev
->smc_idx_lock
, flags
);
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