drivers/gpu/drm/radeon/sumo_smc.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "sumod.h"
  27 #include "sumo_dpm.h"
  28 #include "ppsmc.h"
  29
  30 #define SUMO_SMU_SERVICE_ROUTINE_PG_INIT        1
  31 #define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY  27
  32 #define SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20  20
  33
  34 struct sumo_ps *sumo_get_ps(struct radeon_ps *rps);
  35 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
  36
  37 static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id)
  38 {
  39         u32 gfx_int_req;
  40         int i;
  41
  42         for (i = 0; i < rdev->usec_timeout; i++) {
  43                 if (RREG32(GFX_INT_STATUS) & INT_DONE)
  44                         break;
  45                 udelay(1);
  46         }
  47
  48         gfx_int_req = SERV_INDEX(id) | INT_REQ;
  49         WREG32(GFX_INT_REQ, gfx_int_req);
  50
  51         for (i = 0; i < rdev->usec_timeout; i++) {
  52                 if (RREG32(GFX_INT_REQ) & INT_REQ)
  53                         break;
  54                 udelay(1);
  55         }
  56
  57         for (i = 0; i < rdev->usec_timeout; i++) {
  58                 if (RREG32(GFX_INT_STATUS) & INT_ACK)
  59                         break;
  60                 udelay(1);
  61         }
  62
  63         for (i = 0; i < rdev->usec_timeout; i++) {
  64                 if (RREG32(GFX_INT_STATUS) & INT_DONE)
  65                         break;
  66                 udelay(1);
  67         }
  68
  69         gfx_int_req &= ~INT_REQ;
  70         WREG32(GFX_INT_REQ, gfx_int_req);
  71 }
  72
  73 void sumo_initialize_m3_arb(struct radeon_device *rdev)
  74 {
  75         struct sumo_power_info *pi = sumo_get_pi(rdev);
  76         u32 i;
  77
  78         if (!pi->enable_dynamic_m3_arbiter)
  79                 return;
  80
  81         for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++)
  82                 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
  83                            pi->sys_info.csr_m3_arb_cntl_default[i]);
  84
  85         for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 2; i++)
  86                 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
  87                            pi->sys_info.csr_m3_arb_cntl_uvd[i % NUMBER_OF_M3ARB_PARAM_SETS]);
  88
  89         for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 3; i++)
  90                 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
  91                            pi->sys_info.csr_m3_arb_cntl_fs3d[i % NUMBER_OF_M3ARB_PARAM_SETS]);
  92 }
  93
  94 static bool sumo_is_alt_vddnb_supported(struct radeon_device *rdev)
  95 {
  96         struct sumo_power_info *pi = sumo_get_pi(rdev);
  97         bool return_code = false;
  98
  99         if (!pi->enable_alt_vddnb)
 100                 return return_code;
 101
 102         if ((rdev->family == CHIP_SUMO) || (rdev->family == CHIP_SUMO2)) {
 103                 if (pi->fw_version >= 0x00010C00)
 104                         return_code = true;
 105         }
 106
 107         return return_code;
 108 }
 109
 110 void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
 111                                       bool powersaving, bool force_nbps1)
 112 {
 113         u32 param = 0;
 114
 115         if (!sumo_is_alt_vddnb_supported(rdev))
 116                 return;
 117
 118         if (powersaving)
 119                 param |= 1;
 120
 121         if (force_nbps1)
 122                 param |= 2;
 123
 124         WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param);
 125
 126         sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY);
 127 }
 128
 129 void sumo_smu_pg_init(struct radeon_device *rdev)
 130 {
 131         sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_PG_INIT);
 132 }
 133
 134 static u32 sumo_power_of_4(u32 unit)
 135 {
 136         u32 ret = 1;
 137         u32 i;
 138
 139         for (i = 0; i < unit; i++)
 140                 ret *= 4;
 141
 142         return ret;
 143 }
 144
 145 void sumo_enable_boost_timer(struct radeon_device *rdev)
 146 {
 147         struct sumo_power_info *pi = sumo_get_pi(rdev);
 148         u32 period, unit, timer_value;
 149         u32 xclk = radeon_get_xclk(rdev);
 150
 151         unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK)
 152                 >> LCLK_SCALING_TIMER_PRESCALER_SHIFT;
 153
 154         period = 100 * (xclk / 100 / sumo_power_of_4(unit));
 155
 156         timer_value = (period << 16) | (unit << 4);
 157
 158         WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value);
 159         WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin);
 160         WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin);
 161         WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit);
 162         WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg);
 163
 164         sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20);
 165 }
 166
 167 void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit)
 168 {
 169         u32 regoffset = 0;
 170         u32 shift = 0;
 171         u32 mask = 0xFFF;
 172         u32 sclk_dpm_tdp_limit;
 173
 174         switch (index) {
 175         case 0:
 176                 regoffset = RCU_SclkDpmTdpLimit01;
 177                 shift = 16;
 178                 break;
 179         case 1:
 180                 regoffset = RCU_SclkDpmTdpLimit01;
 181                 shift = 0;
 182                 break;
 183         case 2:
 184                 regoffset = RCU_SclkDpmTdpLimit23;
 185                 shift = 16;
 186                 break;
 187         case 3:
 188                 regoffset = RCU_SclkDpmTdpLimit23;
 189                 shift = 0;
 190                 break;
 191         case 4:
 192                 regoffset = RCU_SclkDpmTdpLimit47;
 193                 shift = 16;
 194                 break;
 195         case 7:
 196                 regoffset = RCU_SclkDpmTdpLimit47;
 197                 shift = 0;
 198                 break;
 199         default:
 200                 break;
 201         }
 202
 203         sclk_dpm_tdp_limit = RREG32_RCU(regoffset);
 204         sclk_dpm_tdp_limit &= ~(mask << shift);
 205         sclk_dpm_tdp_limit |= (tdp_limit << shift);
 206         WREG32_RCU(regoffset, sclk_dpm_tdp_limit);
 207 }
 208
 209 void sumo_boost_state_enable(struct radeon_device *rdev, bool enable)
 210 {
 211         u32 boost_disable = RREG32_RCU(RCU_GPU_BOOST_DISABLE);
 212
 213         boost_disable &= 0xFFFFFFFE;
 214         boost_disable |= (enable ? 0 : 1);
 215         WREG32_RCU(RCU_GPU_BOOST_DISABLE, boost_disable);
 216 }
 217
 218 u32 sumo_get_running_fw_version(struct radeon_device *rdev)
 219 {
 220         return RREG32_RCU(RCU_FW_VERSION);
 221 }
 222