2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
31 #include "radeon_asic.h"
34 static void vce_v2_0_set_sw_cg(struct radeon_device
*rdev
, bool gated
)
39 tmp
= RREG32(VCE_CLOCK_GATING_B
);
41 WREG32(VCE_CLOCK_GATING_B
, tmp
);
43 tmp
= RREG32(VCE_UENC_CLOCK_GATING
);
45 WREG32(VCE_UENC_CLOCK_GATING
, tmp
);
47 tmp
= RREG32(VCE_UENC_REG_CLOCK_GATING
);
49 WREG32(VCE_UENC_REG_CLOCK_GATING
, tmp
);
51 WREG32(VCE_CGTT_CLK_OVERRIDE
, 0);
53 tmp
= RREG32(VCE_CLOCK_GATING_B
);
56 WREG32(VCE_CLOCK_GATING_B
, tmp
);
58 tmp
= RREG32(VCE_UENC_CLOCK_GATING
);
61 WREG32(VCE_UENC_CLOCK_GATING
, tmp
);
63 tmp
= RREG32(VCE_UENC_REG_CLOCK_GATING
);
65 WREG32(VCE_UENC_REG_CLOCK_GATING
, tmp
);
69 static void vce_v2_0_set_dyn_cg(struct radeon_device
*rdev
, bool gated
)
73 tmp
= RREG32(VCE_CLOCK_GATING_B
);
81 WREG32(VCE_CLOCK_GATING_B
, tmp
);
83 orig
= tmp
= RREG32(VCE_UENC_CLOCK_GATING
);
87 WREG32(VCE_UENC_CLOCK_GATING
, tmp
);
89 orig
= tmp
= RREG32(VCE_UENC_REG_CLOCK_GATING
);
92 WREG32(VCE_UENC_REG_CLOCK_GATING
, tmp
);
95 WREG32(VCE_CGTT_CLK_OVERRIDE
, 0);
98 static void vce_v2_0_disable_cg(struct radeon_device
*rdev
)
100 WREG32(VCE_CGTT_CLK_OVERRIDE
, 7);
103 void vce_v2_0_enable_mgcg(struct radeon_device
*rdev
, bool enable
)
107 if (enable
&& (rdev
->cg_flags
& RADEON_CG_SUPPORT_VCE_MGCG
)) {
109 vce_v2_0_set_sw_cg(rdev
, true);
111 vce_v2_0_set_dyn_cg(rdev
, true);
113 vce_v2_0_disable_cg(rdev
);
116 vce_v2_0_set_sw_cg(rdev
, false);
118 vce_v2_0_set_dyn_cg(rdev
, false);
122 static void vce_v2_0_init_cg(struct radeon_device
*rdev
)
126 tmp
= RREG32(VCE_CLOCK_GATING_A
);
127 tmp
&= ~(CGC_CLK_GATE_DLY_TIMER_MASK
| CGC_CLK_GATER_OFF_DLY_TIMER_MASK
);
128 tmp
|= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
129 tmp
|= CGC_UENC_WAIT_AWAKE
;
130 WREG32(VCE_CLOCK_GATING_A
, tmp
);
132 tmp
= RREG32(VCE_UENC_CLOCK_GATING
);
133 tmp
&= ~(CLOCK_ON_DELAY_MASK
| CLOCK_OFF_DELAY_MASK
);
134 tmp
|= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4));
135 WREG32(VCE_UENC_CLOCK_GATING
, tmp
);
137 tmp
= RREG32(VCE_CLOCK_GATING_B
);
140 WREG32(VCE_CLOCK_GATING_B
, tmp
);
143 int vce_v2_0_resume(struct radeon_device
*rdev
)
145 uint64_t addr
= rdev
->vce
.gpu_addr
;
148 WREG32_P(VCE_CLOCK_GATING_A
, 0, ~(1 << 16));
149 WREG32_P(VCE_UENC_CLOCK_GATING
, 0x1FF000, ~0xFF9FF000);
150 WREG32_P(VCE_UENC_REG_CLOCK_GATING
, 0x3F, ~0x3F);
151 WREG32(VCE_CLOCK_GATING_B
, 0xf7);
153 WREG32(VCE_LMI_CTRL
, 0x00398000);
154 WREG32_P(VCE_LMI_CACHE_CTRL
, 0x0, ~0x1);
155 WREG32(VCE_LMI_SWAP_CNTL
, 0);
156 WREG32(VCE_LMI_SWAP_CNTL1
, 0);
157 WREG32(VCE_LMI_VM_CTRL
, 0);
159 size
= RADEON_GPU_PAGE_ALIGN(rdev
->vce_fw
->size
);
160 WREG32(VCE_VCPU_CACHE_OFFSET0
, addr
& 0x7fffffff);
161 WREG32(VCE_VCPU_CACHE_SIZE0
, size
);
164 size
= RADEON_VCE_STACK_SIZE
;
165 WREG32(VCE_VCPU_CACHE_OFFSET1
, addr
& 0x7fffffff);
166 WREG32(VCE_VCPU_CACHE_SIZE1
, size
);
169 size
= RADEON_VCE_HEAP_SIZE
;
170 WREG32(VCE_VCPU_CACHE_OFFSET2
, addr
& 0x7fffffff);
171 WREG32(VCE_VCPU_CACHE_SIZE2
, size
);
173 WREG32_P(VCE_LMI_CTRL2
, 0x0, ~0x100);
175 WREG32_P(VCE_SYS_INT_EN
, VCE_SYS_INT_TRAP_INTERRUPT_EN
,
176 ~VCE_SYS_INT_TRAP_INTERRUPT_EN
);
178 vce_v2_0_init_cg(rdev
);