2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_plane_helper.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/clk.h>
26 #include <linux/of_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/component.h>
30 #include <linux/reset.h>
31 #include <linux/delay.h>
33 #include "rockchip_drm_drv.h"
34 #include "rockchip_drm_gem.h"
35 #include "rockchip_drm_fb.h"
36 #include "rockchip_drm_vop.h"
38 #define VOP_REG(off, _mask, s) \
43 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
44 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
45 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
46 vop_mask_write(x, off, (mask) << shift, (v) << shift)
48 #define REG_SET(x, base, reg, v, mode) \
49 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
51 #define VOP_WIN_SET(x, win, name, v) \
52 REG_SET(x, win->base, win->phy->name, v, RELAXED)
53 #define VOP_CTRL_SET(x, name, v) \
54 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
56 #define VOP_WIN_GET(x, win, name) \
57 vop_read_reg(x, win->base, &win->phy->name)
59 #define VOP_WIN_GET_YRGBADDR(vop, win) \
60 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
62 #define to_vop(x) container_of(x, struct vop, crtc)
63 #define to_vop_win(x) container_of(x, struct vop_win, base)
65 struct vop_win_state
{
66 struct list_head head
;
67 struct drm_framebuffer
*fb
;
69 struct drm_pending_vblank_event
*event
;
73 struct drm_plane base
;
74 const struct vop_win_data
*data
;
77 struct list_head pending
;
78 struct vop_win_state
*active
;
84 struct drm_device
*drm_dev
;
88 int connector_out_mode
;
90 /* mutex vsync_ work */
91 struct mutex vsync_mutex
;
92 bool vsync_work_pending
;
93 struct completion dsp_hold_completion
;
95 const struct vop_data
*data
;
100 /* physical map length of vop register */
103 /* one time only one process allowed to config the register */
105 /* lock vop irq reg */
114 /* vop share memory frequency */
118 struct reset_control
*dclk_rst
;
122 struct vop_win win
[];
125 enum vop_data_format
{
126 VOP_FMT_ARGB8888
= 0,
129 VOP_FMT_YUV420SP
= 4,
134 struct vop_reg_data
{
146 struct vop_reg standby
;
147 struct vop_reg data_blank
;
148 struct vop_reg gate_en
;
149 struct vop_reg mmu_en
;
150 struct vop_reg rgb_en
;
151 struct vop_reg edp_en
;
152 struct vop_reg hdmi_en
;
153 struct vop_reg mipi_en
;
154 struct vop_reg out_mode
;
155 struct vop_reg dither_down
;
156 struct vop_reg dither_up
;
157 struct vop_reg pin_pol
;
159 struct vop_reg htotal_pw
;
160 struct vop_reg hact_st_end
;
161 struct vop_reg vtotal_pw
;
162 struct vop_reg vact_st_end
;
163 struct vop_reg hpost_st_end
;
164 struct vop_reg vpost_st_end
;
168 const uint32_t *data_formats
;
171 struct vop_reg enable
;
172 struct vop_reg format
;
173 struct vop_reg rb_swap
;
174 struct vop_reg act_info
;
175 struct vop_reg dsp_info
;
176 struct vop_reg dsp_st
;
177 struct vop_reg yrgb_mst
;
178 struct vop_reg uv_mst
;
179 struct vop_reg yrgb_vir
;
180 struct vop_reg uv_vir
;
182 struct vop_reg dst_alpha_ctl
;
183 struct vop_reg src_alpha_ctl
;
186 struct vop_win_data
{
188 const struct vop_win_phy
*phy
;
189 enum drm_plane_type type
;
193 const struct vop_reg_data
*init_table
;
194 unsigned int table_size
;
195 const struct vop_ctrl
*ctrl
;
196 const struct vop_win_data
*win
;
197 unsigned int win_size
;
200 static const uint32_t formats_01
[] = {
214 static const uint32_t formats_234
[] = {
225 static const struct vop_win_phy win01_data
= {
226 .data_formats
= formats_01
,
227 .nformats
= ARRAY_SIZE(formats_01
),
228 .enable
= VOP_REG(WIN0_CTRL0
, 0x1, 0),
229 .format
= VOP_REG(WIN0_CTRL0
, 0x7, 1),
230 .rb_swap
= VOP_REG(WIN0_CTRL0
, 0x1, 12),
231 .act_info
= VOP_REG(WIN0_ACT_INFO
, 0x1fff1fff, 0),
232 .dsp_info
= VOP_REG(WIN0_DSP_INFO
, 0x0fff0fff, 0),
233 .dsp_st
= VOP_REG(WIN0_DSP_ST
, 0x1fff1fff, 0),
234 .yrgb_mst
= VOP_REG(WIN0_YRGB_MST
, 0xffffffff, 0),
235 .uv_mst
= VOP_REG(WIN0_CBR_MST
, 0xffffffff, 0),
236 .yrgb_vir
= VOP_REG(WIN0_VIR
, 0x3fff, 0),
237 .uv_vir
= VOP_REG(WIN0_VIR
, 0x3fff, 16),
238 .src_alpha_ctl
= VOP_REG(WIN0_SRC_ALPHA_CTRL
, 0xff, 0),
239 .dst_alpha_ctl
= VOP_REG(WIN0_DST_ALPHA_CTRL
, 0xff, 0),
242 static const struct vop_win_phy win23_data
= {
243 .data_formats
= formats_234
,
244 .nformats
= ARRAY_SIZE(formats_234
),
245 .enable
= VOP_REG(WIN2_CTRL0
, 0x1, 0),
246 .format
= VOP_REG(WIN2_CTRL0
, 0x7, 1),
247 .rb_swap
= VOP_REG(WIN2_CTRL0
, 0x1, 12),
248 .dsp_info
= VOP_REG(WIN2_DSP_INFO0
, 0x0fff0fff, 0),
249 .dsp_st
= VOP_REG(WIN2_DSP_ST0
, 0x1fff1fff, 0),
250 .yrgb_mst
= VOP_REG(WIN2_MST0
, 0xffffffff, 0),
251 .yrgb_vir
= VOP_REG(WIN2_VIR0_1
, 0x1fff, 0),
252 .src_alpha_ctl
= VOP_REG(WIN2_SRC_ALPHA_CTRL
, 0xff, 0),
253 .dst_alpha_ctl
= VOP_REG(WIN2_DST_ALPHA_CTRL
, 0xff, 0),
256 static const struct vop_ctrl ctrl_data
= {
257 .standby
= VOP_REG(SYS_CTRL
, 0x1, 22),
258 .gate_en
= VOP_REG(SYS_CTRL
, 0x1, 23),
259 .mmu_en
= VOP_REG(SYS_CTRL
, 0x1, 20),
260 .rgb_en
= VOP_REG(SYS_CTRL
, 0x1, 12),
261 .hdmi_en
= VOP_REG(SYS_CTRL
, 0x1, 13),
262 .edp_en
= VOP_REG(SYS_CTRL
, 0x1, 14),
263 .mipi_en
= VOP_REG(SYS_CTRL
, 0x1, 15),
264 .dither_down
= VOP_REG(DSP_CTRL1
, 0xf, 1),
265 .dither_up
= VOP_REG(DSP_CTRL1
, 0x1, 6),
266 .data_blank
= VOP_REG(DSP_CTRL0
, 0x1, 19),
267 .out_mode
= VOP_REG(DSP_CTRL0
, 0xf, 0),
268 .pin_pol
= VOP_REG(DSP_CTRL0
, 0xf, 4),
269 .htotal_pw
= VOP_REG(DSP_HTOTAL_HS_END
, 0x1fff1fff, 0),
270 .hact_st_end
= VOP_REG(DSP_HACT_ST_END
, 0x1fff1fff, 0),
271 .vtotal_pw
= VOP_REG(DSP_VTOTAL_VS_END
, 0x1fff1fff, 0),
272 .vact_st_end
= VOP_REG(DSP_VACT_ST_END
, 0x1fff1fff, 0),
273 .hpost_st_end
= VOP_REG(POST_DSP_HACT_INFO
, 0x1fff1fff, 0),
274 .vpost_st_end
= VOP_REG(POST_DSP_VACT_INFO
, 0x1fff1fff, 0),
277 static const struct vop_reg_data vop_init_reg_table
[] = {
278 {SYS_CTRL
, 0x00c00000},
279 {DSP_CTRL0
, 0x00000000},
280 {WIN0_CTRL0
, 0x00000080},
281 {WIN1_CTRL0
, 0x00000080},
285 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
286 * special support to get alpha blending working. For now, just use overlay
287 * window 3 for the drm cursor.
290 static const struct vop_win_data rk3288_vop_win_data
[] = {
291 { .base
= 0x00, .phy
= &win01_data
, .type
= DRM_PLANE_TYPE_PRIMARY
},
292 { .base
= 0x40, .phy
= &win01_data
, .type
= DRM_PLANE_TYPE_OVERLAY
},
293 { .base
= 0x00, .phy
= &win23_data
, .type
= DRM_PLANE_TYPE_OVERLAY
},
294 { .base
= 0x50, .phy
= &win23_data
, .type
= DRM_PLANE_TYPE_CURSOR
},
297 static const struct vop_data rk3288_vop
= {
298 .init_table
= vop_init_reg_table
,
299 .table_size
= ARRAY_SIZE(vop_init_reg_table
),
301 .win
= rk3288_vop_win_data
,
302 .win_size
= ARRAY_SIZE(rk3288_vop_win_data
),
305 static const struct of_device_id vop_driver_dt_match
[] = {
306 { .compatible
= "rockchip,rk3288-vop",
307 .data
= &rk3288_vop
},
311 static inline void vop_writel(struct vop
*vop
, uint32_t offset
, uint32_t v
)
313 writel(v
, vop
->regs
+ offset
);
314 vop
->regsbak
[offset
>> 2] = v
;
317 static inline uint32_t vop_readl(struct vop
*vop
, uint32_t offset
)
319 return readl(vop
->regs
+ offset
);
322 static inline uint32_t vop_read_reg(struct vop
*vop
, uint32_t base
,
323 const struct vop_reg
*reg
)
325 return (vop_readl(vop
, base
+ reg
->offset
) >> reg
->shift
) & reg
->mask
;
328 static inline void vop_cfg_done(struct vop
*vop
)
330 writel(0x01, vop
->regs
+ REG_CFG_DONE
);
333 static inline void vop_mask_write(struct vop
*vop
, uint32_t offset
,
334 uint32_t mask
, uint32_t v
)
337 uint32_t cached_val
= vop
->regsbak
[offset
>> 2];
339 cached_val
= (cached_val
& ~mask
) | v
;
340 writel(cached_val
, vop
->regs
+ offset
);
341 vop
->regsbak
[offset
>> 2] = cached_val
;
345 static inline void vop_mask_write_relaxed(struct vop
*vop
, uint32_t offset
,
346 uint32_t mask
, uint32_t v
)
349 uint32_t cached_val
= vop
->regsbak
[offset
>> 2];
351 cached_val
= (cached_val
& ~mask
) | v
;
352 writel_relaxed(cached_val
, vop
->regs
+ offset
);
353 vop
->regsbak
[offset
>> 2] = cached_val
;
357 static bool has_rb_swapped(uint32_t format
)
360 case DRM_FORMAT_XBGR8888
:
361 case DRM_FORMAT_ABGR8888
:
362 case DRM_FORMAT_BGR888
:
363 case DRM_FORMAT_BGR565
:
370 static enum vop_data_format
vop_convert_format(uint32_t format
)
373 case DRM_FORMAT_XRGB8888
:
374 case DRM_FORMAT_ARGB8888
:
375 case DRM_FORMAT_XBGR8888
:
376 case DRM_FORMAT_ABGR8888
:
377 return VOP_FMT_ARGB8888
;
378 case DRM_FORMAT_RGB888
:
379 case DRM_FORMAT_BGR888
:
380 return VOP_FMT_RGB888
;
381 case DRM_FORMAT_RGB565
:
382 case DRM_FORMAT_BGR565
:
383 return VOP_FMT_RGB565
;
384 case DRM_FORMAT_NV12
:
385 return VOP_FMT_YUV420SP
;
386 case DRM_FORMAT_NV16
:
387 return VOP_FMT_YUV422SP
;
388 case DRM_FORMAT_NV24
:
389 return VOP_FMT_YUV444SP
;
391 DRM_ERROR("unsupport format[%08x]\n", format
);
396 static bool is_alpha_support(uint32_t format
)
399 case DRM_FORMAT_ARGB8888
:
400 case DRM_FORMAT_ABGR8888
:
407 static void vop_dsp_hold_valid_irq_enable(struct vop
*vop
)
411 if (WARN_ON(!vop
->is_enabled
))
414 spin_lock_irqsave(&vop
->irq_lock
, flags
);
416 vop_mask_write(vop
, INTR_CTRL0
, DSP_HOLD_VALID_INTR_MASK
,
417 DSP_HOLD_VALID_INTR_EN(1));
419 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
422 static void vop_dsp_hold_valid_irq_disable(struct vop
*vop
)
426 if (WARN_ON(!vop
->is_enabled
))
429 spin_lock_irqsave(&vop
->irq_lock
, flags
);
431 vop_mask_write(vop
, INTR_CTRL0
, DSP_HOLD_VALID_INTR_MASK
,
432 DSP_HOLD_VALID_INTR_EN(0));
434 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
437 static void vop_enable(struct drm_crtc
*crtc
)
439 struct vop
*vop
= to_vop(crtc
);
445 ret
= pm_runtime_get_sync(vop
->dev
);
447 dev_err(vop
->dev
, "failed to get pm runtime: %d\n", ret
);
451 ret
= clk_enable(vop
->hclk
);
453 dev_err(vop
->dev
, "failed to enable hclk - %d\n", ret
);
457 ret
= clk_enable(vop
->dclk
);
459 dev_err(vop
->dev
, "failed to enable dclk - %d\n", ret
);
460 goto err_disable_hclk
;
463 ret
= clk_enable(vop
->aclk
);
465 dev_err(vop
->dev
, "failed to enable aclk - %d\n", ret
);
466 goto err_disable_dclk
;
470 * Slave iommu shares power, irq and clock with vop. It was associated
471 * automatically with this master device via common driver code.
472 * Now that we have enabled the clock we attach it to the shared drm
475 ret
= rockchip_drm_dma_attach_device(vop
->drm_dev
, vop
->dev
);
477 dev_err(vop
->dev
, "failed to attach dma mapping, %d\n", ret
);
478 goto err_disable_aclk
;
482 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
484 vop
->is_enabled
= true;
486 spin_lock(&vop
->reg_lock
);
488 VOP_CTRL_SET(vop
, standby
, 0);
490 spin_unlock(&vop
->reg_lock
);
492 enable_irq(vop
->irq
);
494 drm_vblank_on(vop
->drm_dev
, vop
->pipe
);
499 clk_disable(vop
->aclk
);
501 clk_disable(vop
->dclk
);
503 clk_disable(vop
->hclk
);
506 static void vop_disable(struct drm_crtc
*crtc
)
508 struct vop
*vop
= to_vop(crtc
);
510 if (!vop
->is_enabled
)
513 drm_vblank_off(crtc
->dev
, vop
->pipe
);
516 * Vop standby will take effect at end of current frame,
517 * if dsp hold valid irq happen, it means standby complete.
519 * we must wait standby complete when we want to disable aclk,
520 * if not, memory bus maybe dead.
522 reinit_completion(&vop
->dsp_hold_completion
);
523 vop_dsp_hold_valid_irq_enable(vop
);
525 spin_lock(&vop
->reg_lock
);
527 VOP_CTRL_SET(vop
, standby
, 1);
529 spin_unlock(&vop
->reg_lock
);
531 wait_for_completion(&vop
->dsp_hold_completion
);
533 vop_dsp_hold_valid_irq_disable(vop
);
535 disable_irq(vop
->irq
);
537 vop
->is_enabled
= false;
540 * vop standby complete, so iommu detach is safe.
542 rockchip_drm_dma_detach_device(vop
->drm_dev
, vop
->dev
);
544 clk_disable(vop
->dclk
);
545 clk_disable(vop
->aclk
);
546 clk_disable(vop
->hclk
);
547 pm_runtime_put(vop
->dev
);
551 * Caller must hold vsync_mutex.
553 static struct drm_framebuffer
*vop_win_last_pending_fb(struct vop_win
*vop_win
)
555 struct vop_win_state
*last
;
556 struct vop_win_state
*active
= vop_win
->active
;
558 if (list_empty(&vop_win
->pending
))
559 return active
? active
->fb
: NULL
;
561 last
= list_last_entry(&vop_win
->pending
, struct vop_win_state
, head
);
562 return last
? last
->fb
: NULL
;
566 * Caller must hold vsync_mutex.
568 static int vop_win_queue_fb(struct vop_win
*vop_win
,
569 struct drm_framebuffer
*fb
, dma_addr_t yrgb_mst
,
570 struct drm_pending_vblank_event
*event
)
572 struct vop_win_state
*state
;
574 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
579 state
->yrgb_mst
= yrgb_mst
;
580 state
->event
= event
;
582 list_add_tail(&state
->head
, &vop_win
->pending
);
587 static int vop_update_plane_event(struct drm_plane
*plane
,
588 struct drm_crtc
*crtc
,
589 struct drm_framebuffer
*fb
, int crtc_x
,
590 int crtc_y
, unsigned int crtc_w
,
591 unsigned int crtc_h
, uint32_t src_x
,
592 uint32_t src_y
, uint32_t src_w
,
594 struct drm_pending_vblank_event
*event
)
596 struct vop_win
*vop_win
= to_vop_win(plane
);
597 const struct vop_win_data
*win
= vop_win
->data
;
598 struct vop
*vop
= to_vop(crtc
);
599 struct drm_gem_object
*obj
;
600 struct rockchip_gem_object
*rk_obj
;
601 unsigned long offset
;
602 unsigned int actual_w
;
603 unsigned int actual_h
;
604 unsigned int dsp_stx
;
605 unsigned int dsp_sty
;
606 unsigned int y_vir_stride
;
608 enum vop_data_format format
;
614 struct drm_rect dest
= {
617 .x2
= crtc_x
+ crtc_w
,
618 .y2
= crtc_y
+ crtc_h
,
620 struct drm_rect src
= {
621 /* 16.16 fixed point */
627 const struct drm_rect clip
= {
628 .x2
= crtc
->mode
.hdisplay
,
629 .y2
= crtc
->mode
.vdisplay
,
631 bool can_position
= plane
->type
!= DRM_PLANE_TYPE_PRIMARY
;
633 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
635 DRM_PLANE_HELPER_NO_SCALING
,
636 DRM_PLANE_HELPER_NO_SCALING
,
637 can_position
, false, &visible
);
644 is_alpha
= is_alpha_support(fb
->pixel_format
);
645 rb_swap
= has_rb_swapped(fb
->pixel_format
);
646 format
= vop_convert_format(fb
->pixel_format
);
650 obj
= rockchip_fb_get_gem_obj(fb
, 0);
652 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
656 rk_obj
= to_rockchip_obj(obj
);
658 actual_w
= (src
.x2
- src
.x1
) >> 16;
659 actual_h
= (src
.y2
- src
.y1
) >> 16;
660 crtc_x
= max(0, crtc_x
);
661 crtc_y
= max(0, crtc_y
);
663 dsp_stx
= crtc_x
+ crtc
->mode
.htotal
- crtc
->mode
.hsync_start
;
664 dsp_sty
= crtc_y
+ crtc
->mode
.vtotal
- crtc
->mode
.vsync_start
;
666 offset
= (src
.x1
>> 16) * (fb
->bits_per_pixel
>> 3);
667 offset
+= (src
.y1
>> 16) * fb
->pitches
[0];
668 yrgb_mst
= rk_obj
->dma_addr
+ offset
;
670 y_vir_stride
= fb
->pitches
[0] / (fb
->bits_per_pixel
>> 3);
673 * If this plane update changes the plane's framebuffer, (or more
674 * precisely, if this update has a different framebuffer than the last
675 * update), enqueue it so we can track when it completes.
677 * Only when we discover that this update has completed, can we
678 * unreference any previous framebuffers.
680 mutex_lock(&vop
->vsync_mutex
);
681 if (fb
!= vop_win_last_pending_fb(vop_win
)) {
682 ret
= drm_vblank_get(plane
->dev
, vop
->pipe
);
684 DRM_ERROR("failed to get vblank, %d\n", ret
);
685 mutex_unlock(&vop
->vsync_mutex
);
689 drm_framebuffer_reference(fb
);
691 ret
= vop_win_queue_fb(vop_win
, fb
, yrgb_mst
, event
);
693 drm_vblank_put(plane
->dev
, vop
->pipe
);
694 mutex_unlock(&vop
->vsync_mutex
);
698 vop
->vsync_work_pending
= true;
700 mutex_unlock(&vop
->vsync_mutex
);
702 spin_lock(&vop
->reg_lock
);
704 VOP_WIN_SET(vop
, win
, format
, format
);
705 VOP_WIN_SET(vop
, win
, yrgb_vir
, y_vir_stride
);
706 VOP_WIN_SET(vop
, win
, yrgb_mst
, yrgb_mst
);
707 val
= (actual_h
- 1) << 16;
708 val
|= (actual_w
- 1) & 0xffff;
709 VOP_WIN_SET(vop
, win
, act_info
, val
);
710 VOP_WIN_SET(vop
, win
, dsp_info
, val
);
711 val
= (dsp_sty
- 1) << 16;
712 val
|= (dsp_stx
- 1) & 0xffff;
713 VOP_WIN_SET(vop
, win
, dsp_st
, val
);
714 VOP_WIN_SET(vop
, win
, rb_swap
, rb_swap
);
717 VOP_WIN_SET(vop
, win
, dst_alpha_ctl
,
718 DST_FACTOR_M0(ALPHA_SRC_INVERSE
));
719 val
= SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL
) |
720 SRC_ALPHA_M0(ALPHA_STRAIGHT
) |
721 SRC_BLEND_M0(ALPHA_PER_PIX
) |
722 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION
) |
723 SRC_FACTOR_M0(ALPHA_ONE
);
724 VOP_WIN_SET(vop
, win
, src_alpha_ctl
, val
);
726 VOP_WIN_SET(vop
, win
, src_alpha_ctl
, SRC_ALPHA_EN(0));
729 VOP_WIN_SET(vop
, win
, enable
, 1);
732 spin_unlock(&vop
->reg_lock
);
737 static int vop_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
738 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
739 unsigned int crtc_w
, unsigned int crtc_h
,
740 uint32_t src_x
, uint32_t src_y
, uint32_t src_w
,
743 return vop_update_plane_event(plane
, crtc
, fb
, crtc_x
, crtc_y
, crtc_w
,
744 crtc_h
, src_x
, src_y
, src_w
, src_h
,
748 static int vop_update_primary_plane(struct drm_crtc
*crtc
,
749 struct drm_pending_vblank_event
*event
)
751 unsigned int crtc_w
, crtc_h
;
753 crtc_w
= crtc
->primary
->fb
->width
- crtc
->x
;
754 crtc_h
= crtc
->primary
->fb
->height
- crtc
->y
;
756 return vop_update_plane_event(crtc
->primary
, crtc
, crtc
->primary
->fb
,
757 0, 0, crtc_w
, crtc_h
, crtc
->x
<< 16,
758 crtc
->y
<< 16, crtc_w
<< 16,
759 crtc_h
<< 16, event
);
762 static int vop_disable_plane(struct drm_plane
*plane
)
764 struct vop_win
*vop_win
= to_vop_win(plane
);
765 const struct vop_win_data
*win
= vop_win
->data
;
772 vop
= to_vop(plane
->crtc
);
774 ret
= drm_vblank_get(plane
->dev
, vop
->pipe
);
776 DRM_ERROR("failed to get vblank, %d\n", ret
);
780 mutex_lock(&vop
->vsync_mutex
);
782 ret
= vop_win_queue_fb(vop_win
, NULL
, 0, NULL
);
784 drm_vblank_put(plane
->dev
, vop
->pipe
);
785 mutex_unlock(&vop
->vsync_mutex
);
789 vop
->vsync_work_pending
= true;
790 mutex_unlock(&vop
->vsync_mutex
);
792 spin_lock(&vop
->reg_lock
);
793 VOP_WIN_SET(vop
, win
, enable
, 0);
795 spin_unlock(&vop
->reg_lock
);
800 static void vop_plane_destroy(struct drm_plane
*plane
)
802 vop_disable_plane(plane
);
803 drm_plane_cleanup(plane
);
806 static const struct drm_plane_funcs vop_plane_funcs
= {
807 .update_plane
= vop_update_plane
,
808 .disable_plane
= vop_disable_plane
,
809 .destroy
= vop_plane_destroy
,
812 int rockchip_drm_crtc_mode_config(struct drm_crtc
*crtc
,
816 struct vop
*vop
= to_vop(crtc
);
818 vop
->connector_type
= connector_type
;
819 vop
->connector_out_mode
= out_mode
;
823 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config
);
825 static int vop_crtc_enable_vblank(struct drm_crtc
*crtc
)
827 struct vop
*vop
= to_vop(crtc
);
830 if (!vop
->is_enabled
)
833 spin_lock_irqsave(&vop
->irq_lock
, flags
);
835 vop_mask_write(vop
, INTR_CTRL0
, FS_INTR_MASK
, FS_INTR_EN(1));
837 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
842 static void vop_crtc_disable_vblank(struct drm_crtc
*crtc
)
844 struct vop
*vop
= to_vop(crtc
);
847 if (!vop
->is_enabled
)
850 spin_lock_irqsave(&vop
->irq_lock
, flags
);
851 vop_mask_write(vop
, INTR_CTRL0
, FS_INTR_MASK
, FS_INTR_EN(0));
852 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
855 static const struct rockchip_crtc_funcs private_crtc_funcs
= {
856 .enable_vblank
= vop_crtc_enable_vblank
,
857 .disable_vblank
= vop_crtc_disable_vblank
,
860 static void vop_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
862 DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc
->base
.id
, mode
);
865 case DRM_MODE_DPMS_ON
:
868 case DRM_MODE_DPMS_STANDBY
:
869 case DRM_MODE_DPMS_SUSPEND
:
870 case DRM_MODE_DPMS_OFF
:
874 DRM_DEBUG_KMS("unspecified mode %d\n", mode
);
879 static void vop_crtc_prepare(struct drm_crtc
*crtc
)
881 vop_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
884 static bool vop_crtc_mode_fixup(struct drm_crtc
*crtc
,
885 const struct drm_display_mode
*mode
,
886 struct drm_display_mode
*adjusted_mode
)
888 if (adjusted_mode
->htotal
== 0 || adjusted_mode
->vtotal
== 0)
894 static int vop_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
895 struct drm_framebuffer
*old_fb
)
902 ret
= vop_update_primary_plane(crtc
, NULL
);
904 DRM_ERROR("fail to update plane\n");
911 static int vop_crtc_mode_set(struct drm_crtc
*crtc
,
912 struct drm_display_mode
*mode
,
913 struct drm_display_mode
*adjusted_mode
,
914 int x
, int y
, struct drm_framebuffer
*fb
)
916 struct vop
*vop
= to_vop(crtc
);
917 u16 hsync_len
= adjusted_mode
->hsync_end
- adjusted_mode
->hsync_start
;
918 u16 hdisplay
= adjusted_mode
->hdisplay
;
919 u16 htotal
= adjusted_mode
->htotal
;
920 u16 hact_st
= adjusted_mode
->htotal
- adjusted_mode
->hsync_start
;
921 u16 hact_end
= hact_st
+ hdisplay
;
922 u16 vdisplay
= adjusted_mode
->vdisplay
;
923 u16 vtotal
= adjusted_mode
->vtotal
;
924 u16 vsync_len
= adjusted_mode
->vsync_end
- adjusted_mode
->vsync_start
;
925 u16 vact_st
= adjusted_mode
->vtotal
- adjusted_mode
->vsync_start
;
926 u16 vact_end
= vact_st
+ vdisplay
;
931 * disable dclk to stop frame scan, so that we can safe config mode and
934 clk_disable(vop
->dclk
);
936 switch (vop
->connector_type
) {
937 case DRM_MODE_CONNECTOR_LVDS
:
938 VOP_CTRL_SET(vop
, rgb_en
, 1);
940 case DRM_MODE_CONNECTOR_eDP
:
941 VOP_CTRL_SET(vop
, edp_en
, 1);
943 case DRM_MODE_CONNECTOR_HDMIA
:
944 VOP_CTRL_SET(vop
, hdmi_en
, 1);
947 DRM_ERROR("unsupport connector_type[%d]\n",
948 vop
->connector_type
);
952 VOP_CTRL_SET(vop
, out_mode
, vop
->connector_out_mode
);
955 val
|= (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
) ? 0 : 1;
956 val
|= (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
) ? 0 : (1 << 1);
957 VOP_CTRL_SET(vop
, pin_pol
, val
);
959 VOP_CTRL_SET(vop
, htotal_pw
, (htotal
<< 16) | hsync_len
);
962 VOP_CTRL_SET(vop
, hact_st_end
, val
);
963 VOP_CTRL_SET(vop
, hpost_st_end
, val
);
965 VOP_CTRL_SET(vop
, vtotal_pw
, (vtotal
<< 16) | vsync_len
);
968 VOP_CTRL_SET(vop
, vact_st_end
, val
);
969 VOP_CTRL_SET(vop
, vpost_st_end
, val
);
971 ret
= vop_crtc_mode_set_base(crtc
, x
, y
, fb
);
976 * reset dclk, take all mode config affect, so the clk would run in
979 reset_control_assert(vop
->dclk_rst
);
980 usleep_range(10, 20);
981 reset_control_deassert(vop
->dclk_rst
);
983 clk_set_rate(vop
->dclk
, adjusted_mode
->clock
* 1000);
985 ret_clk
= clk_enable(vop
->dclk
);
987 dev_err(vop
->dev
, "failed to enable dclk - %d\n", ret_clk
);
994 static void vop_crtc_commit(struct drm_crtc
*crtc
)
998 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs
= {
999 .dpms
= vop_crtc_dpms
,
1000 .prepare
= vop_crtc_prepare
,
1001 .mode_fixup
= vop_crtc_mode_fixup
,
1002 .mode_set
= vop_crtc_mode_set
,
1003 .mode_set_base
= vop_crtc_mode_set_base
,
1004 .commit
= vop_crtc_commit
,
1007 static int vop_crtc_page_flip(struct drm_crtc
*crtc
,
1008 struct drm_framebuffer
*fb
,
1009 struct drm_pending_vblank_event
*event
,
1010 uint32_t page_flip_flags
)
1012 struct vop
*vop
= to_vop(crtc
);
1013 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
1016 /* when the page flip is requested, crtc should be on */
1017 if (!vop
->is_enabled
) {
1018 DRM_DEBUG("page flip request rejected because crtc is off.\n");
1022 crtc
->primary
->fb
= fb
;
1024 ret
= vop_update_primary_plane(crtc
, event
);
1026 crtc
->primary
->fb
= old_fb
;
1031 static void vop_win_state_complete(struct vop_win
*vop_win
,
1032 struct vop_win_state
*state
)
1034 struct vop
*vop
= vop_win
->vop
;
1035 struct drm_crtc
*crtc
= &vop
->crtc
;
1036 struct drm_device
*drm
= crtc
->dev
;
1037 unsigned long flags
;
1040 spin_lock_irqsave(&drm
->event_lock
, flags
);
1041 drm_send_vblank_event(drm
, -1, state
->event
);
1042 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
1045 list_del(&state
->head
);
1046 drm_vblank_put(crtc
->dev
, vop
->pipe
);
1049 static void vop_crtc_destroy(struct drm_crtc
*crtc
)
1051 drm_crtc_cleanup(crtc
);
1054 static const struct drm_crtc_funcs vop_crtc_funcs
= {
1055 .set_config
= drm_crtc_helper_set_config
,
1056 .page_flip
= vop_crtc_page_flip
,
1057 .destroy
= vop_crtc_destroy
,
1060 static bool vop_win_state_is_active(struct vop_win
*vop_win
,
1061 struct vop_win_state
*state
)
1063 bool active
= false;
1066 dma_addr_t yrgb_mst
;
1068 /* check yrgb_mst to tell if pending_fb is now front */
1069 yrgb_mst
= VOP_WIN_GET_YRGBADDR(vop_win
->vop
, vop_win
->data
);
1071 active
= (yrgb_mst
== state
->yrgb_mst
);
1075 /* if enable bit is clear, plane is now disabled */
1076 enabled
= VOP_WIN_GET(vop_win
->vop
, vop_win
->data
, enable
);
1078 active
= (enabled
== 0);
1084 static void vop_win_state_destroy(struct vop_win_state
*state
)
1086 struct drm_framebuffer
*fb
= state
->fb
;
1089 drm_framebuffer_unreference(fb
);
1094 static void vop_win_update_state(struct vop_win
*vop_win
)
1096 struct vop_win_state
*state
, *n
, *new_active
= NULL
;
1098 /* Check if any pending states are now active */
1099 list_for_each_entry(state
, &vop_win
->pending
, head
)
1100 if (vop_win_state_is_active(vop_win
, state
)) {
1109 * Destroy any 'skipped' pending states - states that were queued
1110 * before the newly active state.
1112 list_for_each_entry_safe(state
, n
, &vop_win
->pending
, head
) {
1113 if (state
== new_active
)
1115 vop_win_state_complete(vop_win
, state
);
1116 vop_win_state_destroy(state
);
1119 vop_win_state_complete(vop_win
, new_active
);
1121 if (vop_win
->active
)
1122 vop_win_state_destroy(vop_win
->active
);
1123 vop_win
->active
= new_active
;
1126 static bool vop_win_has_pending_state(struct vop_win
*vop_win
)
1128 return !list_empty(&vop_win
->pending
);
1131 static irqreturn_t
vop_isr_thread(int irq
, void *data
)
1133 struct vop
*vop
= data
;
1134 const struct vop_data
*vop_data
= vop
->data
;
1137 mutex_lock(&vop
->vsync_mutex
);
1139 if (!vop
->vsync_work_pending
)
1142 vop
->vsync_work_pending
= false;
1144 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1145 struct vop_win
*vop_win
= &vop
->win
[i
];
1147 vop_win_update_state(vop_win
);
1148 if (vop_win_has_pending_state(vop_win
))
1149 vop
->vsync_work_pending
= true;
1153 mutex_unlock(&vop
->vsync_mutex
);
1158 static irqreturn_t
vop_isr(int irq
, void *data
)
1160 struct vop
*vop
= data
;
1161 uint32_t intr0_reg
, active_irqs
;
1162 unsigned long flags
;
1166 * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1167 * must hold irq_lock to avoid a race with enable/disable_vblank().
1169 spin_lock_irqsave(&vop
->irq_lock
, flags
);
1170 intr0_reg
= vop_readl(vop
, INTR_CTRL0
);
1171 active_irqs
= intr0_reg
& INTR_MASK
;
1172 /* Clear all active interrupt sources */
1174 vop_writel(vop
, INTR_CTRL0
,
1175 intr0_reg
| (active_irqs
<< INTR_CLR_SHIFT
));
1176 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
1178 /* This is expected for vop iommu irqs, since the irq is shared */
1182 if (active_irqs
& DSP_HOLD_VALID_INTR
) {
1183 complete(&vop
->dsp_hold_completion
);
1184 active_irqs
&= ~DSP_HOLD_VALID_INTR
;
1188 if (active_irqs
& FS_INTR
) {
1189 drm_handle_vblank(vop
->drm_dev
, vop
->pipe
);
1190 active_irqs
&= ~FS_INTR
;
1191 ret
= (vop
->vsync_work_pending
) ? IRQ_WAKE_THREAD
: IRQ_HANDLED
;
1194 /* Unhandled irqs are spurious. */
1196 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs
);
1201 static int vop_create_crtc(struct vop
*vop
)
1203 const struct vop_data
*vop_data
= vop
->data
;
1204 struct device
*dev
= vop
->dev
;
1205 struct drm_device
*drm_dev
= vop
->drm_dev
;
1206 struct drm_plane
*primary
= NULL
, *cursor
= NULL
, *plane
;
1207 struct drm_crtc
*crtc
= &vop
->crtc
;
1208 struct device_node
*port
;
1213 * Create drm_plane for primary and cursor planes first, since we need
1214 * to pass them to drm_crtc_init_with_planes, which sets the
1215 * "possible_crtcs" to the newly initialized crtc.
1217 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1218 struct vop_win
*vop_win
= &vop
->win
[i
];
1219 const struct vop_win_data
*win_data
= vop_win
->data
;
1221 if (win_data
->type
!= DRM_PLANE_TYPE_PRIMARY
&&
1222 win_data
->type
!= DRM_PLANE_TYPE_CURSOR
)
1225 ret
= drm_universal_plane_init(vop
->drm_dev
, &vop_win
->base
,
1226 0, &vop_plane_funcs
,
1227 win_data
->phy
->data_formats
,
1228 win_data
->phy
->nformats
,
1231 DRM_ERROR("failed to initialize plane\n");
1232 goto err_cleanup_planes
;
1235 plane
= &vop_win
->base
;
1236 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
)
1238 else if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
1242 ret
= drm_crtc_init_with_planes(drm_dev
, crtc
, primary
, cursor
,
1247 drm_crtc_helper_add(crtc
, &vop_crtc_helper_funcs
);
1250 * Create drm_planes for overlay windows with possible_crtcs restricted
1251 * to the newly created crtc.
1253 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1254 struct vop_win
*vop_win
= &vop
->win
[i
];
1255 const struct vop_win_data
*win_data
= vop_win
->data
;
1256 unsigned long possible_crtcs
= 1 << drm_crtc_index(crtc
);
1258 if (win_data
->type
!= DRM_PLANE_TYPE_OVERLAY
)
1261 ret
= drm_universal_plane_init(vop
->drm_dev
, &vop_win
->base
,
1264 win_data
->phy
->data_formats
,
1265 win_data
->phy
->nformats
,
1268 DRM_ERROR("failed to initialize overlay plane\n");
1269 goto err_cleanup_crtc
;
1273 port
= of_get_child_by_name(dev
->of_node
, "port");
1275 DRM_ERROR("no port node found in %s\n",
1276 dev
->of_node
->full_name
);
1277 goto err_cleanup_crtc
;
1280 init_completion(&vop
->dsp_hold_completion
);
1282 vop
->pipe
= drm_crtc_index(crtc
);
1283 rockchip_register_crtc_funcs(drm_dev
, &private_crtc_funcs
, vop
->pipe
);
1288 drm_crtc_cleanup(crtc
);
1290 list_for_each_entry(plane
, &drm_dev
->mode_config
.plane_list
, head
)
1291 drm_plane_cleanup(plane
);
1295 static void vop_destroy_crtc(struct vop
*vop
)
1297 struct drm_crtc
*crtc
= &vop
->crtc
;
1299 rockchip_unregister_crtc_funcs(vop
->drm_dev
, vop
->pipe
);
1300 of_node_put(crtc
->port
);
1301 drm_crtc_cleanup(crtc
);
1304 static int vop_initial(struct vop
*vop
)
1306 const struct vop_data
*vop_data
= vop
->data
;
1307 const struct vop_reg_data
*init_table
= vop_data
->init_table
;
1308 struct reset_control
*ahb_rst
;
1311 vop
->hclk
= devm_clk_get(vop
->dev
, "hclk_vop");
1312 if (IS_ERR(vop
->hclk
)) {
1313 dev_err(vop
->dev
, "failed to get hclk source\n");
1314 return PTR_ERR(vop
->hclk
);
1316 vop
->aclk
= devm_clk_get(vop
->dev
, "aclk_vop");
1317 if (IS_ERR(vop
->aclk
)) {
1318 dev_err(vop
->dev
, "failed to get aclk source\n");
1319 return PTR_ERR(vop
->aclk
);
1321 vop
->dclk
= devm_clk_get(vop
->dev
, "dclk_vop");
1322 if (IS_ERR(vop
->dclk
)) {
1323 dev_err(vop
->dev
, "failed to get dclk source\n");
1324 return PTR_ERR(vop
->dclk
);
1327 ret
= clk_prepare(vop
->hclk
);
1329 dev_err(vop
->dev
, "failed to prepare hclk\n");
1333 ret
= clk_prepare(vop
->dclk
);
1335 dev_err(vop
->dev
, "failed to prepare dclk\n");
1336 goto err_unprepare_hclk
;
1339 ret
= clk_prepare(vop
->aclk
);
1341 dev_err(vop
->dev
, "failed to prepare aclk\n");
1342 goto err_unprepare_dclk
;
1346 * enable hclk, so that we can config vop register.
1348 ret
= clk_enable(vop
->hclk
);
1350 dev_err(vop
->dev
, "failed to prepare aclk\n");
1351 goto err_unprepare_aclk
;
1354 * do hclk_reset, reset all vop registers.
1356 ahb_rst
= devm_reset_control_get(vop
->dev
, "ahb");
1357 if (IS_ERR(ahb_rst
)) {
1358 dev_err(vop
->dev
, "failed to get ahb reset\n");
1359 ret
= PTR_ERR(ahb_rst
);
1360 goto err_disable_hclk
;
1362 reset_control_assert(ahb_rst
);
1363 usleep_range(10, 20);
1364 reset_control_deassert(ahb_rst
);
1366 memcpy(vop
->regsbak
, vop
->regs
, vop
->len
);
1368 for (i
= 0; i
< vop_data
->table_size
; i
++)
1369 vop_writel(vop
, init_table
[i
].offset
, init_table
[i
].value
);
1371 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1372 const struct vop_win_data
*win
= &vop_data
->win
[i
];
1374 VOP_WIN_SET(vop
, win
, enable
, 0);
1380 * do dclk_reset, let all config take affect.
1382 vop
->dclk_rst
= devm_reset_control_get(vop
->dev
, "dclk");
1383 if (IS_ERR(vop
->dclk_rst
)) {
1384 dev_err(vop
->dev
, "failed to get dclk reset\n");
1385 ret
= PTR_ERR(vop
->dclk_rst
);
1386 goto err_unprepare_aclk
;
1388 reset_control_assert(vop
->dclk_rst
);
1389 usleep_range(10, 20);
1390 reset_control_deassert(vop
->dclk_rst
);
1392 clk_disable(vop
->hclk
);
1394 vop
->is_enabled
= false;
1399 clk_disable(vop
->hclk
);
1401 clk_unprepare(vop
->aclk
);
1403 clk_unprepare(vop
->dclk
);
1405 clk_unprepare(vop
->hclk
);
1410 * Initialize the vop->win array elements.
1412 static void vop_win_init(struct vop
*vop
)
1414 const struct vop_data
*vop_data
= vop
->data
;
1417 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1418 struct vop_win
*vop_win
= &vop
->win
[i
];
1419 const struct vop_win_data
*win_data
= &vop_data
->win
[i
];
1421 vop_win
->data
= win_data
;
1423 INIT_LIST_HEAD(&vop_win
->pending
);
1427 static int vop_bind(struct device
*dev
, struct device
*master
, void *data
)
1429 struct platform_device
*pdev
= to_platform_device(dev
);
1430 const struct of_device_id
*of_id
;
1431 const struct vop_data
*vop_data
;
1432 struct drm_device
*drm_dev
= data
;
1434 struct resource
*res
;
1438 of_id
= of_match_device(vop_driver_dt_match
, dev
);
1439 vop_data
= of_id
->data
;
1443 /* Allocate vop struct and its vop_win array */
1444 alloc_size
= sizeof(*vop
) + sizeof(*vop
->win
) * vop_data
->win_size
;
1445 vop
= devm_kzalloc(dev
, alloc_size
, GFP_KERNEL
);
1450 vop
->data
= vop_data
;
1451 vop
->drm_dev
= drm_dev
;
1452 dev_set_drvdata(dev
, vop
);
1456 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1457 vop
->len
= resource_size(res
);
1458 vop
->regs
= devm_ioremap_resource(dev
, res
);
1459 if (IS_ERR(vop
->regs
))
1460 return PTR_ERR(vop
->regs
);
1462 vop
->regsbak
= devm_kzalloc(dev
, vop
->len
, GFP_KERNEL
);
1466 ret
= vop_initial(vop
);
1468 dev_err(&pdev
->dev
, "cannot initial vop dev - err %d\n", ret
);
1472 irq
= platform_get_irq(pdev
, 0);
1474 dev_err(dev
, "cannot find irq for vop\n");
1477 vop
->irq
= (unsigned int)irq
;
1479 spin_lock_init(&vop
->reg_lock
);
1480 spin_lock_init(&vop
->irq_lock
);
1482 mutex_init(&vop
->vsync_mutex
);
1484 ret
= devm_request_threaded_irq(dev
, vop
->irq
, vop_isr
, vop_isr_thread
,
1485 IRQF_SHARED
, dev_name(dev
), vop
);
1489 /* IRQ is initially disabled; it gets enabled in power_on */
1490 disable_irq(vop
->irq
);
1492 ret
= vop_create_crtc(vop
);
1496 pm_runtime_enable(&pdev
->dev
);
1500 static void vop_unbind(struct device
*dev
, struct device
*master
, void *data
)
1502 struct vop
*vop
= dev_get_drvdata(dev
);
1504 pm_runtime_disable(dev
);
1505 vop_destroy_crtc(vop
);
1508 static const struct component_ops vop_component_ops
= {
1510 .unbind
= vop_unbind
,
1513 static int vop_probe(struct platform_device
*pdev
)
1515 struct device
*dev
= &pdev
->dev
;
1517 if (!dev
->of_node
) {
1518 dev_err(dev
, "can't find vop devices\n");
1522 return component_add(dev
, &vop_component_ops
);
1525 static int vop_remove(struct platform_device
*pdev
)
1527 component_del(&pdev
->dev
, &vop_component_ops
);
1532 struct platform_driver vop_platform_driver
= {
1534 .remove
= vop_remove
,
1536 .name
= "rockchip-vop",
1537 .owner
= THIS_MODULE
,
1538 .of_match_table
= of_match_ptr(vop_driver_dt_match
),
1542 module_platform_driver(vop_platform_driver
);
1544 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1545 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1546 MODULE_LICENSE("GPL v2");