2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
34 #include "rockchip_drm_drv.h"
35 #include "rockchip_drm_gem.h"
36 #include "rockchip_drm_fb.h"
37 #include "rockchip_drm_vop.h"
39 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
40 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
41 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
42 vop_mask_write(x, off, (mask) << shift, (v) << shift)
44 #define REG_SET(x, base, reg, v, mode) \
45 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
46 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
47 __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v)
49 #define VOP_WIN_SET(x, win, name, v) \
50 REG_SET(x, win->base, win->phy->name, v, RELAXED)
51 #define VOP_SCL_SET(x, win, name, v) \
52 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
53 #define VOP_SCL_SET_EXT(x, win, name, v) \
54 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
55 #define VOP_CTRL_SET(x, name, v) \
56 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
58 #define VOP_INTR_GET(vop, name) \
59 vop_read_reg(vop, 0, &vop->data->ctrl->name)
61 #define VOP_INTR_SET(vop, name, mask, v) \
62 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
63 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
65 int i, reg = 0, mask = 0; \
66 for (i = 0; i < vop->data->intr->nintrs; i++) { \
67 if (vop->data->intr->intrs[i] & type) { \
72 VOP_INTR_SET(vop, name, mask, reg); \
74 #define VOP_INTR_GET_TYPE(vop, name, type) \
75 vop_get_intr_type(vop, &vop->data->intr->name, type)
77 #define VOP_WIN_GET(x, win, name) \
78 vop_read_reg(x, win->base, &win->phy->name)
80 #define VOP_WIN_GET_YRGBADDR(vop, win) \
81 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
83 #define to_vop(x) container_of(x, struct vop, crtc)
84 #define to_vop_win(x) container_of(x, struct vop_win, base)
85 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
87 struct vop_plane_state
{
88 struct drm_plane_state base
;
97 struct drm_plane base
;
98 const struct vop_win_data
*data
;
101 /* protected by dev->event_lock */
107 struct drm_crtc crtc
;
109 struct drm_device
*drm_dev
;
112 /* mutex vsync_ work */
113 struct mutex vsync_mutex
;
114 bool vsync_work_pending
;
115 struct completion dsp_hold_completion
;
116 struct completion wait_update_complete
;
118 /* protected by dev->event_lock */
119 struct drm_pending_vblank_event
*event
;
121 const struct vop_data
*data
;
126 /* physical map length of vop register */
129 /* one time only one process allowed to config the register */
131 /* lock vop irq reg */
140 /* vop share memory frequency */
144 struct reset_control
*dclk_rst
;
146 struct vop_win win
[];
149 static inline void vop_writel(struct vop
*vop
, uint32_t offset
, uint32_t v
)
151 writel(v
, vop
->regs
+ offset
);
152 vop
->regsbak
[offset
>> 2] = v
;
155 static inline uint32_t vop_readl(struct vop
*vop
, uint32_t offset
)
157 return readl(vop
->regs
+ offset
);
160 static inline uint32_t vop_read_reg(struct vop
*vop
, uint32_t base
,
161 const struct vop_reg
*reg
)
163 return (vop_readl(vop
, base
+ reg
->offset
) >> reg
->shift
) & reg
->mask
;
166 static inline void vop_mask_write(struct vop
*vop
, uint32_t offset
,
167 uint32_t mask
, uint32_t v
)
170 uint32_t cached_val
= vop
->regsbak
[offset
>> 2];
172 cached_val
= (cached_val
& ~mask
) | v
;
173 writel(cached_val
, vop
->regs
+ offset
);
174 vop
->regsbak
[offset
>> 2] = cached_val
;
178 static inline void vop_mask_write_relaxed(struct vop
*vop
, uint32_t offset
,
179 uint32_t mask
, uint32_t v
)
182 uint32_t cached_val
= vop
->regsbak
[offset
>> 2];
184 cached_val
= (cached_val
& ~mask
) | v
;
185 writel_relaxed(cached_val
, vop
->regs
+ offset
);
186 vop
->regsbak
[offset
>> 2] = cached_val
;
190 static inline uint32_t vop_get_intr_type(struct vop
*vop
,
191 const struct vop_reg
*reg
, int type
)
194 uint32_t regs
= vop_read_reg(vop
, 0, reg
);
196 for (i
= 0; i
< vop
->data
->intr
->nintrs
; i
++) {
197 if ((type
& vop
->data
->intr
->intrs
[i
]) && (regs
& 1 << i
))
198 ret
|= vop
->data
->intr
->intrs
[i
];
204 static inline void vop_cfg_done(struct vop
*vop
)
206 VOP_CTRL_SET(vop
, cfg_done
, 1);
209 static bool has_rb_swapped(uint32_t format
)
212 case DRM_FORMAT_XBGR8888
:
213 case DRM_FORMAT_ABGR8888
:
214 case DRM_FORMAT_BGR888
:
215 case DRM_FORMAT_BGR565
:
222 static enum vop_data_format
vop_convert_format(uint32_t format
)
225 case DRM_FORMAT_XRGB8888
:
226 case DRM_FORMAT_ARGB8888
:
227 case DRM_FORMAT_XBGR8888
:
228 case DRM_FORMAT_ABGR8888
:
229 return VOP_FMT_ARGB8888
;
230 case DRM_FORMAT_RGB888
:
231 case DRM_FORMAT_BGR888
:
232 return VOP_FMT_RGB888
;
233 case DRM_FORMAT_RGB565
:
234 case DRM_FORMAT_BGR565
:
235 return VOP_FMT_RGB565
;
236 case DRM_FORMAT_NV12
:
237 return VOP_FMT_YUV420SP
;
238 case DRM_FORMAT_NV16
:
239 return VOP_FMT_YUV422SP
;
240 case DRM_FORMAT_NV24
:
241 return VOP_FMT_YUV444SP
;
243 DRM_ERROR("unsupport format[%08x]\n", format
);
248 static bool is_yuv_support(uint32_t format
)
251 case DRM_FORMAT_NV12
:
252 case DRM_FORMAT_NV16
:
253 case DRM_FORMAT_NV24
:
260 static bool is_alpha_support(uint32_t format
)
263 case DRM_FORMAT_ARGB8888
:
264 case DRM_FORMAT_ABGR8888
:
271 static uint16_t scl_vop_cal_scale(enum scale_mode mode
, uint32_t src
,
272 uint32_t dst
, bool is_horizontal
,
273 int vsu_mode
, int *vskiplines
)
275 uint16_t val
= 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT
;
278 if (mode
== SCALE_UP
)
279 val
= GET_SCL_FT_BIC(src
, dst
);
280 else if (mode
== SCALE_DOWN
)
281 val
= GET_SCL_FT_BILI_DN(src
, dst
);
283 if (mode
== SCALE_UP
) {
284 if (vsu_mode
== SCALE_UP_BIL
)
285 val
= GET_SCL_FT_BILI_UP(src
, dst
);
287 val
= GET_SCL_FT_BIC(src
, dst
);
288 } else if (mode
== SCALE_DOWN
) {
290 *vskiplines
= scl_get_vskiplines(src
, dst
);
291 val
= scl_get_bili_dn_vskip(src
, dst
,
294 val
= GET_SCL_FT_BILI_DN(src
, dst
);
302 static void scl_vop_cal_scl_fac(struct vop
*vop
, const struct vop_win_data
*win
,
303 uint32_t src_w
, uint32_t src_h
, uint32_t dst_w
,
304 uint32_t dst_h
, uint32_t pixel_format
)
306 uint16_t yrgb_hor_scl_mode
, yrgb_ver_scl_mode
;
307 uint16_t cbcr_hor_scl_mode
= SCALE_NONE
;
308 uint16_t cbcr_ver_scl_mode
= SCALE_NONE
;
309 int hsub
= drm_format_horz_chroma_subsampling(pixel_format
);
310 int vsub
= drm_format_vert_chroma_subsampling(pixel_format
);
311 bool is_yuv
= is_yuv_support(pixel_format
);
312 uint16_t cbcr_src_w
= src_w
/ hsub
;
313 uint16_t cbcr_src_h
= src_h
/ vsub
;
320 DRM_ERROR("Maximum destination width (3840) exceeded\n");
324 if (!win
->phy
->scl
->ext
) {
325 VOP_SCL_SET(vop
, win
, scale_yrgb_x
,
326 scl_cal_scale2(src_w
, dst_w
));
327 VOP_SCL_SET(vop
, win
, scale_yrgb_y
,
328 scl_cal_scale2(src_h
, dst_h
));
330 VOP_SCL_SET(vop
, win
, scale_cbcr_x
,
331 scl_cal_scale2(src_w
, dst_w
));
332 VOP_SCL_SET(vop
, win
, scale_cbcr_y
,
333 scl_cal_scale2(src_h
, dst_h
));
338 yrgb_hor_scl_mode
= scl_get_scl_mode(src_w
, dst_w
);
339 yrgb_ver_scl_mode
= scl_get_scl_mode(src_h
, dst_h
);
342 cbcr_hor_scl_mode
= scl_get_scl_mode(cbcr_src_w
, dst_w
);
343 cbcr_ver_scl_mode
= scl_get_scl_mode(cbcr_src_h
, dst_h
);
344 if (cbcr_hor_scl_mode
== SCALE_DOWN
)
345 lb_mode
= scl_vop_cal_lb_mode(dst_w
, true);
347 lb_mode
= scl_vop_cal_lb_mode(cbcr_src_w
, true);
349 if (yrgb_hor_scl_mode
== SCALE_DOWN
)
350 lb_mode
= scl_vop_cal_lb_mode(dst_w
, false);
352 lb_mode
= scl_vop_cal_lb_mode(src_w
, false);
355 VOP_SCL_SET_EXT(vop
, win
, lb_mode
, lb_mode
);
356 if (lb_mode
== LB_RGB_3840X2
) {
357 if (yrgb_ver_scl_mode
!= SCALE_NONE
) {
358 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
361 if (cbcr_ver_scl_mode
!= SCALE_NONE
) {
362 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
365 vsu_mode
= SCALE_UP_BIL
;
366 } else if (lb_mode
== LB_RGB_2560X4
) {
367 vsu_mode
= SCALE_UP_BIL
;
369 vsu_mode
= SCALE_UP_BIC
;
372 val
= scl_vop_cal_scale(yrgb_hor_scl_mode
, src_w
, dst_w
,
374 VOP_SCL_SET(vop
, win
, scale_yrgb_x
, val
);
375 val
= scl_vop_cal_scale(yrgb_ver_scl_mode
, src_h
, dst_h
,
376 false, vsu_mode
, &vskiplines
);
377 VOP_SCL_SET(vop
, win
, scale_yrgb_y
, val
);
379 VOP_SCL_SET_EXT(vop
, win
, vsd_yrgb_gt4
, vskiplines
== 4);
380 VOP_SCL_SET_EXT(vop
, win
, vsd_yrgb_gt2
, vskiplines
== 2);
382 VOP_SCL_SET_EXT(vop
, win
, yrgb_hor_scl_mode
, yrgb_hor_scl_mode
);
383 VOP_SCL_SET_EXT(vop
, win
, yrgb_ver_scl_mode
, yrgb_ver_scl_mode
);
384 VOP_SCL_SET_EXT(vop
, win
, yrgb_hsd_mode
, SCALE_DOWN_BIL
);
385 VOP_SCL_SET_EXT(vop
, win
, yrgb_vsd_mode
, SCALE_DOWN_BIL
);
386 VOP_SCL_SET_EXT(vop
, win
, yrgb_vsu_mode
, vsu_mode
);
388 val
= scl_vop_cal_scale(cbcr_hor_scl_mode
, cbcr_src_w
,
389 dst_w
, true, 0, NULL
);
390 VOP_SCL_SET(vop
, win
, scale_cbcr_x
, val
);
391 val
= scl_vop_cal_scale(cbcr_ver_scl_mode
, cbcr_src_h
,
392 dst_h
, false, vsu_mode
, &vskiplines
);
393 VOP_SCL_SET(vop
, win
, scale_cbcr_y
, val
);
395 VOP_SCL_SET_EXT(vop
, win
, vsd_cbcr_gt4
, vskiplines
== 4);
396 VOP_SCL_SET_EXT(vop
, win
, vsd_cbcr_gt2
, vskiplines
== 2);
397 VOP_SCL_SET_EXT(vop
, win
, cbcr_hor_scl_mode
, cbcr_hor_scl_mode
);
398 VOP_SCL_SET_EXT(vop
, win
, cbcr_ver_scl_mode
, cbcr_ver_scl_mode
);
399 VOP_SCL_SET_EXT(vop
, win
, cbcr_hsd_mode
, SCALE_DOWN_BIL
);
400 VOP_SCL_SET_EXT(vop
, win
, cbcr_vsd_mode
, SCALE_DOWN_BIL
);
401 VOP_SCL_SET_EXT(vop
, win
, cbcr_vsu_mode
, vsu_mode
);
405 static void vop_dsp_hold_valid_irq_enable(struct vop
*vop
)
409 if (WARN_ON(!vop
->is_enabled
))
412 spin_lock_irqsave(&vop
->irq_lock
, flags
);
414 VOP_INTR_SET_TYPE(vop
, enable
, DSP_HOLD_VALID_INTR
, 1);
416 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
419 static void vop_dsp_hold_valid_irq_disable(struct vop
*vop
)
423 if (WARN_ON(!vop
->is_enabled
))
426 spin_lock_irqsave(&vop
->irq_lock
, flags
);
428 VOP_INTR_SET_TYPE(vop
, enable
, DSP_HOLD_VALID_INTR
, 0);
430 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
433 static void vop_enable(struct drm_crtc
*crtc
)
435 struct vop
*vop
= to_vop(crtc
);
438 ret
= pm_runtime_get_sync(vop
->dev
);
440 dev_err(vop
->dev
, "failed to get pm runtime: %d\n", ret
);
444 ret
= clk_enable(vop
->hclk
);
446 dev_err(vop
->dev
, "failed to enable hclk - %d\n", ret
);
450 ret
= clk_enable(vop
->dclk
);
452 dev_err(vop
->dev
, "failed to enable dclk - %d\n", ret
);
453 goto err_disable_hclk
;
456 ret
= clk_enable(vop
->aclk
);
458 dev_err(vop
->dev
, "failed to enable aclk - %d\n", ret
);
459 goto err_disable_dclk
;
463 * Slave iommu shares power, irq and clock with vop. It was associated
464 * automatically with this master device via common driver code.
465 * Now that we have enabled the clock we attach it to the shared drm
468 ret
= rockchip_drm_dma_attach_device(vop
->drm_dev
, vop
->dev
);
470 dev_err(vop
->dev
, "failed to attach dma mapping, %d\n", ret
);
471 goto err_disable_aclk
;
474 memcpy(vop
->regs
, vop
->regsbak
, vop
->len
);
476 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
478 vop
->is_enabled
= true;
480 spin_lock(&vop
->reg_lock
);
482 VOP_CTRL_SET(vop
, standby
, 0);
484 spin_unlock(&vop
->reg_lock
);
486 enable_irq(vop
->irq
);
488 drm_crtc_vblank_on(crtc
);
493 clk_disable(vop
->aclk
);
495 clk_disable(vop
->dclk
);
497 clk_disable(vop
->hclk
);
500 static void vop_crtc_disable(struct drm_crtc
*crtc
)
502 struct vop
*vop
= to_vop(crtc
);
508 * We need to make sure that all windows are disabled before we
509 * disable that crtc. Otherwise we might try to scan from a destroyed
512 for (i
= 0; i
< vop
->data
->win_size
; i
++) {
513 struct vop_win
*vop_win
= &vop
->win
[i
];
514 const struct vop_win_data
*win
= vop_win
->data
;
516 spin_lock(&vop
->reg_lock
);
517 VOP_WIN_SET(vop
, win
, enable
, 0);
518 spin_unlock(&vop
->reg_lock
);
521 drm_crtc_vblank_off(crtc
);
524 * Vop standby will take effect at end of current frame,
525 * if dsp hold valid irq happen, it means standby complete.
527 * we must wait standby complete when we want to disable aclk,
528 * if not, memory bus maybe dead.
530 reinit_completion(&vop
->dsp_hold_completion
);
531 vop_dsp_hold_valid_irq_enable(vop
);
533 spin_lock(&vop
->reg_lock
);
535 VOP_CTRL_SET(vop
, standby
, 1);
537 spin_unlock(&vop
->reg_lock
);
539 wait_for_completion(&vop
->dsp_hold_completion
);
541 vop_dsp_hold_valid_irq_disable(vop
);
543 disable_irq(vop
->irq
);
545 vop
->is_enabled
= false;
548 * vop standby complete, so iommu detach is safe.
550 rockchip_drm_dma_detach_device(vop
->drm_dev
, vop
->dev
);
552 clk_disable(vop
->dclk
);
553 clk_disable(vop
->aclk
);
554 clk_disable(vop
->hclk
);
555 pm_runtime_put(vop
->dev
);
557 if (crtc
->state
->event
&& !crtc
->state
->active
) {
558 spin_lock_irq(&crtc
->dev
->event_lock
);
559 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
560 spin_unlock_irq(&crtc
->dev
->event_lock
);
562 crtc
->state
->event
= NULL
;
566 static void vop_plane_destroy(struct drm_plane
*plane
)
568 drm_plane_cleanup(plane
);
571 static int vop_plane_prepare_fb(struct drm_plane
*plane
,
572 const struct drm_plane_state
*new_state
)
574 if (plane
->state
->fb
)
575 drm_framebuffer_reference(plane
->state
->fb
);
580 static void vop_plane_cleanup_fb(struct drm_plane
*plane
,
581 const struct drm_plane_state
*old_state
)
584 drm_framebuffer_unreference(old_state
->fb
);
587 static int vop_plane_atomic_check(struct drm_plane
*plane
,
588 struct drm_plane_state
*state
)
590 struct drm_crtc
*crtc
= state
->crtc
;
591 struct drm_crtc_state
*crtc_state
;
592 struct drm_framebuffer
*fb
= state
->fb
;
593 struct vop_win
*vop_win
= to_vop_win(plane
);
594 struct vop_plane_state
*vop_plane_state
= to_vop_plane_state(state
);
595 const struct vop_win_data
*win
= vop_win
->data
;
598 struct drm_rect
*dest
= &vop_plane_state
->dest
;
599 struct drm_rect
*src
= &vop_plane_state
->src
;
600 struct drm_rect clip
;
601 int min_scale
= win
->phy
->scl
? FRAC_16_16(1, 8) :
602 DRM_PLANE_HELPER_NO_SCALING
;
603 int max_scale
= win
->phy
->scl
? FRAC_16_16(8, 1) :
604 DRM_PLANE_HELPER_NO_SCALING
;
609 crtc_state
= drm_atomic_get_existing_crtc_state(state
->state
, crtc
);
610 if (WARN_ON(!crtc_state
))
613 src
->x1
= state
->src_x
;
614 src
->y1
= state
->src_y
;
615 src
->x2
= state
->src_x
+ state
->src_w
;
616 src
->y2
= state
->src_y
+ state
->src_h
;
617 dest
->x1
= state
->crtc_x
;
618 dest
->y1
= state
->crtc_y
;
619 dest
->x2
= state
->crtc_x
+ state
->crtc_w
;
620 dest
->y2
= state
->crtc_y
+ state
->crtc_h
;
624 clip
.x2
= crtc_state
->adjusted_mode
.hdisplay
;
625 clip
.y2
= crtc_state
->adjusted_mode
.vdisplay
;
627 ret
= drm_plane_helper_check_update(plane
, crtc
, state
->fb
,
632 true, true, &visible
);
639 vop_plane_state
->format
= vop_convert_format(fb
->pixel_format
);
640 if (vop_plane_state
->format
< 0)
641 return vop_plane_state
->format
;
644 * Src.x1 can be odd when do clip, but yuv plane start point
645 * need align with 2 pixel.
647 if (is_yuv_support(fb
->pixel_format
) && ((src
->x1
>> 16) % 2))
650 vop_plane_state
->enable
= true;
655 vop_plane_state
->enable
= false;
659 static void vop_plane_atomic_disable(struct drm_plane
*plane
,
660 struct drm_plane_state
*old_state
)
662 struct vop_plane_state
*vop_plane_state
= to_vop_plane_state(old_state
);
663 struct vop_win
*vop_win
= to_vop_win(plane
);
664 const struct vop_win_data
*win
= vop_win
->data
;
665 struct vop
*vop
= to_vop(old_state
->crtc
);
667 if (!old_state
->crtc
)
670 spin_lock_irq(&plane
->dev
->event_lock
);
671 vop_win
->enable
= false;
672 vop_win
->yrgb_mst
= 0;
673 spin_unlock_irq(&plane
->dev
->event_lock
);
675 spin_lock(&vop
->reg_lock
);
677 VOP_WIN_SET(vop
, win
, enable
, 0);
679 spin_unlock(&vop
->reg_lock
);
681 vop_plane_state
->enable
= false;
684 static void vop_plane_atomic_update(struct drm_plane
*plane
,
685 struct drm_plane_state
*old_state
)
687 struct drm_plane_state
*state
= plane
->state
;
688 struct drm_crtc
*crtc
= state
->crtc
;
689 struct vop_win
*vop_win
= to_vop_win(plane
);
690 struct vop_plane_state
*vop_plane_state
= to_vop_plane_state(state
);
691 const struct vop_win_data
*win
= vop_win
->data
;
692 struct vop
*vop
= to_vop(state
->crtc
);
693 struct drm_framebuffer
*fb
= state
->fb
;
694 unsigned int actual_w
, actual_h
;
695 unsigned int dsp_stx
, dsp_sty
;
696 uint32_t act_info
, dsp_info
, dsp_st
;
697 struct drm_rect
*src
= &vop_plane_state
->src
;
698 struct drm_rect
*dest
= &vop_plane_state
->dest
;
699 struct drm_gem_object
*obj
, *uv_obj
;
700 struct rockchip_gem_object
*rk_obj
, *rk_uv_obj
;
701 unsigned long offset
;
707 * can't update plane when vop is disabled.
712 if (WARN_ON(!vop
->is_enabled
))
715 if (!vop_plane_state
->enable
) {
716 vop_plane_atomic_disable(plane
, old_state
);
720 obj
= rockchip_fb_get_gem_obj(fb
, 0);
721 rk_obj
= to_rockchip_obj(obj
);
723 actual_w
= drm_rect_width(src
) >> 16;
724 actual_h
= drm_rect_height(src
) >> 16;
725 act_info
= (actual_h
- 1) << 16 | ((actual_w
- 1) & 0xffff);
727 dsp_info
= (drm_rect_height(dest
) - 1) << 16;
728 dsp_info
|= (drm_rect_width(dest
) - 1) & 0xffff;
730 dsp_stx
= dest
->x1
+ crtc
->mode
.htotal
- crtc
->mode
.hsync_start
;
731 dsp_sty
= dest
->y1
+ crtc
->mode
.vtotal
- crtc
->mode
.vsync_start
;
732 dsp_st
= dsp_sty
<< 16 | (dsp_stx
& 0xffff);
734 offset
= (src
->x1
>> 16) * drm_format_plane_cpp(fb
->pixel_format
, 0);
735 offset
+= (src
->y1
>> 16) * fb
->pitches
[0];
736 vop_plane_state
->yrgb_mst
= rk_obj
->dma_addr
+ offset
+ fb
->offsets
[0];
738 spin_lock_irq(&plane
->dev
->event_lock
);
739 vop_win
->enable
= true;
740 vop_win
->yrgb_mst
= vop_plane_state
->yrgb_mst
;
741 spin_unlock_irq(&plane
->dev
->event_lock
);
743 spin_lock(&vop
->reg_lock
);
745 VOP_WIN_SET(vop
, win
, format
, vop_plane_state
->format
);
746 VOP_WIN_SET(vop
, win
, yrgb_vir
, fb
->pitches
[0] >> 2);
747 VOP_WIN_SET(vop
, win
, yrgb_mst
, vop_plane_state
->yrgb_mst
);
748 if (is_yuv_support(fb
->pixel_format
)) {
749 int hsub
= drm_format_horz_chroma_subsampling(fb
->pixel_format
);
750 int vsub
= drm_format_vert_chroma_subsampling(fb
->pixel_format
);
751 int bpp
= drm_format_plane_cpp(fb
->pixel_format
, 1);
753 uv_obj
= rockchip_fb_get_gem_obj(fb
, 1);
754 rk_uv_obj
= to_rockchip_obj(uv_obj
);
756 offset
= (src
->x1
>> 16) * bpp
/ hsub
;
757 offset
+= (src
->y1
>> 16) * fb
->pitches
[1] / vsub
;
759 dma_addr
= rk_uv_obj
->dma_addr
+ offset
+ fb
->offsets
[1];
760 VOP_WIN_SET(vop
, win
, uv_vir
, fb
->pitches
[1] >> 2);
761 VOP_WIN_SET(vop
, win
, uv_mst
, dma_addr
);
765 scl_vop_cal_scl_fac(vop
, win
, actual_w
, actual_h
,
766 drm_rect_width(dest
), drm_rect_height(dest
),
769 VOP_WIN_SET(vop
, win
, act_info
, act_info
);
770 VOP_WIN_SET(vop
, win
, dsp_info
, dsp_info
);
771 VOP_WIN_SET(vop
, win
, dsp_st
, dsp_st
);
773 rb_swap
= has_rb_swapped(fb
->pixel_format
);
774 VOP_WIN_SET(vop
, win
, rb_swap
, rb_swap
);
776 if (is_alpha_support(fb
->pixel_format
)) {
777 VOP_WIN_SET(vop
, win
, dst_alpha_ctl
,
778 DST_FACTOR_M0(ALPHA_SRC_INVERSE
));
779 val
= SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL
) |
780 SRC_ALPHA_M0(ALPHA_STRAIGHT
) |
781 SRC_BLEND_M0(ALPHA_PER_PIX
) |
782 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION
) |
783 SRC_FACTOR_M0(ALPHA_ONE
);
784 VOP_WIN_SET(vop
, win
, src_alpha_ctl
, val
);
786 VOP_WIN_SET(vop
, win
, src_alpha_ctl
, SRC_ALPHA_EN(0));
789 VOP_WIN_SET(vop
, win
, enable
, 1);
790 spin_unlock(&vop
->reg_lock
);
793 static const struct drm_plane_helper_funcs plane_helper_funcs
= {
794 .prepare_fb
= vop_plane_prepare_fb
,
795 .cleanup_fb
= vop_plane_cleanup_fb
,
796 .atomic_check
= vop_plane_atomic_check
,
797 .atomic_update
= vop_plane_atomic_update
,
798 .atomic_disable
= vop_plane_atomic_disable
,
801 void vop_atomic_plane_reset(struct drm_plane
*plane
)
803 struct vop_plane_state
*vop_plane_state
=
804 to_vop_plane_state(plane
->state
);
806 if (plane
->state
&& plane
->state
->fb
)
807 drm_framebuffer_unreference(plane
->state
->fb
);
809 kfree(vop_plane_state
);
810 vop_plane_state
= kzalloc(sizeof(*vop_plane_state
), GFP_KERNEL
);
811 if (!vop_plane_state
)
814 plane
->state
= &vop_plane_state
->base
;
815 plane
->state
->plane
= plane
;
818 struct drm_plane_state
*
819 vop_atomic_plane_duplicate_state(struct drm_plane
*plane
)
821 struct vop_plane_state
*old_vop_plane_state
;
822 struct vop_plane_state
*vop_plane_state
;
824 if (WARN_ON(!plane
->state
))
827 old_vop_plane_state
= to_vop_plane_state(plane
->state
);
828 vop_plane_state
= kmemdup(old_vop_plane_state
,
829 sizeof(*vop_plane_state
), GFP_KERNEL
);
830 if (!vop_plane_state
)
833 __drm_atomic_helper_plane_duplicate_state(plane
,
834 &vop_plane_state
->base
);
836 return &vop_plane_state
->base
;
839 static void vop_atomic_plane_destroy_state(struct drm_plane
*plane
,
840 struct drm_plane_state
*state
)
842 struct vop_plane_state
*vop_state
= to_vop_plane_state(state
);
844 __drm_atomic_helper_plane_destroy_state(state
);
849 static const struct drm_plane_funcs vop_plane_funcs
= {
850 .update_plane
= drm_atomic_helper_update_plane
,
851 .disable_plane
= drm_atomic_helper_disable_plane
,
852 .destroy
= vop_plane_destroy
,
853 .reset
= vop_atomic_plane_reset
,
854 .atomic_duplicate_state
= vop_atomic_plane_duplicate_state
,
855 .atomic_destroy_state
= vop_atomic_plane_destroy_state
,
858 static int vop_crtc_enable_vblank(struct drm_crtc
*crtc
)
860 struct vop
*vop
= to_vop(crtc
);
863 if (WARN_ON(!vop
->is_enabled
))
866 spin_lock_irqsave(&vop
->irq_lock
, flags
);
868 VOP_INTR_SET_TYPE(vop
, enable
, FS_INTR
, 1);
870 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
875 static void vop_crtc_disable_vblank(struct drm_crtc
*crtc
)
877 struct vop
*vop
= to_vop(crtc
);
880 if (WARN_ON(!vop
->is_enabled
))
883 spin_lock_irqsave(&vop
->irq_lock
, flags
);
885 VOP_INTR_SET_TYPE(vop
, enable
, FS_INTR
, 0);
887 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
890 static void vop_crtc_wait_for_update(struct drm_crtc
*crtc
)
892 struct vop
*vop
= to_vop(crtc
);
894 reinit_completion(&vop
->wait_update_complete
);
895 WARN_ON(!wait_for_completion_timeout(&vop
->wait_update_complete
, 100));
898 static const struct rockchip_crtc_funcs private_crtc_funcs
= {
899 .enable_vblank
= vop_crtc_enable_vblank
,
900 .disable_vblank
= vop_crtc_disable_vblank
,
901 .wait_for_update
= vop_crtc_wait_for_update
,
904 static bool vop_crtc_mode_fixup(struct drm_crtc
*crtc
,
905 const struct drm_display_mode
*mode
,
906 struct drm_display_mode
*adjusted_mode
)
908 struct vop
*vop
= to_vop(crtc
);
910 adjusted_mode
->clock
=
911 clk_round_rate(vop
->dclk
, mode
->clock
* 1000) / 1000;
916 static void vop_crtc_enable(struct drm_crtc
*crtc
)
918 struct vop
*vop
= to_vop(crtc
);
919 struct rockchip_crtc_state
*s
= to_rockchip_crtc_state(crtc
->state
);
920 struct drm_display_mode
*adjusted_mode
= &crtc
->state
->adjusted_mode
;
921 u16 hsync_len
= adjusted_mode
->hsync_end
- adjusted_mode
->hsync_start
;
922 u16 hdisplay
= adjusted_mode
->hdisplay
;
923 u16 htotal
= adjusted_mode
->htotal
;
924 u16 hact_st
= adjusted_mode
->htotal
- adjusted_mode
->hsync_start
;
925 u16 hact_end
= hact_st
+ hdisplay
;
926 u16 vdisplay
= adjusted_mode
->vdisplay
;
927 u16 vtotal
= adjusted_mode
->vtotal
;
928 u16 vsync_len
= adjusted_mode
->vsync_end
- adjusted_mode
->vsync_start
;
929 u16 vact_st
= adjusted_mode
->vtotal
- adjusted_mode
->vsync_start
;
930 u16 vact_end
= vact_st
+ vdisplay
;
937 * If dclk rate is zero, mean that scanout is stop,
938 * we don't need wait any more.
940 if (clk_get_rate(vop
->dclk
)) {
942 * Rk3288 vop timing register is immediately, when configure
943 * display timing on display time, may cause tearing.
945 * Vop standby will take effect at end of current frame,
946 * if dsp hold valid irq happen, it means standby complete.
949 * standby and wait complete --> |----
953 * configure display timing --> |
958 reinit_completion(&vop
->dsp_hold_completion
);
959 vop_dsp_hold_valid_irq_enable(vop
);
961 spin_lock(&vop
->reg_lock
);
963 VOP_CTRL_SET(vop
, standby
, 1);
965 spin_unlock(&vop
->reg_lock
);
967 wait_for_completion(&vop
->dsp_hold_completion
);
969 vop_dsp_hold_valid_irq_disable(vop
);
973 val
|= (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
) ? 0 : 1;
974 val
|= (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
) ? 0 : (1 << 1);
975 VOP_CTRL_SET(vop
, pin_pol
, val
);
976 switch (s
->output_type
) {
977 case DRM_MODE_CONNECTOR_LVDS
:
978 VOP_CTRL_SET(vop
, rgb_en
, 1);
980 case DRM_MODE_CONNECTOR_eDP
:
981 VOP_CTRL_SET(vop
, edp_en
, 1);
983 case DRM_MODE_CONNECTOR_HDMIA
:
984 VOP_CTRL_SET(vop
, hdmi_en
, 1);
986 case DRM_MODE_CONNECTOR_DSI
:
987 VOP_CTRL_SET(vop
, mipi_en
, 1);
990 DRM_ERROR("unsupport connector_type[%d]\n", s
->output_type
);
992 VOP_CTRL_SET(vop
, out_mode
, s
->output_mode
);
994 VOP_CTRL_SET(vop
, htotal_pw
, (htotal
<< 16) | hsync_len
);
997 VOP_CTRL_SET(vop
, hact_st_end
, val
);
998 VOP_CTRL_SET(vop
, hpost_st_end
, val
);
1000 VOP_CTRL_SET(vop
, vtotal_pw
, (vtotal
<< 16) | vsync_len
);
1001 val
= vact_st
<< 16;
1003 VOP_CTRL_SET(vop
, vact_st_end
, val
);
1004 VOP_CTRL_SET(vop
, vpost_st_end
, val
);
1006 clk_set_rate(vop
->dclk
, adjusted_mode
->clock
* 1000);
1008 VOP_CTRL_SET(vop
, standby
, 0);
1011 static void vop_crtc_atomic_flush(struct drm_crtc
*crtc
,
1012 struct drm_crtc_state
*old_crtc_state
)
1014 struct vop
*vop
= to_vop(crtc
);
1016 if (WARN_ON(!vop
->is_enabled
))
1019 spin_lock(&vop
->reg_lock
);
1023 spin_unlock(&vop
->reg_lock
);
1026 static void vop_crtc_atomic_begin(struct drm_crtc
*crtc
,
1027 struct drm_crtc_state
*old_crtc_state
)
1029 struct vop
*vop
= to_vop(crtc
);
1031 spin_lock_irq(&crtc
->dev
->event_lock
);
1032 if (crtc
->state
->event
) {
1033 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
1034 WARN_ON(vop
->event
);
1036 vop
->event
= crtc
->state
->event
;
1037 crtc
->state
->event
= NULL
;
1039 spin_unlock_irq(&crtc
->dev
->event_lock
);
1042 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs
= {
1043 .enable
= vop_crtc_enable
,
1044 .disable
= vop_crtc_disable
,
1045 .mode_fixup
= vop_crtc_mode_fixup
,
1046 .atomic_flush
= vop_crtc_atomic_flush
,
1047 .atomic_begin
= vop_crtc_atomic_begin
,
1050 static void vop_crtc_destroy(struct drm_crtc
*crtc
)
1052 drm_crtc_cleanup(crtc
);
1055 static struct drm_crtc_state
*vop_crtc_duplicate_state(struct drm_crtc
*crtc
)
1057 struct rockchip_crtc_state
*rockchip_state
;
1059 rockchip_state
= kzalloc(sizeof(*rockchip_state
), GFP_KERNEL
);
1060 if (!rockchip_state
)
1063 __drm_atomic_helper_crtc_duplicate_state(crtc
, &rockchip_state
->base
);
1064 return &rockchip_state
->base
;
1067 static void vop_crtc_destroy_state(struct drm_crtc
*crtc
,
1068 struct drm_crtc_state
*state
)
1070 struct rockchip_crtc_state
*s
= to_rockchip_crtc_state(state
);
1072 __drm_atomic_helper_crtc_destroy_state(&s
->base
);
1076 static const struct drm_crtc_funcs vop_crtc_funcs
= {
1077 .set_config
= drm_atomic_helper_set_config
,
1078 .page_flip
= drm_atomic_helper_page_flip
,
1079 .destroy
= vop_crtc_destroy
,
1080 .reset
= drm_atomic_helper_crtc_reset
,
1081 .atomic_duplicate_state
= vop_crtc_duplicate_state
,
1082 .atomic_destroy_state
= vop_crtc_destroy_state
,
1085 static bool vop_win_pending_is_complete(struct vop_win
*vop_win
)
1087 dma_addr_t yrgb_mst
;
1089 if (!vop_win
->enable
)
1090 return VOP_WIN_GET(vop_win
->vop
, vop_win
->data
, enable
) == 0;
1092 yrgb_mst
= VOP_WIN_GET_YRGBADDR(vop_win
->vop
, vop_win
->data
);
1094 return yrgb_mst
== vop_win
->yrgb_mst
;
1097 static void vop_handle_vblank(struct vop
*vop
)
1099 struct drm_device
*drm
= vop
->drm_dev
;
1100 struct drm_crtc
*crtc
= &vop
->crtc
;
1101 unsigned long flags
;
1104 for (i
= 0; i
< vop
->data
->win_size
; i
++) {
1105 if (!vop_win_pending_is_complete(&vop
->win
[i
]))
1109 spin_lock_irqsave(&drm
->event_lock
, flags
);
1112 drm_crtc_send_vblank_event(crtc
, vop
->event
);
1113 drm_crtc_vblank_put(crtc
);
1117 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
1119 if (!completion_done(&vop
->wait_update_complete
))
1120 complete(&vop
->wait_update_complete
);
1123 static irqreturn_t
vop_isr(int irq
, void *data
)
1125 struct vop
*vop
= data
;
1126 struct drm_crtc
*crtc
= &vop
->crtc
;
1127 uint32_t active_irqs
;
1128 unsigned long flags
;
1132 * interrupt register has interrupt status, enable and clear bits, we
1133 * must hold irq_lock to avoid a race with enable/disable_vblank().
1135 spin_lock_irqsave(&vop
->irq_lock
, flags
);
1137 active_irqs
= VOP_INTR_GET_TYPE(vop
, status
, INTR_MASK
);
1138 /* Clear all active interrupt sources */
1140 VOP_INTR_SET_TYPE(vop
, clear
, active_irqs
, 1);
1142 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
1144 /* This is expected for vop iommu irqs, since the irq is shared */
1148 if (active_irqs
& DSP_HOLD_VALID_INTR
) {
1149 complete(&vop
->dsp_hold_completion
);
1150 active_irqs
&= ~DSP_HOLD_VALID_INTR
;
1154 if (active_irqs
& FS_INTR
) {
1155 drm_crtc_handle_vblank(crtc
);
1156 vop_handle_vblank(vop
);
1157 active_irqs
&= ~FS_INTR
;
1161 /* Unhandled irqs are spurious. */
1163 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs
);
1168 static int vop_create_crtc(struct vop
*vop
)
1170 const struct vop_data
*vop_data
= vop
->data
;
1171 struct device
*dev
= vop
->dev
;
1172 struct drm_device
*drm_dev
= vop
->drm_dev
;
1173 struct drm_plane
*primary
= NULL
, *cursor
= NULL
, *plane
, *tmp
;
1174 struct drm_crtc
*crtc
= &vop
->crtc
;
1175 struct device_node
*port
;
1180 * Create drm_plane for primary and cursor planes first, since we need
1181 * to pass them to drm_crtc_init_with_planes, which sets the
1182 * "possible_crtcs" to the newly initialized crtc.
1184 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1185 struct vop_win
*vop_win
= &vop
->win
[i
];
1186 const struct vop_win_data
*win_data
= vop_win
->data
;
1188 if (win_data
->type
!= DRM_PLANE_TYPE_PRIMARY
&&
1189 win_data
->type
!= DRM_PLANE_TYPE_CURSOR
)
1192 ret
= drm_universal_plane_init(vop
->drm_dev
, &vop_win
->base
,
1193 0, &vop_plane_funcs
,
1194 win_data
->phy
->data_formats
,
1195 win_data
->phy
->nformats
,
1196 win_data
->type
, NULL
);
1198 DRM_ERROR("failed to initialize plane\n");
1199 goto err_cleanup_planes
;
1202 plane
= &vop_win
->base
;
1203 drm_plane_helper_add(plane
, &plane_helper_funcs
);
1204 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
)
1206 else if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
1210 ret
= drm_crtc_init_with_planes(drm_dev
, crtc
, primary
, cursor
,
1211 &vop_crtc_funcs
, NULL
);
1213 goto err_cleanup_planes
;
1215 drm_crtc_helper_add(crtc
, &vop_crtc_helper_funcs
);
1218 * Create drm_planes for overlay windows with possible_crtcs restricted
1219 * to the newly created crtc.
1221 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1222 struct vop_win
*vop_win
= &vop
->win
[i
];
1223 const struct vop_win_data
*win_data
= vop_win
->data
;
1224 unsigned long possible_crtcs
= 1 << drm_crtc_index(crtc
);
1226 if (win_data
->type
!= DRM_PLANE_TYPE_OVERLAY
)
1229 ret
= drm_universal_plane_init(vop
->drm_dev
, &vop_win
->base
,
1232 win_data
->phy
->data_formats
,
1233 win_data
->phy
->nformats
,
1234 win_data
->type
, NULL
);
1236 DRM_ERROR("failed to initialize overlay plane\n");
1237 goto err_cleanup_crtc
;
1239 drm_plane_helper_add(&vop_win
->base
, &plane_helper_funcs
);
1242 port
= of_get_child_by_name(dev
->of_node
, "port");
1244 DRM_ERROR("no port node found in %s\n",
1245 dev
->of_node
->full_name
);
1247 goto err_cleanup_crtc
;
1250 init_completion(&vop
->dsp_hold_completion
);
1251 init_completion(&vop
->wait_update_complete
);
1253 rockchip_register_crtc_funcs(crtc
, &private_crtc_funcs
);
1258 drm_crtc_cleanup(crtc
);
1260 list_for_each_entry_safe(plane
, tmp
, &drm_dev
->mode_config
.plane_list
,
1262 drm_plane_cleanup(plane
);
1266 static void vop_destroy_crtc(struct vop
*vop
)
1268 struct drm_crtc
*crtc
= &vop
->crtc
;
1269 struct drm_device
*drm_dev
= vop
->drm_dev
;
1270 struct drm_plane
*plane
, *tmp
;
1272 rockchip_unregister_crtc_funcs(crtc
);
1273 of_node_put(crtc
->port
);
1276 * We need to cleanup the planes now. Why?
1278 * The planes are "&vop->win[i].base". That means the memory is
1279 * all part of the big "struct vop" chunk of memory. That memory
1280 * was devm allocated and associated with this component. We need to
1281 * free it ourselves before vop_unbind() finishes.
1283 list_for_each_entry_safe(plane
, tmp
, &drm_dev
->mode_config
.plane_list
,
1285 vop_plane_destroy(plane
);
1288 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1289 * references the CRTC.
1291 drm_crtc_cleanup(crtc
);
1294 static int vop_initial(struct vop
*vop
)
1296 const struct vop_data
*vop_data
= vop
->data
;
1297 const struct vop_reg_data
*init_table
= vop_data
->init_table
;
1298 struct reset_control
*ahb_rst
;
1301 vop
->hclk
= devm_clk_get(vop
->dev
, "hclk_vop");
1302 if (IS_ERR(vop
->hclk
)) {
1303 dev_err(vop
->dev
, "failed to get hclk source\n");
1304 return PTR_ERR(vop
->hclk
);
1306 vop
->aclk
= devm_clk_get(vop
->dev
, "aclk_vop");
1307 if (IS_ERR(vop
->aclk
)) {
1308 dev_err(vop
->dev
, "failed to get aclk source\n");
1309 return PTR_ERR(vop
->aclk
);
1311 vop
->dclk
= devm_clk_get(vop
->dev
, "dclk_vop");
1312 if (IS_ERR(vop
->dclk
)) {
1313 dev_err(vop
->dev
, "failed to get dclk source\n");
1314 return PTR_ERR(vop
->dclk
);
1317 ret
= clk_prepare(vop
->dclk
);
1319 dev_err(vop
->dev
, "failed to prepare dclk\n");
1323 /* Enable both the hclk and aclk to setup the vop */
1324 ret
= clk_prepare_enable(vop
->hclk
);
1326 dev_err(vop
->dev
, "failed to prepare/enable hclk\n");
1327 goto err_unprepare_dclk
;
1330 ret
= clk_prepare_enable(vop
->aclk
);
1332 dev_err(vop
->dev
, "failed to prepare/enable aclk\n");
1333 goto err_disable_hclk
;
1337 * do hclk_reset, reset all vop registers.
1339 ahb_rst
= devm_reset_control_get(vop
->dev
, "ahb");
1340 if (IS_ERR(ahb_rst
)) {
1341 dev_err(vop
->dev
, "failed to get ahb reset\n");
1342 ret
= PTR_ERR(ahb_rst
);
1343 goto err_disable_aclk
;
1345 reset_control_assert(ahb_rst
);
1346 usleep_range(10, 20);
1347 reset_control_deassert(ahb_rst
);
1349 memcpy(vop
->regsbak
, vop
->regs
, vop
->len
);
1351 for (i
= 0; i
< vop_data
->table_size
; i
++)
1352 vop_writel(vop
, init_table
[i
].offset
, init_table
[i
].value
);
1354 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1355 const struct vop_win_data
*win
= &vop_data
->win
[i
];
1357 VOP_WIN_SET(vop
, win
, enable
, 0);
1363 * do dclk_reset, let all config take affect.
1365 vop
->dclk_rst
= devm_reset_control_get(vop
->dev
, "dclk");
1366 if (IS_ERR(vop
->dclk_rst
)) {
1367 dev_err(vop
->dev
, "failed to get dclk reset\n");
1368 ret
= PTR_ERR(vop
->dclk_rst
);
1369 goto err_disable_aclk
;
1371 reset_control_assert(vop
->dclk_rst
);
1372 usleep_range(10, 20);
1373 reset_control_deassert(vop
->dclk_rst
);
1375 clk_disable(vop
->hclk
);
1376 clk_disable(vop
->aclk
);
1378 vop
->is_enabled
= false;
1383 clk_disable_unprepare(vop
->aclk
);
1385 clk_disable_unprepare(vop
->hclk
);
1387 clk_unprepare(vop
->dclk
);
1392 * Initialize the vop->win array elements.
1394 static void vop_win_init(struct vop
*vop
)
1396 const struct vop_data
*vop_data
= vop
->data
;
1399 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1400 struct vop_win
*vop_win
= &vop
->win
[i
];
1401 const struct vop_win_data
*win_data
= &vop_data
->win
[i
];
1403 vop_win
->data
= win_data
;
1408 static int vop_bind(struct device
*dev
, struct device
*master
, void *data
)
1410 struct platform_device
*pdev
= to_platform_device(dev
);
1411 const struct vop_data
*vop_data
;
1412 struct drm_device
*drm_dev
= data
;
1414 struct resource
*res
;
1418 vop_data
= of_device_get_match_data(dev
);
1422 /* Allocate vop struct and its vop_win array */
1423 alloc_size
= sizeof(*vop
) + sizeof(*vop
->win
) * vop_data
->win_size
;
1424 vop
= devm_kzalloc(dev
, alloc_size
, GFP_KERNEL
);
1429 vop
->data
= vop_data
;
1430 vop
->drm_dev
= drm_dev
;
1431 dev_set_drvdata(dev
, vop
);
1435 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1436 vop
->len
= resource_size(res
);
1437 vop
->regs
= devm_ioremap_resource(dev
, res
);
1438 if (IS_ERR(vop
->regs
))
1439 return PTR_ERR(vop
->regs
);
1441 vop
->regsbak
= devm_kzalloc(dev
, vop
->len
, GFP_KERNEL
);
1445 ret
= vop_initial(vop
);
1447 dev_err(&pdev
->dev
, "cannot initial vop dev - err %d\n", ret
);
1451 irq
= platform_get_irq(pdev
, 0);
1453 dev_err(dev
, "cannot find irq for vop\n");
1456 vop
->irq
= (unsigned int)irq
;
1458 spin_lock_init(&vop
->reg_lock
);
1459 spin_lock_init(&vop
->irq_lock
);
1461 mutex_init(&vop
->vsync_mutex
);
1463 ret
= devm_request_irq(dev
, vop
->irq
, vop_isr
,
1464 IRQF_SHARED
, dev_name(dev
), vop
);
1468 /* IRQ is initially disabled; it gets enabled in power_on */
1469 disable_irq(vop
->irq
);
1471 ret
= vop_create_crtc(vop
);
1475 pm_runtime_enable(&pdev
->dev
);
1479 static void vop_unbind(struct device
*dev
, struct device
*master
, void *data
)
1481 struct vop
*vop
= dev_get_drvdata(dev
);
1483 pm_runtime_disable(dev
);
1484 vop_destroy_crtc(vop
);
1487 const struct component_ops vop_component_ops
= {
1489 .unbind
= vop_unbind
,
1491 EXPORT_SYMBOL_GPL(vop_component_ops
);