drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG(off, _mask, s) \
  24                 {.offset = off, \
  25                  .mask = _mask, \
  26                  .shift = s,}
  27
  28 static const uint32_t formats_win_full[] = {
  29         DRM_FORMAT_XRGB8888,
  30         DRM_FORMAT_ARGB8888,
  31         DRM_FORMAT_XBGR8888,
  32         DRM_FORMAT_ABGR8888,
  33         DRM_FORMAT_RGB888,
  34         DRM_FORMAT_BGR888,
  35         DRM_FORMAT_RGB565,
  36         DRM_FORMAT_BGR565,
  37         DRM_FORMAT_NV12,
  38         DRM_FORMAT_NV16,
  39         DRM_FORMAT_NV24,
  40 };
  41
  42 static const uint32_t formats_win_lite[] = {
  43         DRM_FORMAT_XRGB8888,
  44         DRM_FORMAT_ARGB8888,
  45         DRM_FORMAT_XBGR8888,
  46         DRM_FORMAT_ABGR8888,
  47         DRM_FORMAT_RGB888,
  48         DRM_FORMAT_BGR888,
  49         DRM_FORMAT_RGB565,
  50         DRM_FORMAT_BGR565,
  51 };
  52
  53 static const struct vop_scl_regs rk3036_win_scl = {
  54         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  55         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
  56         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
  57         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
  58 };
  59
  60 static const struct vop_win_phy rk3036_win0_data = {
  61         .scl = &rk3036_win_scl,
  62         .data_formats = formats_win_full,
  63         .nformats = ARRAY_SIZE(formats_win_full),
  64         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
  65         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
  66         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
  67         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
  68         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
  69         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
  70         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
  71         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
  72         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
  73         .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
  74 };
  75
  76 static const struct vop_win_phy rk3036_win1_data = {
  77         .data_formats = formats_win_lite,
  78         .nformats = ARRAY_SIZE(formats_win_lite),
  79         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
  80         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
  81         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
  82         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
  83         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
  84         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
  85         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
  86         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
  87 };
  88
  89 static const struct vop_win_data rk3036_vop_win_data[] = {
  90         { .base = 0x00, .phy = &rk3036_win0_data,
  91           .type = DRM_PLANE_TYPE_PRIMARY },
  92         { .base = 0x00, .phy = &rk3036_win1_data,
  93           .type = DRM_PLANE_TYPE_CURSOR },
  94 };
  95
  96 static const int rk3036_vop_intrs[] = {
  97         DSP_HOLD_VALID_INTR,
  98         FS_INTR,
  99         LINE_FLAG_INTR,
 100         BUS_ERROR_INTR,
 101 };
 102
 103 static const struct vop_intr rk3036_intr = {
 104         .intrs = rk3036_vop_intrs,
 105         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 106         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 107         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 108         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 109 };
 110
 111 static const struct vop_ctrl rk3036_ctrl_data = {
 112         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 113         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 114         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
 115         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 116         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 117         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 118         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 119         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 120 };
 121
 122 static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
 123         {RK3036_DSP_CTRL1, 0x00000000},
 124 };
 125
 126 static const struct vop_data rk3036_vop = {
 127         .init_table = rk3036_vop_init_reg_table,
 128         .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
 129         .ctrl = &rk3036_ctrl_data,
 130         .intr = &rk3036_intr,
 131         .win = rk3036_vop_win_data,
 132         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 133 };
 134
 135 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
 136         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
 137         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
 138         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
 139         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
 140         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
 141         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
 142         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
 143         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
 144         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
 145         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
 146         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
 147         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
 148         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
 149         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
 150         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
 151         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
 152         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
 153         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
 154         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
 155         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
 156         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
 157 };
 158
 159 static const struct vop_scl_regs rk3288_win_full_scl = {
 160         .ext = &rk3288_win_full_scl_ext,
 161         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 162         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 163         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 164         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 165 };
 166
 167 static const struct vop_win_phy rk3288_win01_data = {
 168         .scl = &rk3288_win_full_scl,
 169         .data_formats = formats_win_full,
 170         .nformats = ARRAY_SIZE(formats_win_full),
 171         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 172         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
 173         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 174         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 175         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 176         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 177         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 178         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 179         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 180         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 181         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 182         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
 183 };
 184
 185 static const struct vop_win_phy rk3288_win23_data = {
 186         .data_formats = formats_win_lite,
 187         .nformats = ARRAY_SIZE(formats_win_lite),
 188         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
 189         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 190         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 191         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 192         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 193         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 194         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 195         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 196         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 197 };
 198
 199 static const struct vop_ctrl rk3288_ctrl_data = {
 200         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 201         .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 202         .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
 203         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 204         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 205         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 206         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 207         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 208         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 209         .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
 210         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 211         .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
 212         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 213         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 214         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 215         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 216         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 217         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 218         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 219 };
 220
 221 static const struct vop_reg_data rk3288_init_reg_table[] = {
 222         {RK3288_SYS_CTRL, 0x00c00000},
 223         {RK3288_DSP_CTRL0, 0x00000000},
 224         {RK3288_WIN0_CTRL0, 0x00000080},
 225         {RK3288_WIN1_CTRL0, 0x00000080},
 226         /* TODO: Win2/3 support multiple area function, but we haven't found
 227          * a suitable way to use it yet, so let's just use them as other windows
 228          * with only area 0 enabled.
 229          */
 230         {RK3288_WIN2_CTRL0, 0x00000010},
 231         {RK3288_WIN3_CTRL0, 0x00000010},
 232 };
 233
 234 /*
 235  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 236  * special support to get alpha blending working.  For now, just use overlay
 237  * window 3 for the drm cursor.
 238  *
 239  */
 240 static const struct vop_win_data rk3288_vop_win_data[] = {
 241         { .base = 0x00, .phy = &rk3288_win01_data,
 242           .type = DRM_PLANE_TYPE_PRIMARY },
 243         { .base = 0x40, .phy = &rk3288_win01_data,
 244           .type = DRM_PLANE_TYPE_OVERLAY },
 245         { .base = 0x00, .phy = &rk3288_win23_data,
 246           .type = DRM_PLANE_TYPE_OVERLAY },
 247         { .base = 0x50, .phy = &rk3288_win23_data,
 248           .type = DRM_PLANE_TYPE_CURSOR },
 249 };
 250
 251 static const int rk3288_vop_intrs[] = {
 252         DSP_HOLD_VALID_INTR,
 253         FS_INTR,
 254         LINE_FLAG_INTR,
 255         BUS_ERROR_INTR,
 256 };
 257
 258 static const struct vop_intr rk3288_vop_intr = {
 259         .intrs = rk3288_vop_intrs,
 260         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 261         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 262         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 263         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 264 };
 265
 266 static const struct vop_data rk3288_vop = {
 267         .init_table = rk3288_init_reg_table,
 268         .table_size = ARRAY_SIZE(rk3288_init_reg_table),
 269         .intr = &rk3288_vop_intr,
 270         .ctrl = &rk3288_ctrl_data,
 271         .win = rk3288_vop_win_data,
 272         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 273 };
 274
 275 static const struct of_device_id vop_driver_dt_match[] = {
 276         { .compatible = "rockchip,rk3036-vop",
 277           .data = &rk3036_vop },
 278         { .compatible = "rockchip,rk3288-vop",
 279           .data = &rk3288_vop },
 280         {},
 281 };
 282 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 283
 284 static int vop_probe(struct platform_device *pdev)
 285 {
 286         struct device *dev = &pdev->dev;
 287
 288         if (!dev->of_node) {
 289                 dev_err(dev, "can't find vop devices\n");
 290                 return -ENODEV;
 291         }
 292
 293         return component_add(dev, &vop_component_ops);
 294 }
 295
 296 static int vop_remove(struct platform_device *pdev)
 297 {
 298         component_del(&pdev->dev, &vop_component_ops);
 299
 300         return 0;
 301 }
 302
 303 static struct platform_driver vop_platform_driver = {
 304         .probe = vop_probe,
 305         .remove = vop_remove,
 306         .driver = {
 307                 .name = "rockchip-vop",
 308                 .owner = THIS_MODULE,
 309                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 310         },
 311 };
 312
 313 module_platform_driver(vop_platform_driver);
 314
 315 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 316 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 317 MODULE_LICENSE("GPL v2");